HM62864 Series

65536-word × 8-bit High Speed CMOS Static RAM

ADE-203-255B (Z)
Rev. 2.0
Jul. 4, 1995

Description

The Hitachi HM62864 is a CMOS static RAM organized 64-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. It
offers low power standby power dissipation; therefore, it is suitable for battery backup systems. The
device, packaged in a 525-mil SOP (460-mil body SOP) and a 8 × 20 mm TSOP with thickness of 1.2
mm, is available for high density mounting. TSOP package is suitable for cards.

Features

• High speed
— Fast access time: 55/70/85 ns (max)
• Low power
— Active: 50 mW (typ) (f = 1 MHz)
— Standby: 2 µW (typ)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery backup operation
2 chip selection for battery backup
HM62864 Series

Ordering Information
Type No. Access Time Package
HM62864LFP-7 70 ns 525-mil 32-pin plastic SOP (FP-32D)
HM62864LFP-8 85 ns
HM62864LFP-5SL 55 ns
HM62864LFP-7SL 70 ns
HM62864LFP-8SL 85 ns
HM62864LT-7 70 ns 8 mm × 20 mm 32-pin TSOP (normal type) (TFP-32D)
HM62864LT-8 85 ns
HM62864LT-5SL 55 ns
HM62864LT-7SL 70 ns
HM62864LT-8SL 85 ns

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 HM62864 Series

Pin Arrangement

HM62864LFP Series HM62864LT Series

NC 1 32 VCC A11 1 32 OE
A9 2 31 A10
NC 2 31 A15 A8 3 30 CS1
A14 3 30 CS2 A13 4 29 I/O7
WE 5 28 I/O6
A12 4 29 WE CS2 6 27 I/O5
A15 7 26 I/O4
A7 5 28 A13 VCC 8 25 I/O3
6 NC 9 24 VSS
A6 27 A8 NC 10 23 I/O2
A5 7 26 A9 A14 11 22 I/O1
A12 12 21 I/O0
A4 8 25 A11 A7 13 20 A0
A6 14 19 A1
A3 9 24 OE A5 15 18 A2
A2 10 23 A10 A4 16 17 A3

A1 11 22 CS1
A0 12 21 I/O7 (Top view)
I/O0 13 20 I/O6
I/O1 14 19 I/O5
I/O2 15 18 I/O4
VSS 16 17 I/O3

(Top view)

Pin Description
Pin Name Function
A0 to A15 Address
I/O0 to I/O7 Input/output
CS1 Chip select 1
CS2 Chip select 2
WE Write enable
OE Output enable
NC No connection
VCC Power supply
VSS Ground

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HM62864 Series

Block Diagram

(MSB) V CC
A14
A6 V SS
A12
•
A7 •
•
A8 Memory Matrix
Row •
A13 •
Decoder 512 x 1,024
A15
A5
(LSB) A4

I/O0 •
• Column I/O •
•

Input Column Decoder

Data
Control

I/O7

A10 A11 A9 A0 A1 A2 A3
(MSB) (LSB)

•
•

CS2
Timing Pulse Generator
CS1
WE Read/Write Control

OE

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 HM62864 Series

Function Table
CS1 CS2 OE WE Mode VCC Current I/O Pin Ref. Cycle
H X X X Not selected I SB , I SB1 High-Z —
X L X X Not selected I SB , I SB1 High-Z —
L H H H Output disable I CC High-Z —
L H L H Read I CC Dout Read cycle (1) to (3)
L H H L Write I CC Din Write cycle (1)
L H L L Write I CC Din Write cycle (2)
Note: X: High or Low

Absolute Maximum Ratings

Parameter Symbol Value Unit
Power supply voltage *1 VCC –0.5 to +7.0 V
*1 *2 *3
Terminal voltage VT –0.5 to V CC + 0.3 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. Relative to VSS
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0V

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 0 0 0 V
Input high (logic 1) voltage VIH 2.2 — VCC + 0.3 V
*1
Input low (logic 0) voltage VIL –0.3 — 0.8 V
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns

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HM62864 Series

DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)

Parameter Symbol Min Typ*1 Max Unit Test conditions
Input leakage current |ILI| — — 1 µA VSS ≤ Vin ≤ VCC
Output leakage current |ILO | — — 1 µA CS1 = VIH or CS2 = VIL or OE = VIH
or WE = VIL, VSS ≤ VI/O ≤ VCC
Operating power supply current I CC — 10 15 mA CS1 = VIL, CS2 = VIH,
Others = VIH/VIL, I I/O = 0 mA
Average operating HM62864-5 I CC1 — 55 70 mA Min cycle, duty = 100%,
power supply CS1 = VIL, CS2 = VIH,
current HM62864-7 I CC1 — 55 70 Others = VIH/VIL, I I/O = 0 mA
HM62864-8 I CC1 — 45 60
I CC2 — 10 15 mA Cycle time = 1 µs, duty = 100%,
I I/O = 0 mA, CS1 ≤ V IL, CS2 ≥ V IH,
Others = VIH/VIL, VIH ≥ VCC – 0.2 V,
0 V ≤ VIL ≤ 0.2 V
Standby power supply current I SB — 0.7 3 mA (1) or (2)
(1) CS1 = VIH, CS2 = VIH
(2) CS2 = VIL
I SB1 — 0.4 100 µA 0 V ≤ Vin ≤ VCC (1) or (2)
(1) CS1 ≥ V CC – 0.2 V,
I SB1 — 0.4 50*2 CS2 ≥ VCC – 0.2V
(2) 0 V ≤ CS2 ≤ 0.2 V
Output low voltage VOL — — 0.4 V I OL = 2.1 mA
Output high voltage VOH 2.4 — — V I OH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for SL version.

Capacitance (Ta = 25°C, f = 1.0 MHz)*1

Parameter Symbol Min Typ Max Unit Test Conditions
Input capacitance Cin — — 5 pF Vin = 0 V
Input/output capacitance CI/O — — 8 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.

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 HM62864 Series

AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: 0.8 V to 2.4 V

• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: HM62864-5: 1 TTL + 30 pF (Including scope & jig)
HM62864-7/8: 1 TTL + 100 pF (Including scope & jig)

Read Cycle

HM62864-5 HM62864-7 HM62864-8

Parameter Symbol Min Max Min Max Min Max Unit Notes
Read cycle time t RC 55 — 70 — 85 — ns
Address access time t AA — 55 — 70 — 85 ns
Chip select access time CS1 t CO1 — 55 — 70 — 85 ns
CS2 t CO2 — 55 — 70 — 85 ns
Output enable to output valid t OE — 30 — 40 — 45 ns
Chip selection to output in CS1 t LZ1 5 — 10 — 10 — ns 2
low-Z CS2 t LZ2 5 — 10 — 10 — ns 2
Output enable to output in t OLZ 5 — 5 — 5 — ns 2
low-Z
Chip deselection in output in CS1 t HZ1 0 20 0 25 0 30 ns 1, 2
high-Z CS2 t HZ2 0 20 0 25 0 30 ns 1, 2
Output disable to output in t OHZ 0 20 0 25 0 30 ns 1, 2
high-Z
Output hold from address t OH 5 — 10 — 10 — ns
change
Notes: 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.

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HM62864 Series

Read Timing Waveform (1) (WE = VIH)

t RC

Address Valid address

t AA

CS1
t CO1
t LZ1 t HZ1

CS2
t CO2
t LZ2 t HZ2

OE
t OE t OHZ
t OLZ t OH

High Impedance
Dout Valid data

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 HM62864 Series

Read Timing Waveform (2) (WE = VIH)

Address Valid address

t AA
t OH
t OH

Dout Valid data

Read Timing Waveform (3) (WE = VIH)

t CO1
CS1
t HZ1

t LZ1
t HZ2
CS2
t CO2

t LZ2

Dout Valid data

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HM62864 Series

Write Cycle

HM62864-5 HM62864-7 HM62864-8

Parameter Symbol Min Max Min Max Min Max Unit Notes
Write cycle time t WC 55 — 70 — 85 — ns
Chip selection to end of write t CW 50 — 60 — 75 — ns 4
Address setup time t AS 0 — 0 — 0 — ns 5
Address valid to end of write t AW 50 — 60 — 75 — ns
Write pulse width t WP 40 — 50 — 55 — ns 3, 8
Write recovery time t WR 0 — 0 — 0 — ns 6
Write to output in high-Z t WHZ 0 20 0 25 0 30 ns 1, 2, 7
Data to write time overlap t DW 30 — 30 — 35 — ns
Data hold from write time t DH 0 — 0 — 0 — ns
Output active from end of write t OW 5 — 5 — 5 — ns 2
Output disable to output in high-Z t OHZ 0 20 0 25 0 30 ns 1, 2, 7
Notes: 1. t WHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at
the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at
the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is
measured from the beginning of write to the end of write.
4. t CW is measured from the later of CS1 going low or CS2 going high to the end of write.
5. t AS is measured from the address valid to the beginning of write.
6. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
7. During this period, I/O pin are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem
of data bus contention, tWP ≥ tWHZ max + tDW min.

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 HM62864 Series

Write Timing Waveform (1) (OE Clock)

t WC

Address Valid address

t AW

OE

t CW

CS1
*1 t WR

CS2

t AS t WP

WE

t OHZ
High Impedance
Dout
t DW t DH

High Impedance
Din Valid data

Notes:1.If CS1 goes low or CS2 goes high simultaneously with WE going low or
after WE going low, the outputs remain in the high impedance state.

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HM62864 Series

Write Timing Waveform (2) (OE Low Fixed)

t WC

Address Valid address

t CW t WR

CS1
*1

CS2

t AW
t OH
t WP

WE t AS
t WHZ t OW
*2 *3

Dout
t DW t DH
*4

High Impedance
Din Valid data

Notes: 1. If CS1 goes low or CS2 goes high simultaneously with WE going low or after WE going low, the
outputs remain in the high impedance state.
2. Dout is the same phase of the latest written data in this write cycle.
3. Dout is the read data of next address.
4. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Therefore, the
input signals of opposite phase to the outputs must not be applied to them.

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 HM62864 Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter Symbol Min Typ*1 Max Unit Test conditions*5

VCC for data retention VDR 2.0 — 5.5 V 0 V ≤ Vin ≤ VCC, (1) or (2)
(1) CS1 ≥ V CC – 0.2 V,
CS2 ≥ V CC – 0.2 V
(2) 0 V ≤ CS2 ≤ 0.2 V
Data retention current I CCDR — 0.1 30*2 µA VCC = 3.0 V, 0 V ≤ Vin ≤ VCC, (1) or (2)
(1) CS1 ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2V
(2) 0 V ≤ CS2 ≤ 0.2 V
I CCDR — 0.1 10*3 µA
Chip deselect to data t CDR 0 — — ns See retention waveform
retention time
Operation recovery time tR t RC*4 — — ns
Notes: 1. Typical values are at VCC = 3.0 V, Ta = 25°C and not guaranteed.
2. 10 µA max at Ta = 0 to 40°C.
3. This characteristics guaranteed for only L-SL version. 3 µA max at Ta = 0 to 40°C.
4. t RC = Read cycle time.
5. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance
state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2
V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.

Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)

t CDR Data retention mode tR

V CC
4.5 V

2.2 V
V DR1

CS1 CS1 ≥ VCC – 0.2 V

0V

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HM62864 Series

Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)

t CDR Data retention mode tR

V CC
4.5 V

CS2

V DR2

0.4 V
0V < CS2 < 0.2 V
0V

Package Dimensions

HM62864LFP Series (FP-32D) Unit: mm

20.45
20.95 Max
32 17
11.30

1 16
3.00 Max

14.14 ± 0.30
+ 0.13
– 0.07

1.00 Max 1.42

0.22

0–8°
+ 0.12
– 0.10

1.27 0.10
0.80 ± 0.20
0.15

0.40 +– 0.05
0.10
0.15 M

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 HM62864 Series

HM62864LT Series (TFP-32D) Unit: mm

8.00
8.20 Max
32 17

18.40

1 16
0.50
0.20 ± 0.10
0.08 M
20.00 ± 0.20 0.80
0.45 Max
0 – 5°
1.20 Max

0.13 ± 0.05
0.17 ± 0.05

0.10 0.50 ± 0.10

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