Scribd
Upload
31 views

VHDL Complete File

This document describes 10 experiments to design various digital logic circuits like gates, adders, decoders, encoders, flip flops, multiplexers, shift registers, counters and combinational logic functions using VHDL. Code snippets and output waveforms are provided for each experiment.

Uploaded by

B.K TECH
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
31 views

VHDL Complete File

This document describes 10 experiments to design various digital logic circuits like gates, adders, decoders, encoders, flip flops, multiplexers, shift registers, counters and combinational logic functions using VHDL. Code snippets and output waveforms are provided for each experiment.

Uploaded by

B.K TECH
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 21

Experiment No.

-01
AIM :- To design various logic gates using VHDL and
study the output waveform.
(A) :- AND GATE
Program :-
library IEEE;

use IEEE.std_logic_1164.all;

entity and1 is

port(a,b:in bit;c:out bit);

end and1;

architecture andg of and1 is

begin

c<=(a and b) ;

end andg;

OUTPUT :-
(B) :- OR GATE
Program :-
library IEEE;

use IEEE.std_logic_1164.all;

entity or1 is

port(a,b:in bit;c:out bit);

end or1;

architecture org of or1 is

begin

c<=(a or b) ;

end org;

OUTPUT :-

(C) :- NOT GATE


Program :-
library IEEE;

use IEEE.std_logic_1164.all;
entity not1 is

port(a:in bit; c:out bit);

end not1;

architecture notg of not1 is

begin

c<= not a ;

end notg;

OUTPUT :-

(D) :- NAND GATE


Program :-
library IEEE;

use IEEE.std_logic_1164.all;

entity nand1 is

port(a,b:in bit; c:out bit);

end nand1;

architecture nandg of nand1 is


begin

c<= a nand b ;

end nandg;

OUTPUT :-

(E) :- NOR GATE


Program :-
library IEEE;

use IEEE.std_logic_1164.all;

entity nor1 is

port(a,b:in bit; c:out bit);

end nor1;

architecture norg of nor1 is

begin

c<= a nor b ;

end norg;
OUTPUT :-

(F) :- XOR GATE


Program :-
library IEEE;

use IEEE.std_logic_1164.all;

entity xor1 is

port(a,b:in bit; c:out bit);

end xor1;

architecture xorg of xor1 is

begin

c<= a xor b ;

end xorg;

OUTPUT :-
Experiment No. -02
AIM :- To design a half adder circuit using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity halfadder1 is

port(a,b:in bit ; sum,carry:out bit);

end halfadder1;

architecture halfadderg of halfadder1 is

begin

sum<=a xor b;

carry<=a and b;

end halfadderg;

OUTPUT :-
Experiment No. -03
AIM :- To design a full adder circuit using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity fulladder1 is

port(a,b,c:in bit ; sum,carry:out bit);

end fulladder1;

architecture fulladderg of fulladder1 is

begin

sum<=(a xor b) xor c;

carry<=((a xor b) and c) or (a and b) ;

end fulladderg;

OUTPUT :-
Experiment No. -04
AIM :- To design 3x8 DECODER using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity decoder3x8 is

port(a,b,c,e:in bit; z:out bit_vector(0 to 7));

end decoder3x8;

architecture decoderg of decoder3x8 is

begin

z(0)<=(not a) and (not b) and (not c) and (not e);

z(1)<=(not a) and (not b) and c and (not e);

z(2)<=(not a) and b and (not c) and (not e);

z(3)<=(not a) and b and c and (not e);

z(4)<=a and (not b) and (not c) and (not e);

z(5)<=a and (not b) and c and (not e);

z(6)<=a and b and (not c) and (not e);

z(7)<=a and b and c and (not e);

end decoderg;
OUTPUT :-
Experiment No. -05
AIM :- To design 8x3 ENCODER using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity encoder8x3 is

port(z:in bit_vector(0 to 7) ; e:in bit ; a,b,c :out bit);

end encoder8x3;

architecture encoderg of encoder8x3 is

begin

a<= (z(4) or z(5) or z(6) or z(7)) and (not e);

b<= (z(2) or z(3) or z(6) or z(7)) and (not e);

c<= (z(1) or z(3) or z(5) or z(7)) and (not e);

end encoderg;

OUTPUT :- Z1 =1
Z3 =1

Z5 =1

Z7 = 1
Experiment No. -06
AIM :-To design D FLIP FLOP using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity DFF is

port(D,clk:in bit; Q: out bit);

end DFF;

architecture DFF1 of DFF is

begin

process(clk,D)

begin

if (clk='1') then

Q<=D;

end if;

end process;

end DFF1;
OUTPUT :-
Experiment No. -07
AIM :- To design 4x1 MUX using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity mux4 is

port(a,b,c,d,s0,s1:in bit ; z: out bit);

end mux4;

architecture muxx of mux4 is

begin

process(s0,s1) is

begin

if(s0='0' and s1='0') then

z<=a;

elsif(s0='0' and s1='1') then

z<=b;

elsif(s0='1' and s1='0') then

z<=c;

else

z<=d;

end if;
end process;

end muxx;

OUTPUT :-
S0 =0 , S1=1

S0 =1 , S1=1
Experiment No. -08
AIM :- To design a shift register using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity shiftregister is

port(din,clk: in bit ; Q:inout bit_vector(3 downto 0 ));

end shiftregister;

architecture shr of shiftregister is

begin

process(clk)

begin

if(clk'event and clk='1') then

Q(3 downto 1)<=Q(2 downto 0);

Q(0)<= din;

end if;

end process;

end shr;
OUTPUT :-
Experiment No. -09
AIM :- To design a decimal counter using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity dc1 is

port(clk:in bit ; q:inout std_logic_vector(3 downto 0));

end dc1;

architecture u1 of dc1 is

signal d:std_logic_vector(3 downto 0);

begin

process(clk)

begin

if d="1010" then

d<="0000";

elsif(clk'event and clk='1') then

d<=d+1;

end if;

end process;

q<=d;
end u1;

OUTPUT :-
Experiment No. -10
AIM :- To design F(A,B,C) = AB’ + AC(A’+B) using VHDL.
Program :-
library ieee;

use ieee.std_logic_1164.all;

entity function10 is

port(a,b,c: in bit; f: out bit);

end function10;

architecture function2 of function10 is

begin

f<=((a and not(b))or((a and c)and(not(a) or b)));

end function2;

OUTPUT :-

You might also like