EC200A&EC2x Series

Compatible Design

LTE Standard Module Series

Version: 1.0

Date: 2022-09-28

Status: Released
 LTE Standard Module Series

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EC200A&EC2x_Series_Compatible_Design 1 / 45
 LTE Standard Module Series

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EC200A&EC2x_Series_Compatible_Design 2 / 45
 LTE Standard Module Series

About the Document

Revision History

Version Date Author Description

Shiye ZHU/
- 2022-07-11 Brant WAN/ Creation of the document
Dylan LIU
Shiye ZHU/
Handor QIN/
1.0 2022-09-28 First official release
Dylan LIU/
Frank WANG

EC200A&EC2x_Series_Compatible_Design 3 / 45
 LTE Standard Module Series

Contents

About the Document ................................................................................................................................... 3

Contents ....................................................................................................................................................... 4
Table Index ................................................................................................................................................... 5
Figure Index ................................................................................................................................................. 6

1 Introduction .......................................................................................................................................... 7
1.1. Special Mark ............................................................................................................................ 7

2 General Descriptions ........................................................................................................................... 8

2.1. Product Description ................................................................................................................. 8
2.1.1. General Information ......................................................................................................... 8
2.2. Feature Overview .................................................................................................................... 9
2.3. Pin Assignment ...................................................................................................................... 11

3 Pin Description ................................................................................................................................... 12

3.1. Pin Description ...................................................................................................................... 13

4 Hardware Reference Design ............................................................................................................. 21

4.1. Power Supply ........................................................................................................................ 21
4.2. Turn-on/-off ............................................................................................................................ 22
4.2.1. Turn-on ........................................................................................................................... 22
4.2.2. Turn-off ........................................................................................................................... 25
4.3. Reset ..................................................................................................................................... 26
4.4. (U)SIM Interface .................................................................................................................... 28
4.5. USB Interface ........................................................................................................................ 29
4.6. PCM and I2C Interfaces ........................................................................................................ 30
4.7. UART Interfaces .................................................................................................................... 31
4.8. Antenna Interfaces ................................................................................................................ 32
4.8.1. RF Antenna Interface ..................................................................................................... 32
4.8.2. GNSS Antenna Interface ................................................................................................ 33

5 Recommended Footprints ................................................................................................................ 35

6 Appendix References ........................................................................................................................ 37

EC200A&EC2x_Series_Compatible_Design 4 / 45
 LTE Standard Module Series

Table Index

Table 1: Special Mark ................................................................................................................................... 7

Table 2: General Information ........................................................................................................................ 8
Table 3: Feature Overview ........................................................................................................................... 9
Table 4: I/O Parameter Definition ............................................................................................................... 12
Table 5: Pin Definition................................................................................................................................. 13
Table 6: Power-up Timing of EC200A and EC2x ...................................................................................... 24
Table 7: Turn-off with PWRKEY Timing for EC200A and EC2x ................................................................. 26
Table 8: Reset Timing of EC200A and EC2x ............................................................................................. 28
Table 9: Related Documents ...................................................................................................................... 37
Table 10: Terms and Abbreviations ............................................................................................................ 37

EC200A&EC2x_Series_Compatible_Design 5 / 45
 LTE Standard Module Series

Figure Index

Figure 1: EC200A & EC2x Pin Assignments...............................................................................................11

Figure 2: Power Supply in Star Configuration Routing .............................................................................. 21
Figure 3: Power Supply Reference Design ................................................................................................ 22
Figure 4: Turn-on Circuit ............................................................................................................................ 22
Figure 5: Power-up Timing (EC200A Series) ............................................................................................. 23
Figure 6: Power-up Timing (EC2x Family) ................................................................................................. 24
Figure 7: Turn-off Circuit ............................................................................................................................ 25
Figure 8: Turn-off with PWRKEY Timing .................................................................................................... 25
Figure 9: RESET_N Reference Circuit ...................................................................................................... 26
Figure 10: Reference Circuit of RESET_N by Using a Button .................................................................. 27
Figure 11: Reset Timing (EC200A Series) ................................................................................................. 27
Figure 12: Reset Timing (EC2x Family) ..................................................................................................... 27
Figure 13: Reference Design of (U)SIM Interface with 8-Pin (U)SIM Card Connector ............................. 28
Figure 14: Reference Design of (U)SIM Interface with 6-Pin (U)SIM Card Connector ............................. 29
Figure 15: USB Interface Reference Design ............................................................................................. 29
Figure 16: Reference Design of PCM and I2C Interface with Audio Codec .............................................. 30
Figure 17: Reference Design of Voltage-Level Translation Using IC ........................................................ 31
Figure 18: Reference Design of Voltage-level Translation Using Transistors ........................................... 32
Figure 19: RF Antenna Interface Reference Design .................................................................................. 33
Figure 20: Reference Design of GNSS Antenna Interface (EC2x Family) ................................................ 33
Figure 21: Recommended Compatible Footprint (EC200A & EC2x)......................................................... 35
Figure 22: Recommended Compatible Footprint Without SGMII, RGMII/RMII, Audio or Wi-Fi Function . 36

EC200A&EC2x_Series_Compatible_Design 6 / 45
 LTE Standard Module Series

1 Introduction
Quectel LTE Standard EC200A series modules are compatible with EC2x family modules (EC25 series,
EC21 series, EC20-CE). This document outlines the compatible design among EC200A series and EC2x
family modules, which can help you easily migrate from one design to either of the others.

NOTE

For conciseness purposes, EC200A, EC25, EC21 and EC20-CE modules will hereinafter be referred
to collectively as ''the module/modules'' in parts hereof applicable to all said modules, and
individually as “EC200A” and “EC2x” in parts hereof referring to the differences between them.

1.1. Special Mark

Table 1: Special Mark

Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface,
pin name, AT command, or argument, it indicates that the function, feature, interface, pin,
*
AT command, or argument is under development and currently not supported; and the
asterisk (*) after a model indicates that the sample of such model is currently unavailable.

EC200A&EC2x_Series_Compatible_Design 7 / 45
 LTE Standard Module Series

2 General Descriptions
2.1. Product Description

The general information and frequency bands of EC200A and EC2x modules are presented in the tables
below.

2.1.1. General Information

Table 2: General Information

Module Name Appearance Packaging Dimensions (mm)

EC200A Series 80 LCC pins + 64 LGA pins 29.0 × 32.0 × 2.4

EC25 Series 80 LCC pins + 64 LGA pins 29.0 × 32.0 × 2.4

EC21 Series 80 LCC pins + 64 LGA pins 29.0 × 32.0 × 2.4

EC20-CE 80 LCC pins + 64 LGA pins 29.0 × 32.0 × 2.4

EC200A&EC2x_Series_Compatible_Design 8 / 45
 LTE Standard Module Series

2.2. Feature Overview

The general features of EC200A and EC2x modules are compared in the table below.

Table 3: Feature Overview

Feature EC200A Series EC25 Series/EC21 Series/EC20-CE

Power Supply Supply voltage: 3.4–4.5 V, Typ. 3.8 V Supply voltage: 3.3–4.3 V, Typ. 3.8 V

Sleep Current < 3 mA. < 4 mA.

(USB Suspend) For more information, see document [1]. For more information, see document [2] & [3] & [4].
GPRS: GPRS:
⚫ Supports GPRS multi-slot class 12 ⚫ Supports GPRS multi-slot class 33 (33 by default)
⚫ Coding scheme: CS 1-4 ⚫ Coding scheme: CS 1-4
⚫ Max. 85.6 kbps (DL)/ Max. 85.6 kbps (UL) ⚫ Max. 107 kbps (DL)/Max. 85.6 kbps (UL)
EDGE: EDGE:
GSM Features ⚫ Supports EDGE multi-slot class 12 ⚫ Supports EDGE multi-slot class 33 (33 by default)
⚫ Supports GMSK and 8-PSK for different MCS (Modulation and Coding ⚫ Supports GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme) Scheme)
⚫ Downlink coding schemes: MCS 1-9 ⚫ Downlink coding schemes: MCS 1-9
⚫ Uplink coding schemes: MCS 1-9 ⚫ Uplink coding schemes: MCS 1-9
⚫ Max. 236.8 kbps (DL)/Max. 236.8 kbps (UL) ⚫ Max. 296 kbps (DL)/Max. 236.8 kbps (UL)
⚫ Supports 3GPP Rel-8 DC-HSDPA, HSPA+, HSDPA, HSUPA and
⚫ Supports 3GPP Rel-7 HSPA+, HSDPA, HSUPA and WCDMA
WCDMA
⚫ Supports QPSK,16-QAM and 64QA modulations
⚫ Supports QPSK, 16QAM and 64QAM modulations
UMTS Features ⚫ HSPA+: Max. 21 Mbps (DL)
⚫ DC-HSDPA: Max 42 Mbps (DL)
⚫ HSUPA: Max. 5.76 Mbps (UL)
⚫ HSUPA: Max. 5.76 Mbps (UL)
⚫ WCDMA: Max. 384 kbps (DL)/Max. 384 kbps (UL)
⚫ WCDMA: Max. 384 kbps (DL)/Max. 384 kbps (UL)
EC25 Series/EC20-CE:
Non-CA LTE Cat 4:
FDD: Max. 150 Mbps (DL), Max. 50 Mbps (UL)
Non-CA LTE Cat 4:
TDD: Max. 130 Mbps (DL), Max. 30 Mbps (UL)
LTE Features FDD: Max. 150 Mbps (DL), Max. 50 Mbps (UL)
EC21 Series:
TDD: Max. 130 Mbps (DL), Max. 30 Mbps (UL)
Non-CA LTE Cat 1:
FDD: Max. 10 Mbps (DL), Max. 5 Mbps (UL)
TDD: Max. 8.96 Mbps (DL), Max. 3.1 Mbps (UL)

EC200A&EC2x_Series_Compatible_Design 9 / 45
 LTE Standard Module Series

Operating temperature range: -35 to +75 °C 1 Operating temperature range: -35 to +75 °C 3
Temperature Ranges Extended temperature range: -40 to +85 °C 2 Extended temperature range: -40 to +85 °C 4
Storage temperature range: -40 to +90 °C Storage temperature range: -40 to +90 °C
Main UART: Main UART:
⚫ Used for AT command communication and data transmission ⚫ Used for AT command communication and data transmission
⚫ Baud rates: up to 921600 bps, 115200 bps by default ⚫ Baud rates: up to 921600 bps, 115200 bps by default
UART Interfaces ⚫ RTS and CTS hardware flow control ⚫ RTS and CTS hardware flow control
Debug UART: Debug UART:
⚫ Used for the output of partial logs ⚫ Used for Linux console and log output
⚫ 115200 bps baud rate ⚫ 115200 bps baud rate
Compliant with USB 2.0 Compliant with USB 2.0
USB Interface
High-speed and full-speed modes (slave only) High-speed and full-speed modes (slave only)

Digital Audio PCM interface PCM interface

I2C Interfaces Supported Supported

SD Card Interface SD 3.0 protocol SD 3.0 protocol

Low-power SDIO 3.0 interface for WLAN;

WLAN/Bluetooth Interface Supported SDIO interface for WLAN
UART & PCM interfaces for Bluetooth

10 Mbps/100 Mbps/1000 Mbps Ethernet work modes

EC25 Series/EC20-CE:
SGMII Interface - Max. 150 Mbps (DL)/50 Mbps (UL) for 4G network
EC21 Series:
Max. 10 Mbps (DL)/Max. 5 Mbps (UL) for 4G network
RMII: 1.8/ 3.3 V; default: 3.3 V
RGMII/RMII -
RGMII: 1.8 V

(U)SIM Card Detection Supported Supported

GNSS - GPS, GLONASS, BDS, Galileo, QZSS 5

Firmware Upgrade USB interface or DFOTA USB interface or DFOTA

1 Within the operating temperature range, the module meets 3GPP specifications.
2 Within the extended temperature range, the module retains the ability to establish and maintain functions such as voice, SMS, data transmission, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while
one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again.
3 Within the operating temperature range, the module meets 3GPP specifications.
4 Within the extended temperature range, the module retains the ability to establish and maintain functions such as voice, SMS, data transmission, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while

one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again.
5 GNSS function is optional.

EC200A&EC2x_Series_Compatible_Design 10 / 45
 LTE Standard Module Series

2.3. Pin Assignment

Pin assignments of EC200A and EC2x modules are presented in the figure below.

EC200A Series EC25 Series/EC21 Series/EC20-CE

RESE RV ED
RESE RV ED
RESE RV ED

RESE RV ED
MA IN_RXD

USB_VB US
RESE RV ED

RESE RV ED
MA IN_DCD
MA IN_DTR

MA IN_CTS
MA IN_TX D

MA IN_RTS
USB_VB US

VB AT_RF
VB AT_BB

VB AT_RF
VB AT_BB
VB AT_BB
VB AT_BB

VB AT_RF
VB AT_RF
MA IN_RI

USB_DP
USB_DP

STA TUS
USB_DM

STA TUS
USB_DM
GND

GND
GND

RXD

DCD
RTS
TXD

CTS
DTR
GND

RI
114

114
113

113

72
72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56
55
WAKE UP _I N 1 54 GND WAKE UP _I N 1 54 GND

AP _REA DY 2 53 GND AP _REA DY 2 53 GND

129 117 129 117
WLAN_S DI O RESE RV ED
RESE RV ED 3 _DA TA3 52 GND RESE RV ED 3 SDC1_DATA3 RESE RV ED
52 GND

108 103 99 95 90 85 108 103 99 95 90 85

4 130 118 4 130 118
W_DI SAB LE #
WLAN_S DI O WLAN_S LP
51 GND W_DI SAB LE #
51 GND
SDC1_DATA2 WLAN_S LP _CLK
_DA TA2 _CLK GND GND GND GND
GND GND GND GND GND GND GND GND
NET_MODE 5 131 119 50 GND NET_MODE 5 131 119 50 GND

WLAN_S DI O RGMII/ RM II SDC1_DATA1 EP HY _RST_N

NET_STA TUS 6 _DA TA1 _RS T 49 ANT_MAI N NET_STA TUS 6 49 ANT_MAI N

132 120 132 120

VDD_E XT 7 WLAN_S DI O RGMII/ RM II
109 104 100 96 91 86 48 GND VDD_E XT 7 SDC1_DATA0 EP HY _I NT_N
109 104 100 96 91 86 48 GND
_DA TA0 _INT

RESE RV ED 141 133 121 GND GND GND GND

GND GND 144 RESE RV ED RESE RV ED 141 133 121 GND GND GND GND
GND GND 144 RESE RV ED

RESE RV ED 142
WLAN_S DI O
_CLK
RGMII/ RM II
_MD_I O
82 79 76 73 143 RESE RV ED RESE RV ED 142
SDC1_CLK SGMI I_MDATA
82 79 76 73 143 RESE RV ED
RGMII_RX_3 RGMII_RX_2 RGMII/ RM II RGMII/ RM II
134 122 134 122
_RX _0 _RX _1 RESE RV ED RESE RV ED RESE RV ED RESE RV ED

GND 8 110 105 83 80 77 74 47 RESE RV ED GND 8 110 105 83 80 77 74 47

WLAN_S DI O RGMII/ RM II
_CM D _MD_CLK
92 87 SDC1_CMD SGMI I_MCLK 92 87 ANT_GNSS

RGMII_CK_TX RGMII_TX _2 RGMII/ RM II RGMII/ RM II RESE RV ED RESE RV ED RESE RV ED RESE RV ED

9 135 123 9 135 123
_TX_0 _CTL_RX
GND 46 GND GND 46 GND

WLAN_WAK E SP K_N
GND GND
84 81 78 75 GND GND
WAKE _ON_ SGMI I_TX_M
GND GND 84 81 78 75 GND GND
RESE RV ED RESE RV ED RESE RV ED RESE RV ED
USIM _GND 10 RGMII_TX _3 RGMII/ RM II RGMII/ RM II RGMII/ RM II
45 ADC0 USIM _GND 10 WIRELES S
45 ADC0

136 124
_CTL_TX _TX_1
136 124
_CLK

DBG_RX D 11 WLAN_E N SP K_P 44 ADC1 DBG_RX D 11 WLAN_E N SGMI I_TX_P 44 ADC1

137 125 111 106 101 97 93 88 111 106 101 97 93 88

DBG_TXD 12 43 RESE RV ED DBG_TXD 12 137 125 43 RESE RV ED
RESE RV ED MI C_P COEX_UART SGMI I_RX_P
GND _RX GND GND GND GND
GND GND GND GND GND
USIM _DET 13 GND GND
42 I2C_SDA USIM _P RE SENCE 13 42 I2C_SDA
138 126 138 126
USIM _V DD 14 RESE RV ED MI C_N
41 I2C_SCL USIM _V DD 14 COEX_UART SGMI I_RX_M
_TX 41 I2C_SCL

139 127 98 94 89 139 127 98 94 89

USIM _DATA 15
RESE RV ED WLAN_P WR
112 107 102 40 SP I_CLK USIM _DATA 15
BT_E N
112 107 102 40 BT_CTS
PM _E NA BLE
_EN
USIM _CLK 16 39 USIM _CLK 16 39 BT_RXD
140 128 140
SP I_DI N
GND GND GND GND GND GND 128 GND GND GND GND
GND GND

USIM _RST 17 MI CB IAS RESE RV ED

38 SP I_DOUT
USIM _RST 17 RESE RV ED USIM 2_VDD
38 BT_TX D

RESE RV ED 18 37 SP I_CS
RESE RV ED 18 37 BT_RTS
116

115

116

115
19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36
RESE T_N
PWRKEY
GND

GND

RESE RV ED
USB_BOOT

PCM_DIN

SDC2_DATA3

SDC2_DATA1
SD_SDIO_CLK
RESE T_N

SD_DE T

GND
SD_SDIO_DA TA0
RESE RV ED

ANT_DI V

GND
SD_SDIO_DA TA3

ANT_DRX
PCM_CLK

PWRKEY

SDC2_CLK
PCM_DOUT

SD_SDIO_DA TA1
PCM_SY NC

VDD_S DI O
SDC2_DATA2

SDC2_DATA0

SDC2_CMD
SD_SDIO_VDD

GND
SD_SDIO_DA TA2

SD_SDIO_CM D

PCM_CLK
USB_BOOT

SD_INS_DE T

PCM_SY NC
GND

PCM_OUT
PCM_IN
Compatible pins Different pins

Figure 1: EC200A & EC2x Pin Assignments

NOTE

1. The USB_BOOT and RGMII/RMII_RST_N pin of EC200A series cannot be pulled to high level before module startup. There are no restrictions on other pins.
2. WAKEUP_IN, NET_MODE, WLAN_EN, COEX_UART_RX, COEX_UART_TX, USB_BOOT, BT_CTS pins of EC2x family cannot be pulled to high level before module startup.

EC200A&EC2x_Series_Compatible_Design 11 / 45
 LTE Standard Module Series

3 Pin Description
The pins on the modules are described below.

Table 4: I/O Parameter Definition

Symbol Description

AI Analog Input

AO Analog Output

AIO Analog Input/Output

DI Digital Input

DO Digital Output

DIO Digital Input/Output

OD Open Drain

PI Power Input

PO Power Output

EC200A&EC2x_Series_Compatible_Design 12 / 45
 LTE Standard Module Series

3.1. Pin Description

Pin definitions of EC200x and EC2x modules are presented in the following table.

Table 5: Pin Definition

EC200A Series EC25 Series/EC21 Series/EC20-CE

Pin No. Pin Name I/O Power Domain Pin No. Pin Name I/O Power Domain

1 WAKEUP_IN* DI 1.8 V 1 WAKEUP_IN DI 1.8 V

2 AP_READY* DI 1.8 V 2 AP_READY DI 1.8 V

3 RESERVED - - 3 RESERVED - -

4 W_DISABLE# DI 1.8 V 4 W_DISABLE# DI 1.8 V

5 NET_MODE DO 1.8 V 5 NET_MODE DO 1.8 V

6 NET_STATUS DO 1.8 V 6 NET_STATUS DO 1.8 V

7 VDD_EXT PO 1.8 V 7 VDD_EXT PO 1.8 V

8 GND - GND 8 GND - GND

9 GND - GND 9 GND - GND

10 USIM_GND - GND 10 USIM_GND - GND

EC200A&EC2x_Series_Compatible_Design 13 / 45
 LTE Standard Module Series

11 DBG_RXD DI 1.8 V 11 DBG_RXD DI 1.8 V

12 DBG_TXD DO 1.8 V 12 DBG_TXD DO 1.8 V

13 USIM_DET DI 1.8 V 13 USIM_PRESENCE DI 1.8 V

14 USIM_VDD PO 1.8/ 3.0 V 14 USIM_VDD PO 1.8/ 3.0 V

15 USIM_DATA DIO 1.8/ 3.0 V 15 USIM_DATA DIO 1.8/ 3.0 V

16 USIM_CLK DO 1.8/ 3.0 V 16 USIM_CLK DO 1.8/ 3.0 V

17 USIM_RST DO 1.8/ 3.0 V 17 USIM_RST DO 1.8/ 3.0 V

18 RESERVED - - 18 RESERVED - -

19 GND - GND 19 GND - GND

20 RESET_N DI 1.8 V 20 RESET_N DI 1.8 V

The output voltage is 0.8
21 PWRKEY DI VBAT 21 PWRKEY DI V when the module is
powered on.
22 GND - GND 22 GND - GND

23 SD_DET* DI 1.8 V 23 SD_INS_DET DI 1.8 V

24 PCM_DIN DI 1.8 V 24 PCM_IN DI 1.8 V

25 PCM_DOUT DO 1.8 V 25 PCM_OUT DO 1.8 V

26 PCM_SYNC DIO 1.8 V 26 PCM_SYNC DIO 1.8 V

27 PCM_CLK DIO 1.8 V 27 PCM_CLK DIO 1.8 V

EC200A&EC2x_Series_Compatible_Design 14 / 45
 LTE Standard Module Series

28 SD_SDIO_DATA3 DIO 1.8/ 2.8 V 28 SDC2_DATA3 DIO 1.8/ 2.85 V

29 SD_SDIO_DATA2 DIO 1.8/ 2.8 V 29 SDC2_DATA2 DIO 1.8/ 2.85 V

30 SD_SDIO_DATA1 DIO 1.8/ 2.8 V 30 SDC2_DATA1 DIO 1.8/ 2.85 V

31 SD_SDIO_DATA0 DIO 1.8/ 2.8 V 31 SDC2_DATA0 DIO 1.8/ 2.85 V

32 SD_SDIO_CLK DO 1.8/ 2.8 V 32 SDC2_CLK DO 1.8/ 2.85 V

33 SD_SDIO_CMD DIO 1.8/ 2.8 V 33 SDC2_CMD DIO 1.8/ 2.85 V

34 SD_SDIO_VDD PO 1.8/ 2.8 V 34 VDD_SDIO PO 1.8/ 2.85 V

35 ANT_DRX AI - 35 ANT_DIV AI -

36 GND - GND 36 GND - GND

37 SPI_CS DO 1.8 V 37 BT_RTS DI 1.8 V

38 SPI_DOUT DO 1.8 V 38 BT_TXD DO 1.8 V

39 SPI_DIN DI 1.8 V 39 BT_RXD DI 1.8 V

40 SPI_CLK DO 1.8 V 40 BT_CTS DO 1.8 V

An external 1.8 V
An external 1.8 V pull-up
41 I2C_SCL OD pull-up resistor is 41 I2C_SCL OD
resistor is required.
required.
An external 1.8 V
An external 1.8 V pull-up
42 I2C_SDA OD pull-up resistor is 42 I2C_SDA OD
resistor is required.
required.
43 RESERVED - - 43 RESERVED - -

EC200A&EC2x_Series_Compatible_Design 15 / 45
 LTE Standard Module Series

44 ADC1 AI 0–VBAT_BB 44 ADC1 AI 0.3 V–VBAT_BB

45 ADC0 AI 0–VBAT_BB 45 ADC0 AI 0.3 V–VBAT_BB

46 GND - GND 46 GND - GND

47 RESERVED - - 47 ANT_GNSS AI -

48 GND - GND 48 GND - GND

49 ANT_MAIN AIO - 49 ANT_MAIN AIO -

50–54 GND - GND 50–54 GND - GND

55 RESERVED - - 55 RESERVED - -

56 GND - GND 56 GND - GND

57 VBAT_RF PI 3.4–4.5 V 57 VBAT_RF PI 3.3–4.3 V

58 VBAT_RF PI 3.4–4.5 V 58 VBAT_RF PI 3.3–4.3 V

59 VBAT_BB PI 3.4–4.5 V 59 VBAT_BB PI 3.3–4.3 V

60 VBAT_BB PI 3.4–4.5 V 60 VBAT_BB PI 3.3–4.3 V

61 STATUS OD - 61 STATUS OD -

62 MAIN_RI DO 1.8 V 62 RI DO 1.8 V

63 MAIN_DCD DO 1.8 V 63 DCD DO 1.8 V

64 MAIN_CTS DO 1.8 V 64 CTS DO 1.8 V

65 MAIN_RTS DI 1.8 V 65 RTS DI 1.8 V

EC200A&EC2x_Series_Compatible_Design 16 / 45
 LTE Standard Module Series

66 MAIN_DTR DI 1.8 V 66 DTR DI 1.8 V

67 MAIN_TXD DO 1.8 V 67 TXD DO 1.8 V

68 MAIN_RXD DI 1.8 V 68 RXD DI 1.8 V

69 USB_DP AIO - 69 USB_DP AIO -

70 USB_DM AIO - 70 USB_DM AIO -

71 USB_VBUS AI 3.0–5.25 V 71 USB_VBUS PI 3.0–5.25 V

72 GND - GND 72 GND - GND

73 RGMII/RMII_RX_1 DI 1.8/ 3.3 V 73 RESERVED - -

74 RGMII/RMII_CTL_RX DI 1.8/ 3.3 V 74 RESERVED - -

75 RGMII/RMII_CLK DI 1.8/ 3.3 V 75 RESERVED - -

76 RGMII/RMII_RX_0 DI 1.8/ 3.3 V 76 RESERVED - -

77 RGMII/RMII_TX_0 DO 1.8/ 3.3 V 77 RESERVED - -

78 RGMII/RMII_TX_1 DO 1.8/ 3.3 V 78 RESERVED - -

79 RGMII_RX_2 DI 1.8 V 79 RESERVED - -

80 RGMII_TX_2 DO 1.8 V 80 RESERVED - -

81 RGMII/RMII_CTL_TX DO 1.8/ 3.3 V 81 RESERVED - -

82 RGMII_RX_3 DI 1.8 V 82 RESERVED - -

83 RGMII_CK_TX DO 1.8 V 83 RESERVED - -

EC200A&EC2x_Series_Compatible_Design 17 / 45
 LTE Standard Module Series

84 RGMII_TX_3 DO 1.8 V 84 RESERVED - -

85– 85–
GND - GND GND - GND
112 112
113 RESERVED - - 113 RESERVED - -

114 RESERVED - - 114 RESERVED - -

115 USB_BOOT DI 1.8 V 115 USB_BOOT DI 1.8 V

116 RESERVED - - 116 RESERVED - -

117 RESERVED - - 117 RESERVED - -

118 RESERVED - 118 WLAN_SLP_CLK DO 1.8 V

119 RGMII/RMII_RST_N DO 1.8 V 119 EPHY_RST_N DO 1.8/ 2.85 V

120 RGMII/RMII_INT DI 1.8/ 3.3 V 120 EPHY_INT_N DI 1.8 V

121 RGMII/RMII_MD_IO DIO 1.8/ 3.3 V 121 SGMII_MDATA DIO 1.8/ 2.85 V

122 RGMII/RMII_MD_CLK DO 1.8/ 3.3 V 122 SGMII_MCLK DO 1.8/ 2.85 V

123 SPK_N AO - 123 SGMII_TX_M AO -

124 SPK_P AO - 124 SGMII_TX_P AO -

125 MIC_P AI - 125 SGMII_RX_P AI -

126 MIC_N AI - 126 SGMII_RX_M AI -

127 WLAN_PWR_EN DO 1.8 V 127 PM_ENABLE DO 1.8 V

128 RESERVED - - 128 USIM2_VDD PO 1.8/ 2.85 V

EC200A&EC2x_Series_Compatible_Design 18 / 45
 LTE Standard Module Series

129 WLAN_SDIO_DATA3 DIO 1.8 V 129 SDC1_DATA3 DIO 1.8 V

130 WLAN_SDIO_DATA2 DIO 1.8 V 130 SDC1_DATA2 DIO 1.8 V

131 WLAN_SDIO_DATA1 DIO 1.8 V 131 SDC1_DATA1 DIO 1.8 V

132 WLAN_SDIO_DATA0 DIO 1.8 V 132 SDC1_DATA0 DIO 1.8 V

133 WLAN_SDIO_CLK DO 1.8 V 133 SDC1_CLK DO 1.8 V

134 WLAN_SDIO_CMD DIO 1.8 V 134 SDC1_CMD DIO 1.8 V

WAKE_ON_
135 WLAN_WAKE DI 1.8 V 135 DI 1.8 V
WIRELESS
136 WLAN_EN DO 1.8 V 136 WLAN_EN DO 1.8 V

137 RESERVED - - 137 COEX_UART_RX DI 1.8 V

138 RESERVED - - 138 COEX_UART_TX DO 1.8 V

139 RESERVED - - 139 BT_EN DO 1.8 V

140 MICBIAS PO - 140 RESERVED - -

141 RESERVED - - 141 RESERVED - -

142 RESERVED - - 142 RESERVED - -

143 RESERVED - - 143 RESERVED - -

144 RESERVED - - 144 RESERVED - -

EC200A&EC2x_Series_Compatible_Design 19 / 45
 LTE Standard Module Series

NOTE

1. Keep all reserved and unused pins unconnected.

2. All GND pins should be connected to ground.
3. For more details about Wi-Fi & Bluetooth, SGMII and RGMII/RMII functions, see document [1] & [2] & [3] & [4].
4. Pins in blue have different functions or voltage domain, but the module footprints are compatible.

EC200A&EC2x_Series_Compatible_Design 20 / 45
 LTE Standard Module Series

4 Hardware Reference Design

The following sub-chapters outline the main functionalities of the compatible design among EC200A and
EC2x modules.

4.1. Power Supply

Use a TVS diode with low reverse stand-off voltage VRWM, low clamping voltage VC and high reverse
peak pulse current IPP to ensure the power source stability. A reference design for +5.0 V input power
source and the power supply in a star configuration routing are presented in the figure below.

VBAT

VBAT_RF

VBAT_BB
+ +
D1 C1 C2 C3 C4 C5 C6 C7 C8

WS4.5D3HV 100 µF 100 nF 33 pF 10 pF 100 µF 100 nF 33 pF 10 pF

Module

Figure 2: Power Supply in Star Configuration Routing

The power supply for EC2x family should be able to provide the current up to 2.0 A. For EC200A series,
the power supply should be able to provide up to 3.0 A as it supports the GSM network.

A reference design for + 5.0 V input power source is presented in the figure below. The typical output of
the power supply is about 3.8 V and the maximum load current is 3.0 A.

EC200A&EC2x_Series_Compatible_Design 21 / 39
 LTE Standard Module Series

MIC29302WU

DC_IN VBAT
2 4
IN OUT

GND

ADJ
EN
100K
1%

5
51K

4.7K 330R
470 μF 100 nF
470 μF 100 nF
47K
VBAT_EN 47K 1%

Figure 3: Power Supply Reference Design

4.2. Turn-on/-off

4.2.1. Turn-on

A reference design for the turn-on circuit of the modules is presented in the figure below.

PWRKEY

≥ 500 ms
4.7K
10 nF
Turn-on pulse

47K

Figure 4: Turn-on Circuit

EC200A&EC2x_Series_Compatible_Design 22 / 39
 LTE Standard Module Series

The power-up scenario of EC200A series is illustrated in the figure below.

NOTE 1

VBAT ≥ 500 ms
T1 VH = VBAT

PWRKEY VIL ≤ 0.5 V

About 5 ms
VDD_EXT T2
≥ 100 ms After this time, the pin can be driven high by
T3 an external circuit.
FORCE_USB_BOOT
About 22 ms
T4
RESET_N
≥ 10 s
T5
STATUS
(OD)

T6 ≥ 10 s

UART I nactive Active

≥ 10 s
T7
USB Inactive Active

Figure 5: Power-up Timing (EC200A Series)

EC200A&EC2x_Series_Compatible_Design 23 / 39
 LTE Standard Module Series

The power-up scenario of EC2x family is illustrated in the figure below.

NOTE 1

VBAT 500 ms
T1 VH = 0.8 V

PWRKEY VIL 0.5 V

About 100 ms
VDD_EXT T2
100 ms. After this time, BOOT_CONFIG/
T3 USB_BOOT pins can be pulled up externally.
BOOT_CONFIG &
USB_BOOT Pins

RESET_N
2.5 s
T5
STATUS
(OD)
12 s
T6
UART Inactive Active

13 s
T7
USB Inactive Active

Figure 6: Power-up Timing (EC2x Family)

The power-up timing for EC200A and EC2x modules is illustrated in the table below.

Table 6: Power-up Timing of EC200A and EC2x

Module T1 T2 T3 T4 T5 T6 T7

EC200A Series ≥ 500 ms Typ. 5 ms ≥ 100 ms Typ. 22 ms ≥ 10 s ≥ 10 s ≥ 10 s

EC25 Series/
EC21 Series/ ≥ 500 ms Typ. 100 ms ≥ 200 ms - ≥ 2.5 s ≥ 12 s ≥ 13 s
EC20-CE

EC200A&EC2x_Series_Compatible_Design 24 / 39
 LTE Standard Module Series

NOTE

1. Make sure that VBAT is stable before pulling down PWRKEY pin. The interval between powering up
VBAT and pulling down PWRKEY pin should be at least 30 ms.
2. PWRKEY can be pulled down directly to GND with a recommended resistor if the module needs to
be powered on automatically and shutdown is not needed. The pull-down resistors of EC200A
series should be 4.7 kΩ each, and the pull-down resistor of EC2x family should be 10 kΩ.
3. RESET_N pin of EC200A series should be pulled up after pulling down the PWRKEY pin, and
RESET_N pin of EC2x family should be pulled up after the VBAT pin is powered on.

4.2.2. Turn-off

The following is a reference design of the turn-off circuit for The modules.

PWRKEY

4.7K

Turn-off impulse
47K

Figure 7: Turn-off Circuit

4.2.2.1. Turn-off with PWRKEY

The turn-off scenario for EC200A and EC2x modules is illustrated in the figure below.

VBAT

T1 T2

PWRKEY

STATUS
(OD)

Module Running Power-down procedure OFF

Status

Figure 8: Turn-off with PWRKEY Timing

EC200A&EC2x_Series_Compatible_Design 25 / 39
 LTE Standard Module Series

The turn-off with PWRKEY timing for EC200A and EC2x modules is illustrated in the table below.

Table 7: Turn-off with PWRKEY Timing for EC200A and EC2x

Module T1 T2

EC200A Series ≥ 650 ms 4~12 s

EC25 Series/EC21 Series/EC20-CE ≥ 650 ms ≥ 29.5 s

4.2.2.2. Turn-off with AT Command

The modules can also be safely turned off with AT+QPOWD, which is similar to turning off the module
via PWRKEY pin. See document [5] & [6] or more information about AT+QPOWD.

NOTE

1. To avoid damaging the internal flash, do not switch off the power supply when the modules are
working normally. The power supply can be cut off only after the modules are shut down with
PWRKEY or AT command.
2. When turning off the modules with the AT command, keep PWRKEY at high level after executing
the command. Otherwise, the modules will turn on again after being turned off.

4.3. Reset

Use RESET_N only in case of failure to turn off the modules with AT+QPOWD or PWRKEY pin. A
reference design for the module reset signal circuit is presented in the figures below.

RESET_N

4.7K

Impulse
47K

Figure 9: RESET_N Reference Circuit

EC200A&EC2x_Series_Compatible_Design 26 / 39
 LTE Standard Module Series

S2
RESET_N

TVS

Close to S2

Figure 10: Reference Circuit of RESET_N by Using a Button

The reset scenarios of EC200A and EC2x modules are illustrated in the figures below.

VBAT

T1

RESET_N
VIL ≤ 0.5 V

Module Running Resetting Baseband restart

Status

Figure 11: Reset Timing (EC200A Series)

VBAT
≤ 460 ms

≥ 150 ms T1
RESET_N VIH ≥ 1.3 V
VIL ≤ 0.5 V

Module
Running Resetting Restart
Status

Figure 12: Reset Timing (EC2x Family)

EC200A&EC2x_Series_Compatible_Design 27 / 39
 LTE Standard Module Series

The reset timing of EC200A and EC2x modules is presented in the table below.

Table 8: Reset Timing of EC200A and EC2x

Module T1

EC200A Series ≥ 300 ms

EC25 Series/EC21 Series/EC20-CE 150 ms ≤ T1 ≤ 460 ms

NOTE

1. The RESET_N pin of EC200A series only resets the baseband chip inside the module, not the
power management chip, whereas EC20-CE’s RESET_N can reset the power management chip.
2. When the RESET_N pin of EC200A series is pulled down, the baseband chip is in the reset state,
and the chip system restarts after the pin is released.
3. Ensure that the load capacitance does not exceed 10 nF on PWRKEY and RESET_N pins.

4.4. (U)SIM Interface

(U)SIM interface of the modules meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM
cards are supported. The reference design of the (U)SIM interface with an 8-pin (U)SIM card connector
is presented in the figure below.

VDD_EXT USIM_VDD

51K 15K
USIM_GND

100 nF (U)SIM Card Connector

USIM_VDD
VCC GND
USIM_RST 0R
Module RST VPP
USIM_CLK 0R
CLK IO
USIM_DET/USIM_PRESENCE

USIM_DATA 0R GND

33 pF 33 pF 33 pF

GND GND

Figure 13: Reference Design of (U)SIM Interface with 8-Pin (U)SIM Card Connector

EC200A&EC2x_Series_Compatible_Design 28 / 39
 LTE Standard Module Series

If (U)SIM card detection function is not needed, keep USIM_DET/USIM_PRESENCE unconnected. The
reference design of (U)SIM interface with a 6-pin (U)SIM card connector is presented in the figure below.

USIM_VDD

15K
USIM_GND 100 nF
(U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
0R
USIM_DATA 0R

33 pF 33 pF 33 pF

GND GND

Figure 14: Reference Design of (U)SIM Interface with 6-Pin (U)SIM Card Connector

4.5. USB Interface

EC200A and EC2x contain one integrated Universal Serial Bus (USB) interface complying with USB 2.0
specification, with high-speed (480 Mbps) and full-speed (12 Mbps) modes supported.

The USB interface of the modules can only be a slave device and is used for AT command
communication, data transmission, GNSS NMEA sentence outputting 6 , software debugging and
firmware upgrading.

The USB interface should be reserved for firmware upgrading in your design. USB interface reference
design is presented in the figure below.

Test Points
Minimize these stubs

Module MCU
R3 NM_0R
VDD R4 NM_0R

USB_VBUS ESD Array

L1 USB_DM
USB_DM
USB_DP USB_DP

Close to Module GND

GND

Figure 15: USB Interface Reference Design

6 The USB interface on EC200A series modules does not support GNSS NMEA sentence outputting.

EC200A&EC2x_Series_Compatible_Design 29 / 39
 LTE Standard Module Series

To suppress EMI spurious transmission, it is recommended to add an L1 common mode choke in series
between the module and your MCU. In addition, the 0 Ω resistors (R1 and R2) should be added in series
between the module and the test points to facilitate debugging, since they are not mounted by default. To
ensure the integrity of USB data line signal, components L1, R1 and R2 must be placed close to the
module, and R1 and R2 resistors should be placed close to each other. Extra trace stubs must be as
short as possible.

4.6. PCM and I2C Interfaces

EC200A and EC2x support one PCM interface for audio applications and one I2C interface.

Reference design of module PCM and I2C interfaces with external codec IC is presented below.

Module MICBIAS

INP

BIAS
PCM_CLK BCLK
INN
PCM_SYNC LRCK
PCM_OUT/PCM_DOUT DAC
PCM_IN/PCM_DIN ADC

LOUTP
I2C_SCL SCL
I2C_SDA SDA LOUTN
4.7K

4.7K

Codec
1.8 V

Figure 16: Reference Design of PCM and I2C Interface with Audio Codec

NOTE

1. Reserve RC (R = 22 Ω, C = 22 pF) circuits on PCM traces, especially for PCM_CLK, and close to
codec.
2. EC200A and EC2x modules are master devices.

EC200A&EC2x_Series_Compatible_Design 30 / 39
 LTE Standard Module Series

4.7. UART Interfaces

EC200A and EC2x support one main UART and one debug UART interface.

The main UART interface can be used for data transmission and AT command communication. In
addition, it supports RTS and CTS hardware flow control.

EC200A series’ debug UART interface supports 115200 bps baud rate, and is used for partial log
outputting. EC2x family’s debug UART interface can be used as a Linux console and a log output.

EC200A and EC2x modules have a 1.8 V UART interface. A level translator should be used if the
application has a 3.3 V UART interface. TXS0108EPWR level translator by Texas Instruments is
recommended. And you can visit http://www.ti.com for more information. A reference design is illustrated
in the following figure.

VDD_EXT VCCA VCCB VDD_MCU

0.1 μF 0.1 μF
10K

EC2x series EC200A series 120K

OE GND
RI MAIN_RI A1 B1 RI_MCU
DCD MAIN_DCD A2 B2 DCD_MCU
CTS MAIN_CTS A3 Translator B3 CTS_MCU
RTS MAIN_RTS A4 B4 RTS_MCU
DTR MAIN_DTR A5 B5 DTR_MCU
TXD MAIN_TXD A6 B6 TXD_MCU
RXD MAIN_RXD A7 B7 RXD_MCU
51K 51K
A8 B8

Figure 17: Reference Design of Voltage-Level Translation Using IC

Another example of a voltage-level translator with transistor reference design is shown below. For the
design of circuits shown in dotted lines, please refer to that shown in solid lines, but pay attention to the
direction of connection.

EC200A&EC2x_Series_Compatible_Design 31 / 39
 LTE Standard Module Series

4.7K
VDD_EXT VDD_EXT Module
1 nF
MCU/ARM
10K (EC200A series) (EC2x Family)

TXD MAIN_RXD RXD

RXD MAIN_TXD TXD
1 nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS MAIN_RTS RTS
CTS MAIN_CTS CTS
GPIO MAIN_DTR DTR
EINT MAIN_RI RI
GPIO MAIN_DCD DCD
GND GND

Figure 18: Reference Design of Voltage-level Translation Using Transistors

NOTE

1. Transistor circuit solution is not suitable for applications with baud rates exceeding 460 kbps.
2. Please note that the module CTS is connected to the host CTS, and the module RTS is connected
to the host RTS.

4.8. Antenna Interfaces

4.8.1. RF Antenna Interface

The ANT_MAIN pins on the modules are compatible. The impedance of RF antenna interface is 50 Ω.
For better RF performance, a π-type matching circuit should be reserved, and the π-type matching
components should be placed as close to the antenna as possible.

EC200A and EC2x support Rx-diversity function via ANT_DIV/ANT_DRX interface. ANT_DIV/ANT_DRX
antenna interface reference design of the modules is shown below.

EC200A&EC2x_Series_Compatible_Design 32 / 39
 LTE Standard Module Series

Main
Module Antenna
R1 0R
ANT_MAIN

C1 C2

NM NM

Diversity
Antenna
R2 0R
ANT_DIV/
ANT_DRX

C3 C4

NM NM

Figure 19: RF Antenna Interface Reference Design

NOTE

1. To improve receiver sensitivity, ensure the proper distance between the main antenna and the
Rx-diversity antenna.
2. Place the π-type matching components (R1 & C1 & C2 and R2 & C3 & C4) as close to the
antenna as possible.

4.8.2. GNSS Antenna Interface

EC25 series, EC21 series, and EC20-CE modules support a GNSS antenna with ANT_GNSS pin. A
reference design of ANT_GNSS antenna interface of EC2x family is shown below.

VDD

C8
0.1 μF GNSS
R4 10 R Antenna
Module
L1
47 nH

R3 0 R C7
100 pF
ANT_GNSS
C5 C6
NM NM

Figure 20: Reference Design of GNSS Antenna Interface (EC2x Family)

EC200A&EC2x_Series_Compatible_Design 33 / 39
 LTE Standard Module Series

It is recommended to reserve C5, R3 and C6 for adjusting antenna impedance. C5 and C6 are not
mounted by default, and R3 is only mounted with a 0 Ω resistor. The impedance of the RF trace should
be controlled at about 50 Ω, and the trace should be as short as possible.

NOTE

1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.

EC200A&EC2x_Series_Compatible_Design 34 / 39
 LTE Standard Module Series

5 Recommended Footprints
The recommended compatible footprint of the modules is shown in the following figure. All dimensions
are in mm, and the dimensional tolerances are ±0.2 mm unless otherwise specified.

Figure 21: Recommended Compatible Footprint (EC200A & EC2x)

EC200A&EC2x_Series_Compatible_Design 35 / 39
 LTE Standard Module Series

If SGMII, RGMII/RMII, audio, or Wi-Fi function is not needed, clear the keepout area for pins 73-84 and
117–140 in the compatible design. The recommended compatible footprint without SGMII, RGMII/RMII,
audio, or Wi-Fi function is presented in the figure below.

Pin 1
Keepout area

29.0
Keepout area

Figure 22: Recommended Compatible Footprint Without SGMII, RGMII/RMII, Audio or Wi-Fi
Function

NOTE

1. If SGMII, RGMII/RMII, audio or Wi-Fi function is not needed, do not design the keepout area
marked in purple and clear the keepout area marked in blue for pins 117–140.
2. Keep at least 3 mm between the module and other components on the motherboard to improve
soldering quality and maintenance convenience.

EC200A&EC2x_Series_Compatible_Design 36 / 39
 LTE Standard Module Series

6 Appendix References
Table 9: Related Documents

Document Name

[1] Quectel_EC200A_Series_Hardware_Design

[2] Quectel_EC25_Series_Hardware_Design

[3] Quectel_EC21_Series_Hardware_Design

[4] Quectel_EC20_R2.1_Hardware_Design

[5] Quectel_EC200x&EG912Y&EC600S_Series_AT_Commands_Manual

[6] Quectel_EC2x&EG9x&EG2x-G&EM05_Series_AT_Commands_Manual

[7] Quectel_EC200A_Series_Reference_Design

[8] Quectel_EC2x&EG2x-G_Reference_Design

Table 10: Terms and Abbreviations

Abbreviation Description

bps Bits Per Second

CDMA Code-Division Multiple Access

CTS Clear to Send

DFOTA Delta Firmware Upgrade Over-The-Air

DL Downlink

DTR Data Terminal Ready

EMI Electromagnetic Interference

FDD Frequency Division Duplex

EC200A&EC2x_Series_Compatible_Design 37 / 39
 LTE Standard Module Series

Galileo Galileo Satellite Navigation System (EU)

GLONASS Russian Global Navigation Satellite System

GND Ground

GNSS Global Navigation Satellite System

GPS Global Positioning System

GSM Global System for Mobile Communications

I2C Inter-Integrated Circuit

I/O Input/Output

LCC Leadless Chip Carrier

LCD Liquid Crystal Display

LDO Low-dropout Regulator

LGA Land Grid Array

LTE Long Term Evolution

MCU Microcontroller Unit/Microprogrammed Control Unit

NMEA NMEA (National Marine Electronics Association) 0183 Interface Standard

QZSS Quasi-Zenith Satellite System

RF Radio Frequency

RTS Real-Time Clock

SDIO Secure Digital Input/Output

SGMII Serial Gigabit Media Independent Interface

SMS Short Message Service

SPI Serial Peripheral Interface

TDD Time Division Duplexing

TVS Transient Voltage Suppressor

UART Universal Asynchronous Receiver/Transmitter

EC200A&EC2x_Series_Compatible_Design 38 / 39
 LTE Standard Module Series

UL Uplink

USB Universal Serial Bus

(U)SIM (Universal) Subscriber Identity Module

VDD Drain Voltage

Vrwm Reverse Working Maximum Voltage

Wi-Fi Wireless Fidelity

WLAN Wireless Local Area Network

EC200A&EC2x_Series_Compatible_Design 39 / 39