Digital Logic Design

University of Gondar
Institute of Technology
Department of Electrical Engineering
Digital Logic Design:
Chapter 5: Sequential Logic Systems
By:
Habtamu Maru

Habtamu M. Digital Logic Design April 10, 2023 1 / 75

Digital Logic Design

Outline

1 Introduction Sequential Circuit

2 Introduction About Flip Flop And Latch

Latch
Flip Flops
counters
Shift Register

Habtamu M. Digital Logic Design April 10, 2023 2 / 75

Digital Logic Design

Part I:
I Latch
I Flip Flop

Habtamu M. Digital Logic Design April 10, 2023 3 / 75

Digital Logic Design

A sequential circuit consists of a combinational circuit to which

storage elements are connected to form feedback path.
The storage elements are devices capable of storing binary infor-
mation. The binary information stored in this at any given time
defines the state of the sequential circuit at that time.

Sequential circuit = combinational logic + memory element

Habtamu M. Digital Logic Design April 10, 2023 4 / 75

Digital Logic Design

Based on the timing of their signals, sequential circuits can be clas-

sified as Synchronous and Asynchronous
Synchronous sequential circuit
Synchronous circuits changes in the output are only allowed to occur in
synchronization with an external clock signal (O/p changes at certain
time).
Asynchronous
Asynchronous sequential circuits perform their operation without depend-
ing on the clock signal but use the input pulses and generate the output.
As there is no clock pulse dependency, these circuits can switch to the
next state quickly when the input signal is changed.
Asynchronous circuits changes in the output are allowed to occur when-
ever there is a change in the input signal (O/p change any time).
So, there is a faster operation with this type of sequential circuits.
Habtamu M. Digital Logic Design April 10, 2023 5 / 75
Digital Logic Design

synchronous Asynchronous

Circuit are easy to design Difficult to design

A clocked ff act as a memory ele- Unclocked ff / time delay ele-

ment ment is used asmemory element

They are slower Fast as clock is not present

The status of memory element is The status of memory element

affected only at the active edge will change at any time as soon
of clock, if input is changed. as input is changed

E.g. Flip flop E.g. Latches

Habtamu M. Digital Logic Design April 10, 2023 6 / 75

Digital Logic Design
Introduction About Flip Flop And Latch

The most important memory element is the FF, which is made up

of an assembly of logic gates. Even though a logic gate, by itself,
has no storage capability, several can be connected together in
ways that permit information to be stored.
Several different gate arrangements are used to produce these
FF.
Sequential logic circuits are may be Bistable, Monostable and Astable
, all are called multivibrators
I Bistable have two state i.e. set & reset, the circuits are letches & FFs.
I Monostable i.e. commonly known as one-shot ,has only one stable
state
I Astable i.e. has no stable state ,used for oscillator, which is self sus-
tained wave form generator.

Habtamu M. Digital Logic Design April 10, 2023 7 / 75

Digital Logic Design
Introduction About Flip Flop And Latch

Latches and FFs are sequential circuits that can store information.
One latch or FF can store one bit of information.
The main difference between latches and FFs is
latches, their outputs are constantly affected by their inputs as
long as the enable signal is asserted i.e. when they are enabled,
their content changes immediately when their inputs change.
FFs, on the other hand, have their content change only either at
the rising or falling edge of the enable signal. This enable signal is
usually the controlling clock signal.
After the rising or falling edge of the clock, the FF content remains
constant even if the input changes.

Habtamu M. Digital Logic Design April 10, 2023 8 / 75

Digital Logic Design
Introduction About Flip Flop And Latch

Storage element that operate with signal level (rather than signal
transition) are referred to as Latches, those controlled by a clock
transition are FFs.
Latches are said to be level sensitive device; FF are edge sensitive
devices.
The major differences in these FF types are the number of inputs
they have and how they change state. For each type, there are
also different variations that enhance their operations.
There are basically four main types of latches & FFs: SR, D, JK, & T.

Habtamu M. Digital Logic Design April 10, 2023 9 / 75

Digital Logic Design
Introduction About Flip Flop And Latch

Flip Flop (FF) Latches

Are building blocks of sequential Are building blocks of sequential
circuit. But built from the latches circuits and these can be built
FF continuously checks its inputs from logic gates.
and changes its output corre-
Latches continuously checks its
spondingly only at times deter-
input and changes its output cor-
mined by clocking signal.
respondingly.
They are sensitive to signal
change. And can transfer data The latches are sensitive to the

only at the single instant and duration of the pulse and can

data can not be changed until send or receive the data when

next signal change. switch is on.

It works on the basis of clock It is based on the enable function

pulses input.
Habtamu M. Digital Logic Design April 10, 2023 10 / 75
Digital Logic Design
Introduction About Flip Flop And Latch

The simplest sequential circuit or storage element is a bistable

element, which is constructed with two inverters connected se-
quentially in a loop.
It has no inputs and two outputs labeled Q and Q. Since the circuit
has no inputs, we cannot change the values of Q and Q.

Using the signal Q as the state variable to describe the state of the circuit,
we can say that the circuit has two stable states: Q =0, and Q = 1; hence
the name bistable.
Habtamu M. Digital Logic Design April 10, 2023 11 / 75
Digital Logic Design
Introduction About Flip Flop And Latch

It shows two outputs, labeled Q and Q that are the inverse of each
other
The Q output is called the normal FF output,and Q is the inverted
FF output.
For example, if we say that a FF is in the HIGH (1) state, we mean
that Q=1, if we say that a FF is in the LOW (0) state, we mean that
Q=0. Of course, Q the state will always be the inverse of Q.
I Note that the HIGH (1) state (Q=1/ Q=0)is also referred to as the
SET state.
I In a similar way, the LOW (1) state (Q=0/ Q=1) is also referred to as
the CLEAR or RESET state.

Habtamu M. Digital Logic Design April 10, 2023 12 / 75

Digital Logic Design
Introduction About Flip Flop And Latch

As the symbol in above figure implies, a FF can have one or more

inputs. These inputs are used to cause the FF to switch back and
forth (“flip-flop”) between its possible output states.

Habtamu M. Digital Logic Design April 10, 2023 13 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

S-R Latch
how to control bistable circuit?
Bistable circuit can’t change the information bit that is stored in it.
In order to change the information bit, we need to add an inputs
to the circuit.
The simplest way to add inputs is to replace the two inverters with
two NAND gates or two NOR gates. This circuit is called a SR latch.
In addition to the two outputs Q and Q, there are two inputs S and
R for SET and RESET respectively.
Following the convention, the prime in S and R denotes that these
inputs are active low.
The SR latch can be in one of two states: a SET state when Q = 1,
or a RESET state when Q = 0.
Habtamu M. Digital Logic Design April 10, 2023 14 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

NAND Gate Latch

The NAND gate version, called a NAND gate latch or simply a latch.

The two NAND gates are cross-coupled so that the output of NAND1 is
connected to one of the inputs of NAND2 , and vice versa. The gate out-
puts, labeled Q and Q respectively, are the latch outputs.

Under normal conditions, these outputs will always be the inverse of each
other.

There are two latch inputs: the SET input is the input that sets Q to the 1
state; the RESET input is the input that RESET Q to the 0 state.

The SET and RESET inputs are both normally resting in the HIGH state and
one of them will be pulsed LOW whenever we want to change the latch
outputs. We begin our analysis by showing that there are two equally
likely output states when SET= RESET= 1.

Habtamu M. Digital Logic Design April 10, 2023 15 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

One possibility is shown in the above Fig.(a), where Q= 0 & Q =1.

With Q= 0, the inputs to NAND2 are 0 and 1, which produce Q= 1.
The 1 from NAND2 causes NAND1 to have a 1 at both inputs to produce
a 0 output at Q.
In effect, what we have is the 0 at the NAND1 output producing a 1 at the
NAND2 output, which in turn, keeps the NAND1 output 0.
Habtamu M. Digital Logic Design April 10, 2023 16 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

The second possibility is shown in the above Fig. (b), where Q=1 & Q=0
The 1 from NAND1 produces a 0 at the NAND2 output, which, in turn,
keeps the NAND1 output 1.
Thus, there are two possible output states when SET=RESET=1 as we shall
soon see, the one that actually exists will depend on what has occurred
previously at the inputs.
SETing the Latch
Now let’s investigate what happens when the SET input is momentarily
pulsed 0 while RESET is kept 1. When Q=0 prior to the occurrence of the
pulse.
As SET is pulsed 0 at time t0 , Q will go 1, and this 1 will force Q to go 0
so that NAND1 now has two 0 inputs. Thus, when SET returns to the 1
state at t1 , the NAND1 output remains 1, which, in turn, keeps the NAND2
output 0.
Habtamu M. Digital Logic Design April 10, 2023 17 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

From the above two figures the second one shows that, when Q=1 and Q
=0 prior to the application of the SET pulse. Since Q =0 is already keeping
the NAND1 output 1, the 0 pulse at SET will not change anything.

Thus, when SET returns 1, the latch outputs are still in the Q=1 , Q=0 state.

We can summarize the above fig. by stating that a 0 pulse on the SET input
will always cause the latch to end up in the Q=1 state. This operation is
called setting the latch or FF.
Habtamu M. Digital Logic Design April 10, 2023 18 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

RESETing the Latch

Now let’s consider what occurs when the RESET input is pulsed 0 (R=0)
while SET is kept 1 (S=1).
Figure below(a) shows what happens when Q= 0 and Q = 1 prior to the
application of the pulse.
Since Q=0 is already keeping the NAND2 output 1 (Q=1), the 0 pulse at
RESET will not have any effect.
When RESET returns 1 (R=1) , the latch outputs are still Q= 0 & Q=1.
Figure (b) shows the situation where Q= 1 prior to the occurrence of the
RESET pulse.
As RESET is pulsed 0 at t0 , Q will go 1, and this 1 (Q=1) forces Q to go 0 so
that NAND2 now has two 0 inputs.
Thus, when RESET returns 1 at t1 , the NAND2 output remains 1, which, in
turn, keeps the NAND1 output 0.
Habtamu M. Digital Logic Design April 10, 2023 19 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

Summarized by stating that a LOW (0) pulse on the RESET input will
always cause the latch to end up in the Q=0 state. This operation
is called clearing or resetting the latch.
Habtamu M. Digital Logic Design April 10, 2023 20 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

Simultaneous SETing and RESETing

The last case to consider is the case where the SET and RESET in-
puts are simultaneously pulsed LOW (0).
This will produce HIGH levels at both NAND outputs so that Q=Q=1.
Clearly, this is an undesired condition, since the two outputs are
supposed to be inverses of each other. Furthermore, when the
SET and RESET inputs return 1, the resulting output state will de-
pend on which input returns 1 first.
Simultaneous transitions back to the 1 state will produce unpre-
dictable results.
For these reasons the SET= RESET= 0 condition is normally not
used for the NAND latch.
Habtamu M. Digital Logic Design April 10, 2023 21 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

Summary of NAND Latch

The operation described above can be conveniently placed in a
function table and is summarized as follows:
I S=R=1. This condition is the normal resting state, and it has no effect
on the output state. The Q and Q outputs will remain in whatever
state they were in prior to this input condition.
I S=0 & R=1. This will always cause the output to go to the Q=1 state,
where it will remain even after S returns 1. This is called setting the
latch.
I S=1 & R=0. This will always produce the Q=0 state, where the output
will remain even after R returns 1. This is called resetting the latch.
I S=R=0, This condition tries to set and clear the latch at the same
time, and it produces Q=Q=1. If the inputs are returned to 1 simul-
taneously, the resulting state is unpredictable. This input condition
should not be used.
Habtamu M. Digital Logic Design April 10, 2023 22 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Latch

Figure: (a) NAND latch; (b) Function table.

Habtamu M. Digital Logic Design April 10, 2023 23 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

NOR Gate Latch

Two cross-coupled NOR gates can be used as a NOR gate latch.
The arrangement is similar to the NAND latch except that the Q
and Q outputs have reversed positions.

Figure: (a) NOR gate latch; (b) Function table; (c) Simplified block symbol.

Habtamu M. Digital Logic Design April 10, 2023 24 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

The analysis of the operation of the NOR latch can be performed in ex-
actly the same manner as for the NAND latch. The results are given in the
function table in above Figure (b) and are summarized as follows:
I S=R=0. This is the normal resting state for the NOR latch, and it has
no effect on the output state. Q and Q will remain in whatever state
they were in prior to the occurrence of this input condition.
I S=1, R= 0. This will always SET Q= 1, where it will remain even after
S returns to 0.
I S= 0, R= 1. This will always RESET Q= 0, where it will remain even
after R returns to 0.
I S= 1, R= 1. This condition tries to SET and RESET the latch at the
same time, and it produces Q=Q =0. If the inputs are returned to
0 simultaneously, the resulting output state is unpredictable. This
input condition should not be used.

Habtamu M. Digital Logic Design April 10, 2023 25 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

The NOR gate latch operates exactly like the NAND latch except that the
S and R inputs are active- HIGH rather than active-LOW, and the normal
resting state is S = R= 0. Q will be set 1 by a HIGH pulse on the S input,
and it will be RESETed LOW by a HIGH pulse on the R input.
The Gated S-R Latch
A gated latch requires an enable EN input.
The S and R inputs determine the output when EN is HIGH.
The output does not change when LOW is applied to EN.
Invalid state: when S and R are simultaneously HIGH.

Habtamu M. Digital Logic Design April 10, 2023 26 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

The Gated D-Latch

It has one input in addition to EN, the input is called data(D).
When D is HIGH and EN is HIGH, the latch will SET.
When D is LOW and EN is HIGH, the latch will RESET.
When EN is LOW, the state of the latch is not changed.

Habtamu M. Digital Logic Design April 10, 2023 27 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Latch

Habtamu M. Digital Logic Design April 10, 2023 28 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clock Signals and Clocked Flip Flops

In asynchronous systems, the outputs of logic circuits can change state
any time one or more of the inputs change.
An asynchronous system is generally more difficult to design and trou-
bleshoot than a synchronous system.
In synchronous systems, the exact times at which any output can change
states are determined by a signal commonly called the clock.
This clock signal is generally a rectangular pulse train or a square wave,
as shown in Figure below.

Habtamu M. Digital Logic Design April 10, 2023 29 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

The clock signal is distributed to all parts of the system, and most (if not
all) of the system outputs can change state only when the clock makes a
transition.
When the clock changes from 0 to 1, this is called the positive-going tran-
sition (PGT); when the clock goes from 1 to 0, this is the negative going
transition (NGT).
The speed at which a synchronous digital system operates is dependent
on how often the clock cycles occur.
A clock cycle is measured from one PGT to the next PGT or from one NGT
to the next NGT. The time it takes to complete one cycle (seconds/cycle)
is called the period (T), as shown in Figure.
The speed of a digital system is normally referred to by the number of
clock cycles that happen in 1 s (cycles/second), which is known as the
frequency (F) of the clock.
Habtamu M. Digital Logic Design April 10, 2023 30 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clocked Flip-Flops
Clocked FFs have a clock input that is typically labeled CLK, CK, or C.
In most clocked FFs, the CLK input is edge-triggered, which means that it
is activated by a signal transition; this is indicated by the presence of a
small triangle on the CLK input.
This contrasts with the latches, which are level-triggered.
Clocked FFs have a clock input (CLK) that is active on either (a) the PGT or
(b) the NGT. The control inputs determine the effect of the active clock.

Habtamu M. Digital Logic Design April 10, 2023 31 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clocked FFs also have one or more control inputs that can have various
names, depending on their operation.

The control inputs will have no effect on Q until the active clock transition
occurs. In other words, their effect is synchronized with the signal applied
to CLK. For this reason they are called synchronous control inputs.

In summary, we can say that the control inputs get the FF outputs ready
to change, while the active transition at the CLK input actually triggers the
change.

The control inputs control the WHAT (i.e., what state the output will go
to); the CLK input determines the WHEN.

Habtamu M. Digital Logic Design April 10, 2023 32 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Edge Triggered Flip-flop

An edge triggered FF changes state either at positive(rising edge)
or at the negative edge(falling edge) of the clock and is sensitive
to the inputs only at this transition of the clock.
Positive edge trigger and Negative edge trigger.

All the above FF have the triggering input called clock (CLK/C).
Habtamu M. Digital Logic Design April 10, 2023 33 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

S-R Flip Flop

The S & R inputs of the S-R FF are called synchronous inputs b/c data on
this input are transferred to the FF’s output only on the triggering edge
of the clock pulse.
A clocked S-R FF that is triggered by the PG edge of the clock signal. This
means that the FF can change states only when a signal applied to its
clock input makes a transition from 0 to 1.
The S-R inputs control the state of the FF in the same manner as described
earlier for the NOR gate latch, but the FF does not respond to these inputs
until the occurrence of the PGT of the clock signal.
When S =1 and R =0, Q output goes HIGH on the triggering edge of the
clock pulse, and the FF is SET. When S =0 and R =1, Q output goes LOW
on the triggering edge of the clock pulse, and the FF is RESET.
When both S & R are 0, the output doesn’t change from its prior state. An
invalid condition exist when both S & R are 1.
Habtamu M. Digital Logic Design April 10, 2023 34 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

(a) Clocked S-R FF that responds only to the PG edge of a clock pulse; (b)
Function table; (c) Typical wave forms.
The S=R=1 condition should not be used because it results in an
ambiguous condition.
Habtamu M. Digital Logic Design April 10, 2023 35 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

It should be noted from these wave forms that the FF is not af-
fected by the NGTs of the clock pulses.
Also, note that the S and R levels have no effect on the FF, except
upon the occurrence of a PGT of the clock signal.
The S and R inputs are synchronous control inputs; they control
which state the FF will go to when the clock pulse occurs.
The CLK input is the trigger input that causes the FF to change
states according to what the S and R inputs are when the active
clock transition occurs.

Habtamu M. Digital Logic Design April 10, 2023 36 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

A clocked S-R flip-flop that triggers on the NGT at its CLK input.
The small circle and triangle on the CLK input indicates that this
FF will trigger only when the CLK input goes from 1 to 0.
This FF operates in the same manner as the positive-edge FF ex-
cept that the output can change states only on the falling edge of
the clock pulses (points b, d, f, h, and j in the above Figure).
Both P-edge and N-edge triggering FFs are used in digital systems.

Figure: Clocked S-R flip-flop that triggers only on NGTs.

Habtamu M. Digital Logic Design April 10, 2023 37 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Example: determine the waveform of Q and Q’ output of S-R flip

flop for the inputs given below. Assume the flip flop was initially
RESET.

Habtamu M. Digital Logic Design April 10, 2023 38 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clocked J-K Flip-Flop

Clocked J-K FF that is triggered by the PG edge of the clock signal.

The J & K inputs control the state of the FF in the same ways as the S & R
inputs do for the clocked S-R FF except for one major difference: the
J=K=1 condition does not result in an ambiguous output.

For this 1, 1 condition, the FF will always go to its opposite state upon
the positive transition of the clock signal. This is called the toggle mode
of operation.

In this mode, if both J and K are left HIGH, the FF will change states
(toggle) for each PGT of the clock.

Habtamu M. Digital Logic Design April 10, 2023 39 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clocked J-K FF that responds only to the positive edge of the clock; with
functional truth table and wave forms.
Note from these wave forms that the FF is not affected by the NG edge
of the clock pulses.
Also, the J & K input levels have no effect except upon the occurrence
of the PGT of the clock signal. The J and K inputs by themselves cannot
cause the FF to change states.
Habtamu M. Digital Logic Design April 10, 2023 40 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

A clocked J-K FF that triggers on the NG clock-signal transitions.

This FF operates in the same manner as the positive-edge FF except that

the output can change states only on NG clock-signal transitions (points
b, d, f, h, and j).

The J-K FF is much more versatile than the S-R FF because it has no am-
biguous states.

The J=K=1 condition, which produces the toggling operation, finds exten-
sive use in all types of binary counters.

Habtamu M. Digital Logic Design April 10, 2023 41 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Clocked D Flip-Flop
A clocked D FF that triggers on a PGT. Unlike the S-R and J-K FFs, this FF
has only one synchronous control input, D, which stands for data.

The operation of the D FF is very simple: Q will go to the same state that
is present on the D input when a PGT occurs at CLK.

In other words, the level present at D will be stored in the FF at the instant
the PGT occurs.

Habtamu M. Digital Logic Design April 10, 2023 42 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Assume that Q is initially 1.

When the first PGT occurs at

point ’a’, the D input is 0; thus, Q
will go to the 0 state.

Even though the D input level changes between points ’a’ and ’b’, it has
no effect on Q; Q is storing the 0 that was on D at point ’a’.
When the PGT at ’b’ occurs, Q goes 1 b/c D is 1 at that time. Q stores this
1 until the PGT at point ’c’ causes Q to go 0 b/c D is 0 at that time.
Q is goes to 1 at ’d’ b/c D is 1. Note that Q stays 1 at point e b/c D is still 1.
Q can change only when a PGT occurs, the D input has no effect b/n PGTs.
A negative-edge-triggered D FF operates in the same way just described
except that Q will take on the value of D when a NGT occurs at CLK.
Habtamu M. Digital Logic Design April 10, 2023 43 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

T Flip Flop
When T=0, the FF does hold. i.e. Q is kept the same as it was before the
clock edge.
When T=1, the FF does toggle. i.e. the output Q is negated after the clock
edge, compared to the value before the clock edge.

Figure: Truth Table

Figure: Characteristics Table

Habtamu M. Digital Logic Design April 10, 2023 44 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

Asynchronous Inputs
For the clocked FFs that we have been studying, the SR, JK, and D inputs
have been referred to as control inputs.These inputs are also called syn-
chronous inputs.
Most clocked FFs also have one or more asynchronous inputs that oper-
ate independently of the synchronous inputs and clock input.
These asynchronous inputs can be used to set the FF to the 1 state or
clear (reset) the FF to the 0 state at any time, regardless of the conditions
at the other inputs.
Stated in another way, the asynchronous inputs are override inputs, which
can be used to override all the other inputs in order to place the FF in one
state or the other.
A JK FF with two asynchronous inputs designated as PRESET and CLEAR.
These are active-LOW inputs, as indicated by the bubbles on the FF sym-
bol.
Habtamu M. Digital Logic Design April 10, 2023 45 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Flip Flops

PRE= CLR=1. The asynchronous inputs are inactive & the FF is free to
respond to the JK, & CLK inputs; i.e. the clocked operation can take place.
PRE=0; CLR=1. The PRE is activated and Q is immediately set to 1 no
matter what conditions are present at the JK, and CLK inputs.
PRE=1; CLR=0. The CLR is activated and Q is immediately cleared to 0
independent of the conditions on the JK, or CLK inputs.
PRE = CLR=0. This condition should not be used because it can result in
an ambiguous response.
Habtamu M. Digital Logic Design April 10, 2023 46 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
counters

Part II:
I Counters
F Asynchronous counter
F Synchronous counter
I Shift Register
F Serial in/serial out (SISO)
F Serial in/parallel out (SIPO)
F Parallel in/serial out (PISO)
F Parallel in/parallel out (PIPO)
I Shift Register counter
F Ring Counter
F Johnson Counter

Habtamu M. Digital Logic Design April 10, 2023 47 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Counters
Counter is a digital device used to count the number of pulses and it can
also used as a frequency divider.
A sequential circuit that goes through a prescribed sequence of states
upon the application of input pulses is called a counter.
The input pulses may be clock pulses, or they may originate from some
external source and may occur at a fixed interval of time or at random.
FF can be connected together to perform counting operation. Such a
group of FF is a counter.
The number of FF used & the way in which they are connected determines
the number of states (called the modulus) & also the specific sequence
of states that the counter goes through during each complete cycle.
The sequence of states may follow the binary number sequence or any
other sequence of states.
Habtamu M. Digital Logic Design April 10, 2023 48 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
counters

A counter that follows the binary number sequence is called a binary

counter.

An n-bit binary counter consists of ”n” FFs and can count in binary from
0 through 2n - 1

Counters are classified in to two broad categories according to the way

they are clocked: Asynchronous and Synchronous.
I In Asynchronous counters, commonly called ripple counter the first
FF is clocked by the external clock pulse and then each successive FF
is clocked by the output of the preceding FF.
I In synchronous counters, the clock input is connected to all of the
FFs so that they are clocked simultaneously.

Habtamu M. Digital Logic Design April 10, 2023 49 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Asynchronous/Ripple Counter
The term Asynchronous refers to events that do not have a fixed time
relation ship with each other, & generally don’t occur at the same time.

In Asynchronous counter the FF with in the counter do not change states

at exactly the same time because they do not have a common clock pulse.

Asynchronous counter are commonly referred to as ripple counter be-

cause the effect of the input clock pulse is first “felt” by first FF (FF0).

Cannot get to the second FF (FF1) immediately because of the propaga-

tion delay through FF0.

So the effect of an input clock pulse “ripples” through the counter, taking
some time, due to propagation delays, to reach the last FF.

Habtamu M. Digital Logic Design April 10, 2023 50 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Two-bit Asynchronous Binary Counter

The external clock is connected to the clock input of the first FF only.
It changes state at the -ve edge of each CLK pulse, but the next FF changes
only when triggered by the negative edge of the Q output of the first one.

The transition of the input CLK pulse & output Q0 can never occur at ex-
actly the same time.
Eg: As shown; there is some small delay between the CLK, Q0 and Q1
transitions.
Habtamu M. Digital Logic Design April 10, 2023 51 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
counters

Four-bit Asynchronous Counter

Habtamu M. Digital Logic Design April 10, 2023 52 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Asynchronous Decade Counter

The Modulus of a counter is the number of unique states that the counter
will sequence through.
The maximum possible number of states (maximum modulus) of a counter
is 2n where n is the number of FF in the counter.
Counter can be designed to have a number of states in their sequence
that is less than the maximum of 2n . This type of sequence is called a
truncated sequence.
To obtain a truncated sequence, it is necessary to force the counter to
recycle before going through all of its possible states.
When a decade counter is at RESET, the count is equal to 0000.
The NAND gate output is connected to clear input, so it reset all the FF
stage in decade counter. i.e. the pulse after count 9(1001) will again start
the count from count 0 (0000).
Habtamu M. Digital Logic Design April 10, 2023 53 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
counters

Habtamu M. Digital Logic Design April 10, 2023 54 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Synchronous (Parallel) Binary Counter

The term Synchronous refers to events that have a fixed time relationship
with each other.

A Synchronous counter is one in which all FF in the counter are clocked

at the same time by a common clock pulse.

A synchronous counter, in contrast to an Asynchronous counter is one

whose bits change state simultaneously, with no ripple. The only way
we can build such a counter circuit from J-K FF is to connect all the clock
inputs together, so that each and every FF receives the exact same clock
pulse at the exact same time.

How to design synchronous counter

For synchronous counter, all the FFs are using the same clock signal.
Thus, the output change synchronously.

Habtamu M. Digital Logic Design April 10, 2023 55 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Procedure to design synchronous counter are as follow:-

I Step1: Obtain the state diagram
I Step2: Obtain the excitation table using state transition table for any
particular FF (JK or D). Determined number of FF used.
I Step3: Obtain and simplifying the function of each FF input using K-
map
I Step4: Draw the circuit or logic diagram

Example: Design 2-bit synchronous up counter

Step 1: Obtain the state transition diagram

Habtamu M. Digital Logic Design April 10, 2023 56 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Step 2: Obtain the excitation table. Two JK FF are used.

Step 3: Obtain the simplified function using K-map.

Habtamu M. Digital Logic Design April 10, 2023 57 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Step 4: Draw the circuit diagram.

Habtamu M. Digital Logic Design April 10, 2023 58 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Habtamu M. Digital Logic Design April 10, 2023 59 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Habtamu M. Digital Logic Design April 10, 2023 60 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

Cascaded Counters
Cascading means that the last stage output of one counter drives the
input of the next counter.

Counters can be connected in cascade to achieve higher modulus oper-

ation.

A two bit and three bit counters can be cascaded as shown with logic high
condition of all inputs.

MOD number is generally equal to the number of states that the counter
goes through in each complete cycle before it recycles back to its starting
state. The MOD number can be increased simply by adding more FFs to
the counter. That is, MOD number =2N ; where N is the number of FFs
connected in the arrangement.

Habtamu M. Digital Logic Design April 10, 2023 61 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
counters

The final output of the modulus 8 counter Q4 occurs once for every 32
input clock pulses. The over all modulus of the cascade counters is 32.
The overall modulus of cascaded counter is equal to the product of the
individual module.
Habtamu M. Digital Logic Design April 10, 2023 62 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Shift Register
Registers is a group of FF capable of storing one bit of information.
Shift register are constructed using several FF, connected in such away to
store and transfer/ shift digital data.
In digital circuits a shift register is a group of FFs set up in a linear fashion
which have their inputs and output connected together in such a way that
the data are shifted down the line when the circuit is activated.
The various types of registers can be classified according to the manner
in which data can be entered into the register for storage and the manner
in which data are outputted from the register.
The various classifications are listed below:
I Serial in/serial out (SISO)
I Serial in/parallel out (SIPO)
I Parallel in/serial out (PISO)
I Parallel in/parallel out (PIPO)
Habtamu M. Digital Logic Design April 10, 2023 63 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Figure: Different types of data movement

The serial input determines what

goes into the leftmost position
during the shift.

The serial out is taken from the

output of the rightmost FF
Habtamu M. Digital Logic Design April 10, 2023 64 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Serial In/Serial Out (SISO) Shift Registers

The serial in/serial out shift register accepts data serially i.e. one bit at a
time on a single line. It produces the stored information on its out put in
serial form.

data bit come in one a time and leave one at a time ,one FF for each bit
to be handled.

Habtamu M. Digital Logic Design April 10, 2023 65 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

The 4-bit data word’1011’is to be

shift in to a 4-bit shift register.

One shift per clock pulse.

Habtamu M. Digital Logic Design April 10, 2023 66 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Serial In/Parallel Out (SIPO) Shift Registers

Data bits are stored serially(right most bit first), Once the data are stored,
each bit appears on its respective output line, and all bits are available
simultaneously, rather than on a bit by bit basis as with the serial output.
Note that we could also use the Q of the rightmost FF as a serial output.

The group of bits 10110101 is serially shifted in to an 8-bit parallel output

shift register with an initial state of 11100100. After 2 clock pulses, what
is the register contains? 01111001.
Habtamu M. Digital Logic Design April 10, 2023 67 / 75
Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Parallel In/Serial Out (PISO) Shift Registers

The shift register which uses parallel input and generates serial
output is known as the parallel input serial output shift register or
PISO shift register.
For a register with parallel data inputs, the bits are entered simul-
taneously in to their respective stages on parallel lines rather than
on a bit by bit basis on one line as with serial data inputs.
This Shift registers can be used to convert parallel data to serial
form.
The i/p of the second FF is the o/p of the first flip flop.

Habtamu M. Digital Logic Design April 10, 2023 68 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Habtamu M. Digital Logic Design April 10, 2023 69 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Parallel In/Parallel Out (PIPO) Shift Registers

The Parallel In/Parallel Out Shift Registers allows the parallel entry of
data and parallel output of data.

Immediately following the simultaneous entry of all data bits, the bits
appear on the parallel output.

Habtamu M. Digital Logic Design April 10, 2023 70 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Shift Register Counters

Shift register counters is basically a shift register with the serial output
connected back to the serial input to produces special sequences.

These devices are often classified as counter because exhibit a specified

sequence of states.

Two of the most common types of shift register counters

I Ring counter: The simplest shift-register counter is essentially a cir-
culating shift register connected so that the last FF shifts its value
into the first FF.
I Johnson counter: The Johnson counter is constructed exactly like a
normal ring counter except that the inverted output of the last FF is
connected to the input of the first FF.

Habtamu M. Digital Logic Design April 10, 2023 71 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Figure: Ring counter

Number of state = number of FF used, b/c it is special type of counter

Ring counter sequence is; 1000, 0100, 0010, 0001. With one of the pat-
terns as its starting state

Habtamu M. Digital Logic Design April 10, 2023 72 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

Habtamu M. Digital Logic Design April 10, 2023 73 / 75

Digital Logic Design
Introduction About Flip Flop And Latch
Shift Register

The Johnson counter is useful when you need a sequence that changes
by only one bit at a time.it has a limited number of states (2n , where
n=number of stages)
Johnson counter has twice as many stats as bit position. i.e. 3 bit counter
has 6 states & 4 bit has 8 active states.
8 active states of 4 bit Johnson counter is; 1000,1100,1110,1111,0111,
0011, 0001,0000. With one of the patterns as its starting state
The first 5 counter for a 4-bit Johnson counter that is initially cleared are:

Habtamu M. Digital Logic Design April 10, 2023 74 / 75

Digital Logic Design

!! !
OU
K Y
A N
T H
Habtamu M. Digital Logic Design April 10, 2023 75 / 75