Digital Electronics Unit 7

Unit 7 Combinational Circuits – Part I

Structure:
7.1 Introduction
Objectives
7.2 Combinational Circuits
7.3 Adders
7.4 Subtractors
7.5 Parallel adder and Subtractor
7.6 Ripple Carry and Carry Look-Ahead Adders.
7.7 Summary
7.8 Terminal Questions
7.9 Answers

7.1 Introduction
In the last unit, we studied Boolean expressions, their functions and
simplification of Boolean expressions using Karnaugh map and Quine-
McCluskey methods. We know that the digital system which drives the
modern computer can be constructed using the basic gates i.e., AND, OR,
and NOT gates. Also the digital circuits can respond directly to the input
change or remember the present state and combine with input changes to
create a new state. So based on how the digital circuits respond to the
inputs, they are classified into two types: Combinational circuits and
Sequential circuits. Combinational circuits’ outputs depend only on the
current inputs and sequential circuits’ outputs depend on both past and
current inputs. Outputs of sequential circuits can be determined by using the
sequence of inputs over the time. Memory circuits are considered sequential
circuits. Adders which are constructed using gates are considered
combinational circuits. In this unit we will study combinational circuits.
Objectives:
After studying this unit, you should be able to:
 define combinational circuits
 explain the operation of half adder and full adder.
 describe the working of half subtractor and subtractor
 explain working of parallel adder and subtractor
 discuss ripple carry and look-ahead carry adders

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7.2 Combinational Circuits

Combinational circuits are those whose outputs depend only on the current
inputs. Here digital circuits generate a set of outputs from a set of inputs
using Boolean operations. Usually many Boolean functions are
implemented using combinational circuit and each Boolean function
corresponds to a particular output. In a combinational circuit, it is important
to observe that each Boolean function implemented is represented by an
output.
Combinational circuits are used to construct the computer’s Central
Processing Unit (CPU). For example, a set of Boolean functions can be
used to implement an adder circuit. Some of the examples of combinational
circuits are: Adders, Subtractors, multiplexers, demultiplexers, encoders,
and decoders.
The following are some of the characteristics of combinational circuits:
 The output of combinational circuit at any instant of time depends only
on the levels present at input terminals.
 The combinational circuits do not use any memory. The previous state
of input does not have any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number
of outputs.
The figure 7.1 shows the general block diagram of a combinational circuit.

Figure 7.1: Block diagram of a combinational circuit.

The A, B, C…n represent inputs and A’,B’.C’,…..m represent outputs.

Self-Assessment Questions
1. ________________________ circuits are those whose outputs depend
only on the current inputs.
2. CPU stands for ___________________________.
3. Multiplexers are examples for combinational circuits. (State true or
false)
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7.3 Adders
Adders are used to add binary numbers producing sum and carry outputs.
There are two types of single bit adders. They are:
 Half adder
 Full adder.
Half adder
A half adder is a digital circuit which accepts two inputs and performs
addition on them and generates two outputs known as sum(S) and carry(C).
As the carry is not included in the addition, this circuit cannot be used to
perform addition of multibit numbers. The figure 7.2 shows the logic symbol
of half adder.

Figure 7.2: Logic symbol of a half adder.

The table 7.1 shows the truth table for a half adder:
Table 7.1: Truth Table for Half adder

Now from the truth table, we can generate SOP expression for sum and
carry outputs considering the 1’s in their respective colums.
Now, in Sum(s) column, there are two 1’s for input combinations of 01
( A=0,B=1) and 10(A=1,B=0) respectively.

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Since A  B represents the output of a two input XOR gate, Sum is

obtained by XOR gate.
Similarly in Carry(C) column, there is only a single 1 for input combination
10(A=1,B=0). So ouput Carry(C) is given by
Carry (C) = AB
Since AB represents the ouput of a two input AND gate, an AND gate
represents the Carry. So it is evident that we can construct an half adder
circuit by using an XOR gate and an AND gate.
The figure 7.3 shows the logic circuit diagram for Half adder.

Figure 7.3 : Logic circuit diagram for Half adder

Full adder:
A full adder is a digital circuit that performs addition on 3 input bits and
generates outputs known as sum(S) and carry (Cout). The three inputs are
are labelled as inputs A and B, and a carry in input labelled as Cin. The
outputs Sum and Carry are labelled as S and Cout (or Co). Multiple full
adders can be used to perform the addition of multibit (binary) inputs. The
figure 7.4 shows the logic symbol of Full adder and the table 7.2 shows the
truth table for Full adder.

Figure 7.4: Logic symbol of Full adder.

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Table 7.2: Truth table for Full adder

We can get the SOP expressions from the truth table for the outputs Sum
and Carry by considering 1’s in their columns and writing the expressions in
terms of variables A,B and C for the corresponding input combinations.

Similarly, the output, carry (Co) is given by:

The figure 7.5 shows the logic circuit diagram of a Full adder.

Figure 7.5: Logic circuit diagram of Full adder

Full adder using two Half Adders:

Two half adder circuits can be used to implement a full adder circuit, the two
inputs A and B are connected to one half adder and its output sum is

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connected as input to the second half adder. Carry in is the other input to
the second half adder and two carry outputs are ORed. The Boolean
function for S can be expressed as XOR of three inputs A, B, Ci and a
majority function of A, B, and Ci is the Carry out equation. Sum of three one-
bit numbers will be the output of the full adder circuit.
The figure 7.6 shows the logic diagram of a full adder using two Half adders.

Figure 7.6: Logic diagram of a Full adder using two Half adders

Full adder using NAND or NOR logic.

The full adder can be made using NAND or NOR logic. These schemes are
universally accepted and their circuit diagrams are shown in figure 7.7 and
7.8 respectively.

Figure 7.7: Full adder using NAND Logic

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The full adder can be made using a NOR logic also. These schemes are
universally accepted and their circuit diagrams are shown in figure 7.8.

Figure 7.8: Full adder using NOR Logic

Activity 7:
Draw the full adder circuits using NAND gates and write the expressions
and simplify them.

Self-Assessment Questions
4. A ______________ adder is a digital circuit which accepts two inputs
and performs addition on them and generates two outputs known as
sum(S) and carry(C).
5. A full adder is a digital circuit which can handle carry input. (State true
or false)

7.4 Subtractors
Subtractor circuits take two binary numbers as input and subtract one binary
number input from the other binary number input. Similar to adders, it gives
out two outputs, difference and borrow (carry-in the case of Adder). There
are two types of subtractors.
 Half Subtractor
 Full Subtractor
Half Subtractor
The half-subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend)

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and two outputs D (difference) and B (borrow). The logic symbol and truth
table are shown in figure 7.9.

Figure 7.9: Half subtractor (a) Logic Symbol (b) Truth table

Now the SOP expression for the outputs- ‘difference’ and ‘borrow’ -are as
follows.

So the difference is implemented by a two input XOR gate and the borrow
by a NOT gate and a AND gate. Figure 7.10 shows the logic diagram of an
Half subtractor.

Figure 7.10: Logic diagram of Half Subtractor

Full Subtractor
The Full subtractor is a combinational circuit which is used to perform
subtraction of three bits. It has three inputs, A (minuend) and B

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(subtrahend) and the third input called Borrow-in and two outputs D
(difference) and B (borrow). The logic symbol and truth table are shown in
figure 7.11.

Figure 7.11: Full subtractor (a) Logic Symbol (b) Truth table

The SOP expressions for the outputs are:

D = A'B'Bin + A'BBin' + AB'Bin' + ABBin
= (A'B' + AB)Bin + (A'B + AB')Bin'
= (A B)'Bin + (A B)Bin'
= A B Bin
Bout = A'.B + B.Bin + A'.Bin
The figure 7.12 shows the logic circuit diagram for a Full adder.

Figure 7.12: Logic diagram of a Full Subtractor

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The figure 7.13 shows the the logic symbol of a Full subtractor using two
half subtractors.

Figure 7.13: Logic symbol of Full subtractor using two half subtractors.

The figure 7.14 shows the the logic diagram of a Full subtractor using two
half subtractors.

Figure 7.14: Logic diagram of Full subtractor using two half subtractors.

7.5 Parallel adder and Subtractor

There are digital circuits which can add or subtract binary numbers that
involve more than one bit at a time. This means they can perform multibit
operation. Now let us study some of these digital circuits.
Parallel adder:
A parallel binary adder adds n multibit number in parallel. Hence the name
parallel adder. The figure 7.15 shows the symbol of Parallel adder.

Figure 7.15: Logic symbol of Parallel adder

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For the addition of two n bits of data, n numbers of full adders can be
cascaded. We know that to add a binary number with more than one bit we
use a full adder. A single Full adder can add three bits, minuend,
subtrahend and a carry in. So full adders are used in the construction of
parallel adders.
4 bit Parallel adder: The parallel adder that adds two four bit numbers is
called 4 bit parallel adder.
The figure 7.16 shows a four bit parallel adder. This adder adds two binary
numbers of 4 bits each. So n=4 here.

Figure 7.16: Block diagram of a 4 bit parallel adder

Consider two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 which are to be
added with a carry input Cin. We can do this by cascading four full adder
circuits as shown in figure 7.16. The least significant bits A0, B0 and Cin are
added to the produce sum output S0 and carry output C1. Carry output C1 is
then added to the next significant bits A1 and B1 producing sum output S1
and carry output C2. C2 is then added to A2 and B2 and so on. Thus finally
producing the four-bit sum output S3S2S1S0 and final carry output Cout.
Since Cout=C4=S4. The final sum is S4S3S2S1S0. This type of four-bit binary
adder is commercially available in an IC package.
For example, consider the two 4 bit binary numbers 0111 and 1111. We
assume previous carry = 0.
Now put the binary value 0111 to A3A2A1A0 (i.e. A3=0, A2=1, A1=1 and
A0=1 ) & 1111 to B3B2B1B0 terminals. Then we have the following operation.

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Sum of two binary numbers 7 and 15 from the above table

is S4S3S2S1S0 = 10110 (In Binary) = 22 (decimal). Note that C4=S4.
Even though this is a simple adder and can be used to add unrestricted bit
length numbers, it is however not very efficient when large bit numbers are
used.
Parallel Binary Subtractor:
A parallel binary subtractor subtracts two n bit binary numbers in parallel.
Parallel binary subtractor can be implemented by cascading several full
subtractors.
4 bit Parallel Binary Subtractor: A parallel binary subtractor which
subtracts two 4 bit binary numbers in parallel is called 4 bit parallel binary
subtractor. We can use a 4-bit binary adder to obtain the 4-bit binary
subtraction.
The figure 7.17 shows the block diagram of a 4-bit parallel binary subtractor,
which subtracts 4-bit B3B2B1B0 from 4-bit A3A2A1A0. It has 4-bit difference
output D3D2D1D0 with borrow output Bout.

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Figure 7.17: The block diagram of a 4-bit serial subtractor

A serial subtractor can be obtained by converting the serial adder using the
2's complement system. The number to be subtracted (i.e. subtrahend) B
must be 2's complemented before it is added to the minuend A. The
subtrahend (B) is first passed through inverters to obtain its 1's complement.
And carry 1 is added to obtain 2’s complement. The 4-bit adder then adds A
and 2's complement of B to produce the subtraction. S3S2S1S0 represent the
result of binary subtraction (A-B) and carry output Cout represents the
polarity of the result. If A > B then Cout =0 indicating the result of binary
form (A-B) as positive and when Cout = 1, the result is negative and is in the
2's complement form.
Four-bit Binary Parallel Adder/Subtractor
Due to the propertyof the 4-bit binary adder that it can perform the
subtraction operation with external inverter gates, a single combinational
circuit may be developed that can perform addition as well as the
subtraction with the help of a control bit. Figure 7.18 shows this type of
arrangement that demonstrates dual-purpose combinational logic circuit.

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Figure 7.18: Four-bit Binary Parallel Adder/Subtractor

XOR gates are used at addend or subtrahend bits when one of the inputs of
the XOR gate is connected to the ADD/SUBTRACT terminal, which is acting
as control terminal. The same terminal is connected to Cin. When this
terminal is connected to logic 0 the combinational circuit behaves like a 4-bit
full adder, as at this instant Cin is logic low and XOR gates are acting as
buffers whose outputs are an uncomplemented form of inputs. If logic 1 is
applied to the ADD/SUBTRACT terminal, the XOR gates behave like
INVERTER gates and data bits are complemented. The 4-bit adder now
performs the addition operation of data A3A2A1A0 with complemented form
of data B3B2B1B0 as well as with a single bit 1, as Cin is now logic 1. This
operation is identical to a subtraction operation using 2’s complment.
Self-Assessment Questions
6. The _____________ is a combinational circuit which is used to perform
subtraction of two bits.
7. The _____________ is used to perform subtraction of three bits, input
A (minuend), input B (subtrahend) and third input called __________
and produces two outputs D (difference) and B (borrow).
8. The _____________ adder that adds two four bit numbers is called
4 bit parallel adder.
9. A parallel binary subtractor which subtracts two n bit binary numbers in
parallel is called a full binary subtractor. (State true or false)
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7.6 Ripple Carry and Look-Ahead Carry Adders

Here we will study Ripple carry adder and look ahead carry adder.
Ripple carry adder (RCA):
We know that it is also possible to create a logical circuit using multiple full
adders to add N-bit binary numbers. Each full adder inputs carries input Cin,
which is the Cout of the previous adder. This kind of adder is a Ripple Carry
Adder.
A ripple carry adder is a logic circuit in which the carry-out of each full adder
is the carry in of the succeeding next most significant full adder. It is called a
ripple carry adder because each carry bit gets rippled into the next stage. In
a ripple carry adder the sum and carry out bits of any half adder stage is not
valid until the carry in of that stage occurs. Propagation delay inside the
logic circuitry is the reason behind this. Propagation delay is the time
elapsed between the application of an input and occurrence of the
corresponding output. Consider a NOT gate, When the input is “0″ the
output will be “1″ and vice versa. The time taken for the NOT gate’s output
to become “0″ after the application of logic “1″ to the NOT gate’s input is the
propagation delay here. Similarly the carry propagation delay is the time
elapsed between the application of the carry in signal and the occurrence of
the carry out (Cout) signal.
The ripple carry adder is constructed by cascading full adders (FA) blocks in
series. One full adder is responsible for the addition of two binary digits at
any stage of the ripple carry. The carryout of one stage is fed directly to the
carry-in of the next stage. A number of full adders may be added to the
ripple carry adder or ripple carry adders of different sizes may be cascaded
in order to accommodate binary vector strings of larger sizes. For an n-bit
parallel adder, it requires n full adders. One of the examples of ripple carry
adder is the 4 bit parallel adder shown in the figure 7.16.
One of the most serious drawbacks of this adder is that the delay increases
linearly with the bit length. As mentioned before, each full adder has to wait
for the carry out of the previous stage to output steady-state result.
Therefore even if the adder has a value at its output terminal, it has to wait
for the propagation of the carry before the output reaches a correct value as
shown in figure 7.19.

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Figure 7.19: Carry Propagation in Carry Ripple Adder

The addition of A3 and B3 cannot reach steady state until C3 becomes

available. In turn, C3 has to wait for C2, and so on down to C1. If one full
adder takes TFA seconds to complete its operation, the final result will reach
its steady-state value only after 4.TFA seconds.
Generally speaking, the worst-case delay of the RCA is when a carry signal
transition ripples through all stages of adder chain from the least significant
bit to the most significant bit, which is approximated by:
t = (n-1)tc +ts
Where tc is the delay through the carry stage of a full adder, and ts is the
delay to compute the sum of the last stage. The delay of ripple carry adder
is linearly proportional to n, the number of bits. Therefore the performance
of the ripple carry adder is limited when n grows bigger. The advantages of
the ripple carry adder are lower power consumption as well as a compact
layout giving smaller chip area. To design a larger adder ripple carry adders
are cascaded.
Carry Look Ahead adders (CLA)
We have observed that in case of ripple-carry adder (RCA), the transition on
the carry signal ripples from one stage to the other (i.e from one full adder to
other full adder) to effect the final value of the MSB of the sum. This ripple-
carry results in the delay in adder and this increases linearly with the
number of bits in the adder. For large adders, this linear delay becomes
prohibitive.

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Waiting for carries to ripple through an adder can significantly slow it down.
The carry look-ahead adder solves this problem by calculating the carry
signals in advance, based on the input signals. The result is a reduced carry
propagation time.
Carry look ahead adders do not wait for the carry to ripple through the
circuit. The adder computes each output bit in the sum directly from the
inputs using a fixed number of levels of logic. The logic gates are used to
look at the lower order bits of augend and addend to see if a higher order
carry is to be generated. It uses two functions- carry generate and carry
propagate. So the easiest way to think of how a carry look ahead adder
works is in terms of "generate (g)" and "propagate (p)".
Now consider the full adder circuit as shown in figure 7.20.

Figure 7.20: Full adder circuit.

Adding two bits, Ai and Bi that are both 1 will always generate a carry,
regardless of any of the less significant bits. Adding a 1 and a 0 or two 1's
will result in a carry out, or propagate the carry, if the carry in is a 1. So for
any bits Ai and Bi the equations for generate (G) and propagate (P) are:
Pi = Ai Bi Carry generate
Gi = AiBi Carry propagate
Adding bits Ai and Bi will result in a carry out if the addition generates a
carry or if it propagates a carry and there is a carry in from the addtion of
bits Ai-1 and Bi-1. In other words:
Ci+1 = Gi + Pi Ci
Of course the sum of adding the two bits is:
Si = Ai XOR Bi XOR Ci i.e. Si= Ai r Bi Ci
which can be shown to be equivalent to:
Si = Pi Ci

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To find the output Si we just need to know Ci in terms of A, B, and C0. We

can find Ci by starting with C1 and substituting into the above equation for
Ci.
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
These expressions show that C2, C3 and C4 do not depend on its previous
carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as
C0 is computed, C4 can reach steady state. The same is also true for C2 and
C3.
The general expression is
Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 …. P1P0C0.
As you can see C1 and C2 do not depend on any intermediate carrys.
However, the number of terms in the equation for Ci grows very quickly
making carry look ahead adders very expensive for a large number of bits.
The limiting factor on carry in terms of A, B and C0 look ahead adders is
generally the number of inputs any one gate can have.
A carry signal will be generated in two cases:
1) If both bits Ai and Bi are 1
2) If either Ai or Bi is 1 and the carry-in Ci is 1.
Carry look-ahead adder’s structure can be divided into three parts: the
propagate/generate generator figure 7.21, the sum generator figure 7.22
and the carry generator figure 7.23.

.
Figure 7.21: Propagate /Generate generator

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Figure 7.22: Sum Generator

Figure 7.23: Look-Ahead Carry generator

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The size and fan-in of the gates needed to implement the Carry-Look-ahead
adder is usually limited to four, so 4-bit Carry-Look ahead adder is designed
as a block. The 4-bit Carry Look Ahead adder block diagram is shown in
figure 7.24.

Figure 7.24: Block diagram of 4-bit Carry Look Ahead adder

In practice, it is not possible to use the CLA to realize constant delay for the
wider-bit adders since there will be a substantial loading capacitance, and
hence larger delay and larger power consumption. The CLA has the fastest
growing area and power requirements with respect to the bit size. Speed
also will drop with increase in bit size. So other techniques may be used.

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Self-Assessment Questions
10. A ripple carry adder is called so because each carry bit gets rippled
into the next stage. (State true or false)
11. One of the most serious drawbacks of this adder is that the delay
increases linearly with the _____________.
12. ________________________adders do not wait for the carry to ripple
through the circuit.

Glossary:
Adders: A digital circuit used to add binary numbers producing sum and
carry outputs.
Half adder: A digital circuit that accepts two inputs and performs addition on
them and generates two outputs known as sum(S) and carry(C).
Full adder: A digital circuit that performs addition on 3 input bits and
generates outputs known as sum(S) and carry (Cout).
Subtractor: A digital circuit that accepts two binary numbers as inputs and
subtracts one binary number from the other binary number.
Full subtractor: A digital circuit that is used to perform subtraction of three
bits namely inputs, A (minuend) and B (subtrahend) and a third input called
Borrow-in and produces two outputs D (difference) and B (borrow).
Parallel binary adder: An adder that adds two n bit binary numbers in
parallel.
Parallel binary subtractor: A subtractor that subtracts two n bit binary
numbers in parallel.
Ripple carry adder: A logic circuit in which the carry-out of each full adder
is the carry in of the succeeding next most significant full adder.
Carry look ahead adder: A digital circuit that do not wait for the carry to
ripple through the circuit and computes each output bit in the sum directly
from the inputs using a fixed number of levels of logic.

7.7 Summary
Let us recapitulate the important concepts discussed in this unit:
 Combinational circuits are those whose outputs depend only on the
current inputs.

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 Some of the examples of combinational circuits are: Adders,

Subtractors, multiplexers, demultiplexer, encoders. decoders etc.
 A half adder is a digital circuit which accepts two inputs and performs
addition on them and generates two outputs known as sum(S) and
carry(C).
 A full adder is a digital circuit that performs addition on 3 input bits and
generates outputs known as sum(S) and carry (Cout).
 The half-subtractor is a combinational circuit that subtracts two bits. And
produces two outputs D (difference) and B (borrow).
 The Full subtractor is a combinational circuit which is used to perform
subtraction of three bits.
 A parallel binary adder adds n multibit number in parallel.
 The parallel adder that adds two four bit numbers is called 4 bit parallel
adder.
 A parallel binary subtractor which subtracts two 4 bit binary numbers in
parallel is called 4 bit parallel binary subtractor.
 A ripple carry adder is a logic circuit in which the carry-out of each full
adder is the carry in of the succeeding next most significant full adder. It
is called a ripple carry adder because each carry bit gets rippled into the
next stage.
 One of the most serious drawbacks of this adder is that the delay
increases linearly with the bit length.
 Carry look ahead adders do not wait for the carry to ripple through the
circuit. The adder computes each output bit in the sum directly from the
inputs using a fixed number of levels of logic.

7.8 Terminal Questions

1. What is a combinational circuit? Explain.
2. What is a half adder? Explain the operation with the help of a truth table
and circuit diagram.
3. Explain the operation of full adder.
4. Discuss subtractors.
5. What is a parallel adder? Explain the operation of a 4 bit parallel adder.
6. Describe the operation of Carry Look-Ahead Adders.

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7.9 Answers
Self-Assessment Questions
1. Combinational
2. Central Processing Unit
3. True
4. Half
5. True
6. Half subtractor
7. Full subtractor, Borrow in
8. Parallel
9. False
10. False
11. Bit length
12. Carry look ahead

Terminal Questions
1. Combinational circuits are those whose outputs depend only on the
current inputs. Refer to section 7.2.
2. A half adder is a digital circuit which accepts two inputs and performs
addition on them and generates two outputs known as sum(S) and
carry(C). Refer to section 7.3.
3. A full adder is a digital circuit that performs addition on 3 input bits and
generates outputs known as sum(S) and carry (Cout). The three inputs
are are labelled as inputs A and B, and a carry in input labelled as Cin.
Refer to section 7.3.
4. Subtractors are circuits which take two binary numbers as input and
subtract one binary number input from the other binary number input.
and gives out two outputs, difference and borrow. Refer to section 7.4.
5. A parallel binary adder adds n multibit number in parallel. The parallel
adder that adds two four bit numbers is called 4 bit parallel adder. Refer
to section 7.5 for more details.
6. Carry look ahead adders do not wait for the carry to ripple through the
circuit. The adder computes each output bit in the sum directly from the
inputs using a fixed number of levels of logic. Refer to section 7.6 for
more details.

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