LTSPICE SIMULATION

Question 1 PMOS (Case 1)

Figure 1.1: PMOS Circuit Configuration

Figure 1.2: PMOS Circuit Simulation Result

Figure 1.3: PMOS Circuit Simulation Error Log

Question 1 PMOS (Case 2)

Figure 1.4: PMOS Circuit Configuration

Figure 1.5: PMOS Circuit Simulation Result

Figure 1.6: PMOS Circuit Simulation Error Log

 Table 1: PMOS Characteristics
ID ID Mode of
VGS(V) VDS (V) VB(V) W/L
(calculation) (simulation) operation
-0.9 -1.5 1 1.5/0.25 8.3120 µA 8.3106 µA Pinch-off
saturation
-1.2 -2 3 0.75/0.25 5.5409 µA 5.54 µA Pinch-off
saturation
 LTSPICE SIMULATION
Question 1 NMOS (Case 1)

Figure 1.7: NMOS Circuit Configuration

Figure 1.8: NMOS Circuit Simulation Result

Figure 1.9: NMOS Circuit Simulation Error Log

Question 1 NMOS (Case 2)

Figure 1.10: NMOS Circuit Configuration

Figure 1.11: NMOS Circuit Simulation Result

Figure 1.12: NMOS Circuit Simulation Error Log

 Table 2: NMOS Characteristics
ID ID Mode of
VGS(V) VDS (V) VB(V) W/L
(calculation) (simulation) operation
1.6 0.5 0 2.5/0.25 529 µA 529 µA Linear
1.2 1.4 -1 1.2/0.25 90.9037 µA 90.8955 µA Pinch-off
saturation
 LTSPICE SIMULATION
Question 2 PMOS (Level 1)

Figure 2.1: PMOS Circuit Configuration

Figure 2.2: PMOS Circuit Simulation Result

 Figure 2.3: PMOS Circuit Simulation Error Log

Figure 2.4: PMOS Circuit Simulation for Ids vs Vds

Figure 2.5: PMOS Circuit Simulation for Ids vs Vgs

Question 2 PMOS (Level 49)

Figure 2.6: PMOS Circuit Configuration

Figure 2.7: PMOS Circuit Simulation Result

 Figure 2.8: PMOS Circuit Simulation Error Log

Figure 2.9: PMOS Circuit Simulation for Ids vs Vds

 Figure 2.10: PMOS Circuit Simulation for Ids vs Vgs

Table 3: PMOS Characteristics

Level 1 BSIM3 Mode of
VG(V) VD (V) VS(V) W/L operation
ID ID ID
(calculation) (simulation) (simulation)
-0.3 -1.5 -0.9 5/3 0A 1.21 pA 610 fA OFF/cut-off
 LTSPICE SIMULATION
Question 2 NMOS (Level 1)

Figure 2.11: NMOS Circuit Configuration

Figure 2.12: NMOS Circuit Simulation Result

 Figure 2.13: NMOS Circuit Simulation Error Log

Figure 2.14: NMOS Circuit Simulation for Ids vs Vds

Figure 2.15: NMOS Circuit Simulation for Ids vs Vgs

Question 2 NMOS (Level 49)

Figure 2.16: NMOS Circuit Configuration

Figure 2.17: NMOS Circuit Simulation Result

 Figure 2.18: NMOS Circuit Simulation Error Log

Figure 2.19: NMOS Circuit Simulation for Ids vs Vds

 Vgs

Figure 2.20: NMOS Circuit Simulation for Ids vs Vgs

Table 4: NMOS Characteristics

Level 1 BSIM3 Mode of
VG(V) VD (V) VS(V) W/L operation
ID ID ID
(calculation) (simulation) (simulation)
1.6 2 0.5 5/1 140.67 µA 140.674 µA 190.697 µA Pinch-off
saturation
 LTSPICE SIMULATION
Question 3a CMOS (Voltage Transfer Characteristic)

Figure 3.1: CMOS Circuit Configuration for Voltage Transfer Characteristic (VTC)

Figure 3.2: CMOS Circuit Simulation Result for Voltage Transfer Characteristic (VTC)
Question 3a CMOS (Transient Analysis: tpHL)

Figure 3.3: CMOS Circuit Configuration for Transient Analysis

Figure 3.4: CMOS Circuit Simulation Result for tpHL

Figure 3.5: CMOS Circuit Simulation Result for tpHL

Question 3a CMOS (Transient Analysis: tpLH)

Figure 3.6: CMOS Circuit Configuration for Transient Analysis

Figure 3.7: CMOS Circuit Simulation Result for tpLH

Figure 3.8: CMOS Circuit Simulation Result for tpLH

 Table 5: CMOS Characteristics
Vm TpHL TpLH
(W/L)p (W/L)n (sim)
(sim) (sim)
1.2097/0.25 0.375/0.25 1.2554 V 87.1429 ps 158.6939 ps

Question 3a CMOS (Noise Margin)

Figure 3.9: CMOS Circuit Simulation Result for VIH at slope -1

Figure 3.10: CMOS Circuit Simulation Result for VIL at slope -1

From Figure 3.9 and Figure 3.10, VIH ≈ 1.3V and VIL ≈ 1.2V
NMH = 2.5V – 1.3V = 1.2V
NML = 1.2 – 0 = 1.2V
∴ Proven that CMOS was operated in equal noise margin
 Table 6: CMOS Parameters Comparison
VIH VIH VIL VIL
(W/L)p (W/L)n (cal) (sim)
(sim) (cal)
1.2097/0.25 0.375/0.25 1.3214 V 1.3V 1.1786 V 1.2V

Table 7: CMOS Noise Margin Comparison

NMH NMH NML NML
(W/L)p (W/L)n (cal) (sim)
(sim) (cal)
1.2097/0.25 0.375/0.25 1.1786 V 1.2 V 1.1786 V 1.2 V
Question 3b CMOS Transistor Ratio Modification (Voltage Transfer Characteristic)

Figure 3.11: CMOS Circuit Configuration for Voltage Transfer Characteristic (VTC)

Figure 3.12: CMOS Circuit Simulation Result for Voltage Transfer Characteristic (VTC)
Question 3b CMOS Transistor Ratio Modification (Transient Analysis: tpHL)

Figure 3.13: CMOS Circuit Configuration for Transient Analysis

Figure 3.14: CMOS Circuit Simulation Result for tpHL

 Figure 3.15: CMOS Circuit Simulation Result for tpHL
Question 3b CMOS Transistor Ratio Modification (Transient Analysis: tpLH)

Figure 3.16: CMOS Circuit Configuration for Transient Analysis

Figure 3.17: CMOS Circuit Simulation Result for tpLH

 Figure 3.18: CMOS Circuit Simulation Result for tpLH

Table 7: CMOS Characteristics

Vm TpHL TpLH
(W/L)p (W/L)n (sim)
(sim) (sim)
0.7125/0.25 0.375/0.25 1.1585 V 63.2653 ps 227.5034 ps

Question 3b CMOS Transistor Ratio Modification (Noise Margin)

Figure 3.19: CMOS Circuit Simulation Result for VIH at slope -1

 Figure 3.20: CMOS Circuit Simulation Result for VIL at slope -1

From Figure 3.9 and Figure 3.10, VIH ≈ 1.2V and VIL ≈ 1.1V
NMH = 2.5V – 1.2V = 1.3V
NML = 1.1 – 0 = 1.1V
∴ CMOS was not operated in equal noise margin anymore

Table 8: CMOS Parameters Comparison

VIH VIL
(W/L)p (W/L)n (sim)
(sim)
0.7125/0.25 0.375/0.25 1.2V 1.1V

Table 9: CMOS Noise Margin Comparison

NMH NML
(W/L)p (W/L)n (sim) (sim)
0.7125/0.25 0.375/0.25 1.3V 1.1 V
 Question 3a and 3b Relationship between Wp, switching voltage, noise margin and Propagation delay
of CMOS inverter discussion.

Table 10: CMOS Parameters Comparison across varied Wp

VIH VIL NMH NML TpHL TpLH
(W/L)p (W/L)n (sim) (sim) (sim) (sim) (sim) (sim)
1.2097/0.25 0.375/0.25 1.3V 1.2V 1.2 V 1.2V 87.1429 ps 158.6939 ps
0.7125/0.25 0.375/0.25 1.2V 1.1V 1.3V 1.1 V 63.2653 ps 227.5034 ps

Decreasing the width of the PMOS transistor, Wp in a CMOS inverter shifts the switching
voltage higher as the weaker PMOS transistor becomes less effective at pulling the output high. This
will lead to higher input voltages required to switch the output. This affects the inverter's high input
voltage, VIH and low input voltage, VIL thresholds by increasing VIH and decreasing VIL. Consequently,
the Noise Margin High, NMH may decrease due to the reduced capability of the PMOS to maintain a
high output in the presence of noise. Meanwhile, the Noise Margin Low NML may improve as the
inverter becomes less sensitive to low input noise. In this simulation, rounding error may occur to VIH,
NMH and NML since the voltage different in all of these parameters for both larger and smaller Wp
transistor was not so significant and thus can be ignored.

Additionally, decreasing Wp increases the rise time delay, tpLH because the PMOS
transistor charges the output capacitance more slowly. In contrast, it can decrease the fall time delay
tpHL as the NMOS transistor can discharge the output capacitance more effectively. Thus, careful
adjustment of Wp is crucial to maintaining balanced noise margins and minimizing overall propagation
delay.
Question 3c CMOS Speed Optimization Method Comparison
Table 11: CMOS Speed Optimization Method Comparison
Aspect Transistor Ratio Beta Scaling Factor Inverter Chain
Description Adjusting the width-to- Reducing the physical Using a series of
length ratio (W/L) of the dimensions of the inverters to drive a load
PMOS to NMOS transistors transistors to decrease capacitance efficiently.
to balance driving strength capacitance and improve
and speed. speed.
Primary Achieve optimal switching Reduce overall gate delay Minimize delay in
Objective speed by balancing the by minimizing driving large capacitive
strength of PMOS and capacitance and loads by using multiple
NMOS transistors. resistance. stages.
Speed Moderate: Properly sized Significant: Smaller High: Reduces delay in
Improvement transistors reduce delay but transistors switch faster driving large loads by
can be limited by physical due to reduced breaking down the load
constraints and power capacitance and shorter into smaller stages with
dissipation. channel length. optimal sizing.

Power Can increase due to larger Can decrease due to lower Increases due to the
Consumption PMOS or NMOS capacitance and shorter additional inverters, but
transistors leading to higher channels, but leakage the power is managed
dynamic power current might increase better compared to a
consumption. with aggressive scaling. single large inverter.

Area Impact Requires more silicon area Decreases area due to Increases area due to
if larger transistors are smaller transistors, but the added inverters in
used. highly scaled devices the chain
might face reliability
issues.
Complexity Low: Only requires Medium to High: Medium: Involves
adjusting the width-to- Involves redesigning the careful design to
length ratios of transistors. layout to accommodate determine the optimal
smaller dimensions and number of stages and
ensuring sizes of inverters.
manufacturability.
Scalability Limited: As technology High: Benefits from High: Can be optimized
scales down, the benefits technology scaling but further with technology
reduce due to increased faces diminishing returns scaling and adapts well
leakage currents and other due to physical and to various load
short-channel effects. material limits. conditions.

Implementati Straightforward Requires thorough design Requires a systematic

on adjustments in the design and verification steps, design approach to
phase. including dealing with determine the optimal
new challenges like number and size of
quantum effects. stages.
Use Case Used when minor speed Applied in advanced Ideal for driving large
improvements are needed technology nodes where capacitive loads, such
without significantly speed is a critical factor as in long interconnects
increasing complexity. and design rules allow for or high fan-out
aggressive scaling. conditions.