IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO.

5 , MAY 1981 511

A Functional GaAs FET Noise Model

ALLEN F. PODELL, SENIOR MEMBER, IEEE

Abstract-It is the purpose of this paper to develop a theory upon

which the design of low noise FET amplifiers can be based. This is not
a fundamental model of the noise mechanisms in GaAs FET’s, but
rather, an endeavor to relate physically measurable device capacitances
and resistances to the device noise figure andoptimum noise source
impedance. It will be shown that the noise performance of an FET can
be adequatelydescribed by two uncorrelated noise sources. One, at
the input of the FET, is the thermal noise generated inthe various resis-
tances in the gate-source loop. This noise source is frequency depen-
dent and it can be calculated from the equivalent circuit of the FET.
The second noise source, in the output of the FET, is frequency inde-
pendent, andnot recognizably related to any measured parameters.
This output noise is a function of drain current and voltage.
The decomposition of the FET noise into two uncorrelated sources
simplifies the design of broad-band low noise amplifiers. Oncethe Fig. 1. GaAs FET cross section.
equivalent circuit of a device and its noise figure at one frequency are
known, the optimum noise source impedance and noise figure over a
broad range of frequencies may be calculated. For the device designer 11. THENOISE MODEL
thismodel also may be helpful in balancing input-output noise
tradeoffs. As with Englemann and Liechti’s paper [ 1 I ] , a very simpli-
fied FET model (Fig. 1) is used, in which:
1) G,, R,, and C,, are solelydetermined by the gradual
I.INTRODUCTION slope portion of the channel, that part of the channel that
extends as far as the drain side of gate. It is assumed that
M ANY EXCELLENT papers have been written on noise
modeling GaAs FET’s [ 11- [ l o ] . Unfortunately, none
is as simple as that which adequately describes silicon FET’s.
in this region the noise temperature of the resistances is
the channel temperature.
This is because the hot electron noise mechanisms in GaAs are 2) There is an excessnoise source associated with the sta-
much more complex than those in silicon, and the frequencies tionary Gunn domain that forms in the channel between
of i.nterest aremuchhigherthanthosegenerallyconsidered the gate and the drain.In addition,theremaybehot
necessaryforsilicon FET modeling. Induced gatenoise and electron substrate current flowing which adds excess noise
gate-drain noise correlation obscure the clear conclusions that in the output circuit. Both these noise sources are in the
are possible when the input (gate) circuit noise is independent output circuitandare notdirectlyinfluencedbythe
of the output circuit (drain) noise. After analyzing the noise ac-gate voltage.
and s parameters of many FET’s from various manufacturers,
itbecame clear that anoisemodelbased on no correlationA . The Input Circuit
betweeninputandoutput noise gave goodagreementwith The above allows us to develop a circuit equivalent for the
measured data. Physically, this had to mean that the excess input portion of the FET in which losses are inR,, Ri, and R,.
drain circuit noise arose in a region sufficiently remote from Thenoisegenerated in theseresistances is normalthermal
the gate to have little influence over the gate current. noise. For the noise calculations, the input circuit can then be
The decomposition of the FET noise into two uncorrelated represented by a series RLC circuit, as shown in Fig. 2. The
sources simplifies the calculation of the optimum noise source gate inductance L,, and the source inductance L,, are ignored
impedance. Once the equivalentcircuit of theFETandits when calculating the “intrinsic” FET noise model. However,
noise figure at one frequency are known, the noise figure and it is important to restore these inductances to the equivalent
the optimum noise sourceimpedance over abroadrangeof circuitwhencalculating the optimum source impedance and
frequencies may be calculated. Since the optimum source con- R, referred to the actual device terminals. In the input noise
ductance is a simple analytical function of frequency, broad- model, L , and L, have essentially the same effect, adding an
band amplifiers may be designed with minimum noise figure at impedance j w ( L , t L,) to the“intrinsic”FETinput.The
each frequency, or flat noise figure over the band, as required. effect of L, on the power gain and input impedance is quite
different,as it adds negative feedback [17], [ Z l ] . Inprac-
tice, Q: >> 1 so that Q? t 1 = Q:. Thismeans that gl =
Manuscript received October 5, 1979; revised July 23, 1980.This
work was supported inpart under JSEP Contract F49620-77-C-0069. (l/(Q: t 1 ) R l ) ( 2 ~ f ) ~ C ~R 1 is essentiallyfrequency
‘R1.
The author is with Podell Associates, Palo Alto, CA94301. independent, so that gl increases as f ’. It will be shown later

0018-9383/81/0500-0511$00.75 01981 IEEE

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512 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1 9 8 1

where
and
(11.1) g1 - -L--
(QI2+1)R1
Rn
F = F m i n +- [(gs - gsopt)' + (bs - bsopt)'].
gs
Q 2
(11.2) c; = 2-
Ql~+l CI However, GaAs MESFET's cannot be characterized by a con-
stant noise parameter Q. At I D S of 5 percent of IDss and
(11.3) Q1 I-f-
ClRl
above,additionaloutput noiseappears, increasing the Q/g,
noise term.
2 ) Fixingthe simplest model. We cansalvage our simple
model if we can show that this additional output noise is ire-
MANUFACTURER'S MODEL MAKE R-C INPUT MODEL CONVERT TO
quency independent and not correlated with the input noise.
OF FET CHIP FOR "INTRINSIC" FET PARALLEL

(ASSLXE Cdg<<Cgs) EQUIVALENT

A stationary Gunn domain lies between the end of the gate
and the drain region, and the voltage drop across it is most of
Fig. 2. Simplified FET input model. the drain to source supply voltage. The length of this domain
depends on the drain-source voltage, and this length modula-
tion helps to shield the gradualchannel FETfrom drain-
source voltage change. This will raise the output impedance of
the FET and its voltagegain p(= g, *Rout). Thisdomain
will be noisy, with electron temperature much higher than in
the gradual channel. As with conventional Gunn diodes, this
noise can depend on such factors as the drain contact quality,
surface treatment, impurities, and interface layers. The noisy
Gunn domain is in series with a quieter low-field FET. There
Fig. 3. Simple noise equivalent circuit. is little correlation of induced gate noise and output noise be-
cause the dominant noisy domain is well away from the chan-
thatthefrequencydependence of gl is responsible for the nel region where high-correlation exists.
noise figure versus frequency behavior of the FET. Current flowing through the substrate, around the FET, as
described by Engelmann, Liechti, and others [14] -[I61 also
B. The Output Circuit probablyadds excessnoise in theoutput circuit. Thesub-
1) The simplest model. In Bruncke and Van der Ziel's paper strate current and the electric field in the noisy Gunn domain
[12] , [13] , the noise in the output circuit of a silicon FET arerelated.Thesubstratecurrentflowsunder the channel,
was conveniently modeled by its equivalent noise resistance, which separates it from the gate; therefore, this noiseis not
R, = Q/g,, in series with the gate. This Q is a noise param- likely to be correlatedwithgatenoise,either. It ispossible
eterwhich they found to be about 0.7 for practical silicon that the effective noise temperature of the output conductance
FET's and it depended on the gate-drain noise correlation. At will be much higher than the channel temperature because of
frequenciesfrom 10 MHz to 4 GHz, modern silicon JFET's the excess output noise sources. By replacing the noise param-
and MESFET's agree well with this theory. It is Bruncke and eter Q with a variable F1,one can reflect the noise in this con-
Van der Ziel's simple noise equivalent circuit, shown in Fig. 3 ductance back to the inputcircuit
that is used in this paper. 1
They also found that the following equations were valid for Rn=-F 1( I D 9 vDS> (5)
grn
silicon FET's.
where F1(ID, VDs)is a function describing the current and
voltage dependence of the excess output noise.Experimen-
tally, one finds that F1( I D ,VDs)is an exponential function of
I D S ~ I D S Sand a weak functionof V D s . Englemannand
Liechti [l 11 discuss the effect of VDson the stationary Gunn
domain, but scant data is available on the effect of VDs on
FET noise figure. FortheHFET1000, gain drops rapidly
below3.5-V V'S, while the noise figure changesslowly. As
VDs is reduced,thesecond-stage noise contribution will
where rapidlyoverwhelm that of theFETundertest unless an
exceptionally low noise second stage is used, and the gain of
A =gl R,. thefirst stageis large. In oneexperimentwhich was per-
Additional algebraic manipulations give the followinguseful formed at 1.5 GHz on HFET 1000 devices, the noise figure
results from the above: improved 0.1 dB in going 3.5 to 3.2 V and another 0.05 dB at
2.8-V VDS,the optimum bias point (N.F. = 0.75 dB). It was
noted that the optimumbias current at 2.8-V VDswas approx-
imately18-percent I D S S ,whereas at 3.5-V VDS, 15-percent

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PODELL: FUNCTIONAL GaAs FET NOISE MODEL 513

o = NEC 244 HFET 2201

A = IIFCT 1000
0 lA8
-
= NEC

V
V
v - IlFBT 2201
V S X 9305

KO
0 V
0 V

V
I
0‘ 0,;s 013 015 0; I
0.54 I
A
Fig. 6 . Comparison of measured and calculated noise figure.

I I I I I I I I
4 6 8 IO 12 14 16 I8
f (GHz)
Fig. 4. Output noise magnitude versus frequency.

‘1
o 0

A
-- NEC 244
IlFEI 1000
o = NEC 308
V - IlFET 2201

K2 3 V v = VSX 9105
A
A 0
V V
2- V , I I 4 J
A m 20 40 60 80 100
0 IDS

Fig. 7 . Current dependence of noise figure for 5 devices.

1 -

2) K O tends to be higher for shorter gate FET’s.

01 I I I I I I I I 3) K O appears to be frequencyindependent,or increases
2 4 6 8 IO 12 14 16 18
f (GHz) somewhat below 4 GHz. In Figs.4-7wehave assumed
Fig. 5 . Output noise current dependence versus frequency. that the FET input can be modeled as a simple series RC
circuit. Any other input losses can cause K O to appear to
IDss was theoptimum.Reducing VDs results in a smaller be frequency dependent. Two explanations are proposed:
lower electron temperature domain formed between gate and a) that there exists another RC series circuit in parallel
drain, which allows a larger drain current before the domain with the FET input that adds a parallel conductance
noise gets dominant again. It should be noted that the asso- at microwave frequencies and is caused by finite sub-
ciated gain (15 dB) @ VDs= 3.5 V, was large enough to allow strate conductivity [6] . It has been shown that the
us to makethis experiment. Had we performedthisexperi- bonding pad, in conjunction with a poor semiinsulat-
mentat 4 GHz, thesecond-stagecontributionwould have ing substrateorbufferlayer can introduce a shunt
been more difficult to ignore. For most practical applications, conductance. This shuntconductancewouldintro-
the weak voltage dependence of noise figure need not be duceanasymptoticminimumlowfrequency noise
included in. our model. It was found empirically that figure even if there were no llfeffects to be reckoned
with. FET’s withlower input capacitancewouldbe
affected more by the bonding pad conductance than
high capacitancedevices.In addition,multiple gate
where bonding pads would make this effect worse.
b) that the system calibration becomes increasingly im-
I = IDSIIDSS perfect at lower frequencies wheretheVSWR gets very
IDS = drain-sourcecurrentand IDSS =IDSat V,, = 0 large.
for a nominal device
K O ,K 2 areempirical constants. It will be shown later (Figs. 8 and 9) that rocalculated from
the simple equivalentcircuit(constant KO)gives excellent
In Figs. 4-7 one cansee the relative agreement between this agreement with measurements at frequencies below 8 GHz. Of
model and the measured results. It was assumed that gl, is course, the effects ofa) and b)can be taken intoconsideration
frequency independent over our frequency range of interest, in determining gl,if it becomes necessary,by the introduction
and that (2) is valid. of an additional input conductance.
A number of interestingthings can be seen in this data. A recent paper [ 171 , described 1.5-GHz amplifiers designed
1) K 2 is frequency independent, and the exponential depen- with this noise model from 10-GHz chip data. The 1.5-GHz
dence of R, is clear. noise figure,0.75 dB,was onlyO.25 dB above that extrapolated

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 514 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1981

6 CHIPS ?IEC 388

CHIPS
3 LOTS
T o p KEAS- U,V,W,X,Y,Z
~~ -
HFET 1000 2 DEVICES
MEAS ( 2 . 2 GHz) GZ, F2

= gz,12
~~

Fig. 8. Zo@measured and calculated-HFET 1000. Fig. 10. Zopt measured and calculated-NEC 388 at 10 GHz.

Fig. 9. Zopt measured and calculated-NEC 244 and brand “X.” Fig. 11. Zopt measured and calculated-DXC 2502.

fromthe10-GHzchipdata. Since the 0.75 dB included all

matching, bias circuit, and connector losses, the assumption of
constant K O cannotbemuchinerrorfortheHFET 1000,
which was used in these amplifiers.
It should be pointed out that the data presented hereare
from good, mediocre, and poor wafer runs of various manu-
facturers, in order to be as general as possible.

111. THE OPTIMUMNOISESOURCEIMPEDANCE

In Section I1 we showed that R,, the reflected output noise
of GaAs FET’s appears t o be independent of frequency. The
conductance gl wasassumed to be as in (11.1) ofFig. 1, Fig. 12. Zopt measured and calculated-HP Labs FET.
approximately proportional to f 2 . If little correlation exists
between the gate and the drain circuits, then we could calcu-
late theoptimumsourceadmittancewith (3) and (11.2) of (l/wCgs) > 300 a)from F 1 1 t (Rn/50). Figs. 8 and 9 show
Fig. 2 that the calculated Yopt and the measured results agree very
well for all devices below 8 GHz. Above 8 GHz the NEC 388,
I
the HP labs, and the Dexcel FET’s appear to be 15 to 20’ off.
In fact, it was noticed that a better fit in this region is a series
RCcircuit, with
bsopt = - w C ; = s w C 1 ,
QI +l
It should be pointed out that C1 is approximately the input
Rsopt = R 1 fi (9)

capacitance of theFET measured at some frequency, say and

2 GHz, with L , and L, removed. (The effect of these induc-
tances is small at 2 GHz). A good estimate for R 1 is to mea- Csopt = - c g s . (1 0)
sure SI1 at 8 GHz, where lSlll is considerably less than one, The noise figure, however, is still accurately given by (2). At
turn this into an impedance, then from its real part, subtract this point, it is difficult t o know which part of our approxima-
g,L,/Cg, (typically 3 to 7 2 ! real). A rough estimate (0 to tion is deteriorating. Note that FET’s A , B , C, and D,mea-
20 percent high) for R , may be obtained from the untuned sured in the same fixture as the NEC 388, and by the same
noise factor measured at a convenient low frequency (where people, still abide by (3) and (11.2) of Fig. 2 . Figs. 10, 11, and

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PODELL: FUNCTIONAL GaAs FET NOISE MODEL 515

12 show Po measured and calculated at8 GHz and above for a used, but it is clear that source induc.tance can effectively in-
number of devices. crease theinput resistance,whichincreases theinputcon-
ductance, makingginput closer to g, opt, which is g l d m ) .
IV. THE OPTIMUM Low NOISE FET This inductance only changes the noise optimum source im-
It is certainly areasonable goal to design anFETthat is pedance by its inductive reactance, so that its effect is quite
simultaneously noise and power matched; that is, its optimum small. Drain-gate feedbackaddsanother degree of freedom,
noise source impedanceis the conjugate of its input impedance. and it has been shown that with both source (series) and drain-
However, it has been shown that the optimum noise source gate (shunt) feedback, a simultaneous noise and power match
conductance g, o p t , is very much different from gl ,the input can be obtained at one frequency [18] . The point of this dis-
conductance of the FET without L, or L,. It is assumed for cussion is that either a source inductance or a resistor at the
nowthatwemay neglect Cd,. Withoutsourceinductance, input could be used to improve the input match and lower the
and without drain-to-gate feedback, we may use (9) to predict effective input Q . However, the resistor will inevitably raise
the degree of mismatch under noise matched conditions, as the noise figure, while thesourceinductance will not.The
b, opt isvery close to - oC;. Then the input VSWR ( W l ) optimumbroad-bandlow noise FETwould be a low noise
would be FET with lossless feedback applied to lower its input Q . The
actual design of such a device involves tradeoffs between input
and output noise, whichwill be discussed in th.e next section.

V.DESIGNTRADEOFFS
Equation(2) relates thenoisefactor to theparameter
A ( = g l R , ) . As a practical matter, it is desirable to minimize
both the noise and the inputQ of the FET, particularly at low
microwave frequencies where the input Q is extremely high,
and losses inthematchingnetwork can beas important as
losses in the input of the FET itself. Another example of this
requirement is in monolithic GaAs IC's, where the Q of the
matchingnetworks is very low.From (11.1) and (11.3) of
Fig. 2 we have

Thuswithoutfeedback,the VSWR W1 (or p l , the reflec- From (5) we have R , = ( K O / g m ) e K z rTherefore,

.
tioncoefficient)andthe noise figure are quitetightly tied
together.
Similarly,
considering
the
input
mismatch loss
(4 Wl/(Wl t l)'), the associated gain (GASS)may be related
to the maximum available gain.
or
fKoeK2' 1
A= * -.
Q1 ft

The ft of the FET is proportional to u,/Lg, where L , is the

Thus effective gate length, and v, the saturation velocity

This showsthat, for small A , theassociated gain increases Equation(18) shows that, for a given gate lengthand us,
3 dB/octave with respect to the MAG, which falls at 6 dB/ either an increase in input Q or a decrease in output noise can
octave, yielding a net drop of 3 dB/octave for the associated lower the noise factor. For broad-band applications lowering
gain with increasing frequency. Of course, at some point the the output noise decreases R , also.
associated gain will merge with the MAG, then it will fall at Another area of question is the width of the FET. If we
6 dB/octave. assume that the gate-metal resistance R , can be kept a minor
It iswell known that source lead inductance increases the part of the input resistance by the addition of gate pads, when
effective value of R , by somewhat les; than gm L,/Cg,. This is required,then we can calculate theoptimum device width
a negative feedback effect, at least at low microwave frequen- as follows.Let p bethemagnitude of theinput reflection
cies; there is no loss introduced, and the noise measure is un- coefficient,which we wouldwant to minimize, in order to
changed [18], [ 2 2 ] . Theoptimum value of thisinductance minimize the matching circuit losses. We assume that the FET
should be determined by analysis of the actual circuit to be has a high input Q , and that we can scale its width without

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516 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 5, MAY 1981

changing the intrinsic noise figure. Then would have the same noise figure, 10 times the g,, and 1/10
the R , of the original small FET. R , as predicted above is not
in agreementwiththisintuitiveargument. Rop aspredicted
above is in agreement with this argument, but itdoes not have
and a frequency dependence, nor is its asymptotic behavior reason-
able. For example, ifg, were very large, and R, and R , were
fixed (for example, a very short gate FET), R , wouldap-
proach 2.2 [R, t R,] . This would limit the minimum noise
where figure to
R, +R,
1 t = 1.45 (1.6 1 dB).
2.2 [R, t R,]
and
However, Fukui’s approximations for the device’s parasitic re-
1
x1 =- sistances should be very useful, in connection with this model,
2rrfC1‘ in indicating the optimization of device doping, active layer
The minimum of p occurs when thickness, etc.
Z: = R : t X?. (2 0) VII. CONCLUSION
Since R <<X1,thismeans that the capacitivereactanceof It has been shown that a simple noise model having 2 uncor-
the device should be equal in magnitude to the impedance it related noise sources adequately describes the noise behavior
is intended to be fedfrom. Undertypicalconditions,this of low noise GaAs FET’s.Onenoisemeasurement and the
impedance is 50 a,although for a push-pull FET, this could small signal equivalent circuit model for the FET are sufficient
be 25 a. By the 5042 criterion,theHFET2201 and the for a complete noise model. Broad-band amplifiers may be de-
NEC 388 are designed to be optimum in width around 10 to signed with prescribed noise figure and gain response. It was
15 GHz,and 100-pm widthwould be appropriatefora shown that 3 dB/octave is the intrinsic gain rolloff of a noise
0.5-pm 30-GHz FET. matched FET, and that there exists an optimum device input
capacitance for minimum matching circuit losses.
VI. A COMPARISONWITH FUKUI’SWORK
The basic similarity between this work and Fukui’s requires ACKNOWLEDGMENT
that some comparison of results be made. If we take (2) and The author wishes to thank W. Ku and L. Liu for many use-
simplify it by assuming that A is small and that Ql>> 1, we ful discussions, and also the staff of Watkins Johnson for pro-
can get an expression for Fminvery close to Fukui’s (2) [ 101 viding device data.

REFERENCES
F. Klaassen,“On the influence of hot carrier effects onthe
thermal noise of field-effect transistors,” IEEE Trans. Electron
Devices,vol. ED-17, pp. 858-862, Oct. 1970.
W. Baechtold, “Noisebehaviorof Schottky barrier gate field-
effect transistors at microwave frequencies,” IEEE Trans. Elec-
tron Devices, vol. ED-18, pp. 97-104, Feb. 1971.
A. Van der Ziel, “Noise behavior of GaAs field-effect transistors
withshort gate lengths,” IEEE Trans. Electron Devices,vol.
ED-19, pp. 674-680, May 1972.
H. Statz, H. Haus, and R. Pucel, “Noise characteristics of gallium
=1t( 4 n a - )

-
iRg
f cgs
2 -t R i *

By analogy, one finds that k l 4 n d K 7 , and ( R g t R t,

arsenide field-effect transistors,” IEEE Trans. Electron Devices,
vol. ED-21, pp. 549-562, Sept. 1974.
R. Pucel, H. Haus, and H. Statz, “Signal and noise properties of
gallium arsenide microwave field-effect transistors,” in Advances

-
R i ) ( R , t R z ) . For 1-pm FET’s we have found K0eK2‘ to
be approximately 1.25, thus we would calculate kl = 0.001 X
in Electronics and Electron Physics, vol. 38. New York: Aca-
demic Press, 1975, pp. 195-265.
W. Baechtold et a/., “Si and GaAs 0.5 pm-gate Schottky-barrier
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4 rr X 1.25 = 0.0157, in reasonable agreement with Fukui’s 1973.
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pF,and requires ,normalization.It is difficult to relate the InP field-effect transistors,” IEEE Trans. Electron Devices, vol.
ED-23, p. 1298,1976.
other terms exactly, because our results are based on measure- H.Fukui, “Optimal noisefigureofmicrowaveGaAs FETs,”
ments made at noise bias (15 percent 1 ~ ~ whereas
s ) Fukui’s IEEE Trans. Electron Devices, vol. ED-26, p. 1032, 1979.
arebasedon“null”bias.However, Fukui’s expressionfor B . S. Hewitt,etal., “Low noise GaAs MESFETs,”Electron. Lett.,
vol. 12,110. 12,pp. 309-310, June 10, 1976.
X o p , e.g., Xop = 160/ f C,, is likely to be within 20 percent H. Fukui, “Design of microwave GaAs MESFET’s for broad-band
of that predicted by our model. The large differences appear low-noise amplifiers,” IEEE Trans. Microwave Theory and Tech.,
to be in the values of R , and R o p . According toFukui, V O ~ MTT-27,
. pp. 643-650, July 1979.
R. W. H. Engelmann and C. A. Liechti, “Gunn domain formation
R , = (O.O3/gL), and Ro, = 2.2 [(1/4g,) t R , t R,] . If one inthesaturatedcurrent region of GaAsMESFETs,” in Proc.
were to take 10 FET’s andparallel them, the resulting FET IEDM, pp. 351-354, Dec. 1976.

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IEEE TRANSACTIONS
ON ELECTRON DEVICES, VOL. ED-28, NO. 5 , MAY 1981 517

[ 121 A. Van der Ziel, “Gate noise in field-effect transistors at moder- wave J., pp. 82-92, Apr. 1979.
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Plasma-Coupled Bipolar Linear Image Sensor

MASAHIRO SAKAUE, TERUO TAMAMA, AND YOSHIHIKO MIZUSHIMA

Abstract-A new bipolar 1728-bit linear image sensor is described. both imagersrequiremultiple voltage powersupplies higher
Combining the plasma-coupled device (PCD) shift registersand a photo- than 10 V.
diode may, a simple structure and unique operation are realized. In On the other hand, at the early stage of the development of
contrast to other MOS or CCD imaging devices, some remarkable charac- imaging devices, the bipolar-type imager using phototransistors
teristics and performance were obtained. High output power, more than
1 mW, and high sensitivity of 2.26 X lo8 pA/pJ (at 6000 A) were mea- [3] , [4] attracted interest. However,its practical development
sured. Spectralresponseis observed from 0.45 pm to 0.95 pm, and has not been achieved so far, because of the many difficulties
linearity is about unity. Large SIN ratio, more than 46 dB, is easily at- in disposing the sensing elements and scanning circuits mono-
tained. Inherent thermal noise, induced spike noise, and transfer noise lithically on a single chip. The problems involved included the
are less than in other conventional imaging devices. Only a single power need for isolation between elements, the low packing density,
supply of less than +5 V is necessary. A wide scanning clock frequency
range from dc to 3 MHz can be used witha power dissipation of 70 mW and large power dissipation.
being obtained. The above features are discussed in terms of a theory Recently,featuressuch asanisolationless structure, high
based on thelow impedance nature of the bipolar sensing circuit. packing density, and low-power dissipation have been increas-
ingly satisfied by the plasma-coupleddevice(PCD) [SI -[7].
The PCDis a novel bipolar static shift register. Its scanning
I.INTRODUCTION
principle relies on an electric potential coupling through the

T 0 DATE, MOST of the developments of imaging devices

have centered on MOS-type devices, such as MOS, CCD,
or CID sensors, and their performance has progressedt o a level
bulk, so that the number of contact holes and aluminum me-
tallized wirings are minimized andthere is no need for isolation.
The PCDis therefore suitable for a new integrated imaging
of practical usage. However, with these devices it is difficult device [8], [9]. The present imager is composed of the PCD
to obtain satisfactory performance at a moderate cost. In the scannerand the associatedp-n junctionphotodiodes. Some
MOS imager, induced spike noise through stray capacitances fundamental performance characteristics of thisimager have al-
and high output capacitanceresults in a reduction in S/N ratio. ready been reported [8]. However, the results obtained with
The CCD imager suffers from an inherent blooming phenom- these sensors were only preliminary since they utilized a small
enon and thesensitivity at shorterwavelengths islow. To avoid number of sensing elements. To clearly illustrate the advantages
these problems, fabrication processes are complicated and the of this device on a practical scale intended for a facsimile appli-
inherent advantages of MOS and CCD imaging devices, such as cation, thispaper reports its performance and features in a 1728-
simple structure, have been compromised [l] , [2]. Moreover, bit linear imager.
Manuscript received September
11, 1980; revised December 1, 1980. 11. STRUCTURE AND OPERATION
The authors are with the Musashino Electrical CommunicationLabora-
tory, Nippon Telegraph and Telephone Public Corporation, Musashino- The layout Of the is shown in Fig. ’. Two
shi, Tokyo 180, Japan. 864-stagelinear PCD-scanner arrays, coupled with respective
0018-9383/81/0500-0517$00.75 0 1981 IEEE

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