DATA SHEET

MOS INTEGRATED CIRCUIT

µPD780851(A), 780852(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD780851(A) and 780852(A) are products of the µPD780852 Subseries in the 78K/0 Series.
The µPD780851(A) and 780852(A) include a meter controller/driver, sound generator, LCD controller/driver, 8-bit
resolution A/D converter, timer, serial interface, interrupt function, and various other peripheral hardware.
A flash memory version, the µPD78F0852, which can operate in the same power supply voltage range as the
mask ROM version, and various development tools are also available.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
µPD780852 Subseries User's Manual: U14581E
78K/0 Series User's Manual - Instruction: U12326E

FEATURES
{ Meter controller/driver: 16 PWM outputs (8-bit resolution)
{ Sound generator: 1 channel
{ Internal ROM and RAM

Item Program Memory Data Memory

(Internal ROM) Internal High-Speed Internal Expansion LCD Display RAM
Part Number RAM RAM
µPD780851(A) 32 KB 1024 bytes 512 bytes 20 × 4 bits
µPD780852(A) 40 KB

{ Minimum instruction execution time can be changed from high-speed (0.24 µs) to low-speed (3.81 µs)
{ I/O ports: 56 (Including segment signal output alternate function pins)
{ 8-bit resolution A/D converter: 5 channels
{ Serial interface: 3 channels
{ Timer: 6 channels
{ Supply voltage: VDD = 4.0 to 5.5 V

APPLICATIONS
Automobile meter (dashboard) control

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. U14577EJ1V0DS00 (1st edition) The mark shows major revised points.
Date Published October 2001 NS CP(K)
2000
Printed in Japan
 µPD780851(A), 780852(A)

ORDERING INFORMATION

Part Number Package Quality Grade

µPD780851GC(A)-×××-8BT 80-pin plastic QFP (14 × 14) Special
µPD780852GC(A)-×××-8BT 80-pin plastic QFP (14 × 14) Special

Remark xxx indicates ROM code suffix.

For the details of the quality grades on the devices and their applications, refer to Quality Grades on NEC
Semiconductor Devices (C11531E) published by NEC Corporation.

2 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

78K/0 SERIES LINEUP

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Y subseries products are compatible with I2C bus.

Control
100-pin µ PD78075B µ PD78078 with reduced EMI noise
100-pin µ PD78078 µPD78078Y µ PD78054 with timer added and enhanced external interface
100-pin µ PD78070A µ PD78070AY ROMless version of µ PD78078
100-pin µPD780018AY µ PD78078Y with enhanced serial I/O and limited functions
80-pin µ PD780058 µ PD780058Y µ PD78054 with enhanced serial I/O
80-pin µ PD78058F µ PD78058FY µ PD78054 with reduced EMI noise
80-pin µ PD78054 µ PD78054Y µ PD78018F with UART and D/A added, and enhanced I/O
80-pin µ PD780065 µ PD780024A with expanded RAM
64-pin µ PD780078 µ PD780078Y µ PD780034A with timer added and enhanced serial I/O
64-pin µPD780034A µPD780034AY µ PD780024A with enhanced A/D
64-pin µPD780024A µPD780024AY µ PD78018F with enhanced serial I/O
64-pin µ PD78014H µ PD78018F with reduced EMI noise
64-pin µ PD78018F µ PD78018FY Basic subseries for control
42/44-pin µ PD78083 On-chip UART and capable of low voltage operation (1.8 V)
Inverter control
64-pin µ PD780988 On-chip inverter controller and UART. Reduced EMI noise.
VFD drive
100-pin µ PD780208 µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin µ PD780232 For panel control. On-chip VFD C/D. Display output total: 53
80-pin µ PD78044H µ PD78044F with N-ch open drain I/O added. Display output total: 34
78K/0 80-pin µ PD78044F Basic subseries for driving VFD. Display output total: 34
Series
LCD drive
120-pin µ PD780338 µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
120-pin µ PD780328 µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
120-pin µ PD780318 µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
100-pin µ PD780308 µ PD780308Y µ PD78064 with enhanced SIO and expanded ROM, RAM
100-pin µ PD78064B µ PD78064 with reduced EMI noise
100-pin µ PD78064 µ PD78064Y Basic subseries for driving LCD. On-chip UART.
Bus interface supported
100-pin µ PD780948 On-chip DCAN controller
80-pin µ PD78098B µ PD78054 with IEBusTM controller added
80-pin µ PD780702Y On-chip IEBus controller
80-pin µ PD780703Y On-chip DCAN controller
80-pin µ PD780833Y On-chip J1850 (CLASS2) controller
64-pin µ PD780816 Specialized for DCAN controller function

Meter control
100-pin µ PD780958 For industrial meter control
80-pin µ PD780852 On-chip controller/driver for automobile meter drive
80-pin µ PD780828B For automobile meter drive. On-chip DCAN controller

TM
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.

Data Sheet U14577EJ1V0DS 3

 µPD780851(A), 780852(A)

The major functional differences among the subseries are listed below.

Function ROM Timer 8-Bit 10-Bit 8-Bit Serial I/O VDD External
Subseries Capacity A/D A/D D/A Interface MIN. Expansion
8-Bit 16-Bit Watch WDT
Name Value

Control µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch − 2 ch 3 ch (UART: 1 ch) 88 1.8 V √

µPD78078 48 K to 60 K

µPD78070A − 61 2.7 V

µPD780058 24 K to 60 K 2 ch 3 ch (time-division 68 1.8 V

UART: 1 ch)

µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.7 V

µPD78054 16 K to 60 K 2.0 V

µPD780065 40 K to 48 K − 4 ch (UART: 1 ch) 60 2.7 V

µPD780078 48 K to 60 K 2 ch − 8 ch 3 ch (UART: 2 ch) 52 1.8 V

µPD780034A 8 K to 32 K 1 ch 3 ch (UART: 1 ch) 51
µPD780024A 8 ch −

µPD78014H 2 ch 53

µPD78018F 8 K to 60 K

µPD78083 8 K to 16 K − − 1 ch (UART: 1 ch) 33 −

Inverter µPD780988 16 K to 60 K 3 ch Note − 1 ch − 8 ch − 3 ch (UART: 2 ch) 47 4.0 V √

control

VFD µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch − − 2 ch 74 2.7 V −

drive
µPD780232 16 K to 24 K 3 ch − − 4 ch 40 4.5 V

µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 V

µPD78044F 16 K to 40 K 2 ch

LCD µPD780338 48 K to 60 K 3 ch 2 ch 1 ch 1 ch − 10 ch 1 ch 2 ch (UART: 1 ch) 54 1.8 V −

drive
µPD780328 48 K to 60 K 62

µPD780318 48 K to 60 K 70

µPD780308 48 K to 60 K 2 ch 1 ch 8 ch − − 3 ch (time-division 57 2.0 V

UART: 1 ch)

µPD78064B 32 K 2 ch (UART: 1 ch)

µPD78064 16 K to 32 K

Bus µPD780948 60 K 2 ch 2 ch 1 ch 1 ch 8 ch − − 3 ch (UART: 1 ch) 79 4.0 V √

interface
µPD78098B 40 K to 60 K 1 ch 2 ch 69 2.7 V −
supported
µPD780816 32 K to 60 K 2 ch 12 ch − 2 ch (UART: 1 ch) 46 4.0 V

Meter µPD780958 48 K to 60 K 4 ch 2 ch − 1 ch − − − 2 ch (UART: 1 ch) 69 2.2 V −

control

Dash- µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch − − 3 ch (UART: 1 ch) 56 4.0 V −

board
µPD780828B 32 K to 60 K 59
control

Note 16-bit timer: 2 channels

10-bit timer: 1 channel

4 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

OVERVIEW OF FUNCTIONS

Part Number µPD780851(A) µPD780852(A)

Item

Internal ROM 32 KB 40 KB
memory High-speed RAM 1024 bytes
Expansion RAM 512 bytes
LCD display RAM 20 × 4 bits
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time On-chip minimum instruction execution time variable function
0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation)
Instruction set • 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports (segment signal output Total: 56
alternate function pins included) • CMOS input: 5
• CMOS output: 16
• CMOS I/O: 35
A/D converter • 8-bit resolution × 5 channels
• Power-fail detection function
LCD controller/driver • Segment signal outputs: Max. 20
• Common signal outputs: Max. 4
• Bias: 1/3 bias only
Serial interface • 3-wire serial I/O mode: 2 channels
• UART mode: 1 channel
Timers • 16-bit timer: 1 channel
• 8-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 2 (capable of 8-bit PWM output: 2)
Meter controller/driver PWM output (8-bit resolution): 16
Pulse width setting of 8 + 1-bit precision is enabled by a 1-bit addition function
Sound generator 1 channel
Clock output 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.04 MHz, 2.09 MHz, 4.19 MHz, 8.38 MHz (@
8.38 MHz operation with main system clock)
Vectored interrupt Maskable Internal: 16, External: 3
sources Non-maskable Internal: 1
Software 1
Supply voltage VDD = SMVDD = 4.0 to 5.5 V
Operating ambient temperature TA = −40 to + 85°C
Package 80-pin plastic QFP (14 × 14 mm)

Data Sheet U14577EJ1V0DS 5

 µPD780851(A), 780852(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................... 7

2. BLOCK DIAGRAM................................................................................................................................... 9

3. PIN FUNCTIONS.................................................................................................................................... 10
3.1 Port Pins ....................................................................................................................................................... 10
3.2 Non-Port Pins ............................................................................................................................................... 11
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................................... 12

4. MEMORY SPACE .................................................................................................................................. 15

5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................... 17

5.1 Ports .............................................................................................................................................................. 17
5.2 Clock Generator ........................................................................................................................................... 18
5.3 Timer/Event Counter.................................................................................................................................... 18
5.4 Clock Output Controller .............................................................................................................................. 21
5.5 A/D Converter ............................................................................................................................................... 22
5.6 Serial Interface ............................................................................................................................................. 23
5.7 LCD Controller/Driver .................................................................................................................................. 24
5.8 Sound Generator.......................................................................................................................................... 25
5.9 Meter Controller/Driver ................................................................................................................................ 25

6. INTERRUPT FUNCTION ....................................................................................................................... 26

7. STANDBY FUNCTION........................................................................................................................... 29

8. RESET FUNCTION ................................................................................................................................ 29

9. INSTRUCTION SET ............................................................................................................................... 30

10. ELECTRICAL SPECIFICATIONS ........................................................................................................ 32

11. PACKAGE DRAWING ......................................................................................................................... 43

12. RECOMMENDED SOLDERING CONDITIONS................................................................................. 44

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................... 45

APPENDIX B. RELATED DOCUMENTS................................................................................................... 47

6 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

1. PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14 × 14)

µPD780851GC(A)-×××-8BT, 780852GC(A)-×××-8BT

P86/S14
P87/S13
P90/S12
P91/S11
P92/S10
P93/S9
P94/S8
P95/S7
P96/S6
P97/S5

COM3
COM2
COM1
COM0
VLCD
S4
S3
S2
S1
S0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P85/S15 1 60 SMVSS
P84/S16 2 59 SMVDD
P83/S17 3 58 P20/SM11
P82/S18 4 57 P21/SM12
P81/S19 5 56 P22/SM13
IC 6 55 P23/SM14
X1 7 54 P24/SM21
X2 8 53 P25/SM22
VSS1 9 52 P26/SM23
VROUT 10 51 P27/SM24
RESET 11 50 P30/SM31
P07 12 49 P31/SM32
P06 13 48 P32/SM33
P05/SI2 14 47 P33/SM34
P04/SO2 15 46 P34/SM41
P03/SCK2 16 45 P35/SM42
P02/INTP2 17 44 P36/SM43
P01/INTP1 18 43 P37/SM44
P00/INTP0 19 42 SMVDD
AVREF 20 41 SMVSS
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVSS
P50/SCK3
P51/SO3
P52/SI3
VDD0
VSS0
P53/RxD
P54/TxD
P40/TI00
P41/TI01
P42/TI02
P43/TIO2
P44/TIO3
P60/TPO/PCL
P61/SGO

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.
3. Connect the AVREF pin to VDD0.

Remark When the µPD780851(A) and 780852(A) are used in applications where the noise generated inside the
microcontroller needs to be reduced, the implementation of noise reduction measures, such as
connecting VSS0 and VSS1 to different ground lines, is recommended.

Data Sheet U14577EJ1V0DS 7

 µPD780851(A), 780852(A)

ANI0 to ANI4: Analog Input S0 to S19: Segment Output

AVREF: Analog Reference Voltage SCK2, SCK3: Serial Clock
AVSS: Analog Ground SGO: Sound Generator Output
COM0 to COM3: Common Output SI2, SI3: Serial Input
IC: Internally Connected SM11 to SM14, SM21 to SM24, SM31 to SM34,
INTP0 to INTP2: External Interrupt Input SM41 to SM44: Meter Output
P00 to P07: Port 0 SMVDD: Meter Controller Power Supply
P10 to P14: Port 1 SMVSS: Meter Controller Ground
P20 to P27: Port 2 SO2, SO3: Serial Output
P30 to P37: Port 3 TI00 to TI02: Timer Output
P40 to P44: Port 4 TIO2, TIO3: Timer Output/Event Counter Input
P50 to P54: Port 5 TPO: Prescaler Output
P60, P61: Port 6 TxD: Transmit Data
P81 to P87: Port 8 VDD0: Power Supply
P90 to P97: Port 9 VLCD: LCD Power Supply
PCL: Programmable Clock Output VROUT: Power Supply Regulator Output
RESET: Reset VSS0, VSS1: Ground
RxD: Receive Data X1, X2: Crystal (Main System Clock)

8 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

2. BLOCK DIAGRAM

TI00/P40 to TI02/P42 16-bit timer 0 Port 0 P00 to P07

TPO/PCL/P60

8-bit timer 1 Port 1 P10 to P14

8-bit timer/
TIO2/P43 event Port 2 P20 to P27
counter 2
8-bit timer/
TIO3/P44 event Port 3 P30 to P37
counter 3

Watchdog Port 4 P40 to P44

timer

Watch timer Port 5 P50 to P54

SCK2/P03 Serial
Port 6 P60, P61
SO2/P04 interface 78K/0
ROM
SI2/P05 SIO2 CPU Core

SCK3/P50 Port 8 P81 to P87

Serial
SO3/P51 interface
SI3/P52 SIO3
Port 9 P90 to P97
RxD/P53
UART
TxD/P54 S0 to S4

ANI0/P10 to ANI4/P14 Internal S5/P97 to S12/P90

A/D RAM expansion LCD
AVSS controller/
converter RAM S13/P87 to S19/P81
AVREF driver
Power fail COM0 to COM3
detector VLCD

INTP0/P00 to Interrupt SM11/P20 to SM14/P23

INTP2/P02 control
SM21/P24 to SM24/P27
Meter
Standby controller/ SM31/P30 to SM34/P33
control driver
SM41/P34 to SM44/P37
Clock output SMVDD
PCL/TPO/P60
control SMVSS

Sound X1
SGO/P61 generator System X2
output control
RESET

Voltage VROUT
VDD0 VSS0 IC
regulator VSS1

Data Sheet U14577EJ1V0DS 9

 µPD780851(A), 780852(A)

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternate

Function

P00 to P02 I/O Port 0 Input INTP0 to INTP2

P03 8-bit I/O port SCK2

P04 Input/output can be specified in 1-bit units. SO2

P05 Use of an on-chip pull-up resistor can be specified by means of SI2

P06, P07 software. −

P10 to P14 Input Port 1 Input ANI0 to ANI4

5-bit input-only port

P20 to P23 Output Port 2 Hi-Z SM11 to SM14

P24 to P27 8-bit output-only port SM21 to SM24

P30 to P33 Output Port 3 Hi-Z SM31 to SM34

P34 to P37 8-bit output-only port SM41 to SM44

P40 to P42 I/O Port 4 Input TI00 to TI02

P43, P44 5-bit I/O port TIO2, TIO3

Input/output can be specified in 1-bit units.

P50 I/O Port 5 Input SCK3

P51 5-bit I/O port SO3

P52 Input/output can be specified in 1-bit units. SI3

P53 RxD

P54 TxD

P60 I/O Port 6 Input PCL/TPO

P61 2-bit I/O port SGO

Input/output can be specified in 1-bit units.

P81 to P87 I/O Port 8 Input S19 to S13

7-bit I/O port
Input/output can be specified in 1-bit units.
The I/O port/segment output function can be specified in 2-bit
units by means of the LCD display control register (LCDC).

P90 to P97 I/O Port 9 Input S12 to S5

8-bit I/O port
Input/output can be specified in 1-bit units.
The I/O port/segment output function can be specified in 2-bit
units by means of the LCD display control register (LCDC).

10 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

3.2 Non-Port Pins

Pin Name I/O Function After Alternate

Reset Function
INTP0 to INTP2 Input External interrupt request input for which the valid edge (rising edge, Input P00 to P02
falling edge, or both rising and falling edges) can be specified
SI2 Input Serial interface SIO2 serial data input Input P05
SO2 Output Serial interface SIO2 serial data output Input P04
SCK2 I/O Serial interface SIO2 serial clock input/output Input P03
SI3 Input Serial interface SIO3 serial data input Input P52
SO3 Output Serial interface SIO3 serial data output Input P51
SCK3 I/O Serial interface SIO3 serial clock input/output Input P50
RxD Input Serial data input for asynchronous serial interface Input P53
TxD Output Serial data output for asynchronous serial interface Input P54
TI00 Input Capture trigger signal input to capture register (CR00) Input P40
TI01 Capture trigger signal input to capture register (CR01) P41
TI02 Capture trigger signal input to capture register (CR02) P42
TIO2 I/O 8-bit timer (TM2) I/O (also used for 8-bit PWM output) Input P43
TIO3 8-bit timer (TM3) I/O (also used for 8-bit PWM output) P44
TPO Output 16-bit timer (TM0) prescaler signal output Input PCL/P60
PCL Output Clock output (for trimming of main system clock) Input TPO/P60
SGO Output Sound generator signal output Input P61
S0 to S4 Output LCD controller/driver segment signal output Output −
S5 to S12 Input P97 to P90
S13 to S19 P87 to P81
COM0 to COM3 Output LCD controller/driver common signal output Output −
VLCD − Power supply for LCD drive − −
SM11 to SM14 Output Meter control signal output Hi-Z P20 to P23
SM21 to SM24 P24 to P27
SM31 to SM34 P30 to P33
SM41 to SM44 P34 to P37
ANI0 to ANI4 Input A/D converter analog input Input P10 to P14
AVREF Input A/D converter reference voltage input (also used for analog power − −
supply)
AVSS − A/D converter ground potential. Connect to VSS0. − −
RESET Input System reset input − −
X1 Input Connecting crystal resonator for main system clock oscillation − −
X2 − − −
SMVDD − Meter controller/driver power supply − −
SMVSS − Meter controller/driver ground potential − −
VDD0 − Port block positive power supply − −
VSS0 − Port block ground potential − −
VROUT − Regulator output pin for positive power supply other than port block. − −
Connect to VSS0 or VSS1 via a 0.1 µF capacitor.
VSS1 − Ground potential (other than port block) − −
IC − Internally connected. Connect directly to VSS0 or VSS1. − −

Data Sheet U14577EJ1V0DS 11

 µPD780851(A), 780852(A)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits

Pin Name Input/Output Circuit I/O Recommended Connection of Unused Pins

Type

P00/INTP0 to P02/INTP2 8-A I/O Independently connect to VSS0 via a resistor.

P03/SCK2

P04/SO2

P05/SI2

P06, P07

P10/ANI0 to P14/ANI4 9 Input Independently connect to VDD0 or VSS0 via a resistor.

P20/SM11 to P23/SM14 4 Output Leave open.

P24/SM21 to P27/SM24

P30/SM31 to P33/SM34

P34/SM41 to P37/SM44

P40/TI00 to P42/TI02 8 I/O Independently connect to VDD0 or VSS0 via a resistor.

P43/TIO2

P44/TIO3

P50/SCK3

P51/SO3 5

P52/SI3 8

P53/RxD

P54/TxD 5

P60/PCL/TPO

P61/SGO

P81/S19 to P87/S13 17-G

P90/S12 to P97/S5

S0 to S4 17 Output Leave open.

COM0 to COM3 18

VLCD − −

RESET 2 Input −

SMVDD − − Connect to VDD0.

SMVSS Connect to VSS0.

AVREF Connect to VDD0.

AVSS Connect to VSS0.

IC Connect directly to VSS0 or VSS1.

12 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Figure 3-1. Pin Input/Output Circuits (1/2)

Type 2 Type 8

VDD
Data
P-ch
IN IN/OUT
Output N-ch
disable

Schmitt-triggered input with hysteresis characteristics

Type 4 Type 8-A

VDD
VDD
Pullup
Data P-ch
P-ch enable
VDD
OUT Data
P-ch
Output N-ch
disable IN/OUT
Output N-ch
disable

Push-pull output that enables high-impedance

output (both P-ch and N-ch are off)

Type 5 Type 9

VDD

Data P-ch
P-ch
IN + Comparator
IN/OUT −
N-ch
Output N-ch
disable VREF (threshold voltage)

Input Input enable

enable

Data Sheet U14577EJ1V0DS 13

 µPD780851(A), 780852(A)

Figure 3-1. Pin Input/Output Circuits (2/2)

Type 17 Type 17-G

VLC0

P-ch
VLC1
N-ch
VDD
P-ch Data
P-ch
SEG
data OUT IN/OUT

N-ch Output N-ch

disable
P-ch
VLC2
N-ch
Input
enable

VLC0

P-ch
Type 18 VLC1
N-ch
VLC0

P-ch P-ch
VLC1 SEG
N-ch
data
N-ch
P-ch N-ch
P-ch
VLC2
N-ch OUT N-ch
P-ch
COM
data

P-ch
VLC2
N-ch

14 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

4. MEMORY SPACE

Figures 4-1 and 4-2 show the memory maps of the µPD780851(A) and 780852(A).

Figure 4-1. Memory Map (µPD780851(A))

FFFFH
Special function
registers (SFRs)
256 × 8 bits
F F 0 0 H
FEFFH General-purpose registers
FEE0H 32 × 8 bits
FEDFH
Internal high-speed RAM
1024 × 8 bits
FB00 H
FAFF H
Reserved
FA6D H
FA6C H
LCD display RAM
20 × 4 bits
FA 5 9 H
FA 5 8 H

Data 7FFFH
memory Reserved
space Program area

1 0 0 0 H
F 8 0 0 H
0FFFH
F7FFH
CALLF entry area

Internal expansion RAM 0 8 0 0 H

512 × 8 bits 0 7 F F H

F 6 0 0 H Program area
F5FFH 0 0 8 0 H
Reserved
8 0 0 0 H 0 0 7 F H
7FFFH CALLT table area
0 0 4 0 H
Program Internal ROM
memory 0 0 3 F H
space 32768 × 8 bits
Vector table area
0 0 0 0 H 0 0 0 0 H

Data Sheet U14577EJ1V0DS 15

 µPD780851(A), 780852(A)

Figure 4-2. Memory Map (µPD780852(A))

FFFFH
Special function
registers (SFRs)
256 × 8 bits
F F 0 0 H
FEFFH General-purpose registers
FEE0H 32 × 8 bits
FEDFH
Internal high-speed RAM
1024 × 8 bits
FB00 H
FAFF H
Reserved
FA6D H
FA6C H
LCD display RAM
20 × 4 bits
FA 5 9 H
FA 5 8 H

Data
memory 9FFFH
Reserved
space Program area

1 0 0 0 H
F 8 0 0 H
0FFFH
F7FFH
CALLF entry area

Internal expansion RAM 0 8 0 0 H

512 × 8 bits 0 7 F F H

F 6 0 0 H Program area
F5FFH 0 0 8 0 H
Reserved
A 0 0 0 H 0 0 7 F H
9FFFH CALLT table area
0 0 4 0 H
Program Internal ROM
memory 0 0 3 F H
space 40960 × 8 bits
Vector table area
0 0 0 0 H 0 0 0 0 H

16 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 Ports
The following three types of I/O ports are available.

• CMOS input (Port 1): 5

• CMOS output (Ports 2 and 3): 16
• CMOS I/O (Ports 0, 4 to 6, 8, and 9): 35
Total: 56

Table 5-1. Port Functions

Port Name Pin Name Function

Port 0 P00 to P07 I/O port. Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by means of software.

Port 1 P10 to P14 Input-only port.

Port 2 P20 to P27 Output-only port.

Port 3 P30 to P37 Output-only port.

Port 4 P40 to P44 I/O port. Input/output can be specified in 1-bit units.

Port 5 P50 to P54 I/O port. Input/output can be specified in 1-bit units.

Port 6 P60, P61 I/O port. Input/output can be specified in 1-bit units.

Port 8 P81 to P87 I/O port. Input/output can be specified in 1-bit units.
The I/O port/segment signal output function can be specified in 2-bit units by means of the
LCD display control register (LCDC).

Port 9 P90 to P97 I/O port. Input/output can be specified in 1-bit units.
The I/O port/segment signal output function can be specified in 2-bit units by means of the
LCD display control register (LCDC).

Data Sheet U14577EJ1V0DS 17

 µPD780851(A), 780852(A)

5.2 Clock Generator

A main system clock generator is incorporated.
The minimum instruction execution time can be changed.
• 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation)

Figure 5-1. Clock Generator Block Diagram

Prescaler

X1 Main
system fX Clock to
Prescaler
clock peripheral hardware
X2 oscillator

fX/2 fX/22 fX/23 fX/24

STOP

Selector
Standby CPU
controller clock (fCPU)

5.3 Timer/Event Counter

Six timer/event counter channels are incorporated.
• 16-bit timer: 1 channel
• 8-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel

Table 5-2. Operations of Timer/Event Counters

16-Bit Timer 8-Bit Timer 8-Bit Watch Timer Watchdog

TM0 TM1 Timer/Event Timer
Counters
TM2, TM3

Operation Interval timer − 1 channel 2 channels 1 channel 1 channel

mode
External event counter − − 2 channels − −

Function Timer output − − 2 outputs − −

PWM output − − 2 outputs − −

Pulse width 3 inputs − − − −

measurement

Square wave output − − 2 outputs − −

Division output 1 output − − − −

Interrupt requests 4 1 2 2 1

18 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Figure 5-2. Block Diagram of 16-Bit Timer 0 TM0

fX/8

Selector
fX/16 16-bit timer
register (TM0) INTOVF
fX/32
fX/64

Noise Prescaler Edge 16-bit capture

TI02/P42 1, 1/2, 1/4, 1/8 register 02 (CR02)
eliminator detector

INTTM02

Noise Edge 16-bit capture

TI01/P41
eliminator detector register 01 (CR01)

INTTM01

Noise Edge
TI00/P40 16-bit capture
eliminator detector
register 00 (CR00)

INTTM00
Output
TPO/PCL/P60
controller

Internal bus

Figure 5-3. Block Diagram of 8-Bit Timer 1 TM1

Internal bus

8-bit compare
register 1 (CR1)

Match
INTTM1
3
fX/2
fX/24
Selector

fX/25
8-bit counter 1 (TM1)
fX/27
fX/29
fX/211 Clear

Internal bus

Data Sheet U14577EJ1V0DS 19

 µPD780851(A), 780852(A)

Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 2 TM2

Internal bus

8-bit compare
register 2 (CR2)

Match
Output
controller INTTM2
TIO2/P43
fX/23
Selector

fX/25 Output
8-bit counter 2 OVF TIO2/P43
fX/27 controller
fX/28 (TM2)
fX/29
fX/211 Clear

Internal bus

Figure 5-5. Block Diagram of 8-Bit Timer/Event Counter 3 TM3

Internal bus

8-bit compare
register 3 (CR3)

Match
Output
INTTM3
controller
TIO3/P44
fX/24
Selector

fX/26 Output
8-bit OVF TIO3/P44
fX/27 controller
fX/28 counter 3 (TM3)
fX/210
fX/212 Clear

Internal bus

20 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Figure 5-6. Watch Timer Block Diagram

Selector
fX/27 5-bit counter INTWT

Selector
fW
Prescaler
fX/211
fW fW fW fW fW fW
24 25 26 27 28 29

Selector
INTWTI

Figure 5-7. Watchdog Timer Block Diagram

fX/28 Prescaler

fW fW fW fW fW fW fW fW
212 213 214 215 216 217 218 220 INTWDT
maskable
interrupt request

Controller
Selector
RESET
INTWDT
non-maskable
interrupt request

5.4 Clock Output Controller

Clocks with the following frequencies can be output as clock output.
• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.04 MHz/2.09 MHz/4.19 MHz/8.38 MHz (@ 8.38 MHz operation with main
system clock)

Figure 5-8. Block Diagram of Clock Output Controller

fX

fX/2

fX/22
Selector

fX/23
Clock controller Output controller PCL/TPO/P60
fX/24

fX/25

fX/26

fX/27

Data Sheet U14577EJ1V0DS 21

 µPD780851(A), 780852(A)

5.5 A/D Converter

An A/D converter consisting of five 8-bit resolution channels is incorporated.
The following two types of functions are available.
• 8-bit resolution A/D conversion
• Power-fail detection function

Figure 5-9. A/D Converter Block Diagram

Series resistor string

ANI0/P10 Sample & hold circuit AVREF

ANI1/P11
Selector

Voltage comparator

Tap selector
ANI2/P12
ANI3/P13
ANI4/P14

AVSS
Successive approximation
register (SAR)

Controller INTAD

A/D conversion
result register (ADCR1)

Internal bus

Figure 5-10. Block Diagram of Power-Fail Detection Function

Selector

ANI0/P10
Multiplexer

ANI1/P11 INTAD
ANI2/P12 A/D converter Comparator
ANI3/P13
ANI4/P14

Power-fail
comparison threshold
register (PFT)

Internal bus

22 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

5.6 Serial Interface

Three serial interface channels are incorporated.
• Serial interface UART
• Serial interface SIO2
• Serial interface SIO3

Figure 5-11. Block Diagram of Serial Interface UART

Internal bus

Receive buffer Direction controller

register (RXB)

Transmit shift
Direction controller register (TXS)

RxD/P53 Receive shift Transmit controller INTST

register (RXS)

TxD/P54

INTSER
Receive controller
INTSR

Selector
Baud rate fSCK
fX/2 to fX/28
generator

Figure 5-12. Block Diagram of Serial Interface SIO2

Internal bus

Receive
buffer register

SI2/P05 Serial I/O shift

register (SIO2)

SO2/P04

SCK2/P03 Serial clock counter INTCSI2

fX/29 to fX/211
Selector

Serial clock controller

Data Sheet U14577EJ1V0DS 23

 µPD780851(A), 780852(A)

Figure 5-13. Block Diagram of Serial Interface SIO3

Internal bus

Serial I/O
SI3/P52
shift register (SIO3)

SO3/P51

SCK3/P50 Serial clock counter INTCSI3

Selector
fX/22 to fX/24
Serial clock controller

5.7 LCD Controller/Driver

An LCD controller/driver with following functions is incorporated.
• Display mode: 1/4 duty (1/3 bias)
• 15 of the segment signal outputs can be switched to I/O ports in 2-output units (P81/S19 to P87/S13 and
P90/S12 to P97/S5).
Figure 5-14. LCD Controller/Driver Block Diagram

Internal bus
fX
Prescaler
214
fX fX fX
Display
217 216 215
data memory
Selector

LCDCL
Timing controller

Segment Port
data selector output data

LCD drive
voltage generator
Segment driver Common driver

... ......

S0 ... S4 S5/P97 ...... S19/P81 COM0 COM1 COM2 COM3 VLCD

24 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

5.8 Sound Generator

The sound generator is a function for generating a buzzer sound by externally connecting a speaker. The
following signal is output from the sound generator.
• Basic cycle output signal
This is a buzzer output signal of variable frequency. Signals of 0.12 to 4.0 kHz (when fx = 8.38 MHz) can be
output by setting bits 0 to 2 (SGCL0 to SGCL2) of the sound generator control register (SGCR).
The basic cycle output signal can be used to change the amplitude of the 7-bit resolution PWM signal for
variable amplitude, enabling the dynamics of the buzzer sound to be expressed.

Figure 5-15. Sound Generator Block Diagram

fX
Selector

Basic cycle
5-bit counter
PWM generator

Selector
fX/2 SGO/P61

Amplitude
generator

Internal bus

5.9 Meter Controller/Driver

The meter controller/driver is a function for driving an externally connected stepper motor or cross-coil for meter
control.
• 8-bit precision pulse width can be set
• 8 + 1-bit precision pulse width can be set using a 1-bit addition function
• Up to four 360°-type meters can be driven

Figure 5-16. Meter Controller/Driver Block Diagram

Internal bus

Compare register
Selector

fX
SMn1 (sin+)
PWM pulse generator Output controller
SMn2 (sin )
fX/2

Remark n = 1 to 4

Data Sheet U14577EJ1V0DS 25

 µPD780851(A), 780852(A)

6. INTERRUPT FUNCTION

A total of 21 interrupt sources are provided, divided into the following three types.
• Non-maskable interrupts: 1
• Maskable interrupts: 19
• Software interrupts: 1

Table 6-1. Interrupt Source List

Interrupt Default Interrupt Source Internal/ Vector Basic

Type PriorityNote 1 Name Trigger External Table ConfigurationNote 2
Address
Non- − INTWDT Watchdog timer overflow (with non-maskable Internal 0004H (A)
maskable interrupt selected)
Maskable 0 INTWDT Watchdog timer overflow (with interval timer (B)
selected)
1 INTAD End of A/D conversion 0006H
2 INTOVF 16-bit timer overflow 0008H
3 INTTM00 TI00 valid edge detection 000AH (C)
4 INTTM01 TI01 valid edge detection 000CH
5 INTTM02 TI02 valid edge detection 000EH
6 INTP0 Pin input edge detection External 0010H (D)
7 INTP1 0012H
8 INTP2 0014H
9 INTCSI3 End of serial interface SIO3 transfer Internal 0016H (B)
10 INTSER Occurrence of serial interface UART reception error 0018H
11 INTSR End of serial interface UART reception 001AH
12 INTST End of serial interface UART transmission 001CH
13 INTTM1 Generation of matching signal of 8-bit timer register 001EH
and capture register (CR1)
14 INTTM2 Generation of matching signal of 8-bit timer register 0020H
and capture register (CR2)
15 INTTM3 Generation of matching signal of 8-bit timer register 0022H
and capture register (CR3)
16 INTCSI2 End of serial interface SIO2 transfer 0024H
17 INTWTI Watch timer overflow 0026H
18 INTWT Reference time interval signal of watch timer 0028H
Software − BRK Execution of BRK instruction − 003EH (E)

Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest priority and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.

26 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Figure 6-1. Basic Configuration of Interrupt Function (1/2)

(A) Internal non-maskable interrupt

Internal bus

Interrupt Priority Vector table

request controller address generator

Standby
release signal

(B) Internal maskable interrupt

Internal bus

MK IE PR ISP

Priority Vector table

Interrupt
IF controller address generator
request

Standby
release signal

(C) Internal maskable interrupt (16-bit timer capture input)

Internal bus

Prescaler mode register (PRM0) MK IE PR ISP

Priority Vector table

Interrupt Sampling Edge IF controller address generator
request clock detector

Standby
release signal

Data Sheet U14577EJ1V0DS 27

 µPD780851(A), 780852(A)

Figure 6-1. Basic Configuration of Interrupt Function (2/2)

(D) External maskable interrupt (except 16-bit timer capture input)

Internal bus

External interrupt edge MK IE PR ISP

enable register (EGP, EGN)

Interrupt Priority Vector table

Edge address generator
request IF controller
detector

Standby
release signal

(E) Software interrupt

Internal bus

Interrupt Priority Vector table

request controller address generator

IF: Interrupt request flag

IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag

28 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

7. STANDBY FUNCTION
The following two types of standby function are available for further reduction of system current consumption.

• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operating mode.
• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the
main system clock are suspended, resulting in extremely small power consumption.

Figure 7-1. Standby Function

Main system clock operation

HALT
STOP instruction
Interrupt instruction Interrupt
request
request

STOP mode HALT mode

 Main system clock  Clock supply to CPU halted,
 oscillation stopped   oscillation maintained 

8. RESET FUNCTION

The following two reset methods are available.

• External reset by RESET signal input

• Internal reset by watchdog timer runaway time detection

Data Sheet U14577EJ1V0DS 29

 µPD780851(A), 780852(A)

9. INSTRUCTION SET

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ

2nd [HL+ Byte]

Operand
#byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None
1st
[HL + C]
Operand
A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR
ADDC XCH XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP
r MOV MOV INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C DBNZ
sfr MOV MOV
saddr MOV MOV DBNZ INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte] MOV
[HL + B]
[HL + C]
X MULU
C DIVUW
Note Except r = A

30 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand
# word AX rpNote sfrp saddrp !addr16 SP None
1st Operand
AX ADDW MOVW MOVW MOVW MOVW MOVW
SUBW XCHW
CMPW
rp MOVW MOVWNote INCW, DECW
PUSH, POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
Note Only when rp = BC, DE, HL

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

2nd Operand
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
1st Operand
A.bit MOV BT SET1
BF CLR1
BTCLR
sfr.bit MOV1 BT SET1
BF CLR1
BTCLR
saddr.bit MOV1 BT SET1
BF CLR1
BTCLR
PSW.bit MOV1 BT SET1
BF CLR1
BTCLR
[HL].bit MOV1 BT SET1
BF CLR1
BTCLR
CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1
AND1 AND1 AND1 AND1 AND1 CLR1
OR1 OR1 OR1 OR1 OR1 NOT1
XOR1 XOR1 XOR1 XOR1 XOR1

(4) Call instructions/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX !addr16 !addr11 [addr5] $addr16
1st Operand
Basic instruction BR CALL CALLF CALLT BR, BC, BNC,
BR BZ, BNZ
Compound instruction BT, BF
BTCLR
DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

Data Sheet U14577EJ1V0DS 31

 µPD780851(A), 780852(A)

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°°C)

Parameter Symbol Conditions Ratings Unit

Supply voltage VDD −0.3 to +6.5 V

AVREF −0.3 to VDD + 0.3 V

AVSS −0.3 to +0.3 V

SMVDD SMVDD = VDD −0.3 to +6.5 V

SMVSS −0.3 to +0.3 V

Input voltage VI −0.3 to VDD + 0.3 V

Output voltage VO1 P00 to P07, P40 to P44, P50 to P54, P60, −0.3 to VDD + 0.3 V
P61, P81 to P87, P90 to P97, RESET

VO2 P20 to P27, P30 to P37 −0.5 to SMVDD + 0.7 V

Analog input voltage VAN P10 to P14 Analog input pin AVSS − 0.3 to AVREF + 0.3 V

Output current, high IOH Per pin (P00 to P07, P40 to P44, P50 to −10 mA
P54, P60, P81 to P87, P90 to P97)

Total for P00 to P07, P40 to P44, P50 to −15 mA

P54, P60, P81 to P87, P90 to P97

P61 −30 mA

Per pin (P20 to P27) −45 mA

Total for P20 to P27 −135 mA

Per pin (P30 to P37) −45 mA

Total for P30 to P37 −135 mA

Output current, low IOL Per pin (P00 to P07, P40 to P44, P50 to 20 mA
P54, P60, P81 to P87, P90 to P97)

Total for P00 to P07, P40 to P44, P50 to 50 mA

P54, P60, P81 to P87, P90 to P97

P61 30 mA

Per pin (P20 to P27) 45 mA

Total for P20 to P27 135 mA

Per pin (P30 to P37) 45 mA

Total for P30 to P37 135 mA

Operating ambient temperature TA −40 to +85 °C

Storage temperature Tstg −65 to +150 °C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.

32 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Capacitance (TA = 25°°C, VDD = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input capacitance CIN f = 1 MHz 15 pF

I/O capacitance CIO Unmeasured pins returned to 0 V. 15 pF

Output COUT f = 1 MHz P00 to P07, P40 to P44, P50 to 15 pF

capacitance Unmeasured pins P54, P60, P81 to P87, P90 to P97
returned to 0 V.
CSM P20 to P27, P30 to P37, P61 40 pF

Main System Clock Oscillator Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Ceramic Oscillation VDD = OSCM = 00H 4.0 8.38 MHz

resonator X2 X1 IC frequency (fX)Note 1 Oscillation
OSCM = 80H 4.0 4.19 MHz
voltage range

Oscillation After VDD reaches oscillation 4 ms

C2 C1 stabilization timeNote 2 voltage range MIN.

Crystal Oscillation VDD = OSCM = 00H 4.0 8.38 MHz

resonator X2 X1 IC frequency (fX)Note 1 Oscillation
OSCM = 80H 4.0 4.19 MHz
voltage range

Oscillation After VDD reaches oscillation 10 ms

C2 C1 stabilization timeNote 2 voltage range MIN.

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.

Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.

Data Sheet U14577EJ1V0DS 33

 µPD780851(A), 780852(A)

 Recommended Oscillator Constant

−40 to +85°°C)
Main system clock: Ceramic resonator (−
8.38 MHz oscillation mode (OSCM = 00H)
Manufacturer Part Number Frequency Recommended Oscillation Remarks
(MHz) Circuit Constant Voltage
Range

C1 C2 MIN. MAX.
(pF)Note (pF)Note (V) (V)

Murata Mfg. Co., Ltd CSTLS4M00G56A-B0 4.0 47 47 4.0 5.5 On-chip capacitor

CSTCR4M00G55A-R0 4.0 39 39

CSTLS4M19G56A-B0 4.194 47 47

CSTCR4M19G55A-R0 4.194 39 39

CSTLS5M00G53A-B0 5.0 15 15

CSTCR5M00G53A-R0 5.0 15 15

CSTLS8M00G53A-B0 8.0 15 15

CSTCC8M00G53A-R0 8.0 15 15

CSTLS8M38G53A-B0 8.388 15 15

CSTCC8M38G53A-R0 8.388 15 15

Note Indicates the capacitance of the on-chip capacitor.

4.19 MHz oscillation mode (OSCM = 80H)

Manufacturer Part Number Frequency Recommended Oscillation Remarks
(MHz) Circuit Constant Voltage
Range

C1 C2 MIN. MAX.
(pF)Note (pF)Note (V) (V)

Murata Mfg. Co., Ltd CSTLS4M00G53A-B0 4.0 15 15 4.0 5.5 On-chip capacitor

CSTCR4M00G53A-R0 4.0 15 15

CSTLS4M19G53A-B0 4.194 15 15

CSTCR4M19G53A-R0 4.194 15 15

Note Indicates the capacitance of the on-chip capacitor.

34 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

DC Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Output current, high IOH1 P00 to P07, P40 to P44, Per pin −5 mA
P50 to P54, P60, P81 to
Total −10 mA
P87, P90 to P97

Output current, low IOL1 P00 to P07, P40 to P44, Per pin 10 mA
P50 to P54, P60, P81 to
Total 20 mA
P87, P90 to P97

Input voltage, high VIH1 P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 0.7VDD VDD V

VIH2 P00 to P07, P40 to P44, P50, P52, P53 0.7VDD VDD V

VIH3 RESET 0.8VDD VDD V

Input voltage, low VIL1 P10 to P14, P51, P54, P60, P61, P81 to P87, P90 to P97 0 0.3VDD V

VIL2 P00 to P07, P40 to P44, P50, P52, P53 0 0.3VDD V

VIL3 RESET 0 0.2VDD V

Output voltage, high VOH1 P00 to P07, P40 to P44, IOH = −1 mA VDD − 1.0 VDD V
P50 to P54, P60, P81 to
P87, P90 to P97

VOH2 P20 to P27, P30 to P37 IOH = −27 mA (TA = 85°C) VDD − 0.5 VDD − 0.07 V

IOH = −30 mA (TA = 25°C) VDD − 0.5 VDD − 0.07 V

IOH = −40 mA (TA = −40°C) VDD − 0.5 VDD − 0.07 V

VOH3 P61 IOH = −20 mA VDD − 0.5 V

Output voltage, low VOL1 P00 to P07, P40 to P44, IOL = 1.6 mA 0.4 V
P50 to P54, P60, P81 to
P87, P90 to P97

VOL2 P20 to P27, P30 to P37 IOL = 27 mA (TA = 85°C) 0.07 0.5 V

IOL = 30 mA (TA = 25°C) 0.07 0.5 V

IOL = 40 mA (TA = −40°C) 0.07 0.5 V

VOL3 P61 IOL = 20 mA 0.5 V

Input leakage ILIH1 P00 to P07, P10 to P14, VIN = VDD 3 µA

current, high P40 to P44, P50 to P54,
P60, P61, P81 to P87,
P90 to P97

Input leakage ILIL1 P00 to P07, P10 to P14, VIN = 0 V −3 µA

current, low P40 to P44, P50 to P54,
P60, P61, P81 to P87,
P90 to P97

Output leakage ILOH VOUT = VDD 3 µA

current, high

Output leakage ILOL VOUT = 0 V −3 µA

current, low

Software pull-up R VIN = 0 V, P00 to P07 10 30 100 kΩ

resistor

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.

Data Sheet U14577EJ1V0DS 35

 µPD780851(A), 780852(A)

DC Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Note 2
Power IDD1 8.38 MHz oscillation operating mode 7 21 mA
supply

Note 2, 3
4.19 MHz oscillation operating mode 3.5 10.5 mA
currentNote 1
Note 2
IDD2 8.38 MHz oscillation HALT mode 0.8 1.6 mA
Note 3
4.19 MHz oscillation HALT mode 0.5 1.0 mA

IDD3 STOP mode 1.0 30 µA

Notes 1. Refers to the current flowing to the CPU, peripheral functions (internal circuits), oscillator, and VDD pin.
The current flowing to the series resistor string of an A/D converter, on-chip pull-up resistors, LCD division
resistor, sound generator (SGO/P61), and meter controller/driver (SM11/P20 to SM14/P23, SM21/P24 to
SM24/P27, SM31/P30 to SM34/P33, SM41/P34 to SM44/P37) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Operation when the oscillator mode register (OSCM) is set to 80H

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.

LCD Controller/Driver Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

1/3 bias mode

Parameter Symbol Conditions MIN. TYP. MAX. Unit

LCD drive voltage VLCD 3.0 VDD V

LCD output voltage VODC IO = ±5 µA 3.0 V ≤ VLCD ≤ VDD 0 ±0.2 V

deviationNote
VLCD0 = VLCD
(Common)
VLCD1 = VLCD × 2/3
LCD output voltage VODS IO = ±1 µA 0 ±0.2 V
VLCD2 = VLCD × 1/3
deviationNote
(Segment)

LCD division ILCD 3.0 V ≤ VLCD < VDD 50 260 µA

resistance current

Note The voltage deviation is the difference between the output voltage and the ideal value of segment and
common outputs (VLCDn: n = 0, 1, 2). Since pins to which a reference voltage (VLCD1 and VLCD2) is applied do
not exist in the µPD780851(A),780852(A), the difference between the segment/common output voltage
generated by the internal division resistance and the ideal reference potential (VDD to 1/3VDD) is regarded as
the voltage deviation.

36 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

AC Characteristics

(1) Basic operation (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Cycle time (MIN. TCY Operating with main system clock 0.238 8 µs
instruction execution
time)

TI00 to TI02 input tTIH2, tTIL2 At capture trigger 3/fSAMNote µs

high-/low-level width TI00/P40 to TI02/P42

TIO2, TIO3 input fTI5 TIO2/P43, TIO3/P44 0 4 MHz

frequency

TIO2, TIO3 input tTIH5, tTIL5 TIO2/P43, TIO3/P44 100 ns

high-/low-level width

Interrupt request input tINTH, tINTL INTP0 to INTP2 1 µs

high-/low-level width

RESET low-level width tRSL 10 µs

Note Selection of fSAM = fX/8, fX/16, fX/32, fX/64 is possible with bits 0 and 1 (PRM00, PRM01) of the prescaler mode
register (PRM0).

TCY vs. VDD (main system clock operation)

10.0
fX = 4.00 MHz, PCC = 04H

5.0
Cycle time TCY [µs]

Guaranteed
operation
range
1.0

0.5

fX = 8.38 MHz, PCC = 00H

0.1
0 1.0 2.0 3.0 4.0 5.0 6.0
5.5

Supply voltage VDD [V]

Data Sheet U14577EJ1V0DS 37

 µPD780851(A), 780852(A)

(2) Serial interface (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

(a) UART mode (Dedicated baud rate generator output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Transfer rate 130.9 kbps

(b) 3-wire serial I/O mode (SIO3)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK3 cycle time tKCY1 800 ns

SCK3 high-/low-level width tKH1, tKL1 Internal clock selected tKCY1/2 − 50 ns

External clock selected 400 ns

SI3 setup time (to SCK3↑) tSIK1 100 ns

SI3 hold time (from SCK3↑) tKSI1 400 ns

Note
Delay time from SCK3↓ to SO3 output tKSO1 C = 100 pF 300 ns

Note C is the load capacitance of the SCK3 and SO3 output lines.

(c) 3-wire serial I/O mode (SIO2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK2 cycle time tKCY2 800 ns

SCK2 high-/low-level width tKH2, tKL2 Internal clock selected tKCY1/2 − 50 ns

External clock selected 400 ns

SI2 setup time (to SCK2↑) tSIK2 100 ns

SI2 hold time (from SCK2↑) tKSI2 400 ns

Note
Delay time from SCK2↓ to SO2 output tKSO2 C = 100 pF 300 ns

Note C is the load capacitance of the SCK2 and SO2 output lines.

AC Timing Test Points (excluding X1 input)

0.8VDD 0.8VDD
Test points
0.2VDD 0.2VDD

Clock Timing

1/fX

tXL tXH

X1 input VDD 0.5 V

0.4 V

38 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

TI Timing

tTIL2 tTIH2

TI00 to TI02

1/fTI5

tTIL5 tTIH5

TIO2, TIO3

Serial Transfer Timing

3-wire serial I/O mode

tKCY1, 2
tKL1, 2 tKH1, 2

SCK

tSIK1, 2 tKSI1, 2

SI Input data

tKSO1, 2

SO Output data

Data Sheet U14577EJ1V0DS 39

 µPD780851(A), 780852(A)

Sound Generator Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Sound generator input frequency fSG1 4.19 MHz

Note
SGO output rise time tr C = 100 pF 80 200 ns
Note
SGO output fall time tf C = 100 pF 80 200 ns

Note C is the load capacitance of the SGO output line.

Sound Generator Output Timing

tr tf

0.9VDD
SGO
0.1VDD

Meter Controller/Driver Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Meter controller input frequency fMCNote 1 4.19 MHz

Note 2
PWM output rise time tr C = 100 pF 80 200 ns
Note 2
PWM output fall time tf C = 100 pF 80 200 ns

Symmetry performance Note 3

∆HSPmn IOH = −30 mA 50 mV
∆HSPmn = I VOH (SMmn) max − VOH (SMmn) min I

∆LSPmn IOL = 30 mA 50 mV
∆LSPmn = I VOL (SMmn) max − VOL (SMmn) min I

Notes 1. Source clock of the free-running counter.

2. C is the load capacitance of the PWM output line.
3. Indicates the dispersion of 16 PWM output voltages.

Remark m = 1 to 4, n = 1 to 4

Meter Controller/Driver Output Timing

tr tf

0.9VDD
SMmn
0.1VDD

Remark m = 1 to 4, n = 1 to 4

40 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

A/D Converter Characteristics (TA = −40 to +85°°C, AVREF = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 8 bit

±0.6
Note
Overall error %FSR

Conversion time tCONV 14.0 µs

Analog input voltage VIAN AVSS AVREF + 0.3 V

Reference voltage AVREF 4.0 VDD V

Resistance between AVREF and IADD A/D converter operating (ADCS1 = 1) 1.0 2.0 mA
AVSS
A/D converter not operating (ADCS1 = 0) 1.0 10 µA

Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value.

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention supply voltage VDDDR 2.0 5.5 V

Data retention power supply current IDDDR VDDDR = 2.0 V 0.1 10 µA

Release signal set time tSREL 0 µs

17
Oscillation stabilization wait time tWAIT Release by RESET 2 /fX s

Release by interrupt request Note s

12 14 17
Note Selection of 2 /fX and 2 /fX to 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).

Data Retention Timing (STOP mode release by RESET)

Internal reset operation

HALT mode

STOP mode Operating mode

Data retention mode

VDD
VDDDR tSREL
STOP instruction execution

RESET

tWAIT

Data Sheet U14577EJ1V0DS 41

 µPD780851(A), 780852(A)

Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)

HALT mode

STOP mode Operating mode

Data retention mode

VDD
VDDDR tSREL

STOP instruction execution

Standby release signal

(interrupt request)
tWAIT

Interrupt Request Input Timing

tINTL tINTH

INTP0 to INTP2

RESET Input Timing

tRSL

RESET

42 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

11. PACKAGE DRAWING

80-PIN PLASTIC QFP (14x14)

60 41
61 40

detail of lead end

C D

R
Q

80 21
1 20

J
G H I M

P
K
S

N S L

NOTE
M
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of A 17.20±0.20
its true position (T.P.) at maximum material condition. B 14.00±0.20
C 14.00±0.20
D 17.20±0.20
F 0.825
G 0.825
H 0.32±0.06
I 0.13
J 0.65 (T.P.)
K 1.60±0.20
L 0.80±0.20
M 0.17 +0.03
−0.07
N 0.10
P 1.40±0.10
Q 0.125±0.075
R 3° +7°
−3°
S 1.70 MAX.
P80GC-65-8BT-1

Data Sheet U14577EJ1V0DS 43

 µPD780851(A), 780852(A)

 12. RECOMMENDED SOLDERING CONDITIONS

The µPD780851(A), 780852(A) should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.

Table 12-1. Surface Mounting Type Soldering Conditions

×××-8BT: 80-pin plastic QFP (14 × 14)

µPD780851GC(A)-×××
×××
×××-8BT: 80-pin plastic QFP (14 × 14)
µPD780852GC(A)-×××
×××

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-2
Count: Twice or less

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-2
Count: Twice or less

Wave soldering Soldering bath temperature: 260°C or less, Time: 10 seconds max., WS60-00-1
Count: Once, Preheating temperature: 120°C max. (package surface temperature)

Partial heating Pin temperature: 300°C or less, Time: 3 seconds max. (per pin row) −

Caution Do not use different soldering methods together (except for partial heating).

44 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD780851(A) and 780852(A).
Also refer to (6) Cautions on Using Development Tools.

(1) Software Package

SP78K0 Software Package common to 78K/0 Series

(2) Language Processing Software

RA78K0 Assembler package common to 78K/0 Series

CC78K0 C compiler package common to 78K/0 Series

DF780852 Device file for µPD780852 Subseries

CC78K0-L C compiler library source file common to 78K/0 Series

(3) Flash Memory Writing Tools

Flashpro III (Part No. Dedicated flash programmer for microcomputers incorporating flash memory
FL-PR3, PG-FP3)

(4) Debugging Tools

IE-78K0-NS(-A) In-circuit emulator common to 78K/0 Series

IE-70000-MC-PS-B Power supply unit for IE-78K0-NS

IE-78K0-NS-PA Performance board to enhance/expand functions of IE-78K0-NS

IE-780852-NS-EM4, Probe board and I/O board used to emulate µPD780852 Subseries products
IE-78K0-NS-P04

IE-70000-98-IF-C Interface adapter necessary when using PC-9800 series PC (except notebook type) as host machine
(C bus supported)

IE-70000-CD-IF-A PC card and interface cable necessary when using notebook PC as host machine (PCMCIA socket
supported)

IE-70000-PC-IF-C Interface adapter necessary when using IBM PC/ATTM compatible as host machine (ISA bus
supported)

IE-70000-PCI-IF-A Adapter necessary when using personal computer incorporating PCI bus as host machine

NP-80GC-TQ Emulation probe for 80-pin plastic QFP (GC-8BT type)

SM78K0 System simulator common to 78K/0 Series

ID78K0-NS Integrated debugger for IE-78K0-NS

DF780852 Device file for µPD780852 Subseries

Data Sheet U14577EJ1V0DS 45

 µPD780851(A), 780852(A)

(5) Real-time OS
RX78K0 Real-time OS for 78K/0 Series

MX78K0 OS for 78K/0 Series

(6) Cautions on Using Development Tools

• The ID78K0-NS and SM78K0 are used in combination with the DF780852.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780852.
• The FL-PR3 and NP-80GC-TQ are products made by Naitou Densei Machidaseisakusho Co., Ltd. (TEL +81-
45-475-4191).
• For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machine and OS suitable for each software are as follows:

Host Machine PC EWS

[OS] PC-9800 series [Japanese WindowsTM]
HP9000 series 700TM [HP-UXTM]
IBM PC/AT and compatibles
SPARCstationTM [SunOSTM, SolarisTM]
Software [Japanese/English Windows]
RA78K0 √Note √

CC78K0 √ Note
√

ID78K0-NS √ −

SM78K0 √ −

RX78K0 √ Note
√

MX78K0 √ Note
√

Note DOS-based software

46 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

APPENDIX B. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.

• Documents Related to Devices

Document Name Document No.

µPD780852 Subseries User's Manual U14581E

µPD780851(A), 780852(A) Data Sheet This document

µPD78F0852 Data Sheet U14576E

78K/0 Series User's Manual Instructions U12326E

• Documents Related to Development Tools (User’s Manuals)

Document Name Document No.

RA78K0 Assembler Package Operation U11802E

Language U11801E

Structured Assembly U11789E

Language

CC78K0 C Compiler Operation U11517E

Language U11518E

PG-FP3 Flash Memory Programmer U13502E

IE-78K0-NS In-Circuit Emulator U13731E

IE-78K0-NS-A In-Circuit Emulator U14889E

IE-780852-NS-EM4, IE-78K0-NS-P04 To be prepared

SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based Operation U14611E

SM78K Series System Simulator Ver. 2.10 or Later External Part User Open U15006E
Interface Specifications

ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based Operation U14379E

ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Operation U14910E
Based

ID78K0 Integrated Debugger Windows Based Guide U11649E

Reference U11539E

Data Sheet U14577EJ1V0DS 47

 µPD780851(A), 780852(A)

• Documents Related to Embedded Software (User’s Manuals)

Document Name Document No.

78K/0 Series Real-Time OS Fundamental U11537E

Installation U11536E

78K/0 Series OS MX78K0 Fundamental U12257E

• Other Related Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769E

Semiconductor Device Mounting Technology Manual C10535E

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.

48 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

[MEMO]

Data Sheet U14577EJ1V0DS 49

 µPD780851(A), 780852(A)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

FIP and IEBus are trademarks of NEC Corporation.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS and Solaris are trademarks of Sun Microsystems, Inc.

50 Data Sheet U14577EJ1V0DS

 µPD780851(A), 780852(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 408-588-6000 Eindhoven, The Netherlands Tel: 2886-9318
800-366-9782 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 408-588-6130 Fax: 040-2444580
800-729-9288 NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A. Seoul Branch
NEC Electronics (Germany) GmbH Velizy-Villacoublay, France Seoul, Korea
Duesseldorf, Germany Tel: 01-3067-5800 Tel: 02-528-0303
Tel: 0211-65 03 02 Fax: 01-3067-5899 Fax: 02-528-4411
Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
NEC Electronics (UK) Ltd. Madrid Office Novena Square, Singapore
Milton Keynes, UK Madrid, Spain Tel: 253-8311
Tel: 01908-691-133 Tel: 091-504-2787 Fax: 250-3583
Fax: 01908-670-290 Fax: 091-504-2860
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Taipei, Taiwan
Milano, Italy Scandinavia Office Tel: 02-2719-2377
Tel: 02-66 75 41 Taeby, Sweden Fax: 02-2719-5951
Fax: 02-66 75 42 99 Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829

J01.2

Data Sheet U14577EJ1V0DS 51

 µPD780851(A), 780852(A)

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

• The information in this document is current as of October, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4