MIMXRT1170HDUG

Hardware Development Guide for the MIMXRT1160/1170 Processor

Rev. 5 — 3 July 2023 User guide

Document Information
Information Content
Keywords MIMXRT1170, tightly-coupled memory (TCM), on-chip RAM (OCRAM)
Abstract The purpose of this document is to help hardware engineers design and test their MIMXRT1170
processor-based designs. It provides information about board layout recommendations and
design checklists to ensure first-pass success and avoid board bring-up problems.
NXP Semiconductors
MIMXRT1170HDUG
Hardware Development Guide for the MIMXRT1160/1170 Processor

1 Introduction
The purpose of this document is to help hardware engineers design and test their MIMXRT1170 processor-
based designs. It provides information about board layout recommendations and design checklists to ensure
first-pass success and avoid board bring-up problems. This guide is released along with the relevant device-
specific hardware documentation such as data sheets, reference manuals, and application notes available on
nxp.com.
Note: RT1160 shares the same design with RT1170, so engineers can also use this document for RT1160.

2 Background
The i.MX RT1170 is a new processor family featuring NXP advanced implementation of the high performance
Arm Cortex-M7 Core and power efficient Arm Cortex-M4 core. It provides high CPU performance and real-time
response.
The i.MX RT1170 has 2 MB of on-chip RAM in total. It includes a 512 kB RAM which can be flexibly configured
as tightly coupled memory (TCM) or general purpose on-chip RAM (OCRAM). The i.MX RT1170 integrates
advanced power management module with DC-DC and LDOs that reduce complexity of external power supply
and simplify power sequencing.
It provides various memory interfaces, including SDRAM, Raw NAND FLASH, NOR FLASH, SD/eMMC, Quad
SPI, Hyper RAM/Flash. It also provides a wide range of other interfaces for connecting external peripherals,
such as WLAN, Bluetooth, GPS, displays, and camera sensors. The i.MX RT1170 has rich audio and video
2
features, including MIPI CSI/DSI, LCD display, graphics accelerator, camera interface, S/PDIF, and I S audio
interface.
The i.MX RT1170 applications processor can be used in areas such as industrial HMI, IoT, high-end audio
appliance, low-end instrument cluster, point-of-sale (PoS), motor control, and home appliances.

3 Power supply
For power supply voltage specifications, refer to the operating ranges table in the device data sheets*. See
Table 1 and Table 2 for power supply decoupling recommendations.
Note: The Figure 1 in this section is applicable to RT1170 silicon. These tables do not include the on-chip LDO
output specification, which can be found in the device data sheet*.

Table 1. Processor supply capacitors when on-chip DC-DC regulators are used
1 1 1 1 1 1
Power rail 0.1 μF 0.22 μF 1 μF 2.2 μF 4.7 μF 22 μF Notes
DCDC_IN 1 1 1 Place 0402 under balls M5, N5.
Place 0603 as close as possible to
the processor.
DCDC_ANA 1 Place under ball M7
DCDC_ANA_SENSE 1 Place under ball M6
DCDC_DIG 1 1 Place 0402 under ball K8. Place
0603 as close as possible to the
processor.
DCDC_DIG_SENSE 1 Place under ball L7
VDDA_1P8_IN 1 Place under ball M11

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Table 1. Processor supply capacitors when on-chip DC-DC regulators are used...continued
1 1 1 1 1 1
Power rail 0.1 μF 0.22 μF 1 μF 2.2 μF 4.7 μF 22 μF Notes
VDD_SOC_IN_X 1 2 2 1 Place 0402 under balls H8, H10,
J8, J10, K10. Place 0603 as close
as possible to the processor.
VDD_LPSR_IN 1 Place under ball R12
VDD_LPSR_ANA 1 Place under ball P12
VDD_LPSR_DIG 1 Place under ball P11
VDD_SNVS_IN 1 Place under ball U12
VDD_SNVS_ANA 1 Place under ball U14
VDD_SNVS_DIG 1 Place under ball T14
VDD_USB_1P8 1 Place under ball H12, isolate from
1V8 source with series ferrite bead
(120 ohm@100MHz)
VDD_USB_3P3 1 Place under ball G12, isolate from
3V3 source with series ferrite bead
(120 ohm@100MHz)
VDDA_ADC_1P8 1 Place under ball K15
VDDA_ADC_3P3 1 Place under ball J13
VDDA_1P0 1 Place under ball N11
VDD_MIPI_1P8 1 Place under ball F9, isolate from
1V8 source with series ferrite bead
(120 ohm@100MHz)
VDD_MIPI_1P0 1 Place under ball F10, power source
is on-chip LDO regulator VDDA_1
P0
NVCC_SD1 1 Place under ball D14
NVCC_SD2 1 Place under ball G13
NVCC_EMC1_X 1 1 Place 2.2 μF under balls F6, F7
NVCC_EMC2_X 1 1 Place 2.2 μF under balls H6, J6
NVCC_GPIO 1 1 Place 2.2 μF under ball M12
NVCC_DISP1 1 Place under ball D12
NVCC_DISP2 1 Place under ball E7
NVCC_LPSR 1 Place under ball P7
NVCC_SNVS 1 Place under ball U11
2
ADC_VREFH 1 Place under ball G16
USB1_VBUS 1 Place under ball D17
USB2_VBUS 1 Place under ball D16

1. 0.1, 0.22, 1, 2.2, 4.7 μF are size 0402, type X5R. 22 µF is size 0603, type X5R.
2. Avoid using the internal DCDC/LDO output for the ADC reference. Use an external voltage reference, which
is more accurate.

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Table 2. Processor supply capacitors when external PMIC or regulators utilized (on-chip DC-DC regulators not
used)
1 1 1 1 1 1
Power rail 0.1 μF 0.22 μF 1 μF 2.2 μF 4.7 μF 22 μF Notes
VDD_SOC_IN_x 2 3 1 Place 0402 under balls H8, J8, J9,
J10, K10
VDD_LPSR_IN 1 Place under ball R12
VDD_LPSR_ANA 1 Place under ball P12
VDD_LPSR_DIG 1 Place under ball P11
VDDA_ADC_3P3 1 1 Place 1 μF under ball J13, place
0.1 μF near J13, isolate from 3V3
source with series ferrite bead (120
ohm@100MHz)
2
ADC_VREFH 1 Place under ball G16
VDDA_ADC_1P8 1 1 Place 1 μF under ball K15, place
4.7 μF near K15, isolate from 1V8
source with series ferrite bead (120
ohm@100MHz)
VDDA_1P8_IN 1 Place under ball M11
VDDA_1P0 1 Place under ball N11
VDD_SNVS_IN 1 Place under ball U12
VDD_SNVS_ANA 1 Place under ball U14
VDD_SNVS_DIG 1 Place under ball T14
NVCC_SNVS 1 Place under ball U11
NVCC_LPSR 1 Place under ball P7
NVCC_GPIO 1 1 Place 2.2 μF under ball M12
NVCC_SD1 1 Place under ball D14
NVCC_SD2 1 Place under ball G13
NVCC_DISP1 1 Place under ball D12
NVCC_DISP2 1 Place under ball E7
NVCC_EMC1_X 1 1 Place under balls F7, G6
NVCC_EMC2_X 1 1 Place under balls H6, J6
VDD_MIPI_1P8 1 Place under ball F9, isolate from
1V8 source with series ferrite bead
(120 ohm@100MHz)
VDD_MIPI_1P0 1 Place under ball F10, power source
is on-chip LDO regulator VDDA_1
P0
VDD_USB_1P8 1 Place under ball H12, isolate from
1V8 source with series ferrite bead
(120 ohm@100MHz)
VDD_USB_3P3 1 Place under ball G12, isolate from
3V3 source with series ferrite bead
(120 ohm@100MHz)
USB1_VBUS 1 Place under ball D17

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Table 2. Processor supply capacitors when external PMIC or regulators utilized (on-chip DC-DC regulators not
used)...continued
1 1 1 1 1 1
Power rail 0.1 μF 0.22 μF 1 μF 2.2 μF 4.7 μF 22 μF Notes
USB2_VBUS 1 Place under ball D16

1. 0.1 μF, 0.22 μF, 1 μF, 2.2 μF, and 4.7 μF are size 0402 and 22 μF is size 0805. Type X6S is used for
automotive cluster and extended temperature range.
2. Avoid using the internal DCDC/LDO output for the ADC reference. Use an external voltage reference, which
is more accurate.

Table 3. Power supply and SNVS domain signals

Item Recommendation Description
Power sequence To guarantee a reliable operation of the Any deviation from these sequences may result in these
device, comply with the power-up/power- situations:
down sequence guidelines (as described in • Excessive current during the power-up phase
the data sheet*). • Prevention of the device from booting
• Irreversible damage to the processor
(worst-case scenario)
SNVS domain Do not overload the coincell backup power Concerning i.MX RT1170:
signals rail VDD_SNVS_IN. • The chip internal LDO VDD_SNVS_ANA output power
These I/Os are associated with VDD_ capacity is 1 mA and should be tied together with
SNVS_IN (most inputs have on-chip pull NVCC_SNVS.
resistors and do not require external • Be careful to use SNVS signals to drive external load
resistors): as the SNVS GPIO drive is low. For more details, refer
• PMIC_STBY_REQ—configurable output to the i.MX RT1170 data sheet*.
• PMIC_ON_REQ—push-pull output • By default, the part number determines the functionality
• TEST_MODE—on-chip pull-down of GPIO_SNVS_XX pin. Tamper function is available
• POR—on-chip pull-up only on tamper-enabled parts, and GPIO is the only
available function on parts which do not support
• WAKEUP—the GPIO that wakes up the
tamper. The MUX_MODE must be configured to select
SoC in the SNVS mode
the function in both cases.
• GPIO_SNVS_XX—on-chip pull-down
• The GPIO_SNVS_XX pins automatically switch
to tamper function in the SNVS mode even on the
part where GPIO function is supported. For more
details, refer to i.MX RT1170 Chip Errata (document i.
MXRT1170CE).
• Access delay occurs on the GPIO_SNVS_xx signals
due to the module's 32 kHz clock source.
Power ripple Maximum ripple voltage limitation. The common limitation for the ripple noise shall be less
than 5 % Vp-p of the supply voltage average value. The
related power rails affected are VDD_XXX, VDD_XXX_
IN, VDDA_1P0, VDD_XXX_ANA, VDD_XXX_DIG.
Supply currents Maximum supply currents comply with Concerning i.MX RT1170:
maximum supply currents in data sheet*. • The DCDC_DIG_X output power capacity is 850 mA
and DCDC_ANA_X output power capacity is 150 mA.
• Do not use DCDC_ANA_X to drive load higher than
150mA.
• For frequencies higher than 600 MHz and up to 800
MHz, refer to the CM7 power source guideline table in
the i.MX RT1170 data sheet* for automotive products.

Power Sequence Requirements:

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• For power supply sequencing requirements, refer to section 4.2.1 of i.MX RT1170 Crossover Processors Data
Sheet for Industrial Products (document IMXRT1170IEC).
The power control logic of the IMXRT1170 EVK board is shown in Figure 1.
• It powers up SNVS first, then PMIC_REQ_ON is asserted to enable external DC-DC to power up other power
domains.
• ON/OFF button is used to switch PMIC_REQ_ON to control power modes.
• RESET button and WDOG output are used to reset the system power.

ONOFF

SNVS_IN
LDO
NVCC_XX
VDD_LPSR_IN
IN VDDA_ADC_3V3
5 V input
OUT DCDC_IN
Reset button DC/DC MIMXRT1170
EN DCDC_DIG system
Reset IC
VDD_SOC_IN

1 ms R/C DCDC_PSWITCH
delay

PMIC_REQ_ON
WDOG

Figure 1. Power control diagram

*To refer to i.MX RT1170 data sheets, see Section 9.

3.1 On-chip DC-DC module

The internal DC-DC of RT1170 has two outputs. One output (VDD_DIG) typical 0.7 V~1.15 V, another output
(VDD_ANA) typical 1.8 V, and its switching frequency is about 1.5 MHz.
The DC-DC requires external inductor and capacitors, as described in Figure 2. Pay attention to the below
items:
• The recommended value for the external inductor is about 4.7 μH with the saturation current > 1.5 A and ESR
< 0.1 Ω.
• The external bulk capacitor total is about 66 μF. It includes all the capacitors used on DCDC_DIG_X and
VDD_SOC_IN.
• DCDC_PSWITCH should delay 1 ms with respect to DCDC_IN to guarantee that DCDC_IN is stable before
the DC-DC starts up.
• If you want to bypass the internal DC-DC, DCDC_PSWITCH and DCDC_MODE must be tied to the ground.
Other signals such as DCDC_IN, DCDC_LP, DCDC_LN, DCDC_ANA, DCDC_ANA_SENSE, DCDC_DIG,
and DCDC_DIG_SENSE can be floating.
• Try to keep the DC-DC current loop as small as possible to avoid EMI issues.

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VDD_3V3 VDD_1V8_OUT
DCDC_IN DCDC_ANA
30 kΩ DCDC_PSWITCH DCDC_ANA_SENSE
4.7 μF
10 μF
0.22 μF
0.1 μF
GND GND
GND GND
DCDC_LP
VDD_SOC_IN
2
DC/DC 22 μF
4.7 μH

1 DCDC_LN GND
DCDC_DIG 0.7 ~ 1.15 V

DCDC_DIG_SENSE 22 μF 22 μF

0.1 μF
GND
GND

Figure 2. DC-DC function diagram

Note: The on-chip DC-DC regulator of the processor is suitable for consumer and industrial applications up to
105 degrees C. For automotive applications, contact your NXP representative.

4 Clocks
See Table 4 for the clock configuration. The 32.768 kHz and 24 MHz oscillators are used for the EVK design.
For RT1170, it is necessary to use 32.768 kHz and 24 MHz crystals for the hardware design.

Table 4. Clocks configurations

Signal name Recommended connections Description
RTC_XTALI/RTC_XTALO For the precision 32.768 kHz oscillator, To hit the exact oscillation frequency,
connect a crystal between RTC_XTALI the board capacitors must be reduced
and RTC_XTALO. Choose a crystal to account for the board and chip
with a maximum ESR (Equivalent parasitics. The integrated oscillation
Series Resistance) of 100 k and follow amplifier is self-biasing, but relatively
the recommendation by manufacturer weak. Care must be taken to limit the
for the loading capacitance. Do not use parasitic leakage from RTC_XTALI and
an external biasing resistor because the RTC_XTALO to either the power or
bias circuit is on the chip. the ground (>100 M). This de-biases
the amplifier and reduces the startup
margin.
For the external kHz source (if feeding If you want to feed an external
an external clock into the device), RTC_ low-frequency clock into RTC_
XTALI can be driven DC-coupled with XTALI, the RTC_XTALO pin must
RTC_XTALO floating or driven by a remain unconnected or driven by a
complimentary signal. complementary signal. The logic level
of this forcing clock must not exceed
the VDD_SNVS_DIG level and the
frequency shall be <100 kHz under the
typical conditions.
An on-chip loose-tolerance ring When a high-accuracy real-time clock
oscillator of approximately 32 kHz is is not required, the system may use the
available. If RTC_XTALI is tied to GND on-chip 32 kHz oscillator. The tolerance
and RTC_XTALO is floating, the on-chip is ±25 %. The ring oscillator starts
oscillator is engaged automatically. faster than the external crystal and is
used until the external crystal reaches a
stable oscillation. If no clock is detected

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Table 4. Clocks configurations...continued

Signal name Recommended connections Description
at RTC_XTALI at any time, the ring
oscillator also starts automatically.
XTALI/XTALO For the precision 24 MHz oscillator, The SDK software requires 24 MHz on
connect a fundamental-mode crystal XTALI/XTALO.
between XTALI and XTALO. A typical The crystal can be eliminated if an
80 ESR crystal rated for a maximum external 24 MHz oscillator is available
drive level of 250 μW is acceptable. in the system. In this case, refer to
Alternately, a typical 50 ESR crystal section of Bypass Configuration (24
rated for a maximum drive level of 200 MHz) from the i.MX RT1170 Processor
μW may be used. Reference Manual (document
For the RT1170 24 MHz OSCILLATOR, IMXRT1170RM). For the bypass mode
the smaller the ESR, the better the pin connection, the external bypass
startup and power consumption. clock can be put in from EXTAL pin. At
To use the high-power mode, populate the same time, XTALO can be used as
the 1 MΩ resistor between XTALI and other functions.
XTALO. The logic level of this forcing clock must
Use a crystal with ESR < 100 Ω and CL not exceed the VDD_LPSR_ANA level.
<= 16 pF for startup. If this clock is used as a reference for
the USB and Ethernet, then there are
strict frequency tolerance and jitter
requirements. The ±50 ppm accuracy
is required for the Ethernet while the
±100 ppm accuracy is required for the
USB. For more details, see Crystal
Oscillator (XTALOSC) chapter in i.MX
RT1170 Processor Reference Manual
(document IMXRT1170RM).
CLK1_P/CLK1_N Internal use only These pins are used for NXP internal
testing. The CLK1_P and CLK1_N pair
should be left floating.

5 Debugging and programming

This section provides the JTAG interface summary and recommendations for using the JTAG, SWD debug, and
Serial downloader I/O.
Note: By default, the RT1170 silicon can use both SWD and JTAG modes using the Arm stitching sequence.
For the RT1170EVK board, it defaults to use the SWD debug without any board modification. If you want to use
the JTAG debug, solder out R187, R208, R195, and R78, because some JTAG signals are multiplexed with
other functions.
The MIMXRT1170-EVK also features a FreeLink circuit, which makes it easier to debug without an external
debugger.

Table 5. JTAG interface summary

1
JTAG signals I/O type On-chip termination External termination
JTAG_TCK Input Pull-down Not required
JTAG_TMS Input Pull-up Not required; can use 10 kΩ pull-up
JTAG_TDI Input Pull-up Not required; can use 10 kΩ pull-up
JTAG_TDO 3-state output None Do not use pullup or pull-down

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Table 5. JTAG interface summary...continued

1
JTAG signals I/O type On-chip termination External termination
JTAG_TRSTB Input Pull-up For the JTAG_TRSTB pin, it is
recommended to add a 4.7 kΩ external
pull-down resistor for mass production.
When in the developing state, this 4.7 kΩ
resistor can be removed.
To use other functions on this pin (such as
GPIO, Timer, and so on), switch JTAG_
TCK and JTAG_TMS first, and then switch
the setting of JTAG_TRSTB.
JTAG_MOD Input Pull-down Use 4.7 kΩ pull-down or tie to GND

1. For on-chip termination values, refer to table 115 of i.MX RT1170 Crossover Processors Data Sheet for
Industrial Products (document IMXRT1170IEC).

Table 6. JTAG recommendation

Signals Recommendation Description
JTAG_TDO Do not add external pull-up or pull-down See Table 5 for a summary of the JTAG interface.
resistors on JTAG_TDO. This I/O has an on-chip keeper circuit which
avoids a floating condition.
JTAG signals other than Ensure that the on-chip pull-up/pull-down External resistors can be used with all JTAG
JTAG_TDO and JTAG_ configuration is followed if external resistors signals except for JTAG_TDO, but they are not
MOD are used with the JTAG signals (except for required. See Table 5 for a summary of the JTAG
JTAG_TDO). For example, do not use an interface.
external pull-down on an input that has an on-
chip pull-up.
JTAG_MOD JTAG_MOD is called SJC_MOD in some When JTAG_MOD is low, the JTAG interface is
documents. Both names refer to the same configured for a common software debug, adding
signal. JTAG_MOD shall be externally all the system TAPs to the chain.
connected to GND for normal operation in a When JTAG_MOD is low, the JTAG interface
system. The termination to GND through an is also configured to a mode compliant with the
external pull-down resistor is allowed. Use a IEEE 1149.1 standard.
4.7 kΩ resistor.

Table 7. SWD recommendation

Signals Recommendation Description
SWD_DIO Same practice as JTAG_TMS On the RT1170EVK board, the SWD debug port is used by default.
There is also a low-cost on-board Freelink debugger using the SWD
SWD_CLK Same practice as JTAG_CLK
port.

The Serial Downloader mode of ROM provides a means to download a program image to the chip over USB or
UART serial connection. In this mode, typically a host PC can communicate to the ROM bootloader using serial
download protocol. NXP ROM flashloader also uses these same serial connections. All boards should make at
least one of the serial downloader ports (USB1 or UART1) available to use NXP image and fuse programming
enablement.

Table 8. Serial downloader I/Os table

Signals Recommendation Description
UART1 The serial downloader provides a means to download a The ROM polls for the UART1 and USB1
program image to the chip over the USB and UART serial activity circularly until the ROM gets 0x5A,
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Table 8. Serial downloader I/Os table...continued

Signals Recommendation Description
USB1 connections. In this mode, if the WDOG_ENABLE eFuse is 0xA6 from the UART RXD or first HID
1 and continuously polls for the USB and UART connection, report from the USB bus. When an active
the ROM loads the value from fuse and sets it as the WDOG connection port is found, the ROM uses it
time-out time (for details, see chapter 26 in i.MX RT1170 for the PC downloading.
Processor Reference Manual (document IMXRT1170RM)).
If no activity is found on the USB OTG1 and UART1 and the
watchdog timer expires, the Arm core is reset.

6 Boot, reset, and miscellaneous

See Table 9 for the boot, reset, and miscellaneous configurations, such as ON/OFF, TEST_MODE, NC pins,
and other.

Table 9. Boot configuration

Item Recommendation Description
BOOT_CFG[11:0] The BOOT_CFG signals are required For the correct boot configuration, see
for a proper functionality and operation. the "System Boot" chapter in your chip
1
If BOOT_CFG fuses and BT_FUSE_ reference manual .
SEL are not configured, the signals Note: An incorrect setting may result in
shall not be left floating during an improper boot sequence.
development. Take the fuse setting for the boot_CFG
in production. Burn the BT_FUSE_SEL
and BOOT_CFG fuses accordingly.
BOOT_MODE[1:0] For logic 0: BOOT_MODE1 and BOOT_MODE0
• Tie to GND through 100 K external each has on-chip pull-down devices
resistor with a nominal value of 35 kΩ. When
For logic 1: the on-chip fuses determine the boot
configuration, both boot mode inputs
• Tie to the NVCC_LPSR power domain
can be disconnected.
through a 4.7 K external resistor
BOOT_CFG and BOOT_MODE signals As the BOOT_CFG pins are Refer to the EVK design for reference
multiplexed with RGMII signals multiplexed with RGMII signals, and try to avoid signal stubs in layout.
add 22 K isolation resistors to avoid
malfunction. For BOOT_MODE pins,
add 4.7 K isolation resistors.

1. i.MX RT1170 Processor Reference Manual (document IMXRT1170RM)

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VDD_1V8 VDD_3V3 VDD_3V3

20
19
18

16
15
14
17

13
12
11

8
7
6
5
SW2 SW1
416131160810 416131160804
1
2
3
4
5
6
7
8
9
10

1
2
3
4
Bus isolation resistors
R56 47 kΩ BT_CFG[0] R356 22 kΩ
GPIO_DISP_B1_06 {7, 19}
R54 47 kΩ BT_CFG[1] R355 22 kΩ
GPIO_DISP_B1_07 {7, 19}
R46 47 kΩ BT_CFG[2] R353 22 kΩ
GPIO_DISP_B1_08 {7, 19}
R36 47 kΩ BT_CFG[3] R352 22 kΩ
GPIO_DISP_B1_09 {7, 19}
R31 47 kΩ BT_CFG[4] R346 22 kΩ
GPIO_DISP_B1_10 {7, 19}
R29 47 kΩ BT_CFG[5] R344 22 kΩ
GPIO_DISP_B1_11 {7, 19}
R28 47 kΩ BT_CFG[6] R340 22 kΩ
GPIO_DISP_B2_00 {7}
R24 47 kΩ BT_CFG[7] R336 22 kΩ
GPIO_DISP_B2_01 {7, 16}
R23 47 kΩ BT_CFG[8] R334 22 kΩ
GPIO_DISP_B2_02 {7, 18}
R21 47 kΩ BT_CFG[9] R331 22 kΩ
GPIO_DISP_B2_03 {7, 18}
R32 47 kΩ BT_CFG[10] R350 22 kΩ
GPIO_DISP_B2_04 {7, 18}
R33 47 kΩ BT_CFG[11] R349 22 kΩ
GPIO_DISP_B2_05 {7, 18}

R34 100 kΩ BOOT_MODE[0] R348 4.7 kΩ

GPIO_LPSR_02 {7}
R35 100 kΩ BOOT_MODE[1] R347 4.7 kΩ
GPIO_LPSR_03 {7}

GND On-chip defaults:

BT_CFG[11:0] = Hign-Z
BOOTMODE[1:0] = 25-50 kΩ PD

Figure 3. Boot mode setting

Table 10. Reset and miscellaneous recommendations

Item Recommendation Description
POR_B The POR_B input (if used) must be For the correct boot configuration, see
immediately asserted at power-up the "System Boot" chapter in your chip
1
and remain asserted until after the reference manual .
last power rail reaches its working Note: An incorrect setting may result
voltage. In the absence of an external from an improper boot sequence.
reset feeding the POR_B input, the POR_B signal has internal 100 K pull
internal POR module takes control. up to SNVS domain. It should pull up
For further details and to ensure that to VDD_SNVS_ANA if need to add
all requirements are being met, see external pull up resistor. Otherwise, it
1
reference manual . causes additional leakage during SNVS
mode.
Add the external reset IC to the circuit
to guarantee POR_B is properly
processed during power up/down, refer
to the EVK design for details.
Note:
1. As the Low DCDC_IN detection
threshold is 2.6 V, the reset threshold
of reset IC must be higher than 2.6 V.
Then the whole chip is reset before
the internal DC-DC module reset to
guarantee the chip safety during power
down.

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Table 10. Reset and miscellaneous recommendations...continued

Item Recommendation Description
2. For power on reset, on any
conditions ones must make sure the
voltage on DCDC_PSWITCH PIN is
below 0.5 V before power up.
ON/OFF For portable applications, the ON/OFF A brief connection to GND in the
input may be connected to the ON/ OFF mode causes the internal
OFF SPST push-button. The on-chip power management state machine
debouncing is provided, and this input to change the state to ON. In the ON
has an on-chip pullup. If not used, ON/ mode, a brief connection to GND
OFF can be a no-connect. A 4.7 kΩ to generates an interrupt (intended to be
10 kΩ series resistor can be used when a software-controllable power-down).
the current drain is critical. Approximately 5 seconds (or more) to
GND causes a forced OFF.
TEST_MODE The TEST_MODE input is internally This input is reserved for NXP
connected to an on-chip pull-down manufacturing use.
device. You may either float this signal
or tie it to GND.

1. i.MX RT1170 Processor Reference Manual (document IMXRT1170RM)

Table 11. ROM bootloader peripheral PinMux

Peripheral Instance Port (IO function) PAD Mode Note
LPUART 1 LPUART1_TX GPIO_AD_24 ALT0 Can be used for serial
downloader mode. For more
LPUART1_RX GPIO_AD_25 ALT0
information, refer to Serial
downloader in reference
1
manual .
LPSPI 1 LPSPI1_SCK GPIO_AD_28 ALT0 Serial NOR/EEPROM
connected to one of the LPSPI
LPSPI1_PCS0 GPIO_AD_29 ALT0
ports can be used as a recovery
LPSPI1_SDO GPIO_AD_30 ALT0 device.
For more information, refer to
LPSPI1_SDI GPIO_AD_31 ALT0
Recovery devices in reference
1
2 LPSPI2_SCK GPIO_SD_B2_07 ALT6 manual .
Note: Recovery device boot
LPSPI2_PCS0 GPIO_SD_B2_08 ALT6
is disabled by default. Fuses
LPSPI2_SDO GPIO_SD_B2_09 ALT6 must be blown to enable and
configure this option.
LPSPI2_SDI GPIO_SD_B2_10 ALT6
3 LPSPI3_SCK GPIO_DISP_B1_04 ALT9
LPSPI3_PCS0 GPIO_DISP_B1_07 ALT9
LPSPI3_SDO GPIO_DISP_B1_06 ALT9
LPSPI3_SDI GPIO_DISP_B1_05 ALT9
4 LPSPI4_SCK GPIO_DISP_B2_12 ALT9
LPSPI4_PCS0 GPIO_DISP_B2_15 ALT9
LPSPI4_SDO GPIO_DISP_B2_14 ALT9
LPSPI4_SDI GPIO_DISP_B2_13 ALT9
SEMC NAND N/A SEMC_DATA00 GPIO_EMC_B1_00 ALT0 Parallel NAND flash connected
to the SEMC is a primary boot
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Table 11. ROM bootloader peripheral PinMux...continued

Peripheral Instance Port (IO function) PAD Mode Note
SEMC_DATA01 GPIO_EMC_B1_01 ALT0 option. For more information,
refer to Parallel NAND flash
SEMC_DATA02 GPIO_EMC_B1_02 ALT0 Boot over SEMC in reference
1
SEMC_DATA03 GPIO_EMC_B1_03 ALT0 manual .

SEMC_DATA04 GPIO_EMC_B1_04 ALT0

SEMC_DATA05 GPIO_EMC_B1_05 ALT0
SEMC_DATA06 GPIO_EMC_B1_06 ALT0
SEMC_DATA07 GPIO_EMC_B1_07 ALT0
SEMC_DATA08 GPIO_EMC_B1_30 ALT0
SEMC_DATA09 GPIO_EMC_B1_31 ALT0
SEMC_DATA10 GPIO_EMC_B1_32 ALT0
SEMC_DATA11 GPIO_EMC_B1_33 ALT0
SEMC_DATA12 GPIO_EMC_B1_34 ALT0
SEMC_DATA13 GPIO_EMC_B1_35 ALT0
SEMC_DATA14 GPIO_EMC_B1_36 ALT0
SEMC_DATA15 GPIO_EMC_B1_37 ALT0
SEMC_ADDR09 GPIO_EMC_B1_18 ALT0
SEMC_ADDR11 GPIO_EMC_B1_19 ALT0
SEMC_ADDR12 GPIO_EMC_B1_20 ALT0
SEMC_BA1 GPIO_EMC_B1_22 ALT0
SEMC_CSX0 GPIO_EMC_B1_41 ALT0
uSDHC 1 USDHC1_CD_B GPIO_AD_32 ALT4 eMMC/MMC or SD/eSD
connected to one of the USDHC
USDHC1_WP GPIO_AD_33 ALT4
ports is a primary boot option.
USDHC1_VSELECT GPIO_AD_34 ALT4 For more information, refer to
Expansion device in reference
USDHC1_RESET_B GPIO_AD_35 ALT4 manual .
1

USDHC1_CMD GPIO_SD_B1_00 ALT0

USDHC1_CLK GPIO_SD_B1_01 ALT0
USDHC1_DATA0 GPIO_SD_B1_02 ALT0
USDHC1_DATA1 GPIO_SD_B1_03 ALT0
USDHC1_DATA2 GPIO_SD_B1_04 ALT0
USDHC1_DATA3 GPIO_SD_B1_05 ALT0
2 USDHC2_CD_B GPIO_AD_26 ALT11
USDHC2_WP GPIO_AD_27 ALT11
USDHC2_VSELECT GPIO_AD_28 ALT11
USDHC2_DATA3 GPIO_SD_B2_00 ALT0
USDHC2_DATA2 GPIO_SD_B2_01 ALT0
USDHC2_DATA1 GPIO_SD_B2_02 ALT0

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Table 11. ROM bootloader peripheral PinMux...continued

Peripheral Instance Port (IO function) PAD Mode Note
USDHC2_DATA0 GPIO_SD_B2_03 ALT0
USDHC2_CLK GPIO_SD_B2_04 ALT0
USDHC2_CMD GPIO_SD_B2_05 ALT0
USDHC2_RESET_B GPIO_SD_B2_06 ALT0
USDHC2_DATA4 GPIO_SD_B2_08 ALT0
USDHC2_DATA5 GPIO_SD_B2_09 ALT0
USDHC2_DATA6 GPIO_SD_B2_10 ALT0
USDHC2_DATA7 GPIO_SD_B2_11 ALT0
FlexSPI1 1 FLEXSPI1_B_ GPIO_SD_B2_00 ALT1 QSPI memory attached to
DATA3 FlexSPI is a primary boot option.
For more information, refer
FLEXSPI1_B_ GPIO_SD_B2_01 ALT1
to Serial NOR Flash Boot via
DATA2 1
FlexSPI in reference manual .
FLEXSPI1_B_ GPIO_SD_B2_02 ALT1 The ROM reads the 512 byte
DATA1 FlexSPI NOR configuration
parameters described in
FLEXSPI1_B_ GPIO_SD_B2_03 ALT1 FlexSPI Serial NOR Flash Boot
DATA0 Operation in reference manual
1

FLEXSPI1_B_SCLK GPIO_SD_B2_04 ALT1 using the non-italicized pins.

Note: These pins are a
FLEXSPI1_B_DQS GPIO_SD_B1_05 ALT8 secondary pinout option for
FLEXSPI1_B_SS0_ GPIO_SD_B1_04 ALT8 FlexSPI serial NOR flash boot.
B
FLEXSPI1_B_SS1_ GPIO_SD_B1_03 ALT9
B
FLEXSPI1_A_DQS GPIO_SD_B2_05 ALT1
FLEXSPI1_A_SS0_ GPIO_SD_B2_06 ALT1
B
FLEXSPI1_A_SS1_ GPIO_SD_B1_02 ALT9
B
FLEXSPI1_A_SCLK GPIO_SD_B2_07 ALT1
FLEXSPI1_A_ GPIO_SD_B2_08 ALT1
DATA0
FLEXSPI1_A_ GPIO_SD_B2_09 ALT1
DATA1
FLEXSPI1_A_ GPIO_SD_B2_10 ALT1
DATA2
FLEXSPI1_A_ GPIO_SD_B2_11 ALT1
DATA3
FLEXSPI1_A_DQS GPIO_EMC_B2_18 ALT6 Second option
FlexSPI2 (QSPI / 2 FLEXSPI2_B_ GPIO_EMC_B1_41 ALT4 Octal serial NOR flash memory
HyperFLASH) DATA7 attached to FlexSPI is a
primary boot option. For more
FLEXSPI2_B_ GPIO_EMC_B2_00 ALT4
information, refer to Serial
DATA6
NOR Flash Boot via FlexSPI in

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Table 11. ROM bootloader peripheral PinMux...continued

Peripheral Instance Port (IO function) PAD Mode Note
1
FLEXSPI2_B_ GPIO_EMC_B2_01 ALT4 reference manual . The ROM
DATA5 reads the 512 byte FlexSPI
NOR configuration parameters
FLEXSPI2_B_ GPIO_EMC_B2_02 ALT4 described in FlexSPI Serial
DATA4 NOR Flash Boot Operation in
1
FLEXSPI2_B_ GPIO_EMC_B2_03 ALT4 reference manual using the
DATA3 non-italicized pins. For 8-bit
wide memories, the FLEXSPI_
FLEXSPI2_B_ GPIO_EMC_B2_04 ALT4 B_DATA[3:0] pins are combined
DATA2 with the FLEXSPI_A_DATA[3:0]
lines to get the full 8-bit port.
FLEXSPI2_B_ GPIO_EMC_B2_05 ALT4
DATA1 Note: ROM can configure the
italicized signals based on the
FLEXSPI2_B_ GPIO_EMC_B2_06 ALT4 FlexSPI NOR configuration
DATA0 parameters provided.
FLEXSPI2_B_DQS GPIO_EMC_B2_07 ALT4
FLEXSPI2_B_SS0_ GPIO_EMC_B2_08 ALT4
B
FLEXSPI2_B_SCLK GPIO_EMC_B2_09 ALT4
FLEXSPI2_A_SCLK GPIO_EMC_B2_10 ALT4
FLEXSPI2_A_SS0_ GPIO_EMC_B2_11 ALT4
B
FLEXSPI2_A_DQS GPIO_EMC_B2_12 ALT4
FLEXSPI2_A_ GPIO_EMC_B2_13 ALT4
DATA0
FLEXSPI2_A_ GPIO_EMC_B2_14 ALT4
DATA1
FLEXSPI2_A_ GPIO_EMC_B2_15 ALT4
DATA2
FLEXSPI2_A_ GPIO_EMC_B2_16 ALT4
DATA3
FLEXSPI2_A_ GPIO_EMC_B2_17 ALT4
DATA4
FLEXSPI2_A_ GPIO_EMC_B2_18 ALT4
DATA5
FLEXSPI2_A_ GPIO_EMC_B2_19 ALT4
DATA6
FLEXSPI2_A_ GPIO_EMC_B2_20 ALT4
DATA7
GPIO_MUX2_IO08 GPIO_EMC_B1_40 ALT5 Second option
GPIO_MUX4_IO03 GPIO_SD_B1_00 ALT5 FlexSPI Reset
SEMC_ADDR09 GPIO_EMC_18 ALT0
SEMC_ADDR11 GPIO_EMC_19 ALT0
SEMC_ADDR12 GPIO_EMC_20 ALT0
SEMC_BA1 GPIO_EMC_22 ALT0

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Table 11. ROM bootloader peripheral PinMux...continued

Peripheral Instance Port (IO function) PAD Mode Note
SEMC_RDY GPIO_EMC_40 ALT0
SEMC_CSX0 GPIO_EMC_41 ALT0
SEMC_CSX1 GPIO_B0_00 ALT6
SEMC_CSX2 GPIO_B0_01 ALT6
SEMC_CSX3 GPIO_B0_02 ALT6
SEMC_ADDR08 GPIO_EMC_17 ALT0
FlexSPIN OR Flash- 1 FLEXSPI_B_DATA3 GPIO_SD_B1_00 ALT1 QSPI memory attached to
QSPI FlexSPI is a primary boot
FLEXSPI_B_DATA2 GPIO_SD_B1_01 ALT1
option. For more information,
FLEXSPI_B_DATA1 GPIO_SD_B1_02 ALT1 refer to Serial NOR Flash
Boot via FlexSPI in reference
FLEXSPI_B_DA TA0 GPIO_SD_B1_03 ALT1 1
manual . The ROM reads the
FLEXSPI_B_SCLK GPIO_SD_B1_01 ALT1 512 byte FlexSPI described in
FlexSPI Serial NOR Flash Boot
FLEXSPI_B_DQS GPIO_SD_B0_05 ALT4 Operation in reference manual
1

FLEXSPI_B_SS0_B GPIO_SD_B0_04 ALT4 using the non-italicized pins.

Note: ROM can configure the
FLEXSPI_B_SS1_B GPIO_SD_B0_01 ALT6 italicized signals based on the
FLEXSPI_A_DQS GPIO_SD_B1_05 ALT1 FlexSPI NOR configuration
parameters provided.
FLEXSPI_A_SS0_B GPIO_SD_B1_06 ALT1
FLEXSPI_A_SS1_B GPIO_SD_B0_00 ALT6
FLEXSPI_A_SCLK GPIO_SD_B1_07 ALT1
FLEXSPI_A_DATA0 GPIO_SD_B1_08 ALT1
FLEXSPI_A_DATA1 GPIO_SD_B1_09 ALT1
FLEXSPI_A_DATA2 GPIO_SD_B1_10 ALT1
FLEXSPI_A_DATA3 GPIO_SD_B1_11 ALT1
FlexSPIN OR-QSPI- 1 FLEXSPI_A_SS0_B GPIO_AD_B1_15 ALT0 QSPI memory attached to
2nd Option FlexSPI is a primary boot option.
FLEXSPI_A_SCLK GPIO_AD_B1_14 ALT0
for more information, refer to
FLEXSPI_A_DQS GPIO_AD_B1_09 ALT0 Serial NOR Flash Boot via
1
FlexSPI in reference manual .
FLEXSPI_A_DATA0 GPIO_AD_B1_13 ALT0 The ROMreadss the 512 byte
FLEXSPI_A_DATA1 GPIO_AD_B1_12 ALT0 FlexSPI NOR configuration
parameters described in
FLEXSPI_A_DATA2 GPIO_AD_B1_11 ALT0 FlexSPI Serial NOR Flash Boot
1
FLEXSPI_A_DATA3 GPIO_AD_B1_10 ALT0 Operation reference manual
using the non-italicized pins.
Note: These pins are a
secondary pinout option for
FlexSPI serial NOR flash boot.
FlexSPIN OR Flash- 1 FLEXSPI_B_DATA3 GPIO_SD_B1_00 ALT1 Octal serial NOR flash memory
Octal attached to FlexSPI is a
FLEXSPI_B_DATA2 GPIO_SD_B 1_01 ALT1
primary boot option. For more
FLEXSPI_B_DATA1 GPIO_SD_B1_02 ALT1 information, refer to Serial
NOR Flash Boot via FlexSPI in
FLEXSPI_B_DATA0 GPIO_SD_B1_03 ALT1 1
reference manual . The ROM
FLEXSPI_B_SCLK GPIO_SD_B1_01 ALT1 reads the 512 byte FlexSPI

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Table 11. ROM bootloader peripheral PinMux...continued

Peripheral Instance Port (IO function) PAD Mode Note
FLEXSPI_B_DQS GPIO_SD_B0_05 ALT4 NOR configuration parameters
described in FlexSPI Serial
FLEXSPI_B_SS0_B GPIO_SD_B0_04 ALT4 NOR Flash Boot Operation in
1
FLEXSPI_B_SS1_B GPIO_SD_B0_01 ALT6 reference manual using the
non-italicized pins. For 8-bit
FLEXSPI_A_DQS GPIO_SD_B1_05 ALT1 wide memories, the FLEXSPI_
B_DATA[3:0] pins are combined
FLEXSPI_A_SS0_B GPIO_SD_B1_06 ALT1
with the FLEXSPI_A_DATA[3:0]
FLEXSPI_A_SS1_B GPIO_SD_B0_00 ALT6 lines to get the full 8-bit port.
FlexSPI NOR configuration
FLEXSPI_A_SCLK GPIO_SD_B1_07 ALT1
parameters provided.
FLEXSPI_A_DATA0 GPIO_SD_B1_08 ALT1
FLEXSPI_A_DATA1 GPIO_SD_B1_09 ALT1
FLEXSPI_A_DATA2 GPIO_SD_B1_10 ALT1
FLEXSPI_A_DATA3 GPIO_SD_B1_11 ALT1
FlexSPI NAND Flash 1 FLEXSPI_A_DQS GPIO_SD_B1_05 ALT1 Serial NAND memory attached
to FlexSPI is a primary boot
FLEXSPI_A_SS0_B GPIO_SD_B1_06 ALT1
option. For more information,
FLEXSPI_A_SCLK GPIO_SD_B1_07 ALT1 refer to Serial NAND Flash
Boot over FlexSPI in reference
FLEXSPI_A_DATA0 GPIO_SD_B1_08 ALT1 manual .
1

FLEXSPI_A_DATA1 GPIO_SD_B1_09 ALT1

FLEXSPI_A_DATA2 GPIO_SD_B1_10 ALT1
FLEXSPI_A_DATA3 GPIO_SD_B1_11 ALT1
FlexSPI RESET GPIO1_IO29 GPIO_AD_B1_13 ALT5

1. i.MX RT1170 Processor Reference Manual (document IMXRT1170RM)

Note: ROM does not support boot from FLEXSPI_B port directly. ROM always seeks a valid Flash
Configuration Block from the FLEXSPI_A port and then reconfigures the FLEXSPI controller using the valid
parameters in the block read-out. This reconfiguration can include, but is not limited to, FLEXSPI_B port
support.

7 Layout recommendations

7.1 Stackup
A high-speed design requires a good stackup to have the right impedance for the critical traces.

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Figure 4. IMXRT1170EVK stackup

The constraints for the trace width depend on many factors. These factors are board stackup and the
associated dielectric and copper thickness, required impedance, and required current (for power traces). The
stackup also determines the constraints for routing and spacing. Consider the following when designing the
stackup and selecting the material for your board:
• The board stackup is critical for the high-speed signal quality.
• Preplan the impedance of the critical traces.
• The high-speed signals must have reference planes on adjacent layers to minimize crosstalk.
• The NXP reference design equals Isola FR4.
• The NXP validation boards equal Isola FR4.
• The recommended stackup is six layers, with the layer stack shown in Figure 4.The left-hand image shows
the detail provided by NXP inside the fabrication detail as a part of the Gerber files. The right-hand side
shows the solution suggested by the PCB fabrication company for the requirements. Figure 5 shows the
IMXRT1170EVK PCB stackup implementation.

Figure 5. IMXRT1170EVK stackup implementation

7.2 Placement of bulk and decoupling capacitors

Place the small decoupling capacitors and the larger bulk capacitors on the bottom side of the CPU. The 0402
decoupling capacitors and the 0603 bulk capacitors must be placed as close as possible to the power balls.
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Placing the decoupling capacitors close to the power balls is critical to minimize inductance and ensure the
high-speed transient current demand of the processor. The correct via size, trace width, and trace space are
critical to preserve the adequate routing space. The recommended geometry is as follows:
• For the BGA constraint area:
– The via type is 18/8 mils, the trace width is 4 mils, and the trace space is 3.79 mils.
• For the default area (except for the BGA):
– The via type is 18/8 mils, the trace width is 7 mils, and the trace space is 7 mils.
– The preferred BGA power-decoupling design layout is available at www.nxp.com.
– Use the NXP design strategy for power and decoupling.

7.3 FlexSPI
FlexSPI is a flexible SPI host controller which supports two SPI channels and up to 4 external devices. Each
channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines). FlexSPI is the
most commonly used external memory.
For more information, refer to section FlexSPI parameters from the data sheet (see Section 9). There are
several sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
– (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through
– DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from
– DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3)
For QSPI Flash without a DQS provided by the memory, only the option of FlexSPIn_MCR0[RXCLKSRC] = 0x1
can achieve 133 MHz SDR R/W speed, and FlexSPI_DQS pin should be left floating.
The Octal Flash, where a DQS signal is provided by the memory, must use the option of
FlexSPIn_MCR0[RXCLKSRC] = 0x3 which can achieve 166 MHz DDR R/W. In such case, FlexSPI_DQS pin
should be connected to the flash directly.

7.4 SDRAM
The SDRAM interface (running at up to 200 MHz) is one of the critical interfaces for the chip routing. The
controlled impedance for the single-ended traces must be 50 Ω. Ideally, route all signals at the same length as
the EVK board. To route all signals at the same length (±50 mils), see the IMXRT1170-EVK layout.
The SDRAM routing must be separated into two groups: data and address/control. To separate all SDRAM
signals into two groups, see the EVK layout:
• SEMC_DQS signal line should be left floating.
• All data lines and DM[x]
• All address lines and control lines
RT1170EVK is a 6-layer board design, both routing groups refer to the GND plane for the impedance control.
One group is routed at the top layer (the reference plane is the second layer), while the other group is routed at
the bottom layer (the reference plane is the fifth layer).

7.5 USB
Use these recommendations for the USB:
• Route the DP and DM differential pair first.
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• Route the DP and DM signals on the top (or bottom) layer of the board.
• The trace width and spacing of the DP and DM signals must meet the differential impedance requirement of
90 Ω.
• Route the traces over the continuous planes (power and ground):
– They must not pass over any power/GND plane slots or anti-etch.
– When placing the connectors, make sure that the ground plane clearouts around each pin have ground
continuity between all pins.
• Maintain the parallelism (skew-matched) between DP and DM, and match the overall differential length
difference to fewer than 5 mils.
• Maintain the symmetric routing for each differential pair.
• Do not route the DP and DM traces under the oscillators or parallel to the clock traces (and/or data buses).
• Minimize the lengths of the high-speed signals that run parallel to the DP and DM pair.
• Keep the DP and DM traces as short as possible.
• Route the DP and DM signals with a minimum number of corners. Use 45-degree turns instead of 90-degree
turns.
• Avoid layer changes (vias) on the DP and DM signals. Do not create stubs or branches.
• Provide the ground return vias within a 50 mil distance from the signal layer-transition vias when transitioning
between different reference ground planes.
• When the USB signals are not used, it is recommended to follow Section 8.

7.6 Ethernet
RT1170 has two Ethernet controllers, one is 10M/100M Ethernet controller with support for IEEE1588 and the
other one is Gigabit Ethernet controller with support for AVB/TSN. For the RGMII port, the layout is critical and
below are the guidelines.
• To ensure correct RGMII function, the length of PCB trace should be less than 15 cm with a 5 pF loading to
comply with maximum 1 ns delay regulation, and the total trace loading (5 pF input loading included) should
be within 15 pF.
• Clock and other high-speed traces must be as short as possible. It is necessary to have a GND plane under
these traces.
• RXC and TXC are high-speed (125 MHz) signals; Keep a 20 mil space between clock and data signals.
• Match each RGMII TX and RX (RXC/RXD/RXCTL/RXDV) group trace length to within +/-50mil.
• Route the RGMII traces at 50 ohm impedance, and make sure to route those traces over an unbroken GND
reference ground plane.
• For the RXC signal from the PHY, place R/C close to the PHY (fewer than 500 mils) and adjust the R/C value
to tune the timing.

7.7 High-speed signal routing recommendations

The following list provides recommendations for routing the traces for high-speed signals.
Note: The propagation delay and the impedance control must match to have a correct communication with the
devices.
• The high-speed signals (SDRAM, RMII, RGMII, USB, Display, HyperFlash, SD card) must not cross gaps in
the reference plane.
• Avoid creating slots, voids, and splits in the reference planes. To ensure that they do not create splits (space
out vias), review the via voids.
• Provide ground return vias within a 100 mil distance from the signal layer-transition vias when transitioning
between different reference ground planes.
• A solid GND plane must be directly under the crystal-associated components, and traces.
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• The clocks or strobes that are on the same layer need at least 2.5× spacing from the adjacent traces (2.5×
height from the reference plane) to reduce crosstalk.
• All synchronous modules must have the bus length matching and relative clock length control.
• For the SD module interfaces:
– Match the data, clock, and CMD trace lengths (length delta depends on the bus rates).
– Follow similar SDRAM rules for data, address, and control as for the SD module interfaces.
• For the RT1170 FlexSPI module to support QSPI flash, FlexSPI_DQS pin should be kept floating to achieve
high-speed access.

8 Unused pins recommendation

Table 12. Recommended connections for unused analog interfaces

Module Ball Name Recommendations if Unused
32 kHz OSC RTC_XTALI, RTC_XTALO Not connected
It is recommended that RTC_XTALI ties to GND if external crystal is
not connected.
ADC ADC_VREFH 10 kΩ resistor to ground
VDDA_ADC_1P8 10 kΩ resistor to ground
VDDA_ADC_3P3 10 kΩ resistor to ground
CCM CLK1_N, CLK1_P Not connected
DAC DAC_OUT Not connected
MIPI VDD_MIPI_1P0 For lowest leakage, 10 kΩ resistor to ground. For possible easier
layout but higher leakage, tie directly to power (inductors and
capacitors are not required). Leakage is typically 45 μA but could be a
few hundred μA at high temperature.
VDD_MIPI_1P8 For lowest leakage, 10 kΩ resistor to ground. For possible easier
layout but higher leakage, tie directly to power (inductors and
capacitors are not required). Leakage is typically 45 μA but could be a
few hundred μA at high temperature.
MIPI_DSI_CKN, MIPI_DSI_ Not connected
CKP, MIPI_DSI_DN0, MIPI_
DSI_DP0, MIPI_DSI_DN1,
MIPI_DSI_DP1
MIPI_CSI_CKN, MIPI_CSI_ Not connected
CKP, MIPI_CSI_DN0, MIPI_
CSI_DP0, MIPI_CSI_DN1,
MIPI_CSI_DP1
DCDC DCDC_IN, DCDC_IN_Q, Not connected
DCDC_DIG, DCDC_ANA
DCDC_DIG_SEANSE, DCDC_ Not connected
ANA_SENSE, DCDC_LP,
DCDC_LN
DCDC_PSWITCH, DCDC_ To ground
MODE
USB USB1_DN, USB1_DP, USB1_ Not connected
VBUS, USB2_DN, USB2_DP,
USB2_VBUS

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Table 12. Recommended connections for unused analog interfaces...continued

Module Ball Name Recommendations if Unused
VDD_USB_1P8 Tie directly to power; capacitors are not required.
VDD_USB_3P3 Tie directly to power; capacitors are not required.
SYS OSC XTALI, XTALO Not connected

Note: For unused digital IO, suggest tying low or configure it to pull down.

9 Related resources
• i.MX RT1170 Crossover Processors Data Sheet for Consumer Products (document IMXRT1170CEC)
• i.MX RT1170 Crossover Processors Data Sheet for Industrial Products (document IMXRT1170IEC)
• i.MX RT1170 Crossover Processors Data Sheet for Automotive Products (document IMXRT1170AEC)
• i.MX RT1170 Processor Reference Manual (document IMXRT1170RM)

10 Revision history
Table 13 summarizes the revisions to this document.

Revision history
Revision number Date Substantive changes
5 03 July 2023 • Updated capacitance value of VDDA_1P8_IN in Table 1 and Table 2
4 16 May 2023 • Updated Figure 2
• Updated few reference links
• Made few editorial changes
3 13 February • Added notes to Section 3.
2023 • Added a recommended setting for a 24 MHz crystal.
2 09/2021 • Updated the document title from "Hardware Development Guide for the
MIMXRT1170 Processors" to "Hardware Development Guide for the
MIMXRT1160/1170 Processors"
• Added a note to provide support on RT1160 in Section 1
• In Section 3,
– Removed the table "Power domains"
– Updated the power rail values and notes in Table 1
– Added Table 2
– Renamed the table from "Power sequence and recommendations" to "Power
supply and SNVS domain signals" and updated the description of SNVS domain
signals in Table 3
– Removed the figure "Power up and power down sequences"
– Updated power sequence requirements
• Updated the on-chip termination values and added a footnote in Table 5
• Updated the description of JTAG_TDO in Table 6
• Removed an item "For the RT1170 SEMC module to support SDRAM, SEMC_DQS
pin (GPIO_EMC_B1_39) should be kept floating to achieve high-speed access"
from Section 7.7
• In Section 8,
– Renamed the column "Pad Name" to "Ball Name"
– Updated the recommendation values of MIPI and USB modules

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Revision history...continued
Revision number Date Substantive changes
– Added a note
• Added Section 9

1 03/2021 Minor updates in Section 3, Section 3.1, and Table 6

0 11/2020 Initial public release

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AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, i.MX — is a trademark of NXP B.V.
Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle,
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Contents
1 Introduction ......................................................... 2
2 Background ......................................................... 2
3 Power supply .......................................................2
3.1 On-chip DC-DC module .....................................6
4 Clocks ...................................................................7
5 Debugging and programming ............................8
6 Boot, reset, and miscellaneous ....................... 10
7 Layout recommendations .................................17
7.1 Stackup ............................................................ 17
7.2 Placement of bulk and decoupling
capacitors .........................................................18
7.3 FlexSPI ............................................................ 19
7.4 SDRAM ............................................................ 19
7.5 USB ..................................................................19
7.6 Ethernet ........................................................... 20
7.7 High-speed signal routing
recommendations ............................................ 20
8 Unused pins recommendation .........................21
9 Related resources ............................................. 22
10 Revision history ................................................ 22
11 Legal information .............................................. 24

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.

© 2023 NXP B.V. All rights reserved.

For more information, please visit: http://www.nxp.com
Date of release: 3 July 2023
Document identifier: MIMXRT1170HDUG