Binary Arithmetic

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 Readings and Exercises
• P & H: Section 3.1 – 3.4
• ARMv8 Instruction Set Overview:
▪ Section 5.5.6

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 Objective
At the end of this module, you will able to
1. Work with addition, subtraction, multiplication,
and division in binary

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 Modulus Arithmetic
• Constrains numbers to the range 0 to M-1, where
M is the modulus
• CPUs normally do modulus arithmetic
▪ Calculation results must fit into a fixed-size register
• If n is the size in bits, then M = 2n
• Eg: M is 16 for a 4-bit register
▪ Unsigned integers range from 0 to 15 (0000 to 1111)

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 Modulus Arithmetic (cont’d)
▪ Any carry out is ignored when using ordinary
arithmetic instructions
• Eg: 9 + 8 should give 17
▪ But actually gives (9 + 8) mod 16 on a 4-bit CPU:
1001
+ 1000
1 0001
carry out ignored

▪ Instructions like adds or subs do set the carry flag

• Can be used to do extended precision arithmetic

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 Addition
• Single bits can be added together using the
following rules:
carry in a b carry sum
out
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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 Addition (cont’d)
• A full adder circuit implements these rules in
hardware:
carry
a b in

carry sum
out

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 Addition (cont’d)
• Multi-bit numbers can be summed together using
a full adder for each bit:

a3 b3 a2 b2 a1 b1 a0 b0

...

sum3 sum2 sum1 sum0

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 1
1011 a
+ 1010 b
1 0101

1 1 0 0 1 1 1 0
a3 b3 0 a2 b2 1 a1 b1 0 a0 b0

...

1 sum3 sum2 sum1 sum0

0 1 0 1

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 Subtraction
• Is done in the ALU by negating the subtrahend,
and then adding
▪ Reuses the addition circuitry, thus minimizing
hardware complexity
▪ 4-bit example: 7 – 5 = 7 + (– 5) = 2

0111
+ 1011
1 0010
carry out ignored

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Signed Number Branching Conditions
• Recall that signed branch instructions use the N,
Z, V flags:

Name Meaning C equivalent Flags

eq equal == Z == 1
ne not equal != Z == 0
gt greater than > Z == 0 && N == V
ge greater than or equal >= N == V
lt less than < N != V
le less than or equal <= !(Z == 0 && N == V)

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Signed Number Branching Conditions
(cont’d)
• subs Xd, Xn, Xm // Xd = Xn - Xm
• The subs instruction (alias of cmp) sets the flags
using these rules (64-bit form):
▪ N = (Xd<63> == 1)
▪ Z = (Xd == 0)
▪ V = ((~Xd<63> & Xn<63> & ~Xm<63>) |
(Xd<63> & ~Xn<63> & Xm<63>))
▪ Sign bits for Xd, Xn, and Xm are: 0 1 0 or 1 0 1

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 Example
• 4-bit example:
▪ – 7 – 5 is – 14, which is out of range (the modulus result is 4)
1001 Xn 1001
- 0101 Xm same as: + 1011
0100 Xd 0100

V set to 1, N to 0, Z to 0
▪ Note that:
• – 7 != – 5, since Z == 0
• – 7 < – 5, since N != V
• – 7 <= – 5, since !(Z == 0 && N == V)
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 Unsigned Arithmetic
• Uses the same registers and hardware operations
as signed arithmetic
▪ However, one interprets the data as unsigned numbers
• When adding, a carry out (C = 1) indicates
overflow
▪ 4-bit example: 15 + 1
1111
+ 0001
1 0000
carry set
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 Unsigned Number Branching
Conditions
• Ignore N and V flags, since they have no meaning
for unsigned integers:
Name Meaning C equivalent Flags
eq equal == Z == 1
ne not equal != Z == 0
hi unsigned higher > C == 1 && Z == 0
hs unsigned higher or same >= C == 1
lo unsigned lower < C == 0
ls unsigned lower or same <= !(C == 1 && Z == 0)

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 Unsigned Number Branching
Conditions (cont’d)
• Must use these condition codes in conditional
branches when comparing unsigned integers
▪ Eg: C code
unsigned int a, b;
. . .
if (a < b) {
. . .
}

Assembly:
. . .
cmp a_r, b_r
b.hs endif // logical complement
. . .
endif: . . .
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 Multiplication
• Can be done with an iterative procedure
▪ Repeated for every bit in the source registers
• Each step consists of two sub-steps:
▪ A conditional addition
▪ An arithmetic shift right
• The product may require twice as many bits as for
the source registers
▪ The result is put into 2 concatenated registers
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 Multiplication (cont’d)
• If the original multiplier is negative, an extra step
is needed:
▪ Subtract the multiplicand from the high-order part of
the result (i.e. from the product register)

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 Multiplication Algorithm
• M, N, T: binary array[n]; T = 0; assumes only N can be negative
• Calculates M  N; returns result in T:N
repeat n times:
if (N[0] == 1) • Early RISCs used this technique for
multiplication, embodied in a library
T=T+M
function
ARS T:N • Now done in hardware
end repeat
if (N < 0)
T=T–M
return T:N
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 Multiplication (cont’d)
• 4-bit example: 2 × – 5 0010 × 1011
▪ Initial values
M T N
0010 0000 1011

▪ Iteration 1
• N[0] == 1, add M to T
0010 1011

• Arithmetic shift right T:N

0001 0101
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 Multiplication (cont’d)
▪ Iteration 2
• N[0] == 1, add M to T
0011 0101

• Arithmetic shift right T:N

0001 1010

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 Multiplication (cont’d)
▪ Iteration 3
• N[0] != 1, do nothing
0001 1010

• Arithmetic shift right T:N

0000 1101

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 Multiplication (cont’d)
▪ Iteration 4
• N[0] == 1, add M to T
0010 1101

• Arithmetic shift right T:N

0001 0110

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 Multiplication (cont’d)
▪ Since the original multiplier is negative, subtract
multiplicand from product
• i.e. add two's complement of 0010, which is 1110

1111 0110

▪ Result is 11110110, which is -10

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 Division
• Can be done using an iterated procedure similar
to manual long division
▪ Eg: 245 / 5 = 49
110001 quotient
101 11110101
-101
0101
-101
0000101
-101
000 remainder

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 Division (cont’d)
• Early RISCs used a similar technique, embodied
in a callable library function
▪ Now done in hardware

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 Extended Precision Arithmetic
• Is used when you need more than 64 bits of
precision
• Achieved by using two or more registers to
represent a number
▪ Eg: 192-bit unit uses 3 registers
63 0 63 0 63 0

x19 x20 x21

sign bit

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 Extended Precision Arithmetic
(cont’d)
• Extended precision numbers can be added
together
▪ Eg:
191 128 127 64 63 0

x19 x20 x21

+
191 128 127 64 63 0

x22 x23 x24

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 Extended Precision Arithmetic
(cont’d)
• Procedure:
▪ x21 + x24
• Set the C flag to 0 or 1
▪ x20 + x23 + C
• Set the C flag to 0 or 1
▪ x19 + x22 + C
• The adc and adcs instruction use the C flag when
adding

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 Extended Precision Arithmetic
(cont’d)
▪ Eg:
adds x27, x21, x24 // bits 0-63
adcs x26, x20, x23 // bits 64-127
adc x25, x19, x22 // bits 128-191

• Subtraction is done in a similar way using the

subs, sbcs, and sbc instructions

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