“Assignment group 5”

Submitted to : Dr. MARYAM LIAQAT

Topic :FET Amplifiers
Submitted by:
• Rabail Tariq 1027
• Noreen Rashid 1039
• Irsa Gazal 1032
• Sarmad Usama 1025
• Salman Haider 1003
• Malaika Iqbal 1037
• Sana Mushtaq 1040
• Darakshan Rafique 1033
 • Junction Field Effect Transistor (JFET) Small Signal Model:

“The small signal model of a Junction Field Effect Transistor (JFET) is a simplified
representation used to analyze the behavior of the JFET under small signal conditions,
in which ac input signal is applied to the gate and ac output is taken out.”
Major component:
A major component of the ac model will reflect the fact that an ac voltage applied to
the input gate-to-source terminals will control the level of current from drain to
source.
The gate-to-source voltage controls the drain-to-source (channel) current of a JFET.
A dc gate-to-source voltage controls the level of dc drain current through a
relationship known as Shockley’s equation:
�� =���� (1- Vgs/Vp)
Change in drain current:
The change in drain current that will result from a change in gate-to-source
voltage can be determined using the transconductance factor g m in the following
manner:
Transconductance:
The prefix trans - in the terminology applied to gm reveals that it establishes a relationship
between an output and an input quantity.
The root word conductance was chosen because gm is determined by a current-to-voltage ratio
similar to the ratio that defines the conductance of a resistor, G = 1/R = I/V.
Solving for gm in Eq. (1), we have

Geometrical determination of gm:

If we now examine the transfer characteristics of Fig. 8.1 , we find that g m is actually the slope of
the characteristics at the point of operation. That is,
• Following the curvature of the transfer characteristics, it is reasonably clear that the slope and,
therefore, g m increase as we progress from V P to I DSS .
• In other words, as Vgs approaches 0 V, the magnitude of gm increases.
• Equation (2) reveals that gm can be determined at any Q -point on the transfer characteristics by
simply choosing a finite increment in Vgs (or in I D ) about the Q -point and then finding the
corresponding change in I D (or V GS , respectively).
• The resulting changes in each quantity are then substituted in Eq. (2) to determine gm .
• Mathematical Definition of gm:
It was stated that:
“The derivative of a function at a point is equal to the slope of the tangent line drawn at that
point. “
JFET Input Impedence Zi :
The input impedence of JFETs is large to assume that the input terminal approximate an open circuit
Zi (JFET) = ∞Ω
For a JFET a practical value of 10 (1000 MΩ) , whereas a value of 10 12 Ω to 10 15 Ω is typical for MOSFETs and
9

MESFETs.

JFET Output Impedance Zo :

The output impedance of JFETs is similar in magnitude to that of conventional BJTs. On JFET, the output impedance
will typically appear as gos or yos. with the units of µS. The parameter yos is a component of an admittance
equivalent circuit , with the subscript o signifying an output network parameter and s the terminal ( source) to
which it is attached in the model. For the JFET , g os has a range of 10 µS to 50µS or 20 kΩ
(R = 1/G = 1/50 µS) to 100 k Ω (R = 1/G = 1/10µS). In equation form,
Zo (JFET) = rd = 1/ gos = 1/ yos
The output impedance is defined on the characteristics of as the slope of the horizontal characteristic curve at the
point of operation. The more horizontal the curve, the greater is the output impedance. If it is perfectly horizontal,
the ideal situation is on hand with the output impedance being infinite (an open circuit)—an often applied
approximation. In equation form,
rd = VDS/ ID | VGS=constant
when applying that the voltage V GS remain constant when rd is determined. A V DS or I D is then chosen and the
other quantity measured.
JFET AC Equivalent Circuit : A model for the JFET transistor in the ac domain can be constructed. The
control of Id by Vgs is included as a current source gmVgs connected from drain to source. The current source has
its arrow pointing from drain to source to establish a 180° phase shift between output and input voltages as will
occur in actual operation.
The input impedance is represented by the open circuit at the input terminals and the output impedance by the
resistor rd from drain to source. Note that the gate-to-source voltage is now represented by V gs (lowercase
subscripts) to distinguish it from dc levels. In addition, note that the source is common to both input and output
circuits, whereas the gate and drain terminals are only in “touch” through the controlled current source gmVgs.
In situations where rd is ignored , the equivalent circuit is simply a current source whose magnitude is controlled
by the signal Vgs and parameter g m —clearly a voltage-controlled current source.
 Fixed-bias configuration
The gate of JFET is connected in such a way that VGS of JFET remains negative all the time.
The fixed-bias configuration includes the coupling capacitors C1 and C2 they act as
shortcircuit equivalents for the ac analysis. because reactance is less than as compared to
impedance level. Dc batteries VGG and VDD are set to zero volt for short circuit.
. Note the defined polarity of Vgs
which defines the direction of
gmVgs.
If V gs is negative, the direction
of the current source reverses.
The applied signal is represented
by V i and the output signal by
Vo.
Mathematically:
Input Impedance:
Zi =RG because of infinite impedance at input terminal.
output impedance Zo: Vi =0V as by the definition of Zo will establish Vgs
as 0V also.

If the resistance rd is sufficiently large (at least 10:1) compared to RD.

• Voltage gain Av :so that
• ss
Phase
Relationship:
The negative sign in the resulting equation for A v clearly reveals a
phase shift of 180° between input and output voltages.
 Voltage Divider
Configuration
• Voltage division is the result of distributing the input voltage
among the components of the divider. A simple example of a
voltage divider is two resistors connected in series, with the
input voltage applied across the resistor pair and the output
voltage emerging from the connection between them.
Example of Voltage Divider Configuration
 Voltage Divider baising of JFET
Two series connected Resistance from voltage Divider
circuit .
The voltage at the Gate terminal Can be calculated by
voltage division rule. In this way the applied voltage is
utilized to get the gate terminal Voltage .A resistance is
inserted into a source terminal in series. The device current
flows through the resistance and Cause a voltage drop if this
source voltage drop is greater than the voltage appear at
gate terminal then the voltage is negative so required for JFEt
Operation
Why we use voltage Divider baise?
• The applied drain voltage is utilized to get terminal
Voltage Appears at the gate terminal , the gate to
source voltage has negative value which is desired for
JFET Operation
• The purpose of JFET baising is to select the proper Dc
gate to source voltage to establish the desire value of
drain current & thus a proper Q point .
 Common Gate Configuration
It is called common gate configuration because the GATE is common to
the input side and output side. The input is applied to the source
terminal and the output signal is taken from drain terminal.
JFET common-gate configuration:
Common Gate Configuration
JFET ac equivalent model
 Common Gate Configuration
• The gate is grounded and external load resistor RD is connected to the drain
terminal D through coupling capacitor C2. In ac equivalent circuit, current source is
connected between the drain and source terminals, as usual. However, since source
and drain are the input and output terminals respectively, gmVgs appears between
the input and output.
Input impedance Zi:
If rd Ú 10RD in equation permits the following approximation since
RD>rd V 1 and 1>rd V gm:
Common Gate Configuration

Z o Substituting Vi = 0 V in Fig. 8.25 will “short-out” the effects of R S

and set V gs to 0 V. The result is gmVgs = 0, and r d will be in parallel
with R D . Therefore
Common Gate Configuration

For rd Ú 10RD, the factor RD>rd of Eq. (8.38) can be dropped as a

good approximation, and

Phase Relationship :The fact that A v is a positive number will

result in an in-phase relationship between V. ana Vi of Common
Gate Configuration.
Source Follower
• T h e J FE E T eq uiva len t of th e B J T em itted follower con fig ura tion
is th e source follower con fig ura tion .
• From fig ure th e outp ut is ta ken off th e source term in a l a n d
wh en th e d c sup p ly is rep la ced b y sh ort circuit eq uiva len t th e
d ra in is g roun d ed .
• Sub stitutin g th e J FE T eq uiva len t circuit result in th e con fig ura tion of
fig ure

• T h e con trolled source a n d in tern a l outp ut im p ed a n ce of J FE T a re

tried to g roun d a t on e en d a n d R s on th e oth er with V o a cross R s.
• G s V g s ,rd a n d R s a re con n ected in th e sa m e term in a l a n d
g roun d th ey ca n a ll b e p la ced in p a ra llel a s sh own in fig ure

• T h e curren t resource reversed d irection b ut V g s is still

d efin ed b etween th e g a te a n d source term in a l.
• Z i is d efin ed b y
• Z i= R g
• V i = 0 V result in th e g a te term in a l b ein g con n ected d irectly to
th e g roun d .
• A p p lyin g K irch h off’s curren t la w a t n od e S
Io + g m V g s= Ird + IR s
= V o/rd + V o/R s
= V o [ 1 /rd + 1 /R s] – g m V g s
= V o [ 1 /rd + 1 /R s ] – g m [-V o]
= V o [ 1 / rd + 1 / R s + g m ]
• T h e sa m e form a t a s th e tota l resista n ce of th ree p a ra llel
resistor.
 Z o= rd ||R s
• R d > 10 R s
Z o= R s ||g m
• T h e outp ut volta g e is V o is d efin ed b y
V o = g m V g s ( rd ||R s)
• A p p lyin g krich off ‘s volta g e la w a roun d th e p a ra m eter.
V i= V g s + V o
V g s= V i-V o
V o= g n (V i-V o) ( rd ||R s)
V o[1 + g m (rd ||R s)]= g m V i(rd ||R s)
 A v= V o/V i = g m (rd ||R s)/1 + g m (rd ||R s)
• In th e a b sen ce of rd
A v = V o/V i= g m R s/1 + g m R s
• T h e d en om in a tor of up p er eq ua tion is la rg er th a n th e n om in a tor
b y th e fa ctor of on e ,th e g a in ca n n ever b e eq ua l to or g ra ter
th a n on e
• P h a se rela tion sh ip :
A v is p ositive q ua n tity,V o a n d V i a re in
th e p h a se for th e J FE T source follower con fig ura tion .