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High-performance programmable grounded

resistor and its applications
Charu Rana, Dinesh Prasad  & Neelofar Afzal
Pages 71-77 | Received 27 Sep 2016, Accepted 29 May 2018, Published online: 27 Jul 2018

 Cite this article  https://doi.org/10.1080/00051144.2018.1498206

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ABSTRACT

Programmable resistor and analog computational circuits are essential for many
applications such as analog signal processing units, automatic gain control, neural, fuzzy
and instrumentation systems. A high-performance programmable grounded resistor
(PGR) using complementary metal oxide semiconductor (CMOS) technology is proposed
in this paper. A highly linear CMOS resistor with equivalent resistance ranging from 9.4
to 1.5 kΩ is obtained by cancelling the non-linear term present in the current equation of
an MOSFET working in the linear region. The proposed resistor operates on both
positive as well as negative input voltage. The inherited features of PGR are simplicity,
In this article

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extensive All Journals
control Automatika
voltage List bandwidth
range, wider of Issues Volume 59, Issue 1 dissipation.
and low-power
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Additionally, analog computational units such as multiplier, squarer and divider are also
discussed as applications of the PGR. All circuits are implemented and simulated using
TSMC 0.13 µm CMOS technology in SPICE.
 KEYWORDS: CMOS resistor analog computational blocks programmable

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Introduction

Resistor is one of the basic elements of analog signal processing applications [1,2].
Programmable resistors with accurate resistance value are imperative to on-chip-based
systems and specific applications where variable resistance value is required.
Unfortunately, the use of resistors has reduced in the field of integrated circuits due to
the non-availability of accurate and programmable resistors. Many configurations have
been proposed to implement programmable resistors using different techniques.
Several resistors have been realized [3–12] using complementary metal oxide
semiconductor (CMOS) technology and can be programmed externally. Few resistors are
implemented using current conveyors, operational transconductance amplifier (OTA)
arrays and the floating-gate metal oxide semiconductor transistor (FGMOS) technique.
The drawbacks of these proposed resistors are short range of programmability, large
silicon area and high power dissipation. Various applications of CMOS resistors are
current to voltage converters, current mode dividers [12–14], multipliers [13,15–17,19–
21], filters [22–24] and automated measurement systems [25]. These analog
computational blocks which are implemented using these reported resistors lack high
performance.

A simple CMOS-based programmable grounded resistor (PGR) is proposed in this paper

which is operating on minimal power of only 34.1 µW. The other salient characteristics of
the presented block are broad control range, high linearity, wider bandwidth, less silicon
area and ability to operate on both positive and negative input voltage values which

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proves Allbe
Journals Automatika
the most appropriateList
forof various
Issues Volumeprocessing
signal 59, Issue 1 applications. Three
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simple and programmable analog computational blocks based on PGR, namely analog
amplitude modulator (using multiplier), squarer and voltage divider have been
suggested. These proposed circuits are most appropriate for analog systems where
accuracy and programmability are crucial.

The paper is organized as follows: the second section presents proposed PGR. Second-
order effects are considered in the third section. An amplitude modulator and squarer
are presented in the fourth section in addition to voltage mode divider. The fifth section
validates the theoretical results from simulation outcomes to confirm the effectiveness
of proposed circuits. Lastly, the paper is concluded in the sixth section.

Proposed PGR

The proposed PGR and its symbol are shown in Figures 1 and 2. It consists of two N-type
metal oxide semiconductor (NMOS) transistors M1 and M2, operating in linear region. Vin
and Iin are the input voltage and current, respectively and Vc is the control voltage to
tune the resistance of the circuit.

Figure 1. Symbol of PGR.

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Figure 2. Proposed PGR.

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According to the square law relation, the drain current of M1 operating in the triode
region is given by Equation (1).

(1)

This drain current is valid for the condition given in Equation (2) where k1 is the
transconductance parameter of M1.
(2)

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The value All
of Journals
Vc should Automatika List of Issues
be selected greater Volume
than the 59, Issuevoltage
threshold 1 Vtn1 for proper
High-performance programmable grounded r ....
operation of circuit. The gate voltage applied to transistor M2 is Vin + Vc and the
corresponding drain current is

(3)

According to Figure 2, the input current Iin is summation of I1 and I2

(4)

Since the drain to source voltages of both transistors are equal and it is fair enough to
assume that threshold voltages are the same, Vtn1 = Vtn2 = Vtn in addition to the same
transconductance parameters; k1 = k2 = k, the current expression is rewritten as
(5)

Hence, input resistance can be given as

(6)

It can be seen that the non-linear term of Equation (1) is cancelled by current I2, entailing
the proposed circuit to behave as a linear resistor.

Bias voltage Vin + Vc is generated by the summation circuit consisting of transistors M3,
M4, M5 and M6 as shown in Figure 3. NMOS transistors M3 and M4 are working in the
saturation region, whereas P-type metal oxide semiconductor (PMOS) M5 and M6 are
biased to act as a current mirror. The drain currents of I3 and I4 are equal with
assumption that transconductance parameters and threshold voltages of PMOS and
NMOS transistors are equal respectively. Thus, gate to source voltages of M3 and M4 are
also same and can be given as
(7)

where Vss = −Vc and Vt3 = Vt4 for the desired operation.

Figure 3. Bias circuit for Vin + Vc.

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Thus,
(8)

Second-order effects

It is necessary to consider second-order effects on the proposed circuits to analyse non-

idealities [26].

Mobility degradation

The carrier’s mobility decreases under high electric field circumstances and is given by
the expression:
(9)

The equivalent resistance equation will be modified by factor m and is expressed by

(10)

k is µ0CoxW/L and m is and the value mobility degradation parameter of θ

ranges from 0.001 to 0.1 V−1. The errors due to extremely small value of degradation

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parameter θJournals Automatika
are insignificant. Thus, List
theofoutput
Issues function
Volume 59, Issue
will be 1slightly affected, except
High-performance programmable grounded r ....
the voltage mode divider circuit which is independent of this factor.

Temperature variation

The relationship between the mobility of carriers and the temperature is given below:

(11)

It is known that the temperature variation affects the transconductance parameter β.

Mobility is calculated at Tc to analyse the temperature variation where T is the absolute
temperature (300 K). The value of constant parameter γ ranges from 1.5 to 2. The
mobility decreases by maximum 6.3% ( ) and minimum by 4.7% for .

The interconnect resistance of MOSFET also gets affected by temperature variations and
is expressed as below:
(12)

where Ri is a resistance at temperature Ti and the value of α is an empirical temperature

coefficient of resistance with value 0.004 for copper wire and 0.0043 for aluminium wire.
R0 and T0 are reference resistance and temperature, respectively. Suppose R0 is 30 kΩ at
20°C, the value of Ri at 30°C is 30.12 kΩ for copper and 30.129 kΩ for aluminium after
using Equation (12) and results in an increase of 4% and 4.3%, respectively. It can be
seen that the variations in interconnect resistance and mobility due to temperature will
almost nullify each other. Thus, proposed circuits are less prone to error due to
temperature variations.

Mismatch effect

The mismatches in threshold voltages of transistors in the PGR circuit can add a DC
offset to expression of equivalent resistance which can be nullified by offset applied
externally. Second, the inequality of transconductance parameters can also cause
deviation from the desired result. Assume that the k1 is transconductance parameter of
M1 and k1 + Δk1 of M2 of PGR. The current expression given in Equation (4) can be
rewritten as follows:

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(13)
High-performance programmable grounded r ....
(14)

The value of Δk1 is much smaller to affect the expression given in Equation (14) by a
considerable amount. Moreover, a DC offset current added to circuit can nullify this
mismatch.

Applications

Proposed analog multiplier and squarer

An analog voltage multiplier can be implemented using two proposed PGRs as depicted
in Figure 4. The gate voltages of VG1a and VG2a are Vc + V2, and V1 + Vc and input voltages
for VG1b and VG2b are Vc and Vc − V1, respectively. This analog multiplier can be utilized to
realize amplitude modulating function.

Figure 4. Configuration of analog multiplier.

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After All Journals using
Automatika
Equations List of Issues
(1)–(6), Volume 59,
the currents Issue I1 are as follows:
Ia and b
High-performance programmable grounded r ....
(15)
(16)

Thus, Iout is found to be Ia + Ib and is given by

(17)

Hence, the above expression results in the multiplication of two input voltages with the
assumption of matched transistors. Thus, it can be used to realize analog amplitude
modulator.

For squarer, if V1 = V2 = Vin is chosen then the configuration shown in Figure 4 will
function as a amplitude squarer with expression given below.
(18)

Bias voltages V1 + Vc, V2 + Vc and –V1 + Vc are generated using the bias circuit shown in
Figure 3.

Proposed analog voltage divider

A new voltage mode divider is shown in Figure 5 and implemented using two PGRs and
one NMOS transistor M3 operating in the saturation region. Using Equations (1)–(6), the
current I1 can be given as
(19)

The expression for is

(20)

Figure 5. Proposed voltage divider.

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The output voltage can be obtained from Equations (19) and (20) and expressed as

(21)

Thus, the function of voltage division is achieved which can be programmed by control
voltage Vc.

Bias voltages Vc + Vth and V2 + Vth are obtained from the circuit mentioned in Figure 3
with Vss = −Vth. Vc + V1 and Vout + V2 are achieved using the bias circuit shown in Figure 3
again when the source of the M3 of Figure 3 is connected to Vth instead of ground.

Simulation results and comparisons

All the circuits proposed in this paper are validated through simulations using T-Spice in
0.13 µm TSMC BSIM3, CMOS technology with level 49. The aspect ratios of all transistors
are chosen to be 1:1. Vdd and Vss vary as the value of Vc varies from 0.5 to 1.5. Figure 6
shows I–V characteristics where the input current is applied to the circuit and
corresponding voltage Vin is measured for different values of control voltage Vc. The
respective values of Req are shown in Table 1. It can be seen that it is validating the

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it functions as Issues resistor
Volume 59, Issue 1
programmable by Vc with
High-performance programmable grounded r ....
equivalent values of resistance, Req ranging from 9.46 kΩ to 1.5 kΩ. The effect of
temperature on Req is analysed and shown in Figure 7. Req varies from 9.8 kΩ to 9.0 kΩ
for temperature ranging from 50°C to −50°C leading to minor deviations.

Figure 6. DC characteristics of PGR for different values of Vc.

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Figure 7. Variation in Vin with respect to temperature.

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Table 1. Req for different values of Vc.

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
In Figure 8, distortion analysis of PGR is measured for different values of sinusoidal
input current of magnitude up to 50 µA at a frequency of 1 MHz. Maximum total
harmonic distortion (THD) measured is 2.7% at Iin = 50 µA. The power dissipation
observed for the circuit shown in Figure 2 is 946 nW which is remarkably low. The total
power dissipation of PGR including bias circuit for Vin + Vc is 34.1 µW at Vc = 1 V, which is
again low. The frequency response of PGR for Req = 9.4 KΩ at Vc = 0.5 V is shown in
Figure 9 with constant magnitude of equivalent resistance up to 130 MHz. The transient
analysis and fast Fourier transform characteristics of the proposed PGR is given in
Figure 10 for current input signal of magnitude 45 µA at frequency of 1 MHz. The value
of Req is set to approximately 2 kΩ to get both the responses.

Figure 8. THD analysis of PGR at Vc = 1.

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Figure 9. Frequency response of PGR.

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PGR1 for R ∼ 2 kΩ when
eq
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sinusoidal input current of 45 µA amplitude is applied.

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The output of the summation circuit is also shown in Figure 11 to verify the
implementation given in Figure 2. Figure 11 depicts the linear increase in the output, Vin
+ Vc when Vin is varying and Vc is constant at a value of 1 V.

Figure 11. Output of summation circuit.

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Table 2 compares the proposed PGR with existing resistors available in the literature.
The presented CMOS resistor is linear due to cancellation of non-linear terms of drain
equations of both NMOS transistors. It works on positive as well as negative values of
the input voltage Vin(Vin > 0 and Vin < 0), whereas many reported resistor realizations
operate only for positive values of Vin. It is evident that the proposed PGR achieved
wider bandwidth of 130 MHz and provides broad range of programmability using
control voltage Vc varying from 0.5 to 2.5 V. It also dissipates less power up to 34.1 µW
when compared to the reported circuits. THD observed is 2.7% which also low. Thus, the
proposed PGR is most suitable for high-performance analog applications demanding
low-power dissipation, tunablility, linearity and less silicon area.

Table 2. Comparison of proposed PGR with reported literature.

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
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The All Journals
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modulatorVolume
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theIssue 1
proposed voltage multiplier
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is analysed with input waveforms of V1(t) = 100 mV sin(2π × 105) and V2(t) = 200 mV sin(2π
× 106) shown in Figure 12. The aspect ratio chosen for all transistors is 6.5 µm/0.13 µm.
The modulated output waveform is depicted in Figure 13 for given input signal. For
squarer function, Figure 14 depicts V1 = V2 = 100 mV sin(2π*106) and the output
waveform is given in Figure 15 justifying the analytical analysis. The bandwidth
measured is 79.9 MHz with a linear range of input voltage from +0.6 V to −0.6 V. The DC
simulation results of the proposed voltage divider are shown in Figure 16 when V1 is
varied from 0 to 800 mV for different values of V2 ranging from 0.6 to 1 V. The aspect
ratio of all transistors chosen for the voltage mode divider circuit is 1:1 except M3 which
is 10:1. The bandwidth of the voltage divider is found to be 89 MHz and depicted in
Figure 17.

Figure 12. Input signals V1 and V2 for four-quadrant multiplier.

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Figure 13. Output waveform of four-quadrant multiplier.

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Figure 14. Input waveforms of squarer.

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Figure 16. Variation in Vout with respect to V2.

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Conclusion

This paper proposed a new high-performance PGR and its applications in analog
arithmetic circuits such as analog amplitude modulator, squarer and voltage mode
divider. The power dissipation of PGR measured is 34.1 µW which is quite low. Wider
bandwidth and broad programmability range are achieved. All circuits exhibit simplicity
while validating the claimed theoretical results from simulation results. These blocks are
believed to be beneficial for low-power analog applications such as analog fuzzy
hardware, artificial neural networks and automated measurement systems.

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