Microprocessor I

Chapter 11 – The PIC18F Microcontrollers:

Bank Switching and Table Processing

Dr. Mohamad Mroué

Lebanese University - Faculty of Engineering

Beirut, Lebanon
1
Introduction
 The CPU can access data in various ways. The data could be in a
register, or in memory, or provided as an immediate value.

 The PIC18 provides a total of four distinct addressing modes. They are
as follows:
1. Immediate
2. Direct
3. Register indirect
4. Indexed-ROM

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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Immediate addressing mode
 In immediate addressing mode, the operand is a literal constant and comes
immediately after the opcode when the instruction is assembled.
‒ Notice that immediate data is called a literal in the PIC.
 This addressing mode can be used to load information into WREG and selected
registers, but not to any file register.
 The immediate addressing mode is also used for arithmetic and logic instructions.
Example:

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Direct addressing mode
 As mentioned previously, the 256-byte access
bank file register is split into two sections:
‒ The lower addresses, 00 to 7FH, are assigned to the
general purpose registers.
‒ The upper addresses, F80-FFFH, to the SFR.

 The access bank is the default bank when the

PIC18 is powered up.
‒ It is the minimum bank that all PIC18 processors
have.
 The MOVFF instruction also plays a role in
choosing the access bank.
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Direct addressing mode
 The entire data RAM file register can be accessed using either direct
or register indirect addressing modes.
 In direct addressing mode, the operand data is in a RAM memory
location whose address is known, and this address is given as a part
of the instruction.
 While the letter "L" in the instruction means literal (immediate), the
letter "F" in the instruction signifies the address in the file register
location.

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Direct addressing mode
 MOVWF direct addressing opcode
‒ The address field is an 8-bit address and can take values from 00-FFH.
‒ It must be noted that file register data RAM does not support immediate
addressing mode.
‒ To move data into any file register, we must first move it to WREG, and then
move it from WREG to the file register using the MOVWF instruction.

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Direct addressing mode
 The difference between “INCF fileReg, W” and “INCF fileReg, F”

‒ Notice that When the second parameter is not stated, it is assumed to be fileReg (F)

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Direct addressing mode
 Notice that if we use “DECF MYREG, W” instead of “DECF MYREG, F” in the BNZ
program, we will never get out of the loop because the values of MYREG and
WREG will remain unchanged.

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SFR registers and their addresses
 Selected PIC18 Special Function Register (SFR) addresses

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SFR registers and their addresses
 The SFRs can be accessed by their names (which is much easier) or by
their addresses.

 Not all the address space of F80H to FFFH is used by the SFR. The
unused locations are reserved and must not be used by the PIC18
programmer.

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SFR registers and their addresses
 Regarding direct addressing mode in the PIC18, notice the following
points:
1. If you examine the .lst file for an Assembly language program,
you will see that SFR register names are replaced with their
addresses.
2. The WREG register is one of the SFR registers and has address
FE8H.
3. The direct addressing mode is also called register direct.

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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Register indirect addressing mode
 In the indirect addressing mode, a register is used as a pointer to the
data RAM location.
 In the PIC18, three registers are used for this purpose: FSR0, FSR1,
and FSR2.
‒ FSR stands for file select register.
‒ The FSR is a 12-bit register allowing access to the entire 4096 bytes of data
RAM space in the PIC18.
‒ We use LFSR (Load FSR) to load the RAM address.

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Register indirect addressing mode
 Because FSR0, FSR1, and FSR2 are 12-bit registers they cannot fit into
the SFR address space unless they are split into pieces of an 8-bit size.

 The FSR registers have the low-byte and high-byte parts called FSRxL
and FSRxH.

 Note that the FSRxH is only 4-bit and the upper 4 bits are not used.

 Each of the FSR0, FSR1, and FSR2 registers has an INDF register
associated with it, and these are called INDF0, INDF1, and INDF2.

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Register indirect addressing mode
 When we move data into INDFx we are moving data into a RAM
location pointed to by the FSR.
 In the same way, when we read data from the INDF register, we are
reading data from a RAM location pointed to by the FSR.

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Advantages of register indirect addressing mode
 One of the advantages of register indirect addressing mode is that it
makes accessing data dynamic rather than static, as with direct
addressing mode.

 Example: Write a program to copy the value 55H into RAM memory
locations 40H to 45H using:
a. Direct addressing mode.
b. Register indirect addressing mode without loop.
c. A loop.

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Advantages of register indirect addressing mode
 Using the direct addressing mode.

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Advantages of register indirect addressing mode
 Using the register indirect addressing mode without loop.

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Advantages of register indirect addressing mode
 Using the register indirect addressing mode with loop.

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Auto-increment option for FSR
 Because the FSR is a 12-bit register, it can go from 000 to FFFH, which
covers the entire 4K RAM space of the PIC18.

 Using the "INCF FSR0L, F" instruction to increment the pointer can
cause a problem when an address such as 5FF is incremented.

 The instruction "INCF FSR0L, F" will not propagate the carry into the
FSR0H register.

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Auto-increment option for FSR
 The PIC18 gives us the options of auto-increment and auto-
decrement for FSRn to overcome this problem.
 Example with CLRF instruction:

‒ Note: This table shows the syntax for the CLRF instruction, it works for all such
instructions.
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Auto-increment option for FSR
 The auto-decrement or auto-increment affects the entire 12 bits of
the FSRn and has no effect on status register.
‒ This means that FSR0 going from FFF to 000 will not raise any flag.

 The option of PLUSWn is widely used for a RAM-based look-up table.

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Auto-increment option for FSR

• LFSR FSR1,0x0120
• LFSR FSR2,0x0150
• MOVFF POSTINC1, POSTINC2

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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DB (define byte) and fixed data in program ROM
 So far, we have seen that the PIC18 has a maximum of 2M of code (program)
space and 4K of data RAM space.
 While we never use any of the data RAM space for storing code, we can use the
code space to store fixed data.

 The DB data directive is widely used to allocate ROM program (code) memory in
byte-sized chunks.
 DB is used to define an 8-bit fixed data.
‒ The numbers can be in decimal, binary, hex, or ASCII formats.
 The DB is used to define ASCII strings.
‒ We must use single quotes (') for a single character or double quotes (") for a string.

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DB (define byte) and fixed data in program ROM

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Reading table elements in the PIC18
 The 2M of program (code) space is under the direct control of the
program counter register.
‒ This means that we need to have a special function register
pointer to point to the data to be fetched from the code space.

‒ For this reason we can call it register indirect ROM addressing

mode.

‒ This is an addressing mode widely used to access data elements

located in the program ROM space of the PIC18.
• This is often called table processing.
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Reading table elements in the PIC18
 There is a group of instructions in the PIC18 designed for table processing.
‒ These can be used for both table read and table write.

 To read the fixed data byte, we need an address pointer that points to the
data and a register to store the data when it is brought into the CPU.
‒ TBLPTR is a 21-bit register and is used to point to the byte to be fetched.
 TBLPTR is divided into three 8-bit parts.
‒ These are called TBLPTRL (low), TBLPTRH (high), and TBLPTRU (upper), and all are
part of the SFRs.

 The other SFR register used for the table processing is TABLAT.
‒ The TABLAT (TABle LATch) register is used for keeping the byte once it is fetched into
the CPU.

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Reading table elements in the PIC18

8-bit data registers

21 bit

16 bit

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Auto-increment option for TBLPTR
 Using the "INCF TBLPTRL, F" instruction to increment the pointer can cause a
problem when an address such as 5FFH is incremented.
‒ The carry will not propagate into TBLPTRH. The PIC18 gives us the options of TBLRD*+ (table
read and increment), TBLRD*- (table read and decrement), or so on.

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Look-up table and RETLW instruction
 The look-up table is a widely used concept in microcontroller
programming.
‒ It allows access to elements of a frequently used table with minimum
operations.

 In the PIC, to get the table element we first call the look-up table,
then we add a fixed value to the PCL (low-byte portion of the program
counter) to index into the look-up table.
‒ Upon return from the table, the RETLW instruction will provide the desired
look-up table element in the WREG register.

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Accessing a look-up table in RAM
 The look-up table elements can also be in RAM instead of ROM.

 The PIC18 allows us to do that using the SFR as pointer.

 For example, the instruction "MOVFF PLUSW2, PORTD" will bring

elements of the look-up table pointed to by the address location
formed by the addition of FSR2 + WREG.
‒ In this case, WREG is used as an index into the look-up table.

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Writing table elements in PIC18
 In PIC18 we also have the TBLWT instruction, which allows us to write
(store) data into program ROM space.

 The TBLWT can be used only with PIC18 chips that have flash ROM for
the program ROM space.

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Writing table elements in PIC18

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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Bit-addressability of Data RAM
 Many microprocessors such as the 386 or Pentium allow programs to
access registers and I/O ports in byte size only.
‒ In other words, if you need to check a single bit of an I/O port, you must read the
entire byte first and then manipulate the whole byte with some logic instructions to
get hold of the desired single bit.
‒ Indeed, one of the most important features of the PIC is its ability to access the file
register's RAM location in bits as well as bytes.

 This means that all I/O ports, SFRs, and general purpose RAM areas for the
PIC18 are bit-addressable because they are part of the file register data
RAM.
‒ WREG is also bit-addressable because it is part of the SFRs.
 This is a very powerful feature of the PIC18 family.

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Bit-addressable file register data RAM
 The entire 4096 bytes of file register data RAM of the PIC18 are bit-
addressable.
‒ This means that while ROM program space is only byte-addressable, the 4K of data
RAM is both byte- and bit-addressable.
 The PIC18 provides two categories of instructions: bit-oriented and byte-
oriented instructions.
‒ Bit-oriented instructions are called bit-addressable, while byte-oriented instructions
are referred to byte-addressable.

 The bit-oriented instructions use only the direct addressing mode.

 There is no register indirect addressing mode for bit-oriented instructions
in the PIC18.

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File register bit-addressability
 The PIC18 can have up to 4096 bytes of file register data RAM
depending on the family member.
‒ We can access either the entire 8 bits or any single bit without altering the
rest.
‒ when accessing a file register in a single-bit manner, we use the syntax "Bit-
Oriented-instr fileReg, X" where fileReg is any register in the file register and
X is the desired bit number from 0 to 7 for data bits D0 to D7.

 Every register, including WREG, is assigned a byte address in the file

register and ports PORTA-PORTE are part of the file register.

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Status register bit-addressability
 In the status register, 5 bits are set aside for the flags C, DC, Z, N, and OV.

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Presentation Progress

1. Immediate and direct addressing modes

2. Register indirect addressing mode
3. Look-up table and table processing
4. Bit-addressability of data RAM
5. Bank switching in the PIC18

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Bank switching in the PIC18
 The 4K file register RAM is divided into banks
of 256 bytes each, which gives us a total of 16
banks in the PIC18.

 The access bank is made of 128 bytes of lower

addresses and 128 bytes of higher addresses.

 While the lower 128 bytes of address space

000-07FH are used for general-purpose RAM,
the higher 128 bytes are dedicated to the
SFRs (special function registers) residing in
address space F80-FFFH.
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The A bit and bank switching
 The instruction "MOVWF fileReg" is really "MOVWF fileReg, A" where
the A bit can be 0 or 1.
‒ If A = 0, then the access bank is the default bank.
‒ If A = 1, however, then the instruction will use the bank selector register (BSR)
to select the bank instead of using the access bank.

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The BSR register and bank switching
 With A = 1, we use the BSR (bank select register) to choose the
desired bank. The BSR is an 8-bit register and is part of the SFRs.

 Of the 8 bits of the BSR, only 4 least-significant bits are used in the
PIC18.

 The upper 4 bits are set to zero and are ignored by the PIC18.

 The 4-bit BSR gives us 16 banks, and because each bank is 256 bytes,
we cover the entire 4096 (16 * 256 = 4096) bytes of data RAM file
register using bank switching.
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The BSR register and bank switching
 Upon power-on reset, BSR = 0 (0000 binary), which indicates that
only the lowest addresses of data RAM, from 000 to 0FFH, can be
used for the general-purpose register in addition to the SFRs, which
always reside in the last half of bank F.

‒ To select bank 2, we load BSR with the value 02 (0010 binary),

which allows access to the bank addresses 200-2FF in addition to
the SFR addresses of F80-FFFH.

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The BSR register and bank switching
 Note that although we can use any of the addressing modes, such as immediate,
direct, or register indirect to access the GP register regions, we use only direct
addressing mode in accessing the SFR registers.

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The BSR register and bank switching
 Data RAM bank for selected PIC18 chips

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Bank switching and “INCF F, D, A” instruction
 With A = 0, the access bank is the default bank. Now to use banks
other than the access bank, two things must be done:
1. Load the BSR with the desired bank number, and
2. Make A = 1 in the instruction itself.

 Therefore, instruction "INCF MYREG, F, 1" has a totally

different meaning from "INCF MYREG, F, 0".
‒ The A = 1 means to use the bank pointed to by BSR.

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Bank switching and “INCF F, D, A” instruction
 In the following code, we first load the bank number into the BSR register using
the MOVLB instruction, and then manipulate the contents of RAM location 0x240
(location 40 of bank 2):

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Bank switching and “INCF F, D, A” instruction
 In the following code, although we loaded BSR, location 0x40 of the access bank
is used because the A bit was not indicated.

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Bank switching and “INCF F, D, A” instruction
 Example: The role of the D and A bits.

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PIC18 Data Memory Range
 The following table shows the banks for
various sizes of the data RAM in the
PIC18 chip.

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MOVFF and banks
 The great thing about the MOVFF instruction is that there is no need
to worry about bank switching because it can move data anywhere
within the 4K of RAM space.

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