Chapter 3

Single-Stage Amplifiers
1

3.1 Basic Concept

1. Input(x)- output(y)
Characteristic of an amplifier
𝑦 𝑡 = 𝛼0 + 𝛼1 𝑥 𝑡 + 𝛼2 𝑥 2 𝑡 + ⋯ + 𝛼𝑛 𝑥 𝑛 𝑡
𝑥1 ≤ 𝑥 ≤ 𝑥2 𝑛 ∶ 𝑖𝑛𝑡𝑒𝑔𝑒𝑟 𝛼𝑖 ∶ 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
Under the small-signal consideration,
𝑥𝑛 𝑡 ≪ 𝑥 𝑡 𝑛 = 2, ⋯ , 𝑛
𝑦 𝑡 ≅ 𝛼0 + 𝛼1 𝑥 𝑡 𝛼0 ∶ dc operating bias point
∆𝑦 = 𝛼1 ∆𝑥 𝛼1 ∶ small−signal gain
∆𝑦 ∶ small−signal output ∆𝑥 ∶ small−signal input

Chung-Yu (Peter) Wu 2018

 Chapter 3
Single-Stage Amplifiers
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3.1 Basic Concept

2. Design tradeoffs
Analog design octagon

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load

RD : Drain load resistor

M1 : Amplifier transistor
RS : Internal resistance of signal generator
or output resistance of the previous stage

S: Input signal (DC+AC)

OUT : Output signal (DC+AC)

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)

M1 SAT :
1 𝑊 2
𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝐼𝑁 − 𝑉𝑇𝐻
2 𝐿

( 𝑂𝑈𝑇 > 𝐼𝑁 − 𝑉𝑇𝐻 ) ( → 0)

n : n-channel carrier mobility

Cox : Gate oxide capacitance per unit area
W(L) : Channel width (length) of M1

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
At point A ,

IN=VIN1 , GD=VTH , 𝑂𝑈𝑇 = VIN1 −V𝑇𝐻

1 𝑊 2
𝑂𝑈𝑇 = VIN1 − V𝑇𝐻 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 VIN1 − 𝑉𝑇𝐻
2 𝐿

VIN1 can be solved.

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
M1 LINEAR : ( 𝑂𝑈𝑇 < 𝐼𝑁 − 𝑉𝑇𝐻 )
1 𝑊 2]
𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 [2 𝐼𝑁 − 𝑉𝑇𝐻 𝑂𝑈𝑇 − 𝑂𝑈𝑇
2 𝐿

If 𝑂𝑈𝑇 ≪2 𝐼𝑁 − 𝑉𝑇𝐻 , deep linear (triode) region,

𝑉𝐷𝐷
𝑂𝑈𝑇 = 𝑊
1+𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝐷 𝐼𝑁 −𝑉𝑇𝐻

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
At point B , M1 SAT ,

𝑖𝑛 ȁ𝐷𝐶 = 𝑉𝐼𝑁𝐵 , 𝑂𝑈𝑇 ȁ𝐷𝐶 = 𝑉𝑂𝑈𝑇𝐵

Small-signal gain ,
𝜕 𝑂𝑈𝑇 𝑊
𝐴 ≡ ቚ = −𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐼𝑁𝐵 − 𝑉𝑇𝐻 = −𝑔𝑚 𝑅𝐷
𝜕 𝐼𝑁 𝐵 𝐿

𝑔𝑚 ∝ 𝑉𝐼𝑁𝐵

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
Small-signal model:
𝑉𝑖𝑛 (𝑎𝑐) ≪ 𝑉𝐼𝑁 (𝐷𝐶)
1
𝑟𝑜 = → ∞ (∵ 𝜆 = 0)
𝐼𝐷
𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡
𝐴𝜐 ≡ = = −𝑔𝑚 𝑅𝐷
𝑉𝑠 𝑉𝑖𝑛
Small-signal equivalent circuit
If 𝑉𝑖𝑛 ≪ 𝑉𝐼𝑁 , 𝑔𝑚 is a constant.
If 𝑉𝑖𝑛 is not much smaller than 𝑉𝐼𝑁 ,
𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁 + V𝑖𝑛 − 𝑉𝑇𝐻 is not a constant
𝐿
→ Large-signal model is considered → nonlinearity or distortion

Chung-Yu (Peter) Wu 2018

 Chapter 3
Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
Example 3.1

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
How to maximize 𝐴𝜐 ?
𝑊 𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁 − 𝑉𝑇𝐻 = 2𝜇𝑛 𝐶𝑜𝑥 𝐼
𝐿 𝐿 𝐷

𝑊
𝐴𝜐 = −𝑔𝑚 𝑅𝐷 = − 2𝜇𝑛 𝐶𝑜𝑥 𝐼 𝑅 ∝ 𝐼𝐷
𝐿 𝐷 𝐷

𝑊
↑ → 𝐴𝜐 ↑ → large device capacitances → speed ↓
𝐿

𝑅𝐷 ↑ → 𝐴𝜐 ↑ → 𝐼𝐷 𝑅𝐷 ↑
𝐼𝐷 ↑ → 𝐴𝜐 ↑ → 𝐼𝐷 𝑅𝐷 ↑
𝐼𝐷 𝑅𝐷 ↑ → swing ↓ or M1 is driven to linear region
Thus 𝐴𝜐 cannot be increased indefinitely by increasing RD or ID.

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
Channel length modulation effect
1 𝑊
𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝐼𝑁 − 𝑉𝑇𝐻 2 (1 + 𝜆 𝑂𝑈𝑇 )
2 𝐿
𝜕 𝑂𝑈𝑇 𝑊
𝐴 ≡ ቚ = −𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁 − 𝑉𝑇𝐻 (1 + 𝜆𝑉𝑂𝑈𝑇 )
𝜕 𝐼𝑁 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛 𝑝𝑜𝑖𝑛𝑡 𝐿

1 𝑊 2 𝜕 𝑂𝑈𝑇
−𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁 − 𝑉𝑇𝐻 𝜆 ቚ
2 𝐿 𝜕 𝐼𝑁 𝑜𝑝

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
Channel length modulation effect
1 𝑊 2
At the operating point , 𝐼𝐷 ≅ 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁 − 𝑉𝑇𝐻
2 𝐿
𝐴𝜐 ≅ −𝑅𝐷 𝑔𝑚 − 𝑅𝐷 𝐼𝐷 𝜆𝐴𝜐
𝑔𝑚 𝑅𝐷
𝐴𝜐 ≅ −
1+𝑅𝐷 𝜆𝐼𝐷
1
𝜆𝐼𝐷 =
𝑟𝑜
𝑟𝑜 𝑅𝐷
𝐴𝜐 ≅ −𝑔𝑚
𝑟𝑜 +𝑅𝐷
The same result can be derived from the small-signal equivalent
circuit.
Chung-Yu (Peter) Wu 2018
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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.1 NMOS CS amplifier with resistor load (Cont.)
Example 3.2

𝐴𝜐 = −𝑔𝑚 𝑟𝑜 ฮ𝑅𝐷
Active load CS stage
I1 : Ideal current source , ro1 → , RD = ro1 →
𝐴𝜐 = −𝑔𝑚 𝑟𝑜 ：“ intrinsic gain “
1 1
𝐴𝜐 ∝ 𝐼𝐷 ∙ 𝐼 = 𝐼𝐷 ↓ → 𝐴𝜐 ↑
𝐷 𝐼𝐷
Chung-Yu (Peter) Wu 2018
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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.2 Common Source with Diode-Connected Load

(a) (b)
𝑉
∵ 𝑉𝐷𝑆1 = 𝑉𝐺𝑆1 > 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 𝑔𝑚 + 𝑔𝑚𝑏 𝑉𝑥 + 𝑟𝑥 = 𝐼𝑥
𝑜
𝑉𝑥 1 1
is valid always. =𝑔 ฮ𝑟𝑜 ≈𝑔
𝐼𝑥 𝑚 +𝑔𝑚𝑏 𝑚 +𝑔𝑚𝑏
𝑉𝑥 1
⇒ 𝑀1 SAT if turned on. If 𝑔𝑚𝑏 = 0 , ≈𝑔
𝐼𝑥 𝑚

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.2 Common Source with Diode-Connected Load (Cont.)
𝑟𝑜1 , 𝑟𝑜2 → ∞
1 𝑔 1
𝐴𝑣 = −𝑔𝑚1 𝑔 = − 𝑔𝑚1 1+𝜂
𝑚2 +𝑔𝑚𝑏2 𝑚2

𝑊ൗ
𝐿 1 1 𝑔𝑚𝑏2
𝐴𝑣 = − 𝑊ൗ 𝜂≡
𝐿 2 1+𝜂 𝑔𝑚2

Vout max : VDD - VTH2 ; At Point A: V in > Vout + V TH1 →M1 Linear
PMOS M2 : Bulk is connected to source Vbs2 = 0
𝑟𝑜1 , 𝑟𝑜2 → ∞
𝜇𝑛 𝑊ൗ𝐿 1
𝐴𝑣 = − Gain is independent of bias current!
𝜇𝑝 𝑊ൗ𝐿
2

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.2 Common Source with Diode-Connected Load (Cont.)
ID1 = ID2 ,
𝑊 𝑊
∴ 𝜇𝑛 (𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 )2 = 𝜇𝑝 ( 𝑉GS2 − 𝑉𝑇𝐻2 )2
𝐿 1 𝐿 2

𝜇𝑛 𝑊ൗ𝐿 1 𝑉𝐺𝑆2 − 𝑉𝑇𝐻2

𝐴𝑣 = − =
𝜇𝑝 𝑊ൗ𝐿 2 (𝑉𝐺𝑆1 −𝑉𝑇𝐻1 )

𝐴𝑣 > 1 ⇒ 𝑉𝐺𝑆2 − 𝑉𝑇𝐻2 > (𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 )

⇒ 𝑉𝐺𝑆2 > (𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 ) + 𝑉𝑇𝐻2 is large.
This implies substantial voltage swing constraint.
Vout max : VDD - 𝑉𝑇𝐻2

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.3 CS with Current Source Load
VOUT max : Vb + 𝑉𝑇𝐻2
𝐴𝑉 = −𝑔𝑚 𝑟𝑜1 ฮ𝑟𝑜2
Assuming ro2 is much larger than 𝑟𝑜1 ,
𝑊 1
𝐴𝑉 ≈ −𝑔𝑚 𝑟𝑜1 = − 2𝜇𝑛 𝐶𝑜𝑥 𝐼𝐷
𝐿 1 𝜆𝐼𝐷

𝑊 1
= − 2𝜇𝑛 𝐶𝑜𝑥
𝐿 1 𝜆 𝐼𝐷

1
M1 , M2 : SAT 𝐴𝑉 ∝
𝐼𝐷
Chung-Yu (Peter) Wu 2018
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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.4 CS with Triode Region Load
M1 : Sat
M2 : Deep linear (triode)

𝐴𝜐 = −𝑔𝑚 𝑅𝑂𝑁2
1
𝑅𝑂𝑁2 = 𝑊
𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐷𝐷 −𝑉𝑏 − 𝑉𝑇𝐻𝑃 )
2
1
A depends on Vb and 𝑉𝑇𝐻𝑃 , 𝐴𝜐 ∝
𝐼𝐷

VOUT min : 𝑉𝑏 + 𝑉𝑇𝐻𝑃 , VOUT max : 𝑉𝐷𝐷

﹡Lower voltage headroom, higher signal swing than diode-connected load.
﹡Variations with process and temperature

Chung-Yu (Peter) Wu 2018

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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.5 CS with Source Degeneration If ro → , 𝜆=0

𝑔𝑚
𝐺𝑚 =
1+𝑔𝑚 𝑅𝑆
𝐴𝜈 = −𝐺𝑚 𝑅𝐷
−𝑔𝑚 𝑅𝐷
(a) (b) 𝐴𝜈 =
1+𝑔𝑚 𝑅𝑆

Rs : Source degeneration resistor

1 1
If 𝑅𝑠 ≫ ,𝐺 ≈
𝑔𝑚 𝑚 𝑅𝑆
𝑅𝐷
𝐴𝜐 ≈ −
𝑅𝑆
Chung-Yu (Peter) Wu 2018
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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.5 CS with Source Degeneration (Cont.)
Considering gmb and ro : 𝑉𝑏𝑠 = 𝑉1 − 𝑉𝑖𝑛
𝑔𝑚 𝑟𝑜
𝐺𝑚 =
𝑅𝑆 +[1+(𝑔𝑚 +𝑔𝑚𝑏 )𝑅𝑆 ]𝑟𝑜
𝑔𝑚
𝐺𝑚 = 𝑅𝑆
+[1+(𝑔𝑚 +𝑔𝑚𝑏 )𝑅𝑆 ]
𝑟𝑜

𝐴𝜐 = −𝐺𝑚 𝑅𝐷 ฮ𝑅𝑂𝑈𝑇
𝑉𝑜𝑢𝑡
𝑅𝑂𝑈𝑇 ≡ ቚ = 𝑅𝑆 + 𝑟𝑜 (1 + 𝑔𝑚 𝑅𝑠 + 𝑔𝑚𝑏 𝑅𝑠 )
𝐼𝑜𝑢𝑡 𝑉𝑖𝑛 = 0

R OUT ↑ with R S ↑
Chung-Yu (Peter) Wu 2018
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Single-Stage Amplifiers
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3.2 Common-Source (CS) Stage

3.2.5 CS with Source Degeneration (Cont.)

−𝑔𝑚 𝑅𝐷 −𝑅𝐷
𝐴𝜐 = =1
1+𝑔𝑚 𝑅𝑆 ൗ𝑔𝑚 +𝑅𝑆

CS without Rs CS with Rs

Chung-Yu (Peter) Wu 2018

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3.2 Common-Source (CS) Stage

3.2.5 CS with Source Degeneration (Cont.)
𝑉𝑏𝑠 = 𝑉1

𝑅𝑂𝑈𝑇 = 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑟𝑜 𝑅𝑆 + 𝑟𝑜
= 𝑅𝑆 + 𝑟𝑜 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆
If 𝑅𝑆 ≪ 𝑟𝑜 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆 ,
𝑅𝑂𝑈𝑇 = 𝑟𝑜 ′ ≈ 𝑟𝑜 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆

𝐴𝜐 = −𝐺𝑚 𝑅𝐷 ฮ𝑅𝑂𝑈𝑇 ≈ −𝐺𝑚 𝑅𝐷 ቛ𝑟𝑜 ′

Chung-Yu (Peter) Wu 2018
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3.2 Common-Source (CS) Stage

3.2.5 CS with Source Degeneration (Cont.)
Example 3.6: Io is an idea current source.

𝐴𝜐 = −𝐺𝑚 𝑅𝐷 ቛ𝑟𝑜 ′
𝑔𝑚 𝑟𝑜
𝐺𝑚 =
𝑅𝑆 +[1+(𝑔𝑚 +𝑔𝑚𝑏 )𝑅𝑆 ]𝑟𝑜

𝑅𝐷 ቛ𝑟𝑜 ′ = ∞ԡ{𝑅𝑆 +[1 + (𝑔𝑚 +𝑔𝑚𝑏 )𝑅𝑆 ]𝑟𝑜 }

𝐴𝜐 = −𝑔𝑚 𝑟𝑜 ′

Chung-Yu (Peter) Wu 2018

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3.3 Source Follower

1 𝑊
𝜇 𝐶
2 𝑛 𝑜𝑥 𝐿
V𝑖𝑛 − 𝑉𝑇𝐻 − 𝑉𝑜𝑢𝑡 2 𝑅𝑆 = 𝑉𝑜𝑢𝑡 , 𝜆=0
𝑉𝑇𝐻 = 𝑉𝑇𝐻𝑂 + 𝛾( 2𝜙𝐹 + 𝑉𝑜𝑢𝑡 − 2 𝜙𝐹 )

𝑊
𝜕𝑉𝑜𝑢𝑡 𝜇𝑛 𝐶𝑜𝑥
𝐿
V𝑖𝑛 −𝑉𝑇𝐻 −𝑉𝑜𝑢𝑡 𝑅𝑆
⇒ ฬ = 𝑊 <1
𝜕𝑉𝑖𝑛 𝐴 1+𝜇𝑛 𝐶𝑜𝑥
𝐿
V
𝑖𝑛 −𝑉𝑇𝐻 −𝑉𝑜𝑢𝑡 𝑅𝑆 (1+𝜂)

(a)
At the operating point A ,
𝑊
𝑔𝑚 ȁ𝐴 = 𝜇𝑛 𝐶𝑜𝑥 V𝐼𝑁𝐴 − 𝑉𝑇𝐻𝐴 − 𝑉𝑂𝑈𝐴
𝐿

𝑔𝑚 𝑅𝑆
⇒ 𝐴𝜐 ȁ𝐴 = <1
1+𝑔𝑚 (1+𝜂)𝑅𝑆

(b) Chung-Yu (Peter) Wu 2018

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3.3 Source Follower (Cont.)

If 𝜂 ≪1,
𝑅𝑆
⇒ 𝐴𝜐 ȁ𝐴 ≈ 1 <1
𝑔𝑚
+𝑅𝑆

If 𝑔𝑚 𝑅𝑠 (1 + 𝜂) ≫ 1 ,
1
⇒ 𝐴𝜐 ȁ𝐴 ≈ <1
1+𝜂

Chung-Yu (Peter) Wu 2018

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3.3 Source Follower (Cont.)

𝑉𝑏𝑠 = −𝑉𝑜𝑢𝑡

𝑉𝑖𝑛 ≥ 𝑉𝑇𝐻 ⇒Gain nonlinearity.

Chung-Yu (Peter) Wu 2018

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3.3 Source Follower (Cont.)

(a) (b) (c)

1 1 1
Rout = = ||
g m + g mb g m g mb

Chung-Yu (Peter) Wu 2018

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3.3 Source Follower with Current Source Load (Cont.)

(a) (b)
1
|| ro1 || ro 2 || RL
g mb
M1 : Sat Av = 1
1 1 Rout = || ro1 || ro 2 || RL
M2 : Sat || ro1 || ro 2 || RL + g m + g mb
DC current g mb gm
M2 : 𝐼2
𝑅𝐿 : 𝐼𝐿 ﹡If 𝑅𝐿 is too small, 𝐼1 ↑ ⇒ 𝑉GS1 ↑⇒ 𝑀2 could be driven to linear.
M1 : 𝐼2 +𝐼𝐿 = 𝐼1 ﹡Different 𝑅𝐿 ⇒ different 𝐼𝐿 ⇒ bias current of 𝑀1 is changed.
Chung-Yu (Peter) Wu 2018
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3.3 Source Follower with Current Source Load (Cont.)

﹡Gain nonlinearity.
﹡Voltage headroom consumption (level shift).
﹡Low output resistance (lower than CS).
﹡Can be used to a level shifter.

Chung-Yu (Peter) Wu 2018

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3.3 Source Follower (Cont.)

Nonlinearity
Nonlinear dependence of VTH upon the source potential.
rO of the transistor also changes substantially with VDS in
submicron technology due to DIBL effect.
PMOS source follower with no body effect.

Higher output impedance using PMOS source follower.

Chung-Yu (Peter) Wu 2018
 Chapter 3
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3.4 Common-Gate Stage

If M1 is saturated, the output voltage can be
expressed as (𝜆=0):
1 W
Vout = VDD − n Cox (Vb − Vin − VTH )2 RD
2 L IN = VIN+Vin
Vbs = - Vin
Vout W VTH
= − nCox (Vb − IN − VTH ) −1 − RD ( = 0)
Vin L Vin
VTH V
For = TH = =
Vin VSB 2 2 F +V SB
Vout W
= n Cox (Vb − Vin − VTH )(1 + )RD = g m (1 + ) RD
Vin L
1 1
Rin = =
g m + g mb g m (1 + )

Body effect increases the equivalent transconductance of the stage.

Chung-Yu (Peter) Wu 2018
2015
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3.4 Common-Gate Stage (Cont.)

Example 3.10:

RD = 50

1
Rin = 50
M2
g m + g mb
RD can be larger without reflection loss.

Chung-Yu (Peter) Wu 2018

2015
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3.4 Common-Gate Stage (Cont.)

By taking into account both the output impedance of the transistor ( ≠0) and the
impedance of the signal source (or the output impedance of the previous stage)

Vbs = V1

Vout Vout V
V1 − RS + Vin = 0 rO − − g mV1 − g mbV1 − out RS + Vin = Vout
RD RD RD
− Vout R VoutRS
rO − ( g m + g mb ) Vout S − Vin − + Vin = Vout
RD RD RD
Vout ( gm + gmb )rO + 1 1 + 1 /( gm + gmb )rO
= RD = RD
Vin rO + ( gm + gmb )rO R S + RS + RD RS + 1 /( gm + gmb ) + ( RS + RD ) /( gm + gmb )rO
Chung-Yu (Peter) Wu 2018 2015
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3.4 Common-Gate Stage (Cont.)

By taking into account both the output impedance of the transistor ( ≠0) and the
impedance of the signal source (or the output impedance of the previous stage) :

VX RD + rO RD 1
RD I X + rO I X − ( g m + g mb )VX = VX Rin = = +
I X 1 + ( g m + g mb )rO ( g m + g mb )rO g m + g mb
(if ( gm + gmb )rO >>1)
For RD=0
VX rO 1 1 1
Rin = = = Rin = rO || ||
I X 1 + ( g m + g mb )rO g m + g mb + 1 / rO g m g mb
For RD→∞ (ideal current source), Rin→∞
Chung-Yu (Peter) Wu 2018
2015
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3.4 Common-Gate Stage (Cont.)

Rout = {[1 + ( g m + g mb )rO ]RS + rO } || RD

The output impedance is similar to that of a common source gain stage with
source degeneration.

CG stage : Low Rin , High Rout

Chung-Yu (Peter) Wu 2018

2015
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3.5 Cascode Stage

Cascade of a CS stage and a CG stage.

Vout (min) = VDS1( sat ) + VDS 2 ( sat )

Vx = VDS1

Av = − g m1 ( RD || Rout ) Rout = [1 + ( g m2 + g mb 2 )rO 2 ]rO1 + rO 2 ( g m2 + g mb 2 )rO 2 rO1

− g m1 RD ∵ shielding property: △V in Vout, smaller change in Vx.
The voltage gain is nearly independent of the transconductance and body effect of M2.
Chung-Yu (Peter) Wu 2018
2014
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3.5 Cascode Stage (Cont.)

I1 is an ideal current source.

If both M1 and M2 operate in saturation.

Gm gm1 Rout ( gm2 + gmb 2 )rO 2 rO1 Av −[( gm2 + gmb 2 )rO 2 ]( gm1rO1 )

The maximum voltage gain is roughly equal to the square of the intrinsic gain of
the transistors.

Chung-Yu (Peter) Wu 2018

2015
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3.5 Cascode Stage (Cont.)

The maximum output swing is equal to

Vout,swing = VDD − VDS1 − VDS 2 − VSD3 − VSD4

VDSi = VGSi − VTHi i = 1, ,4

Rout = { 1 + (g m2 + g mb 2 )rO 2 rO1 + rO 2 } || { 1 + ( g m3 + g mb3 )rO3 rO 4 + rO3}

Av − g m1 (g m2 rO 2 rO1 ) || ( g m3rO3rO 4 )

Chung-Yu (Peter) Wu 2018

2015
 Chapter 3
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3.5 Cascode Stage (Cont.)

3.5.1 Folded Cascode

CS
CG

Vin=Vin1, ID1=I1 ID2=0; Vin=VDD –VTH1, ID1=0 ID2=I1

A PMOS-NMOS combination.
The total bias current in this case must be higher to achieve comparable performance.
Chung-Yu (Peter) Wu 2018
2015