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Assignment 2 Vlsi

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Nivedita Acharyya 2035
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34 views

Assignment 2 Vlsi

Uploaded by

Nivedita Acharyya 2035
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

ASSIGNMENT 2 (VLSI)

BY
NIVEDITA ACHARYYA

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Question1: Design 4:1 and 8:1 Mux using n-FET based Pass transistor logic.
Show the circuit diagram and input/output waveforms.

Answer: First we need to design a 4*1 MUX. We know that it contains 2


select lines and 4 inputs to obtain an output. Based on the knowledge of the
digital circuit design it is designed in form of:

It’s truth table is in form of:

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Its logical expression is in form of:

Y = I0S0’S1’+I1S0’S1+I2S0S1’+I3S0S1

Now we have to design it using nFET transistor logic as shown in simulation:

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It is run on ADL software by selecting on the I0,I1,I2 and I3 lines & OUT line we will get the
Input and Output waveform as :

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By selecting the select lines in diagram as:

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It’s total response is as:

Now we will design 8*1 MUX that contains 3 select lines and 8 input lines and produce one
output, by having the knowledge of digital circuit design we draw the diagram as:

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It’s truth table is expressed as:

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It’s logical expression is as:

Y = S0 S1 S2 I0 + S0 S1 S2 I1 + S0 S1 S2 I2 + S0 S1 S2 I3 + S0 S1 S2 I4 + S0
S1 S2 I5 + S0 S1 S2 I6 + S0 S1 S2 I7

Now we will design it using nFET transistor logic as:

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Now we will run it using ADL software by selecting I0,I1,I2,I3,I4,I5,I6 and I7
input lines and an output line we will get the input and output waveform as:

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By selecting the select lines in the diagram we will get the total response as:

In this way we have completed the task.

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Question 2: Design 4:1 and 8:1 Mux using p-FET based Pass transistor logic.
Show circuit diagram and input/output waveforms.

Answer: First we need to design a 4*1 MUX . We know that it contains 2


select lines and 4 inputs to obtain an output. Based on the knowledge of the
digital circuit design it is designed in form of:

Page 15 of 21
It’s truth table is in form of:

Its logical expression is in form of:

Y = I0S0’S1’+I1S0’S1+I2S0S1’+I3S0S1

Now we have to design it using pFET transistor logic as shown in simulation:

Page 16 of 21
Now we will run it by using ADL software by selecting the select lines and output line as shown
in the figure, we will obtain the input and output waveforms as:

Now we will design 8*1 MUX that contains 3 select lines and 8 input lines and produce one
output, by having the knowledge of digital circuit design we draw the diagram as:

Page 17 of 21
It’s truth table is expressed as:

Page 18 of 21
It’s logical expression is as:

Y = S0 S1 S2 I0 + S0 S1 S2 I1 + S0 S1 S2 I2 + S0 S1 S2 I3 + S0 S1 S2 I4 + S0
S1 S2 I5 + S0 S1 S2 I6 + S0 S1 S2 I7

Now we will design it using pFET transistor logic as:

Page 19 of 21
Now we will run it by using the I0,I1,I2,I3,I4,I5,I6 and I7 lines and output line
as shown in the figure ,we will get the input and output responses as:

By selecting the A, B, C select lines and output lines we will get the graph as:

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In this way, we have completed the task.

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