Reconfigurable Computing

CS G553

Dr. A. Amalin Prince

BITS - Pilani K K Birla Goa Campus
Department of Electrical and Electronics Engineering

‹#›
Lecture –24
Mapping Design to Reconfigurable Platform: Logic
Synthesis, Logic Representation and Node Manipulation

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FPGA Physical Design Flow

Design Synthesis Logic

Entry Optimization

Placement Packing LUTs Mapping

to CLBs to k-LUT

Routing Simulation Configure an

FPGA

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Synthesis

 Synthesis is the process by which the system specifications

and constraints are translated to an implementation (a net
list of connected components).
 Synthesis is considered to be a key stage in automated
design tools (CAD Tools).
 A significant area of research in EDA is in the development
of tools that can synthesize hardware from a design written
in the form of high-level programming language such as C.
 It is believed that these ``hardware compilers” will help to
decrease development time, thus shortening the crucial
time to market for designs.

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Design Flow for Programmable Logic

RTL design
RTL
RTL elaboration and Synthesis
controller datapath optimization

Architecture-independent
optimization
Logic
Technology mapping & Synthesis
Architecture-specific
optimization
net list
Clustering & placement

Placement-driven Physical
optimization & incremental
placement Design
Routing (backend
design)
1001110010… Bitstream generation

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Taxonomy of Synthesis

Architecture Level Logic Level Circuit Level

Behavioral I = 1.. 16
Sum = sum *z-1
View

* Logic * Circuit
* Architectural Synthesis
Synthesis Synthesis

VDD

Structural FSM
B

View
* A

What is system level synthesis? CS G553 6

Logic “Synthesis”?
 Logic synthesis
o A program that “designs” logic from abstract descriptions of the logic
(Boolean equations).
• takes constraints (e.g. size, speed, power, etc)
• uses a library (e.g. standard cells, Macro Cells, 3-input gates)

 How?
o You write an “abstract” VHDL/Verilog description of the logic
o The synthesis tool provides alternative implementations
constraints

VHDL/Verilog synthesis or …

library
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Goal
 A structured system is made upon a set
of combinatorial parts separated by
memory elements

 The goal of the logic synthesis is to

provide an implementation of a
structured system for a given platform
or for a given target library

 FPGA-Goal: Generation of configuration

data A structured digital system
 The implementation must be optimized
according to factors like
o area, delay,
o power consumption,
o testability, etc...

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Logic Synthesis: Categories

Three categories of logic synthesis can be

distinguished:
1. Two Level combinational logic
2. Multi Level combinational logic
3. Sequential logic

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Two-level-logic
 Two approaches to logic synthesis:
o Two-level logic synthesis: targets designs X1
represented in two-level logic sum of *
product-terms
X2
• sums are implemented on the first level F
and the product on the second level X3 *
X2 +
o Advantages:
*
• Natural representation of Boolean
X4
functions
• Well understood and Easy *
manipulation X3

o Drawbacks: not representative of the logic Two-level logic

complexity.
• bad estimator of complexity during logic
optimization
o Initially developed for PALs and PLAs

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Multi-level-logic

 Multi-level logic synthesis X1 F2

o Multi-level logic synthesis: targets multi-
level designs X2
• many Boolean function on the path from
the inputs to the outputs X3
o Advantages: F1
• Small X2
• Faster X4
• Consume less power in most cases X6 F3
• Representative of the logic complexity
o Drawbacks: X5

• Difficult to manipulate
X5
• Few manipulation algorithms exist Multi-level logic
o Appropriate for mask-programmable or
field programmable devices
Multi-level will therefore be considered in this course

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Boolean Networks
 Multi-level logic:
o are usually represented using Boolean networks

 A Boolean network
o is a directed Acyclic graph (DAG) in which:
• A node represents an arbitrary Boolean
function
• An edge represents the (data) dependency
between nodes

 viable representation is required for

Manipulation.
y1 = x1 + x2
 Important factors are:
y2 = x3 · x4
o memory efficiency
y3 = (x5 · x6)’
o correlation with the final representation
y4 = (y1 + y2)’
z1 = y1 + y4
z2 = y2y3
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FPGA Physical Design Flow

Design Synthesis Logic

Entry Optimization

Placement Packing LUTs Mapping

to CLBs to k-LUT

Routing Simulation Configure an

FPGA

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Logic Optimization

 Divide logic optimization into two subproblems:

o Technology-independent optimization
• determine overall logic structure
• estimate costs (mostly) independent of technology
• simplified cost modeling
o Technology-dependent optimization (technology mapping)
• binding onto the gates in the library
• detailed technology-specific cost model

Orchestration of various optimization/transformation techniques for each

subproblem

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Logic Synthesis

Technology
independent

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Node Representation
 Node representation choices:
1. Sum-Of-Products (SOP)
2. Factored Form (FF)
3. Binary Decision Diagram (BDD)

 Sum-Of-Products:
✓ Well understood
✓ Easy to manipulate
✓ Many optimization algorithms available
 Not representative of the logic complexity
• Estimation of progress during logic minimization is difficult

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Node Representation : (FF)

 Factored form (FF):

o Defined recursively:
• (FF = product) or (FF = sum).
• (product = literal) or (product = FF1*FF2).
• (sum = literal) or (sum = FF1+FF2).
c(a + b(d + e))
 Example:
c a + b ( d + e)

 Few manipulation algorithms.

a b(d + e)

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Node Representation: BDD

 BDD:
o A rooted DAG
o Nodes:
• Variable node:
• non-terminal:
– index(v)  {1, …,n} (for
A + B . C’
variable xi)
– Two children low(v) , high(v)
• Constant node:
• terminal node:
– value(v)  {0,1}

A+B+C A B C
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Node Representation: BDD

 BDD from Truth Table:

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Node Representation: BDD

 BDD Simplification
ABC + A’C’

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Node Representation: BDD

 Implementation by MUX

F = ABC +AC

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Node Representation: BDD

 BDD → Boolean function

o Root v : Boolean function f(v)

o If v is terminal,
• fv = value(v)

o If v is non-terminal with index i, Shannon expansion theorem is

used:
• fv = xi’ flow(v) + xi fhigh(v)

o Traverse from root to terminals

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Node Representation : BDD
 Example:
o f = abc + bd + cd
b
0 1
b c c
0 1 0 0 1
cd ac + d + cd 0 d d
0 1 0
b 1
0 1 0 1 a 1
0 1
c c
0 1 0 1 0 1
0 d d a+d

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Node Representation: OBDD

 OBDD:
o If we fix the order of nodes (give a fix index)

o Ordering the nodes from the root to the terminal

• For each non-terminal v
– if low(v) is non-terminal, then index(low(v)) < index(v).
– if high(v) is non terminal, then index(high(v)) < index(v).

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Node Representation: ROBDD

 ROBDD (Reduced Ordered BDD)

o An ROBDD of G is an OBDD with:
• low(v) ≠ high(v),  v G
•  v, v’ G the subtree rooted at v and the one
rooted at v’ are not isomorphic

o Two BDDs G and G’ are isomorphic iff there

exists a obijective function  : G → G ' s.t.
• For a terminal node v in G, σ(v) is a terminal
node in G’
• For a non-terminal node v, σ(v) is a non-
terminal node with
– σ(low(v)) = low(σ(v)) and
– σ(high(v)) = high(σ(v))

f = abc + bd + cd
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Node Representation: ROBDD

 BDD → ROBDD
o Fix order of variables
o Delete redundant nodes
o Share subgraphs that represent same function

ROBDD is canonical/Unique

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Node Representation: ROBDD Example

 f = (a + b).c

OBDD for order OBDD for order ROBDD for order

(a,c,b) (a,b,c) (a,b,c)

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Node Representation: ROBDD Example

a a
c
f f
c
b b

c c
0 0
1 1
b Isomorphic b
1 graphs 1
a a
0 0
1 1
0 0
0 1 0 1
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Node Manipulation

 Node Manipulation:
o Input:
• A suitable node representation
o Goal:
• Generation of an equivalent and cost effective simplified function

 Operations:
o Decomposition
o Extraction
o Factoring
o Substitution
o Collapsing (Elimination)

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Node Manipulation: Decomposition

 Decomposition:
➢ Take a single Boolean expression and replace with collection of
new expressions:
➢ A Boolean function f(X) is decomposable if we can find a
function g(X) such that f(X) = f’(g(X), X).
(12 literals)
F = A B C + A B D + A' C' D' + B' C' D'

F = M N + M' N'
A M=AB (8 literals)
B N=C+D
C
A A
B B
D
F
A F
C C
D D
B
C
D
Before Decomposition After Decomposition

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Node Manipulation:

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Node Manipulation: Decomposition

 Decomposition:
o Example 2:

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Node Manipulation: Extraction

 Extraction:
o Identify common intermediate sub-functions from a set of given
functions.
F = (A + B) C D + E (11 literals & 8 gates)
G = (A + B) E'
H=CDE

(11 literals & 7 gates)

F=XY + E
G = X E' "Kernels":
H=YE primary divisors
X=A+B
Y=CD
E A X
A B
B F F
C Y
C D
D G E G
A C
B D H H
E
Before Extraction After Extraction

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Node Manipulation: Extraction

 Extraction:
o Example 2:

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Node Manipulation: Factoring

 Factoring:
o Transformation of SOP-expressions in factored form
F=AC + AD + BC + BD + E (9 literals & 5 gates)

F = (A + B) (C + D) + E
(5 literals & 4 gates)
A
C

A
D A
B
B
F F
C C
D
B E
D
E

Before Factoring After Factoring

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Node Manipulation: Substitution

 Substitution:
o A function is reduced in complexity by using an additional input that
was not previously in its support set.
• The transformation requires the creation of a dependency,

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Node Manipulation: Substitution

 Substitution:
o Example:

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Node Manipulation: Collapsing

 Collapsing (Elimination):
o The elimination of an internal vertex is its removal from the network.

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Node Manipulation: Collapsing

 Collapsing:
o Example:

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The End

 Questions ?

 Thank you for your attention

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