4 Bit Carry Look Ahead Adder in Verilog

DataFlow Model : 4 Bit CLA

module CLA_4bit(
output [3:0] S,
output Cout,PG,GG,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule

Test Bench : 4 Bit CLA

module Test_CLA_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] S;
wire Cout;
wire PG;
wire GG;

// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),
.Cin(Cin)
);

initial begin
// Initialize Inputs
A = 0; B = 0; Cin = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b100;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
#10 A=4'b1110;B=4'b1001;Cin=1'b0;
#10 A=4'b1111;B=4'b1010;Cin=1'b0;
end

initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b GG=%b",A,B,Cin,S,Cout,PG,GG);
end
endmodule

Simulation Results

time = 0 A=0000 B=0000 Cin=0 : Sum=0000 Cout=0 PG=0 GG=0

time = 100 A=0001 B=0000 Cin=0 : Sum=0001 Cout=0 PG=0 GG=0
time = 110 A=0100 B=0011 Cin=0 : Sum=0111 Cout=0 PG=0 GG=0
time = 120 A=1101 B=1010 Cin=1 : Sum=1000 Cout=1 PG=0 GG=1
time = 130 A=1110 B=1001 Cin=0 : Sum=0111 Cout=1 PG=0 GG=1
time = 140 A=1111 B=1010 Cin=0 : Sum=1001 Cout=1 PG=0 GG=1

module CLA_4bit(
output [3:0] S,
output Cout,PG,GG,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
 assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule

Test Bench : 4 Bit CLA

module Test_CLA_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] S;
wire Cout;
wire PG;
wire GG;

// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),
.Cin(Cin)
);

initial begin
// Initialize Inputs
A = 0; B = 0; Cin = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b100;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
#10 A=4'b1110;B=4'b1001;Cin=1'b0;
#10 A=4'b1111;B=4'b1010;Cin=1'b0;
end

initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b GG=%b",A,B,Cin,S,Cout,PG,GG);
end
endmodule

Simulation Results

time = 0 A=0000 B=0000 Cin=0 : Sum=0000 Cout=0 PG=0 GG=0

time = 100 A=0001 B=0000 Cin=0 : Sum=0001 Cout=0 PG=0 GG=0
time = 110 A=0100 B=0011 Cin=0 : Sum=0111 Cout=0 PG=0 GG=0
time = 120 A=1101 B=1010 Cin=1 : Sum=1000 Cout=1 PG=0 GG=1
time = 130 A=1110 B=1001 Cin=0 : Sum=0111 Cout=1 PG=0 GG=1
time = 140 A=1111 B=1010 Cin=0 : Sum=1001 Cout=1 PG=0 GG=1

module CLA_4bit(

output [3:0] S,

output Cout,PG,GG,

input [3:0] A,B,

input Cin

);

wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
 assign C[0] = Cin;

assign C[1] = G[0] | (P[0] & C[0]);

assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);

assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);

assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] &
P[1] & P[0] & C[0]);

assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);

endmodule

Test Bench : 4 Bit CLA

module Test_CLA_4bit;

// Inputs

reg [3:0] A;

reg [3:0] B;

reg Cin;

// Outputs

wire [3:0] S;

wire Cout;

wire PG;

wire GG;
// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (

.S(S),

.Cout(Cout),

.PG(PG),

.GG(GG),

.A(A),

.B(B),

.Cin(Cin)

);

initial begin

// Initialize Inputs

A = 0; B = 0; Cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;

#10 A=4'b100;B=4'b0011;Cin=1'b0;

#10 A=4'b1101;B=4'b1010;Cin=1'b1;

#10 A=4'b1110;B=4'b1001;Cin=1'b0;

#10 A=4'b1111;B=4'b1010;Cin=1'b0;

end
 initial begin

$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b GG=

%b",A,B,Cin,S,Cout,PG,GG);

end

endmodule

Simulation Results

time = 0 A=0000 B=0000 Cin=0 : Sum=0000 Cout=0 PG=0 GG=0

time = 100 A=0001 B=0000 Cin=0 : Sum=0001 Cout=0 PG=0 GG=0

time = 110 A=0100 B=0011 Cin=0 : Sum=0111 Cout=0 PG=0 GG=0

time = 120 A=1101 B=1010 Cin=1 : Sum=1000 Cout=1 PG=0 GG=1

time = 130 A=1110 B=1001 Cin=0 : Sum=0111 Cout=1 PG=0 GG=1

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4 Bit Carry Look Ahead Adder in Verilog
DataFlow Model : 4 Bit CLA

module CLA_4bit(
output [3:0] S,
output Cout,PG,GG,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule

Test Bench : 4 Bit CLA

module Test_CLA_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] S;
wire Cout;
 wire PG;
wire GG;

// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),
.Cin(Cin)
);

initial begin
// Initialize Inputs
A = 0; B = 0; Cin = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b100;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
#10 A=4'b1110;B=4'b1001;Cin=1'b0;
#10 A=4'b1111;B=4'b1010;Cin=1'b0;
end

initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b GG=%b",A,B,Cin,S,Cout,PG,GG);
end
endmodule

Simulation Results

time = 0 A=0000 B=0000 Cin=0 : Sum=0000 Cout=0 PG=0 GG=0

time = 100 A=0001 B=0000 Cin=0 : Sum=0001 Cout=0 PG=0 GG=0
time = 110 A=0100 B=0011 Cin=0 : Sum=0111 Cout=0 PG=0 GG=0
time = 120 A=1101 B=1010 Cin=1 : Sum=1000 Cout=1 PG=0 GG=1
time = 130 A=1110 B=1001 Cin=0 : Sum=0111 Cout=1 PG=0 GG=1
time = 140 A=1111 B=1010 Cin=0 : Sum=1001 Cout=1 PG=0 GG=1

4 Bit Carry Look Ahead Adder in Verilog

DataFlow Model : 4 Bit CLA

module CLA_4bit(

output [3:0] S,

output Cout,PG,GG,

input [3:0] A,B,

input Cin

);

wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
 assign C[0] = Cin;

assign C[1] = G[0] | (P[0] & C[0]);

assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);

assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);

assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] &
P[1] & P[0] & C[0]);

assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);

endmodule

Test Bench : 4 Bit CLA

module Test_CLA_4bit;

// Inputs

reg [3:0] A;

reg [3:0] B;

reg Cin;

// Outputs

wire [3:0] S;

wire Cout;

wire PG;

wire GG;
// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (

.S(S),

.Cout(Cout),

.PG(PG),

.GG(GG),

.A(A),

.B(B),

.Cin(Cin)

);

initial begin

// Initialize Inputs

A = 0; B = 0; Cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;

#10 A=4'b100;B=4'b0011;Cin=1'b0;

#10 A=4'b1101;B=4'b1010;Cin=1'b1;

#10 A=4'b1110;B=4'b1001;Cin=1'b0;

#10 A=4'b1111;B=4'b1010;Cin=1'b0;

end
 initial begin

$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b GG=

%b",A,B,Cin,S,Cout,PG,GG);

end

endmodule

Simulation Results

time = 0 A=0000 B=0000 Cin=0 : Sum=0000 Cout=0 PG=0 GG=0

time = 100 A=0001 B=0000 Cin=0 : Sum=0001 Cout=0 PG=0 GG=0

time = 110 A=0100 B=0011 Cin=0 : Sum=0111 Cout=0 PG=0 GG=0

time = 120 A=1101 B=1010 Cin=1 : Sum=1000 Cout=1 PG=0 GG=1

time = 130 A=1110 B=1001 Cin=0 : Sum=0111 Cout=1 PG=0 GG=1

time = 140 A=1111 B=1010 Cin=0 : Sum=1001 Cout=1 PG=0 GG=1