REJ09B0016-0120Z

M16C/62 Group (M16C/62P)

16 Hardware Manual

RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER

M16C FAMILY / M16C/60 SERIES

Before using this material, please visit the our website to confirm that this is the most
current document available.

Rev. 1.20
Revision date: Sep. 11, 2003 www.renesas.com
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 How to Use This Manual

This hardware manual provides detailed information on features in the M16C/62 Group
(M16C/62P) microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and micro-
computer.

Each register diagram contains bit functions with the following symbols and descriptions.
*1
XXX register
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 XXX XXX 0016

Bit symbol Bit name Function RW *2

b1 b0
XXX0 XXX bit 1 0: XXX RW
0 1: XXX
1 0: Avoid this setting
XXX1 1 1: XXX RW

Nothing is assigned.
(b2) When write, should set to "0". When read, its content is indeterminate.

(b3) Reserved bit Should set to "0" RW

*3

XXX4 XXX bit Function varies depending on each RW

operation mode

XXX5 WO

XXX6 RW

0: XXX
XXX7 XXX bit RO
1: XXX

*1
Blank:Set to "0" or "1" according to your intended use
0: Set to "0"
1: Set to "1"
X: Nothing is assigned

*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
M16C Family Documents

Document Contents

Short Sheet Hardware overview

Data Sheet Hardware overview and electrical characteristics

Hardware Manual Hardware specifications (pin assignments,

memory maps, specifications of peripheral func-
tions, electrical characteristics, timing charts)

Software Manual Detailed description about instructions and mi-

crocomputer performance by each instruction

Application Note • Application examples of peripheral functions

• Sample programs
• Introductory description about basic functions in
M16C family
• Programming method with the assembly and C
languages
 Table of Contents
Quick Reference to Pages Classified by Address _____________ B-1

Overview ________________________________________________ 1
Applications........................................................................................................................................... 1

Performance Outline ............................................................................................................................. 2

Block Diagram....................................................................................................................................... 3

Product List ........................................................................................................................................... 4

Pin Configuration .................................................................................................................................. 6

Pin Description ...................................................................................................................................... 9

Memory ________________________________________________ 11

Central Processing Unit (CPU) _____________________________ 12

SFR ___________________________________________________ 14

Reset __________________________________________________ 20
Hardware Reset .................................................................................................................................. 20

Software Reset ................................................................................................................................... 21

Voltage Detection Circuit .................................................................................................................... 24

Voltage Down Detection Interrupt ....................................................................................................... 27

Processor Mode _________________________________________ 29

(1) Types of Processor Mode ............................................................................................................. 29

(2) Setting Processor Modes .............................................................................................................. 29

Bus ___________________________________________________ 33
Bus Mode ............................................................................................................................................ 33

Bus Control ......................................................................................................................................... 34

Memory Space Expansion Function ________________________ 44

(1) 1 Mbyte Mode ................................................................................................................................ 44

(2) 4 Mbyte Mode ................................................................................................................................ 44

Clock Generation Circuit __________________________________ 51

(1) Main Clock ................................................................................................................................. 58

(2) Sub Clock .................................................................................................................................. 59

A-1
 (3) Ring Oscillator Clock ................................................................................................................. 60

(4) PLL Clock .................................................................................................................................. 60

CPU Clock and Peripheral Function Clock ......................................................................................... 62

(1) CPU Clock and BCLK ............................................................................................................... 62

(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) .............................. 62

Clock Output Function ........................................................................................................................ 62

Power Control ..................................................................................................................................... 63

(1) Normal Operation Mode ............................................................................................................ 63

(2) Wait Mode ................................................................................................................................. 64

(3) Stop Mode ................................................................................................................................. 66

System Clock Protective Function ...................................................................................................... 71

How to Use Oscillation Stop and Re-oscillation Detect Function ....................................................... 73

Protection ______________________________________________ 74

Interrupts ______________________________________________ 75
Type of Interrupts ............................................................................................................................ 75

Software Interrupts ......................................................................................................................... 76

Hardware Interrupts ........................................................................................................................ 77

Interrupts and Interrupt Vector ........................................................................................................ 78

Interrupt Control .............................................................................................................................. 80

Interrupt Sequence ......................................................................................................................... 83

Variation of IPL when Interrupt Request is Accepted ..................................................................... 84

Interrupt Response Time ................................................................................................................ 84

Saving Registers ............................................................................................................................. 85

Returning from an Interrupt Routine ............................................................................................... 87

Interrupt Priority .............................................................................................................................. 87

Interrupt Priority Resolution Circuit ................................................................................................. 87

______
INT Interrupt ........................................................................................................................................ 89
______
NMI Interrupt ....................................................................................................................................... 90

Key Input Interrupt .............................................................................................................................. 90

Address Match Interrupt ..................................................................................................................... 91

Watchdog Timer _________________________________________ 93

DMAC _________________________________________________ 95

A-2
1. Transfer Cycles ............................................................................................................................. 100

2. DMA Transfer Cycles .................................................................................................................... 102

3. DMA Enable .................................................................................................................................. 103

4. DMA Request ................................................................................................................................ 103

5. Channel Priority and DMA Transfer Timing .................................................................................. 104

Timers ________________________________________________ 105

Timer A _______________________________________________ 107

1. Timer Mode ................................................................................................................................... 110

2. Event Counter Mode ..................................................................................................................... 111

3. One-shot Timer Mode ................................................................................................................... 116

4. Pulse Width Modulation (PWM) Mode .......................................................................................... 118

Timer B _______________________________________________ 121

1. Timer Mode ................................................................................................................................... 123

2. Event Counter Mode ..................................................................................................................... 124

3. Pulse Period and Pulse Width Measurement Mode ..................................................................... 125

Three-phase Motor Control Timer Function _________________ 127

Serial I/O ______________________________________________ 137

Clock Synchronous serial I/O Mode ................................................................................................. 146

Clock Asynchronous Serial I/O (UART) Mode .................................................................................. 153

Special Mode 1 (I2C mode) .......................................................................................................... 160

Special Mode 2 ............................................................................................................................. 170

Special Mode 3 (IE mode) ............................................................................................................ 175

Special Mode 4 (SIM Mode) (UART2) .......................................................................................... 177

SI/O3 and SI/O4 ................................................................................................................................ 182

A-D Converter__________________________________________ 187

(1) One-shot Mode ............................................................................................................................ 191

(2) Repeat mode ............................................................................................................................... 193

(3) Single Sweep Mode ................................................................................................................... 195

(4) Repeat Sweep Mode 0 ................................................................................................................ 197

(5) Repeat Sweep Mode 1 ................................................................................................................ 199

D-A Converter__________________________________________ 203

CRC Calculation ________________________________________ 205

A-3
Programmable I/O Ports _________________________________ 207
(1) Port Pi Direction Register (PDi Register, i = 0 to 13) ................................................................... 207

(2) Port Pi Register (Pi Register, i = 0 to 13) .................................................................................... 207

(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ................. 207

(4) Port Control Register ................................................................................................................... 207

Electrical Characteristics ________________________________ 220

Electrical Characteristics (Vcc1 = Vcc2 = 5V) ................................................................................... 225

Electrical Characteristics (Vcc1 = Vcc2 = 3V) ................................................................................... 242

Flash Memory Version___________________________________ 259

Memory Map ..................................................................................................................................... 261

Boot Mode ........................................................................................................................................ 262

Functions To Prevent Flash Memory from Rewriting ........................................................................ 262

• ROM Code Protect Function ...................................................................................................... 262

• ID Code Check Function ............................................................................................................ 262

CPU Rewrite Mode ........................................................................................................................... 264

• EW0 Mode .................................................................................................................................. 265

• EW1 Mode .................................................................................................................................. 265

Software Commands .................................................................................................................... 273

Data Protect Function ................................................................................................................... 278

Status Register ............................................................................................................................. 278

Full Status Check .......................................................................................................................... 280

Standard Serial I/O Mode ............................................................................................................. 282

Parallel I/O Mode _______________________________________ 289

User ROM and Boot ROM Areas ...................................................................................................... 289

ROM Code Protect Function ............................................................................................................. 289

Package Dimensions ____________________________________ 290

Register Index _________________________________________ 295

M16C/62 Group (M16C/62P) Usage Notes Reference Book

For the most current Usage Notes Reference Book, please visit our website.

A-4
Quick Reference to Pages Classified by Address

Address Register Symbol Page Address Register Symbol Page

000016 004016
000116 004116
000216 004216
000316 004316
000416 Processor mode register 0 PM0 30 004416 INT3 interrupt control register INT3IC 81
000516 Processor mode register 1 PM1 31 004516 Timer B5 interrupt control register TB5IC 81
000616 System clock control register 0 CM0 53 004616 Timer B4 interrupt control register, TB4IC,
81
000716 System clock control register 1 CM1 54 UART1 BUS collision detection interrupt control register U1BCNIC
000816 Chip select control register CSR 34 004716 Timer B3 interrupt control register, TB3IC, 81
000916 Address match interrupt enable register AIER 92 UART0 BUS collision detection interrupt control register U0BCNIC
000A16 Protect register PRCR 74 004816 SI/O4 interrupt control register S4IC, 81
000B16 Data bank register DBR 44 INT5 interrupt control register INT5IC
000C16 Oscillation stop detection register CM2 55 004916 SI/O3 interrupt control register, S3IC, 81
000D16 INT4 interrupt control register INT4IC
000E16 Watchdog timer start register WDTS 94 004A16 UART2 Bus collision detection interrupt control register BCNIC 81
000F16 Watchdog timer control register WDC 24, 94 004B16 DMA0 interrupt control register DM0IC 81
001016 004C16 DMA1 interrupt control register DM1IC 81
001116 Address match interrupt register 0 RMAD0 92 004D16 Key input interrupt control register KUPIC 81
001216 004E16 A-D conversion interrupt control register ADIC 81
001316 004F16 UART2 transmit interrupt control register S2TIC 81
001416 005016 UART2 receive interrupt control register S2RIC 81
001516 Address match interrupt register 1 RMAD1 92 005116 UART0 transmit interrupt control register S0TIC 81
001616 005216 UART0 receive interrupt control register S0RIC 81
001716 005316 UART1 transmit interrupt control register S1TIC 81
001816 005416 UART1 receive interrupt control register S1RIC 81
001916 Voltage detection register 1 VCR1 25 005516 Timer A0 interrupt control register TA0IC 81
001A16 Voltage detection register 2 VCR2 25 005616 Timer A1 interrupt control register TA1IC 81
001B16 Chip select expansion control register CSE 40 005716 Timer A2 interrupt control register TA2IC 81
001C16 PLL control register 0 PLC0 57 005816 Timer A3 interrupt control register TA3IC 81
001D16 005916 Timer A4 interrupt control register TA4IC 81
001E16 Processor mode register 2 PM2 56 005A16 Timer B0 interrupt control register TB0IC 81
001F16 Voltage down detection interrupt register D4INT 25 005B16 Timer B1 interrupt control register TB1IC 81
002016 005C16 Timer B2 interrupt control register TB2IC 81
002116 DMA0 source pointer SAR0 99 005D16 INT0 interrupt control register INT0IC 81
002216 005E16 INT1 interrupt control register INT1IC 81
002316 005F16 INT2 interrupt control register INT2IC 81
002416 006016
002516 DMA0 destination pointer DAR0 99 006116
002616 006216
002716 006316
002816 006416
DMA0 transfer counter TCR0 99
002916 006516
002A16 006616
002B16 006716
002C16 DMA0 control register DM0CON 98 006816
002D16 006916
002E16 006A16
002F16 006B16
003016 006C16
003116 DMA1 source pointer SAR1 99 006D16
003216 006E16
003316 006F16
003416 007016
003516 DMA1 destination pointer DAR1 99 007116
003616 007216
003716 007316
003816 007416
DMA1 transfer counter TCR1 99
003916 007516
003A16 007616
003B16 007716
003C16 DMA1 control register DM1CON 98 007816
003D16 007916
003E16 007A16
003F16 007B16
007C16
Note: The blank areas are reserved and cannot be accessed by users.
007D16
007E16
007F16

B-1
Quick Reference to Pages Classified by Address

Address Register Symbol Page Address Register Symbol Page

008016 034016 Timer B3, 4, 5 count start flag TBSR 122
008116 034116
008216 034216 132
Timer A1-1 register TA11
008316 034316
008416 034416
Timer A2-1 register TA21 132
008516 034516
008616 034616 132
Timer A4-1 register TA41
034716
≈ ≈ 034816 Three-phase PWM control register 0 INVC0 129
034916 Three-phase PWM control register 1 INVC1 130
01B016 034A16 Three-phase output buffer register 0 IDB0 131
01B116 034B16 Three-phase output buffer register 1 IDB1 131
01B216 034C16 Dead time timer DTT 131
01B316 034D16 Timer B2 interrupt occurrence frequency set counter ICTB2 132
01B416 Flash identification register (Note 2) FID R 267 034E16
01B516 Flash memory control register 1 (Note 2) FMR1 267 034F16
01B616 035016
Timer B3 register TB3 122
01B716 Flash memory control register 0 (Note 2) FMR0 267 035116
01B816 035216
Timer B4 register TB4 122
01B916 Address match interrupt register 2 RMAD2 92 035316
01BA16 035416
Timer B5 register TB5 122
01BB16 Address match interrupt enabl e regi ster 2 AIER2 92 035516
01BC16 035616
01BD16 Address match interrupt register 3 RMAD3 92 035716
01BE16 035816
01BF16 035916
035A16
≈ ≈ 035B16 Timer B3 mode register TB3MR 121
035C16 Timer B4 mode register TB4MR 121
025016 035D16 Timer B5 mode register TB5MR 121
025116 035E16 Interrupt cause select register 2 IFSR2A 89
025216 035F16 Interrupt cause select register IFSR 89
025316 036016 SI/O3 transmit/receive register S3TRR 183
025416 036116
025516 036216 SI/O3 control register S3C 183
025616 036316 SI/O3 bit rate generator S3BRG 183
025716 036416 SI/O4 transmit/receive register S4TRR 183
025816 036516
025916 036616 SI/O4 control register S4C 183
025A16 036716 SI/O4 bit rate generator S4BRG 183
025B16 036816
025C16 036916
025D16 036A16
025E16 Peripheral clock select register PCLKR 56 036B16
025F16 036C16 UART0 special mode register 4 U0SMR4 145
036D16 UART0 special ode register 3 U0SMR3 144
≈ ≈ 036E16 UART0 special mode register 2 U0SMR2 144
036F16 UART0 special mode register U0SMR 143
033016 037016 UART1 special mode register 4 U1SMR4 145
033116 037116 UART1 special mode register 3 U1SMR3 144
033216 037216 UART1 special mode register 2 U1SMR2 144
033316 037316 UART1 special mode register U1SMR 143
033416 037416 UART2 special mode register 4 U2SMR4 145
033516 037516 UART2 special mode register 3 U2SMR3 144
033616 037616 UART2 special mode register 2 U2SMR2 144
033716 037716 UART2 special mode register U2SMR 143
033816 037816 UART2 transmit/receive mode register U2MR 141
033916 037916 UART2 bit rate generator U2BRG 140
033A16 037A16
UART2 transmit buffer register U2TB 140
033B16 037B16
033C16 037C16 UART2 transmit/receive control register 0 U2C0 141
033D16 037D16 UART2 transmit/receive control register 1 U2C1 142
033E16 037E16
UART2 receive buffer register U2RB 140
033F16 037F16

Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.

B-2
Quick Reference to Pages Classified by Address

Address Register Symbol Page Address Register Symbol Page

038016 Count start flag TABSR 108, 122, 03C016

133 A-D register 0 AD0 190
03C116
038116 Clock prescaler reset flag CPSRF 109, 122 03C216
A-D register 1 AD1 190
038216 One-shot start flag ONSF 109 03C316
038316 Trigger select register TRGSR 109, 133 03C416
A-D register 2 AD2 190
038416 Up-down flag UDF 108 03C516
038516 03C616
A-D register 3 AD3 190
038616 03C716
Timer A0 register TA0 108
038716 03C816
A-D register 4 AD4 190
038816 03C916
Timer A1 register TA1 108, 132
038916 03CA16
A-D register 5 AD5 190
038A16 03CB16
Timer A2 register TA2 108, 132
038B16 03CC16
A-D register 6 AD6 190
038C16 03CD16
Timer A3 register TA3 108
038D16 03CE16
A-D register 7 AD7 190
038E16 03CF16
Timer A4 register TA4 108, 132
038F16 03D016
039016 03D116
Timer B0 register TB0 122
039116 03D216
039216 03D316
Timer B1 register TB1 122
039316 03D416 A-D control register 2 ADCON2 190
039416 03D516
Timer B2 register TB2 122, 133
039516 03D616 A-D control register 0 ADCON0 189
039616 Timer A0 mode register TA0MR 107 03D716 A-D control register 1 ADCON1 189
039716 Timer A1 mode register TA1MR 107, 134 03D816 D-A register 0 DA0 204
039816 Timer A2 mode register TA2MR 107, 134 03D916
039916 Timer A3 mode register TA3MR 107 03DA16 D-A register 1 DA1 204
039A16 Timer A4 mode register TA4MR 107, 134 03DB16
039B16 Timer B0 mode register TB0MR 121 03DC16 D-A control register DACON 204
039C16 Timer B1 mode register TB1MR 121 03DD16
039D16 Timer B2 mode register TB2MR 121, 134 03DE16 Port P14 control register PC14 215
039E16 Timer B2 special mode register TB2SC 132 03DF16 Pull-up control register 3 PUR3 215
039F16 03E016 Port P0 register P0 214
03A016 UART0 transmit/receive mode register U0MR 141 03E116 Port P1 register P1 214
03A116 UART0 bit rate generator U0BRG 140 03E216 Port P0 direction register PD0 213
03A216 03E316 Port P1 direction register PD1 213
UART0 transmit buffer register U0TB 140
03A316 03E416 Port P2 register P2 214
03A416 UART0 transmit/receive control register 0 U0C0 141 03E516 Port P3 register P3 214
03A516 UART0 transmit/receive control register 1 U0C1 142 03E616 Port P2 direction register PD2 213
03A616 03E716 Port P3 direction register PD3 213
UART0 receive buffer register U0RB 140
03A716 03E816 Port P4 register P4 214
03A816 UART1 transmit/receive mode register U1MR 141 03E916 Port P5 register P5 214
03A916 UART1 bit rate generator U1BRG 140 03EA16 Port P4 direction register PD4 213
03AA16
140 03EB16 Port P5 direction register PD5 213
UART1 transmit buffer register U1TB 214
03AB16 03EC16 Port P6 register P6
03AC16 UART1 transmit/receive control register 0 U1C0 141 03ED16 Port P7 register P7 214
03AD16 UART1 transmit/receive control register 1 U1C1 142 03EE16 Port P6 direction register PD6 213
03AE16 03EF16 Port P7 direction register PD7 213
UART1 receive buffer register U1RB 140
03AF16 03F016 Port P8 register P8 214
03B016 UART transmit/receive control register 2 UCON 143 03F116 Port P9 register P9 214
03B116 03F216 Port P8 direction register PD8 213
03B216 03F316 Port P9 direction register PD9 213
03B316 03F416 Port P10 register P10 214
03B416 03F516 Port P11 register P11 214
03B516 03F616 Port P10 direction register PD10 213
03B616 03F716 Port P11 direction register PD11 213
03B716 03F816 Port P12 register P12 214
03B816 DMA0 request cause select register DM0SL 97 03F916 Port P13 register P13 214
03B916 03FA16 Port P12 direction register PD12 213
03BA16 DMA1 request cause select register DM1SL 98 03FB16 Port P13 direction register PD13 213
03BB16 03FC16 Pull-up control register 0 PUR0 216
03BC16 03FD16 Pull-up control register 1 PUR1 216
CRC data register CRCD 205
03BD16 03FE16 Pull-up control register 2 PUR2 216
03BE16 CRC input register CRCIN 205 03FF16 Port control register PCR 217
03BF16

Note : The blank areas are reserved and cannot be accessed by users.

B-3
 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Overview
The M16C/62 group (M16C/62P) of single-chip microcomputers are built using the high-performance sili-
con gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring
a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instruc-
tions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with
fast instruction processing capability, makes it suitable for control of various OA, communication, and in-
dustrial equipment which requires high-speed arithmetic/logic operations.

Applications
Audio, cameras, office/communications/portable/industrial equipment, etc

Specifications written in this manual are believed to be accurate, but are

not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.

1
 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Performance Outline
Table 1.1.1 lists performance outline of M16C/62P group.
Table 1.1.1. Performance outline of M16C/62P group
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 41.7 ns (f(BCLK)= 24MHZ, VCC1= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V)
Memory ROM (See the product list)
capacity RAM (See the product list)
I/O port 100-pin version 8 bits x 10, 7 bits x 1 P0 to P5: VCC2 ports
P0 to P10 (except P85) P6 to P10: VCC1 ports
128-pin version 8 bits x 13, 7 bits x 1, P0 to P5, P12, P13: VCC2 ports
P0 to P14 (except P85) 2 bits x 1 _______ P6 to P10, P11, P14: VCC1 ports
Input port P85 1 bit x 1 (NMI pin level judgment): VCC1 ports
Multifunction timer
Output 16 bits x 5 channels (TA0, TA1, TA2, TA3, TA4)
Input 16 bits x 6 channels (TB0, TB1, TB2, TB3, TB4, TB5)
Serial I/O 3 channels (UART0, UART1, UART2)
UART, clock synchronous, I2C bus1 (option4), or IEBus2 (option4)
2 channels (SI/O3, SI/O4)
Clock synchronous
A-D converter 10 bits x (8 x 3 + 2) channels
D-A converter 8 bits x 2
DMAC 2 channels (trigger: 25 sources)
CRC calculation circuit CRC-CCITT
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 29 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit 4 circuits
• Main clock  (These circuits contain a built-in feedback

• Sub-clock  resistor and external ceramic/quartz oscillator)
• Ring oscillator(main-clock oscillation stop detect function)
• PLL frequency synthesizer
Voltage detection circuit Present (option4)
Power supply voltage VCC1=3.0V to 5.5V, VCC2=3.0V to VCC1(f(BCLK)=24MHZ)
VCC1=VCC2=2.7V to 5.5V (f(BCLK)=10MHZ)
Flash memory Program/erase voltage 3.3V ± 0.3V or 5.0V ± 0.5V
Number of program/erase 100 times, 10000 times3 (option4)
Power consumption 14mA (VCC1=VCC2=5V, f(BCLK)=24MHZ)
8mA (VCC1=VCC2=3V, f(BCLK)=10MHZ)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHZ, when wait mode)
I/O I/O withstand voltage 5.0V
characteristics Output current 5mA
Memory expansion Available (to 4M bytes)
Operating ambient temperature -20 to 85°C
-40 to 85°C (option4)
Device configuration CMOS high performance silicon gate
Package 100-pin and 128-pin plastic mold QFP
Notes:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. Block 1 and block A are a 10,000 times of programming and erasure. All other blocks are guaranteed of 1,000 times
of programming and erasure. (Under development; mass production scheduled to start in the 3rd quarter of 2003)
4. If you desire this option, please so specify.

2
 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Block Diagram
Figure 1.1.1 is a block diagram of the M16C/62P group.

8 8 8 8 8 8 8

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6

<VCC2 ports> <VCC1 ports>

Port P7

8
Internal peripheral functions A-D converter System clock generator
(10 bits X 8 channels XIN-XOUT
Timer (16-bit)
Expandable up to 26 channels)

Port P8
Output (timer A): 5 XCIN-XCOUT
Input (timer B): 6 PLL frequency synthesizer
UART or Ring oscillator

7
clock synchronous serial I/O

<VCC1 ports>
Three-phase motor (8 bits X 3 channels) Clock synchronous serial I/O
control circuit (8 bits X 2 channels)

Port P85
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)

Watchdog timer M16C/60 series16-bit CPU core Memory

(15 bits) R0H R0L SB ROM
R1H R1L USP (Note 1) Port P9
R2
DMAC

8
R3 ISP RAM
(2 channels) (Note 2)
INTB
A0
PC
D-A converter A1
Port P10

(8 bits X 2 channels) FB FLG

Multiplier
8

<VCC1 ports> <VCC2 ports>

Port P11 Port P14 Port P12 Port P13
(Note 3) (Note 3) (Note 3) (Note 3)

8 2 8 8 Note 1: ROM size depends on microcomputer type.

Note 2: RAM size depends on microcomputer type.
Note 3: Ports P11 to P14 exist only in 128-pin version.

Figure 1.1.1. Block Diagram

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 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Product List
Tables 1.1.2 and 1.1.3 list the M16C/62P group products and Figure 1.1.2 shows the type numbers,
memory sizes and packages.

Table 1.1.2. Product List (1) As of April 2003

Type No. ROM capacity RAM capacity Package type Remarks
M30622M6P-XXXFP 100P6S-A
48K bytes 4K bytes
M30622M6P-XXXGP 100P6Q-A
M30622M8P-XXXFP 100P6S-A
64K bytes 4K bytes
M30622M8P-XXXGP 100P6Q-A
M30622MAP-XXXFP 100P6S-A
96K bytes 5K bytes
M30622MAP-XXXGP 100P6Q-A
M30620MCP-XXXFP 100P6S-A
128K bytes 10K bytes
M30620MCP-XXXGP 100P6Q-A
M30622MEP-XXXFP 100P6S-A
M30622MEP-XXXGP 192K bytes 12K bytes 100P6Q-A
M30623MEP-XXXGP 128P6Q-A
M30622MGP-XXXFP 100P6S-A
M30622MGP-XXXGP 12K bytes 100P6Q-A
M30623MGP-XXXGP 128P6Q-A
256K bytes
M30624MGP-XXXFP 100P6S-A
M30624MGP-XXXGP 20K bytes 100P6Q-A
MASK ROM version
M30625MGP-XXXGP 128P6Q-A
M30622MWP-XXXFP 100P6S-A
M30622MWP-XXXGP 16K bytes 100P6Q-A
M30623MWP-XXXGP 128P6Q-A
M30624MWP-XXXFP 100P6S-A
M30624MWP-XXXGP 24K bytes 100P6Q-A
320K bytes
M30625MWP-XXXGP 128P6Q-A
M30626MWP-XXXFP 100P6S-A
M30626MWP-XXXGP 31K bytes 100P6Q-A
M30627MWP-XXXGP 128P6Q-A
M30622MHP-XXXFP 100P6S-A
M30622MHP-XXXGP 16K bytes 100P6Q-A
M30623MHP-XXXGP 128P6Q-A
M30624MHP-XXXFP 100P6S-A
M30624MHP-XXXGP 384K bytes 24K bytes 100P6Q-A
M30625MHP-XXXGP 128P6Q-A
M30626MHP-XXXFP 100P6S-A
M30626MHP-XXXGP 31K bytes 100P6Q-A
M30627MHP-XXXGP 128P6Q-A
: Under development
: Under planning

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 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.1.3. Product List (2) As of April 2003

Type No. ROM capacity RAM capacity Package type Remarks
M30622F8PFP 100P6S-A
64K bytes 4K bytes
M30622F8PGP 100P6Q-A
M30620FCPFP 100P6S-A
128K bytes 10K bytes
M30620FCPGP 100P6Q-A
M30624FGPFP 100P6S-A
M30624FGPGP 256K bytes 20K bytes 100P6Q-A Flash memory version
M30625FGPGP 128P6Q-A
M30626FHPFP 100P6S-A
M30626FHPGP 384K bytes 31K bytes 100P6Q-A
M30627FHPGP 128P6Q-A
M30626FJPFP 100P6S-A
M30626FJPGP 512K bytes 31K bytes 100P6Q-A
M30627FJPGP 128P6Q-A

M30620SPFP 100P6S-A
10K bytes
M30620SPGP 100P6Q-A
External ROM version
M30622SPFP 100P6S-A
4K bytes
M30622SPGP 100P6Q-A

: Under development
: Under planning

Type No. M 3 0 6 2 6 M H P– X X X F P
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 128P6Q-A

ROM No.
Omitted for flash memory version and
external ROM version

ROM capacity:
6: 48K bytes G: 256K bytes
8: 64K bytes W: 320K bytes
A: 96K bytes H: 384K bytes
C: 128K bytes J: 512K bytes
E: 192K bytes

Memory type:
M: Mask ROM version
F: Flash memory version
S: External ROM version

Shows RAM capacity, pin count, etc

(The value itself has no specific meaning)

M16C/62 Group

M16C Family
Figure 1.1.2. Type No., Memory Size, and Package

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 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Configuration
Figures 1.1.3 to 1.1.5 show the pin configurations (top view).

PIN CONFIGURATION (top view)

P27/AN27/A7(/D7/D6)
P25/AN25/A5(/D5/D4)
P26/AN26/A6(/D6/D5)
P21/AN21/A1(/D1/D0)

P24/AN24/A4(/D4/D3)
P22/AN22/A2(/D2/D1)
P23/AN23/A3(/D3/D2)
P20/AN20/A0(/D0/-)
P17/D15/INT5
P16/D14/INT4
P15/D13/INT3

P30/A8(/-/D7)
P12/D10

P36/A14
P13/D11

P37/A15
P14/D12

P40/A16
P41/A17
P32/A10

P42/A18
P33/A11

P43/A19
P34/A12
P35/A13
P10/D8
P11/D9

P31/A9
VCC2
VSS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P07/AN07/D7 81 50 P44/CS0
P06/AN06/D6 82 49 P45/CS1
P05/AN05/D5 83 48 P46/CS2
P04/AN04/D4 84 47 P47/CS3
P03/AN03/D3 85 46 P50/WRL/WR
P02/AN02/D2 86 45 P51/WRH/BHE
P01/AN01/D1 87 44 P52/RD
P00/AN00/D0 88 43 P53/BCLK
P107/AN7/KI3 89 42 P54/HLDA
P106/AN6/KI2 90 M16C/62P Group 41 P55/HOLD
P105/AN5/KI1 91 40 P56/ALE
P104/AN4/KI0 92 39 P57/RDY/CLKOUT
P103/AN3 93 38 P60/CTS0/RTS0
P102/AN2 94 37 P61/CLK0
P101/AN1 95 36 P62/RxD0/SCL0
AVSS 96 35 P63/TXD0/SDA0
P100/AN0 97 34 P64/CTS1/RTS1/CTS0/CLKS1
VREF 98 33 P65/CLK1
AVCC 99 32 P66/RxD1/SCL1
P97/ADTRG/SIN4 100 31 P67/TXD1/SDA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P83/INT1

P73/CTS2/RTS2/TA1IN/V
VSS
BYTE

P81/TA4IN/U
XOUT

P74/TA2OUT/W
P90/TB0IN/CLK3

P82/INT0

P72/CLK2/TA1OUT/V
XIN
P91/TB1IN/SIN3

CNVss

P80/TA4OUT/U
P87/XCIN

P71/RxD2/SCL2/TA0IN/TB5IN(Note)
P76/TA3OUT
P92/TB2IN/SOUT3
P95/ANEX0/CLK4

P86/XCOUT

VCC1

P84/INT2

P70/TXD2/SDA2/TA0OUT(Note)
P77/TA3IN
P93/DA0/TB3IN
P96/ANEX1/SOUT4

P75/TA2IN/W
P94/DA1/TB4IN

RESET

P85/NMI

Package: 100P6S-A
Note: P70 and P71 are N channel open-drain output pins.

Figure 1.1.3. Pin Configuration (Top View)

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 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (top view)

P21/AN21/A1(/D1/D0)
P22/AN22/A2(/D2/D1)
P23/AN23/A3(/D3/D2)
P24/AN24/A4(/D4/D3)
P25/AN25/A5(/D5/D4)
P26/AN26/A6(/D6/D5)
P27/AN27/A7(/D7/D6)
P20/AN20/A0(/D0/-)
P15/D13/INT3
P16/D14/INT4
P17/D15/INT5

P30/A8(/-/D7)
P13/D11
P14/D12

P37/A15
P40/A16
P41/A17
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P31/A9
VCC2
VSS

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P12/D10 76 50 P42/A18
P11/D9 77 49 P43/A19
P10/D8 78 48 P44/CS0
P07/AN07/D7 79 47 P45/CS1
P06/AN06/D6 80 46 P46/CS2
P05/AN05/D5 81 45 P47/CS3
P04/AN04/D4 82 44 P50/WRL/WR
P03/AN03/D3 83 43 P51/WRH/BHE
P02/AN02/D2 84 42 P52/RD
P01/AN01/D1 85 41 P53/BCLK
P00/AN00/D0 86 40 P54/HLDA
P107/AN7/KI3 87 M16C/62P Group 39 P55/HOLD
P106/AN6/KI2 88 38 P56/ALE
P105/AN5/KI1 89 37 P57/RDY/CLKOUT
P104/AN4/KI0 90 36 P60/CTS0/RTS0
P103/AN3 91 35 P61/CLK0
P102/AN2 92 34 P62/RxD0/SCL0
P101/AN1 93 33 P63/TXD0/SDA0
AVSS 94 32 P64/CTS1/RTS1/CTS0/CLKS1
P100/AN0 95 31 P65/CLK1
VREF 96 30 P66/RxD1/SCL1
AVcc 97 29 P67/TXD1/SDA1
P97/ADTRG/SIN4 98 28 P70/TXD2/SDA2/TA0OUT(Note)
99 27 P71/RxD2/SCL2/TA0IN/TB5IN(Note)
P96/ANEX1/SOUT4
P95/ANEX0/CLK4 100 26 P72/CLK2/TA1OUT/V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
XOUT
P94/DA1/TB4IN

P80/TA4OUT/U
P86/XCOUT

XIN
CNVss

P81/TA4IN/U
VCC1
P91/TB1IN/SIN3
P90/TB0IN/CLK3

P82/INT0
BYTE

P73/CTS2/RTS2/TA1IN/V
P87/XCIN
P92/TB2IN/SOUT3

P74/TA2OUT/W
P83/INT1
RESET
P93/DA0/TB3IN

P75/TA2IN/W
P84/INT2
P85/NMI
VSS

P76/TA3OUT
P77/TA3IN

Package: 100P6Q-A
Note: P70 and P71 are N channel open-drain output pins.

Figure 1.1.4. Pin Configuration (Top View)

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 Renesas microcomputers
M16C / 62P Group
Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (top view)

P27/AN27/A7(/D7/D6)
P25/AN25/A5(/D5/D4)
P26/AN26/A6(/D6/D5)
P21/AN21/A1(/D1/D0)

P24/AN24/A4(/D4/D3)
P22/AN22/A2(/D2/D1)
P23/AN23/A3(/D3/D2)
P20/AN20/A0(/D0/-)
P17/D15/INT5
P16/D14/INT4
P15/D13/INT3

P30/A8(/-/D7)

P47/CS3
P44/CS0
P45/CS1
P46/CS2
P13/D11
P14/D12

P32/A10
P33/A11

P40/A16
P34/A12

P41/A17
P35/A13

P42/A18
P36/A14

P43/A19
P37/A15
P12/D10

P31/A9
P11/D9

P123
P124
P121
P122
VCC2
P120
VSS

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P10/D8 103 64 P125

P07/AN07/D7 104 63 P126
P06/AN06/D6 105 62 P127
P05/AN05/D5 106 61 P50/WRL/WR
P04/AN04/D4 107 60 P51/WRH/BHE
P03/AN03/D3 108 59 P52/RD
P02/AN02/D2 109 58 P53/BCLK
P01/AN01/D1 110 57 P130
P00/AN00/D0 111 56 P131
P117 112 55 P132
P116 113 54 P133
P115 114 53 P54/HLDA
P114 115 52 P55/HOLD
P113 116 M16C/62P Group 51 P56/ALE
P112 117 50 P57/RDY/CLKOUT
P111 118 49 P134
P110 119 48 P135
P107/AN7/KI3 120 47 P136
P106/AN6/KI2 121 46 P137
P105/AN5/KI1 122 45 P60/CTS0/RTS0
P104/AN4/KI0 123 44 P61/CLK0
P103/AN3 124 43 P62/RxD0/SCL0
P102/AN2 125 42 P63/TXD0/SDA0
P101/AN1 126 41 P64/CTS1/RTS1/CTS0/CLKS1
AVSS 127 40 P65/CLK1
P100/AN0 128 39 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
P97/ADTRG/SIN4
AVCC

P71/RxD2/SCL2/TA0IN/TB5IN(Note)
VREF

P74/TA2OUT/W
P91/TB1IN/SIN3

P86/XCOUT

VCC1

P84/INT2
P92/TB2IN/SOUT3
P95/ANEX0/CLK4

P70/TXD2/SDA2/TA0OUT(Note)
P73/CTS2/RTS2/TA1IN/V
P83/INT1

VCC1
P66/RxD1/SCL1
P93/DA0/TB3IN

P87/XCIN

VSS
P96/ANEX1/SOUT4

BYTE

P81/TA4IN/U
P94/DA1/TB4IN

XOUT
P140

P76/TA3OUT
P82/INT0

P75/TA2IN/W
XIN
CNVss

P80/TA4OUT/U
RESET

P67/TXD1/SDA1
P77/TA3IN
P90/TB0IN/CLK3

P72/CLK2/TA1OUT/V
P141

P85/NMI

Package: 128P6Q-A
Note: P70 and P71 are N channel open-drain output pins.

Figure 1.1.5. Pin Configuration (Top View)

8
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview

Pin Description
Table 1.1.4 Pin Description (100-pin and 128-pin Packages)
Pin name Signal name I/O type Power supply Function
VCC1, VCC2, Power supply Apply 2.7V to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
VSS input pin. The Vcc apply condition is that VCC2 ≤ VCC1 (Note)
CNVSS CNVSS Input VCC1 This pin switches between processor modes. Connect this pin to
VSS pin when after a reset you want to start operation in single-
chip mode (memory expansion mode) or the VCC1 pin when
starting operation in microprocessor mode.
RESET Reset input Input VCC1 “L” on this input resets the microcomputer.
XIN Clock input Input VCC1 These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the XIN
XOUT Clock output Output and the XOUT pins. To use an externally derived clock, input it to
the XIN pin and leave the XOUT pin open.

BYTE External data Input This pin selects the width of an external data bus. A 16-bit width is
bus width selected when this input is “L”; an 8-bit width is selected when this
select input input is “H”. This input must be fixed to either “H” or “L”. Connect
this pin to the VSS pin when operating in single-chip mode.
AVCC Analog power This pin is a power supply input for the A-D converter. Connect
supply input this pin to VCC1.
AVSS Analog power This pin is a power supply input for the A-D converter. Connect
supply input this pin to VSS.
VREF Reference Input This pin is a reference voltage input for the A-D converter.
voltage input
P00 to P07 I/O port P0 Input/output VCC2 This is an 8-bit CMOS I/O port. This port has an input/output select
direction register, allowing each pin in that port to be directed for
input or output individually.
If any port is set for input, selection can be made for it in a program
whether or not to have a pull-up resistor in 4 bit units. This selection
is unavailable in memory extension and microprocessor modes.
This port can function as input pins for the A-D converter when so
selected in a program.
D0 to D7 Input/output When set as a separate bus, these pins input and output data (D0
–D7).
P10 to P17 I/O port P1 Input/output VCC2 This is an 8-bit I/O port equivalent to P0. P15 to P17 also function
as INT interrupt input pins as selected by a program.
D8 to D15 Input/output When set as a separate bus, these pins input and output data (D8
–D15).
P20 to P27 I/O port P2 Input/output VCC2 This is an 8-bit I/O port equivalent to P0. This port can function as
input pins for the A-D converter when so selected in a program.
A0 to A7 Output These pins output 8 low-order address bits (A0 to A7).
A0/D0 to Input/output If the external bus is set as an 8-bit wide multiplexed bus, these
A7/D7 pins input and output data (D0 to D7) and output 8 low-order
address bits (A0 to A7) separated in time by multiplexing.
A0 Output If the external bus is set as a 16-bit wide multiplexed bus, these
A1/D0 to Input/output pins input and output data (D0 to D6) and output address (A1 to A7)
A7/D6 separated in time by multiplexing. They also output address (A0).
P30 to P37 I/O port P3 Input/output VCC2 This is an 8-bit I/O port equivalent to P0.
A8 to A15 Output These pins output 8 middle-order address bits (A8 to A15).
A8/D7, Input/output If the external bus is set as a 16-bit wide multiplexed bus, these
A9 to A15 Output pins input and output data (D7) and output address (A8)
separated in time by multiplexing. They also output address (A9
to A15).
P40 to P47 I/O port P4 Input/output VCC2 This is an 8-bit I/O port equivalent to P0.
A16 to A19, Output These pins output A16 to A19 and CS0 to CS3 signals. A16 to A19
CS0 to CS3 Output are 4 high- order address bits. CS0 to CS3 are chip select signals
used to specify an access space.

Note: In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview

Table 1.1.5 Pin Description (100-pin and 128-pin Packages) (Continued)

Pin name Signal name I/O type Power supply Function

P50 to P57 I/O port P5 Input/output VCC2 This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57
in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program.

WRL / WR, Output Output WRL/WR, WRH/BHE, RD, BCLK, HLDA, and ALE signals.
WRH / BHE, Output WRL/WR and WRH/BHE are switchable in a program. Note that
RD, Output WRL and WRH are always used as a pair, so as WR and BHE.
BCLK, Output WRL, WRH, and RD selected
HLDA, Output If the external data bus is 16 bits wide, data are written to even
HOLD, Input addresses when the WRL signal is low, and written to odd
ALE, Output addresses when the WRH signal is low. Data are read out when the
RDY Input RD signal is low.
WR, BHE, and RD selected
Data are written when the WR signal is low, or read out when the
RD signal is low. Odd addresses are accessed when the BHE
signal is low. Use this mode when the external data bus is 8 bits
wide.
The microcomputer goes to a hold state when input to the HOLD
pin is held low. While in the hold state, HLDA outputs a low
level. ALE is used to latch the address. While the input level of the
RDY pin is low, the bus of the microcomputer goes to a wait state.
P60 to P67 I/O port P6 Input/output VCC1 This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as UART0 and UART1 I/O pins as selected by program.
P70 to P77 I/O port P7 Input/output VCC1 This is an 8-bit I/O port equivalent to P0 (P70 and P71 are N
channel open-drain output). This port can function as input/output
pins for timers A0 to A3 when so selected in a program.
Furthermore, P70 to P75, P71, and P72 to P75 can also function as
input/output pins for UART2, an input pin for timer B5, and output
pins for the three-phase motor control timer, respectively.
P80 to P84, I/O port P8 Input/output VCC1 P80 to P84, P86, and P87 are I/O ports with the same functions as
P86, P0. When so selected in a program, P80 to P81 and P82 to P84 can
Input/output
function as input/output pins for timer A4 or output pins for the
P87, Input/output three-phase motor control timer and INT interrupt input pins,
P85 I/O port P85 Input respectively. P86 and P87, when so selected in a program, both
can function as input/output pins for the subclock oscillator circuit.
In that case, connect a crystal resonator between P86 (XCOUT pin)
and P87 (XCIN pin).
P85 is an input-only port shared with NMI. An NMI interrupt request
is generated when input on this pin changes state from high to low.
The NMI function cannot be disabled in a program.
A pull-up cannot be set for this pin.
P90 to P97 I/O port P9 Input/output VCC1 This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as SI/O3 and SI/O4 I/O pins, Timer B0 to B4 input pins, D-
A converter output pins, A-D converter input pins, or A-D trigger
input pins as selected by program.
P100 to I/O port P10 Input/output VCC1 This is an 8-bit I/O port equivalent to P0. Pins in this port also
P107 function as A-D converter input pins as selected by program.
Furthermore, P104 to P107 also function as input pins for the key
input interrupt function.

Table 1.1.6 Pin Description (128-pin Package)

Pin name Signal name I/O type Power supply Function
circuit block
P110 to P117 I/O port P11 Input/output VCC1 This is an 8-bit I/O port equivalent to P0.
P120 to P127 I/O port P12 Input/output VCC2 This is an 8-bit I/O port equivalent to P0.
P130 to P137 I/O port P13 Input/output VCC2 This is an 8-bit I/O port equivalent to P0.
P140, P141 I/O port P14 Input/output VCC1 This is an 2-bit I/O port equivalent to P0.

10
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory

Memory
Figure 1.2.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from
address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,
a 64-Kbyte internal ROM is allocated to the addresses from F000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 10-Kbytes internal RAM is allocated to the addresses from 0040016 to 02BFF16. In addition to storing
data, the internal RAM also stores the stack used when calling subroutines and when interrupts are gener-
ated.
The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.

0000016
SFR
FFE0016
0040016

Internal RAM

XXXXX16 Special page

AAAAAA
Reserved area vector table
1000016 (Note 1)

AAAAAA
Internal RAM Internal ROM
External area
Size Address XXXXX16 Size Address YYYYY16

AAAAAA
2700016
4K bytes 013FF16 48K bytes F400016
Reserved area FFFDC16 Undefined instruction

AAAAAA
5K bytes 017FF16 64K bytes F000016
2800016
10K bytes 02BFF16 96K bytes E800016 Overflow
External area
12K bytes 033FF16 128K bytes E000016
BRK instruction
8000016 Address match
16K bytes 043FF16 192K bytes D000016 Reserved area Single step
20K bytes 053FF16 (Note 2)
256K bytes C000016 YYYYY16 Watchdog timer
24K bytes 063FF16 320K bytes B000016
DBC
31K bytes 07FFF16 384K bytes A000016 Internal ROM
NMI
512K bytes 8000016
FFFFF16 Reset
FFFFF16

Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Note 3: Shown here is a memory map for the case where the PM10 bit in the PM1
register is “1” and the PM13 bit in the PM1 register is “1”.

Figure 1.2.1. Memory Map

11
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)

Central Processing Unit (CPU)

Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31 b15 b8 b7 b0
R2 R0H(R0's high bits) R0L(R0's low bits)
R3 R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1 Address registers (Note)
FB Frame base registers (Note)

b19 b15 b0

INTBH INTBL Interrupt table register

The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19 b0

PC Program counter

b15 b0

USP User stack pointer

ISP Interrupt stack pointer
SB Static base register

b15 b0
FLG Flag register

AA
AAAAAAA
AA AA
A
b15

AAAAAAA AAAA
A
AA
AAAAAAA AA
AA
AAAAA
AA
IPL
b8 b7

U I O B S Z D C
b0

Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area

Note: These registers comprise a register bank. There are two register banks.

Figure 1.3.1. Central Processing Unit Register

(1) Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

12
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)

(3) Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
• Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.

13
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

SFR
Address Register Symbol After reset
000016
000116
000216
000316
000416 Processor mode register 0 (Note 2) PM0 000000002(CNVSS pin is “L”)
000000112(CNVSS pin is “H”)
000516 Processor mode register 1 PM1 000010002
000616 System clock control register 0 CM0 010010002
000716 System clock control register 1 CM1 001000002
000816 Chip select control register CSR 000000012
000916 Address match interrupt enable register AIER XXXXXX002
000A16 Protect register PRCR XX0000002
000B16 Data bank register DBR 0016
000C16 Oscillation stop detection register (Note 3) CM2 0000X0002
000D16
000E16 Watchdog timer start register WDTS XX16
000F16 Watchdog timer control register WDC 00XXXXXX2(Note 4)
001016 Address match interrupt register 0 RMAD0 0016
001116 0016
001216 X016
001316
001416 Address match interrupt register 1 RMAD1 0016
001516 0016
001616 X016
001716
001816
001916 Voltage detection register 1 (Note 5) VCR1 000010002
001A16 Voltage detection register 2 (Note 5) VCR2 0016
001B16 Chip select expansion control register CSE 0016
001C16 PLL control register 0 PLC0 0001X0102
001D16
001E16 Processor mode register 2 PM2 XXX000002
001F16 Voltage down detection interrupt register D4INT 0016
002016 DMA0 source pointer SAR0 XX16
002116 XX16
002216 XX16
002316
002416 DMA0 destination pointer DAR0 XX16
002516 XX16
002616 XX16
002716
002816 DMA0 transfer counter TCR0 XX16
002916 XX16
002A16
002B16
002C16 DMA0 control register DM0CON 00000X002
002D16
002E16
002F16
003016
DMA1 source pointer SAR1 XX16
003116
XX16
003216
XX16
003316
003416 DMA1 destination pointer DAR1 XX16
003516 XX16
003616 XX16
003716
003816 DMA1 transfer counter TCR1 XX16
003916 XX16
003A16
003B16
003C16 DMA1 control register DM1CON 00000X002
003D16
003E16
003F16

Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 4: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage
at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable
Note 5: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Nothing is mapped to this bit

14
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

Address Register Symbol After reset

004016
004116
004216
004316
004416 INT3 interrupt control register INT3IC XX00X0002
004516 Timer B5 interrupt control register TB5IC XXXXX0002
004616 Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register TB4IC, U1BCNIC XXXXX0002
004716 Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register TB3IC, U0BCNIC XXXXX0002
004816 SI/O4 interrupt control register (S4IC), INT5 interrupt control register S4IC, INT5IC XX00X0002
004916
SI/O3 interrupt control register, INT4 interrupt control register S3IC, INT4IC XX00X0002
004A16 UART2 Bus collision detection interrupt control register BCNIC XXXXX0002
004B16 DMA0 interrupt control register DM0IC XXXXX0002
004C16 DMA1 interrupt control register DM1IC XXXXX0002
004D16 Key input interrupt control register KUPIC XXXXX0002
004E16 A-D conversion interrupt control register ADIC XXXXX0002
004F16 UART2 transmit interrupt control register S2TIC XXXXX0002
005016 UART2 receive interrupt control register S2RIC XXXXX0002
005116 UART0 transmit interrupt control register S0TIC XXXXX0002
005216 UART0 receive interrupt control register S0RIC XXXXX0002
005316 UART1 transmit interrupt control register S1TIC XXXXX0002
005416 UART1 receive interrupt control register S1RIC XXXXX0002
005516 Timer A0 interrupt control register TA0IC XXXXX0002
005616 Timer A1 interrupt control register TA1IC XXXXX0002
005716 Timer A2 interrupt control register TA2IC XXXXX0002
005816 Timer A3 interrupt control register TA3IC XXXXX0002
005916 Timer A4 interrupt control register TA4IC XXXXX0002
005A16 Timer B0 interrupt control register TB0IC XXXXX0002
005B16 Timer B1 interrupt control register TB1IC XXXXX0002
005C16 Timer B2 interrupt control register TB2IC XXXXX0002
005D16 INT0 interrupt control register INT0IC XX00X0002
005E16 INT1 interrupt control register INT1IC XX00X0002
005F16 INT2 interrupt control register INT2IC XX00X0002
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16

Note :The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

15
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

Address Register Symbol After reset

008016
008116
008216
008316
008416
008516
008616

~ ~
01B016
01B116
01B216
01B316
01B416 Flash identification register (Note 2) FIDR XXXXXX002
01B516 Flash memory control register 1 (Note 2) FMR1 0X00XX0X2
01B616
01B716 Flash memory control register 0 (Note 2) FMR0 XX0000012
01B816 Address match interrupt register 2 RMAD2 0016
01B916 0016
01BA16 X016
01BB16 Address match interrupt enable register 2 AIER2 XXXXXX002
01BC16 Address match interrupt register 3 RMAD3 0016
01BD16 0016
01BE16 X016
01BF16

~ ~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16 Peripheral clock select register PCLKR 000000112
025F16

~ ~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.

X : Nothing is mapped to this bit

16
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

Address Register Symbol After reset

034016 Timer B3, 4, 5 count start flag TBSR 000XXXXX2
034116
034216 Timer A1-1 register TA11 XX16
034316 XX16
034416 Timer A2-1 register TA21 XX16
034516 XX16
034616 Timer A4-1 register TA41 XX16
034716 XX16
034816 Three-phase PWM control register 0 INVC0 0016
034916 Three-phase PWM control register 1 INVC1 0016
034A16 Three-phase output buffer register 0 IDB0 0016
034B16 Three-phase output buffer register 1 IDB1 0016
034C16 Dead time timer DTT XX16
034D16 Timer B2 interrupt occurrence frequency set counter ICTB2 XX16
034E16
034F16
035016 Timer B3 register TB3 XX16
035116 XX16
035216 Timer B4 register TB4 XX16
035316 XX16
035416 Timer B5 register TB5 XX16
035516 XX16
035616
035716
035816
035916
035A16
035B16 Timer B3 mode register TB3MR 00XX00002
035C16 Timer B4 mode register TB4MR 00XX00002
035D16 Timer B5 mode register TB5MR 00XX00002
035E16 Interrupt cause select register 2 IFSR2A 00XXXXXX2
035F16 Interrupt cause select register IFSR 0016
036016 SI/O3 transmit/receive register S3TRR XX16
036116
036216 SI/O3 control register S3C 010000002
036316 SI/O3 bit rate generator S3BRG XX16
036416 SI/O4 transmit/receive register S4TRR XX16
036516
036616 SI/O4 control register S4C 010000002
036716 SI/O4 bit rate generator S4BRG XX16
036816
036916
036A16
036B16
036C16 UART0 special mode register 4 U0SMR4 0016
036D16 UART0 special mode register 3 U0SMR3 000X0X0X2
036E16 UART0 special mode register 2 U0SMR2 X00000002
036F16 UART0 special mode register U0SMR X00000002
037016 UART1 special mode register 4 U1SMR4 0016
037116 UART1 special mode register 3 U1SMR3 000X0X0X2
037216 UART1 special mode register 2 U1SMR2 X00000002
037316 UART1 special mode register U1SMR X00000002
037416 UART2 special mode register 4 U2SMR4 0016
037516 UART2 special mode register 3 U2SMR3 000X0X0X2
037616 UART2 special mode register 2 U2SMR2 X00000002
037716 UART2 special mode register U2SMR X00000002
037816 UART2 transmit/receive mode register U2MR 0016
037916 UART2 bit rate generator U2BRG XX16
037A16 UART2 transmit buffer register U2TB XXXXXXXX2
037B16 XXXXXXXX2
037C16 UART2 transmit/receive control register 0 U2C0 000010002
037D16 UART2 transmit/receive control register 1 U2C1 000000102
037E16 UART2 receive buffer register U2RB XXXXXXXX2
037F16 XXXXXXXX2
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit

17
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

Address Register Symbol After reset

038016 Count start flag TABSR 0016
038116 Clock prescaler reset flag CPSRF 0XXXXXXX2
038216 One-shot start flag ONSF 0016
038316 Trigger select register TRGSR 0016
038416 Up-down flag UDF 0016
038516
038616 Timer A0 register TA0 XX16
038716 XX16
038816 Timer A1 register TA1 XX16
038916 XX16
038A16 Timer A2 register TA2 XX16
038B16 XX16
038C16 Timer A3 register TA3 XX16
038D16 XX16
038E16 Timer A4 register TA4 XX16
038F16 XX16
039016 Timer B0 register TB0 XX16
039116 XX16
039216 Timer B1 register TB1 XX16
039316 XX16
039416 Timer B2 register TB2 XX16
039516 XX16
039616 Timer A0 mode register TA0MR 0016
039716 Timer A1 mode register TA1MR 0016
039816 Timer A2 mode register TA2MR 0016
039916 Timer A3 mode register TA3MR 0016
039A16 Timer A4 mode register TA4MR 0016
039B16 Timer B0 mode register TB0MR 00XX00002
039C16 Timer B1 mode register TB1MR 00XX00002
039D16 Timer B2 mode register TB2MR 00XX00002
039E16 Timer B2 special mode register TB2SC XXXXXX002
039F16
03A016 UART0 transmit/receive mode register U0MR 0016
03A116 UART0 bit rate generator U0BRG XX16
03A216 UART0 transmit buffer register U0TB XXXXXXXX2
03A316 XXXXXXXX2
03A416 UART0 transmit/receive control register 0 U0C0 000010002
03A516 UART0 transmit/receive control register 1 U0C1 000000102
03A616 UART0 receive buffer register U0RB XXXXXXXX2
03A716 XXXXXXXX2
03A816 UART1 transmit/receive mode register U1MR 0016
03A916 UART1 bit rate generator U1BRG XX16
03AA16 UART1 transmit buffer register U1TB XXXXXXXX2
03AB16 XXXXXXXX2
03AC16 UART1 transmit/receive control register 0 U1C0 000010002
03AD16 UART1 transmit/receive control register 1 U1C1 000000102
03AE16 UART1 receive buffer register U1RB XXXXXXXX2
03AF16 XXXXXXXX2
03B016 UART transmit/receive control register 2 UCON X00000002
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816 DMA0 request cause select register DM0SL 0016
03B916
03BA16 DMA1 request cause select register DM1SL 0016
03BB16
03BC16 CRC data register CRCD XX16
03BD16 XX16
03BE16 CRC input register CRCIN XX16
03BF16
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit

18
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR

Address Register Symbol After reset

03C016 A-D register 0 AD0 XXXXXXXX2
03C116 XXXXXXXX2
03C216 A-D register 1 AD1 XXXXXXXX2
03C316 XXXXXXXX2
03C416 A-D register 2 AD2 XXXXXXXX2
03C516 XXXXXXXX2
03C616 A-D register 3 AD3 XXXXXXXX2
03C716 XXXXXXXX2
03C816 A-D register 4 AD4 XXXXXXXX2
03C916 XXXXXXXX2
03CA16 A-D register 5 AD5 XXXXXXXX2
03CB16 XXXXXXXX2
03CC16 A-D register 6 AD6 XXXXXXXX2
03CD16 XXXXXXXX2
03CE16 A-D register 7 AD7 XXXXXXXX2
03CF16 XXXXXXXX2
03D016
03D116
03D216
03D316
03D416 A-D control register 2 ADCON2 0016
03D516
03D616 A-D control register 0 ADCON0 00000XXX2
03D716 A-D control register 1 ADCON1 0016
03D816 D-A register 0 DA0 XX16
03D916
03DA16 D-A register 1 DA1 XX16
03DB16
03DC16 D-A control register DACON 0016
03DD16
03DE16 Port P14 control register PC14 XX00XXXX2
03DF16 Pull-up control register 3 PUR3 0016
03E016 Port P0 register P0 XX16
03E116 Port P1 register P1 XX16
03E216 Port P0 direction register PD0 0016
03E316 Port P1 direction register PD1 0016
03E416 Port P2 register P2 XX16
03E516 Port P3 register P3 XX16
03E616 Port P2 direction register PD2 0016
03E716 Port P3 direction register PD3 0016
03E816 Port P4 register P4 XX16
03E916 Port P5 register P5 XX16
03EA16 Port P4 direction register PD4 0016
03EB16 Port P5 direction register PD5 0016
03EC16 Port P6 register P6 XX16
03ED16 Port P7 register P7 XX16
03EE16 Port P6 direction register PD6 0016
03EF16 Port P7 direction register PD7 0016
03F016 Port P8 register P8 XX16
03F116 Port P9 register P9 XX16
03F216 Port P8 direction register PD8 00X000002
03F316 Port P9 direction register PD9 0016
03F416 Port P10 register P10 XX16
03F516 Port P11 register P11 XX16
03F616 Port P10 direction register PD10 0016
03F716 Port P11 direction register PD11 0016
03F816 Port P12 register P12 XX16
03F916 Port P13 register P13 XX16
03FA16 Port P12 direction register PD12 0016
03FB16 Port P13 direction register PD13 0016
03FC16 Pull-up control register 0 PUR0 0016
03FD16 Pull-up control register 1 PUR1 000000002
(Note 2)
000000102
03FE16 Pull-up control register 2 PUR2 0016
03FF16 Port control register PCR 0016
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: At hardware reset 1 or hardware reset 2, the register is as follows:
• “000000002” where “L” is inputted to the CNVSS pin
• “000000102” where “H” is inputted to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “000000002” where the PM01 to PM00 bits in the PM0 register are “002” (single-chip mode)
• “000000102” where the PM01 to PM00 bits in the PM0 register are “012” (memory expansion mode) or
“112” (microprocessor mode)

X : Nothing is mapped to this bit

19
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-
tion stop detection reset.
Hardware Reset
There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.
Hardware Reset 1
____________ _____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
____________
Table 1.5.1. Pin Status When RESET Pin Level is “L”). The oscillation circuit is initialized and the main
____________
clock starts oscillating. When the input level at the RESET pin is released from “L” to “H”, the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
____________
vector. The internal RAM is not initialized. If the RESET pin is pulled “L” while writing to the internal
RAM, the internal RAM becomes indeterminate.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1
____________
shows the status of the other pins while the RESET pin is “L”. Figure 1.5.3 shows the CPU register
status after reset. Refer to “SFR” for SFR status after reset.

1. When the power supply is stable

____________
(1) Apply an “L” signal to the RESET pin.
(2) Supply a clock for 20 cycles or more to the XIN pin.
(3) Apply an “H” signal to the RESET pin.

2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Supply a clock for 20 cycles or more to the XIN pin.
____________
(5) Apply an “H” signal to the RESET pin.

Hardware Reset 2
This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-
tion circuit monitors the voltage supplied to the VCC1 pin.
If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-
puter is reset when the voltage at the VCC1 input pin drops below Vdet3.
Similarly, if the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit en-
abled), the microcomputer is reset when the voltage at the VCC1 input pin drops below Vdet2.
Conversely, when the input voltage at the VCC1 pin rises to Vdet3 or more, the pins and the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
vector. It takes about td(S-R) before the program starts running after Vdet3 is detected. The initialized
pins and registers and the status thereof are the same as in hardware reset 1.
Set the CM10 bit in the CM1 register to “1” (stop mode) after setting the VC25 bit to “1” (RAM retention
limit detection circuit enabled), and the microcomputer will be reset when the voltage at the VCC1 input
pin drops below Vdet2 and comes out of reset when the voltage at the VCC1 input pin rises above
Vdet3. During stop mode, the value set in the VC26 bit has no effect. Therefore, no reset is generated
even when the input voltage at the VCC1 pin drops to Vdet3 or less.

20
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

Recommended
operating
voltage
VCC1

0V
RESET VCC1

RESET
Equal to or less Equal to or less
than 0.2VCC1 than 0.2VCC1
0V
More than 20 cycles of XIN + td(P-R)
are needed.

Note : When the microcomputer is used under the condition VCC1 ≥ VCC2, make sure the VCC2 voltage does not
exceed the VCC1 voltage when powering up, or powering down the microcomputer.

Figure 1.5.1 shows the example reset circuit

Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.

Watchdog Timer Reset

Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom-
puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector.
At watchdog timer reset, some SFR ’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00
bits in the PM0 register are not initialized, the processor mode remains unchanged.

Oscillation Stop Detection Reset

Where the CM27 bit in the CM2 register is “0” (reset at oscillation stop detection), the microcomputer
initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to
the section “oscillation stop, re-oscillation detection function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”. Also, since
the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.

21
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

VCC1, VCC2

XIN

td(P-R) More than

20 cycles
are needed

Microprocessor
mode BYTE = “H”

RESET BCLK 28cycles

BCLK
Content of reset vector

Address FFFFC16 FFFFD16 FFFFE16

RD

WR

CS0

Microprocessor
mode BYTE = “L” Content of reset vector

Address FFFFC16 FFFFE16

RD

WR

CS0

Single chip FFFFC16 Content of reset vector

mode

Address FFFFE16

Figure 1.5.2. Reset sequence

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

____________
Table 1.5.1. Pin Status When RESET Pin Level is “L”
Status
Pin name CNVSS = VCC1 (Note 1)
CNVSS = VSS
BYTE = VSS BYTE = VCC

P0 Input port Data input Data input

P1 Input port Data input Input port
P2, P3, P40 to P43 Input port Address output (undefined) Address output (undefined)
P44 Input port CS0 output (“H” is output) CS0 output (“H” is output)
P45 to P47 Input port Input port (Pulled high) Input port (Pulled high)

P50 Input port WR output (“H” is output) WR output (“H” is output)

P51 Input port BHE output (undefined) BHE output (undefined)
P52 Input port RD output (“H” is output) RD output (“H” is output)
P53 Input port BCLK output BCLK output

HLDA output (The output value HLDA output (The output value
P54 Input port depends on the input to the depends on the input to the
HOLD pin) HOLD pin)

P55 Input port HOLD input HOLD input

P56 Input port ALE output (“L” is output) ALE output (“L” is output)
P57 Input port RDY input RDY input

P6, P7, P80 to P84, Input port Input port Input port
P86, P87, P9, P10
P11, P12, P13, Input port Input port Input port
P140, P141 (Note 2)
Note 1: Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.
When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.
Note 2: P11, P12, P13, P140, P141 pins exist in 128-pin version.

b15 b0

000016 Data register(R0)

000016 Data register(R1)
000016 Data register(R2)
000016 Data register(R3)
000016 Address register(A0)
000016 Address register(A1)
000016 Frame base register(FB)

b19 b0
0000016 Interrupt table register(INTB)
Content of addresses FFFFE16 to FFFFC16 Program counter(PC)

b15 b0

000016 User stack pointer(USP)

000016 Interrupt stack pointer(ISP)
000016 Static base register(SB)

b15 b0

000016 Flag register(FLG)

AA
AAAAAA
AA
AAAAAAA
AA
b15 b8 b7 b0

IPL U I O B S Z D C

Figure 1.5.3. CPU Register Status After Reset

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

Voltage Detection Circuit

The voltage detection circuit has circuits to monitor the input voltage at the VCC1 pin, each checking the
input voltage with respect to Vdet2, Vdet3, and Vdet4, respectively. Use the VC25 to VC27 bits in the
VCR2 register to select whether or not to enable these circuits.
The VC25 bit in the VCR2 register needs to be set to “1” (WDC register the internal RAM retention limit
detection circuit enable), when using hardware reset 2 in stop mode, or when using the WDC5 bit.
Use the reset level detection circuit for hardware reset 2.
The voltage down detection circuit can be set to detect whether the input voltage is equal to or greater
than Vdet4 or less than Vdet4 by using the VC13 bit in the VCR1 register. Furthermore, a voltage down
detection interrupt can be used.

WDC5 bit

Write to WDC register S Q WARM/COLD

(Cold start, warm start)
Internal power on reset
VCR2 register R
RESET
b7 b6 b5
Internal power supply
1 shot voltage stable time
+ td(S-R)
Vdet2 >T
Half latch
E Q
D Q

T +
Vdet3 Internal reset signal
(“L” active)
E
CM10 bit=1
(stop mode)

VCC1 +
Vdet4 Voltage down
Noise rejection
E detection signal
VCR1 register

b3

VC13 bit

Figure 1.5.4. Voltage Detection Circuit Block

Watchdog timer control register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 WDC 000F16 00XXXXXX2(Note 2)

Bit symbol Bit name Function RW

(b4-b0) High-order bit of watchdog timer RO

Cold start / warm start 0 : Cold start
WDC5 RW
discrimination flag (Note 1) 1 : Warm start

Reserved bit Must set to “0” RW

(b6)
WDC7 Prescaler select bit 0 : Divided by 16
RW
1 : Divided by 128

Note 1: Writing to the WDC register causes the WDC5 bit to be set to “1” (warm start).
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set
to “0” when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register
is set to “1” (RAM retention limit detection circuit enable).

Figure 1.5.5. WDC Register

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

Voltage detection register 1

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset (Note 2)
0 0 0 0 0 0 0 VCR1 001916 000010002

Bit symbol Bit name Function RW

(b2-b0) Reserved bit Must set to “0” RW

VC13 Voltage down monitor flag 0:VCC1 < Vdet4 RO

(Note 1) 1:VCC1 ≥ Vdet4
(b7-b4) Reserved bit Must set to “0” RW

Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (voltage down detection circuit
enable). The VC13 bit is always “1” (VCC1≥ 4 V) when the VC27 bit in the VCR2 register is set to “0” (voltage
down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

Voltage detection register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset (Note 6)
0 0 0 0 0 VCR2 001A16 0016

Bit symbol Bit name Function RW

(b4-b0) Reserved bit Must set to “0” RW

VC25 RAM retention limit 0: Disable RAM retention limit

detection monitor bit detection circuit
(Notes 3, 4, 7) 1: Enable RAM retention limit RW
detection circuit

VC26 Reset level monitor bit 0: Disable reset level detection

(Notes 2, 3, 7) circuit
1: Enable reset level detection RW
circuit

VC27 Voltage down monitor 0: Disable voltage down

bit (Note 5, 7) detection circuit
1: Enable voltage down RW
detection circuit

Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: To use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: To use hardware reset 2 in stop mode, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc1 pin
becomes lower than Vdet3.)
Note 4: To use the WDC5 bit in the WDC register, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
Note 5: Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
Note 6: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 7: The detection circuit does not start operation until td(E-A) elapses after the VC25 bit, VC26 bit, or VC27 bit is
set to “1”.

Voltage down detection interrupt register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
D4INT 001F16 0016

Bit symbol Bit name Function RW

D40 Voltage down detection 0 : Disable
RW
interrupt enable bit (Note 5) 1 : Enable
D41 STOP mode deactivation 0: Disable (do not use the power
control bit supply down detection
interrupt to get out of stop mode)
(Note 4) 1: Enable (use the voltage RW
down detection interrupt to get
out of stop mode)

Voltage change detection flag 0: Not detected RW

D42
(Note 2) (Note 3)
1: Vdet4 passing detection

D43 WDT overflow detect flag 0: Not detected RW

1: Detected (Note 3)

Sampling clock select bit b5b4

DF0 RW
00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
DF1 RW
11 : CPU clock divided by 64

Nothing is assigned. When write, set to “0”. When read, its

(b7-b6) content is “0”.
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is effective when the VCR2 register VC27 bit = 1. To set the D40 bit to “1”, follow the
procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E–A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 1.5.3. Sampling Time”).

Figure 1.5.5. VCR Register, VCR2 Register, and D4INT Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

(1) When stop mode is not used

5.0V 5.0V
Vdet4
Vdet3r
VCC1 Vdet3
Vdet2
Vdet3s
VSS

RESET

Internal reset signal

VC13 bit undefined

Set to “1” in a program (reset level detection circuit enable)

VC26 bit undefined

Set to “1” in a program
(RAM retention limit detection circuit enable)
VC25 bit undefined

Set to “1” in a program (warm start)

WDC5 bit undefined

The above diagram applies to the following case:

• The CM10 bit in the CM1 register =0 (clock oscillating, not in stop mode)
• The VC27 bit in the VCR2 register is set to “1” after reset (voltage down detection circuit enabled)(to use VC13)

(1) When stop mode is used

5.0V
5.0V
Vdet4
VCC1 Vdet3r
Vdet2
Vdet3s
VSS
RESET

Internal reset signal

Set to “1” in a program (warm start)

WDC5 bit undefined
Set to “1” in a program (stop mode)

CM10 bit undefined

VC13 bit undefined

Set to “1” in a program
(RAM retention limit detection circuit enable)
undefined
VC25 bit

The above diagram applies to the following case:

• The VC27 bit in the VCR2 register is set to “1” after reset (voltage down detection circuit enabled)(to use VC13)

Figure 1.5.7. Typical Operation of Hardware Reset 2

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

Voltage Down Detection Interrupt

A voltage down detection interrupt request is generated when the input voltage at the VCC1 pin rises to
Vdet4 or more or drops below Vdet4 while the D40 bit in the D4INT register is set to “1” (voltage down
detection interrupt enable). The voltage down detection interrupt shares the interrupt vector with the
watch-dog timer interrupt and oscillation stop, re-oscillation detection interrupt.
To use the voltage down detection interrupt to get out of stop mode, set the D41 bit in the D4INT register
to “1” (enable).
The D42 bit in the D4INT register becomes “1” when passing through Vdet4 is detected after the voltage
inputted to the VCC1 pin is up or down.
A voltage down detection interrupt is generated when the D42 bit changes state from “0” to “1”. The D42
bit needs to be set to “0” in a program. However, where the D41 bit is “1” and the stop mode is selected,
the voltage down detection interrupt request arises, and the microcomputer is reset from the stop mode
with no regard for the status of D42 bit if it is detected that the voltage applied to the VCC1 pin has
increased, passing through Vdet4.
Table 1.5.2 shows the voltage down detection interrupt request generation conditions.
It is possible to set the sampling clock detecting that the voltage applied to the VCC1 pin has passed
through Vdet4 with the DF1 to DF0 bits of D4INT register. Table 1.5.3 shows sampling times.
Table 1.5.2. Voltage Down Detection Interrupt Request Generation Conditions
operation mode VC27 bit D40 bit D41 bit D42 bit CM02 bit VC13 bit
Normal
operation 0 to 1 (Note 3)
0 to 1
mode(Note 1) 1 to 0 (Note 3)
0 to 1 (Note 3)
Wait mode 0 to 1 0
(Note 2) 1 1 1 to 0 (Note 3)
1 0 to 1
Stop mode 1 0 0 to 1
(Note 2)
– : “0”or “1”
Note 1: The status except the wait mode and stop mode is handled as the normal mode.(Refer to “Clock generating circuit”)
Note 2: Refer to “Limitations on stop mode”, “Limitations on wait mode”.
Note 3: An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
Refer to the “Figure 1.5.9. Voltage Down Detection Interrupt Generation Circuit Operation Example” for details.
Table 1.5.3. Sampling Times

CPU Sampling time (µs)

clock DF1 to DF0=00 DF1 to DF0=01 DF1 to DF0=10 DF1 to DF0=11
(MHz) (CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)

16 3.0 6.0 12.0 24.0

Precautions
1. Limitations on Stop Mode
Before setting the CM10 bit in the CM1 register to “1” (stop mode), be sure to clear the CM02 bit in the
CM0 register to “0” (do not stop the peripheral function clock).
If the CM10 bit in the CM1 register is set to “1” (stop mode) when the VC13 bit in the VCR1 register is “1”
(VCC1 ≥ Vdet4) while the VC27 bit in the VCR2 register is “1” (voltage down detection circuit enable) and
the D40 bit in the D4INT register is “1” (voltage down detection interrupt enable) and D41 bit in the D4INT
register is “1” (voltage down detection interrupt is used to get out of stop mode), a voltage down detection
interrupt request is immediately generated, causing the microcomputer to exit stop mode.
In systems where the microcomputer enters stop mode when the input voltage at the VCC1 pin drops
below Vdet4 and exits stop mode when the input voltage rises to Vdet4 or more, make sure the CM10 bit
is set to “1” when VC13 bit is “0” (VCC1 < Vdet4).

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset

2. Limitations on WAIT Instruction

In cases where the CM02 bit in the CM0 register is “1” (stop the peripheral function clock) while the VC27
bit in the VCR2 register = 1 (enable the voltage down detection circuit) and the D40 bit in the D4INT
register = 1 (enable the voltage down detection interrupt), if the WAIT instruction is executed when the
VC13 bit in the VCR1 register = 1 (VCC1 ≥ Vdet4), a voltage down detection interrupt will be generated
immediately after that, causing the microcomputer to return from wait mode.
In systems where the microcomputer enters wait mode when the voltage applied to the VCC1 pin drops to
Vdet4 or below and leaves wait mode when the applied voltage rises to Vdet4 or above, make sure the
D42 bit is cleared to “0” when the VC13 bit = 0 (VCC1 < Vdet4) before executing the WAIT instruction.

Voltage down detection interrupt generation circuit

DF1, DF0
002
012 D42 bit is set to “0”(not detected) by
writing a “0” in a program. VC27 bit
Voltage down detection circuit 102
is set to “0” (voltage down detection
D4INT clock(the 112 circuit disabled), the D42 bit is set to
1/8 1/2 1/2 1/2
VC27 clock with which it “0”.
operates also in
wait mode) D42
VC13 Watchdog
timer interrupt
VCC1 + Noise signal
Noise rejection Digital
VREF rejection Voltage down circuit filter
-
detection signal
(Rejection wide:200 ns)

“H” when VC27 bit= 0 Voltage down

D41 detection Non-maskable
(disabled)
interrupt signal interrupt signal
CM10 Oscillation stop,
re-oscillation
detection
CM02
interrupt signal
WAIT instruction(wait mode)
Watchdog timer block
D43

D40
Watchdog timer
underflow signal This bit is set to “0”(not detected) by writing a “0” in a program.

Figure 1.5.8. Power Supply Down Detection Interrupt Generation Block

VCC1

VC13 bit

sampling sampling sampling sampling

No voltage down detection interrupt signals are

generated when the D42 bit is “H”.

Output of the digital filter (Note 2)

D42 bit

Set to “0” in a Set to “0” in a

program (not program (not
detected) detected)

Voltage down detection

interrupt signal

Note 1 : D40 is “1”(voltage down detection interrupt enabled)

Note 2 : Output of the digital filter shown in Figure 1.5.8.

Figure 1.5.9. Power Supply Down Detection Interrupt Generation Circuit Operation Example

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode

Processor Mode
(1) Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 1.6.1 shows the features of these processor modes.

Table 1.6.1. Features of Processor Modes

Processor modes Access space Pins which are assigned I/O ports
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Memory expansion mode SFR, internal RAM, internal ROM, Some pins serve as bus control pins (Note)
external area (Note)
Microprocessor mode SFR, internal RAM, external area (Note) Some pins serve as bus control pins (Note)
Note : Refer to “Bus”.

(2) Setting Processor Modes

Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 1.6.2 shows the processor mode after hardware reset. Table 1.6.3 shows the PM01 to PM00 bit set
values and processor modes.

Table 1.6.2. Processor Mode After Hardware Reset

CNVSS pin input level Processor mode
VSS Single-chip mode
VCC1 (Note 1, Note 2) Microprocessor mode
Note 1: If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1
or hardware reset 2), the internal ROM cannot be accessed regardless of PM10 to PM00 bits.
Note 2: The multiplexed bus cannot be assigned to the entire CS space.

Table 1.6.3. PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 bits Processor modes
002 Single-chip mode
012 Memory expansion mode
102 Must not be set
112 Microprocessor mode

Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regard-
less of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits
cannot be rewritten to “012” (memory expansion mode) or “112” (microprocessor mode) at the same time
the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or hard-
ware reset 2), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 1.6.1 and 1.6.2 show the registers associated with processor modes. Figure 1.6.3 show the
memory map in single chip mode.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode

Processor mode register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset (Note 4)
PM0 000416 000000002 (CNVSS pin = “L”)
000000112 (CNVSS pin = “H”)

Bit symbol Bit name Function RW

b1 b0
PM00 Processor mode bit
0 0: Single-chip mode RW
(Note 4)
0 1: Memory expansion mode
PM01 1 0: Must not be set
1 1: Microprocessor mode
RW

PM02 R/W mode select bit 0 : RD,BHE,WR

(Note 2) 1 : RD,WRH,WRL
RW

PM03 Software reset bit Setting this bit to “1” resets the
microcomputer. When read, its content RW
is “0”.
b5 b4
PM04 Multiplexed bus space
0 0 : Multiplexed bus is unused
select bit (Note 2) (Separate bus in the entire CS RW
space)
PM05 0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space RW
(Note 3)
PM06 Port P40 to P43 function 0 : Address output
select bit (Note 2) 1 : Port function RW
(Address is not output)
PM07 BCLK output disable bit 0 : BCLK is output
(Note 2) 1 : BCLK is not output RW
(Pin is left high-impedance)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Note 3: To set the PM01 to PM00 bits are “012” and the PM05 to PM04 bits are “112” (multiplexed bus assigned to
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the
CNVSS pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “112” after reset.
If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 4: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop
detection reset.

Figure 1.6.1. PM0 Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode

Processor mode register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 PM1 000516 0X0010002

Bit symbol Bit name Function RW

PM10 CS2 area switch bit 0: 0800016 to 26FFF16
RW
(data block enable bit) (block A disable)
(Note 2) 1: 1000016 to 26FFF16
(block A enable)

PM11 Port P37 to P34 0 : Address output

function select bit (Note 3) 1 : Port function
RW

PM12 Watchdog timer function 0 : Watchdog timer interrupt

RW
select bit 1 : Watchdog timer reset (Note 4)

PM13 Internal reserved area See Note 7 RW

expansion bit (Note 6)
b5 b4
Memory area
PM14 0 0 : 1 Mbyte mode RW
expansion bit (Note 3)
(Do not expand)
0 1 : Must not be set
PM15 1 0 : Must not be set RW
1 1 : 4 Mbyte mode

Reserved bit Should be set to “0”.

(b6) RW
PM17 Wait bit (Note 5) 0 : No wait state
1 : With wait state (1 wait) RW

Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: For the mask ROM version, this bit must be set to “0” . For the flash memory version, the PM10 bit also
controls block A by enabling or disabling it. However, the PM10 bit is automatically set to “1” when the FMR0
1 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Note 4: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 5: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area. If the CSiW bit (i = 0 to 3) in the CSR register is “0” (with wait state), the
CSi area is always accessed with one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplex bus is used, set the CSiW bit to “0” (with wait state).
Note 6: The PM13 bit is automatically set to “1” when the FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 7: The access area is changed by the PM13 bit as listed in the table below.

Access area PM13=0 PM13=1

Internal RAM Up to addresses 0040016 to 03FFF16 (15 Kbytes) The entire area is usable
ROM Up to addresses D000016 to FFFFF16 (192 Kbytes) The entire area is usable
External Addresses 0400016 to 07FFF16 are usable Addresses 0400016 to 07FFF16 are reserved
Addresses 8000016 to CFFFF16 are usable Addresses 8000016 to CFFFF16 are reserved

Figure 1.6.2. PM1 Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode

Single-chip mode PM13=0

Internal RAM Internal ROM
0000016 Capacity Address XXXXX16 Capacity Address YYYYY16
SFR
4K bytes 013FF16 48K bytes F400016
0040016
5K bytes 017FF16 64K bytes F000016
Internal RAM 10K bytes 02BFF16 96K bytes E800016
12K bytes 033FF16 128K bytes E000016
XXXXX16 16K bytes 03FFF16(Note 2) 192K bytes D000016
20K bytes 03FFF16(Note 2) 256K bytes D000016(Note 2)
24K bytes 03FFF16(Note 2) 320K bytes D000016(Note 2)
31K bytes 03FFF16(Note 2) 384K bytes D000016(Note 2)
512K bytes D000016(Note 2)
Can not PM13=1
use
Internal RAM Internal ROM
Capacity Address XXXXX16 Capacity Address YYYYY16
4K bytes 013FF16 48K bytes F400016
5K bytes 017FF16 64K bytes F000016
YYYYY16
10K bytes 02BFF16 96K bytes E800016
Internal ROM 12K bytes 033FF16 128K bytes E000016
16K bytes 043FF16 192K bytes D000016
FFFFF16 20K bytes 053FF16 256K bytes C000016
24K bytes 063FF16 320K bytes B000016
31K bytes 07FFF16 384K bytes A000016
512K bytes 8000016
Note 1: For the mask ROM version, set the PM10 bit to “0” (0800016 to 26FFF16 for CS2 area).
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

Figure 1.6.3. Memory Map in Single Chip Mode

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Bus

Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
_______
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0
_______ _____ ________ ______ ________ ________ ________ __________ _________
to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.

Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0
register.

Separate Bus
In this bus mode, data and address are separate.

Multiplexed Bus
In this bus mode, data and address are multiplexed.
• When the input level on BYTE pin is high (8-bit data bus)
D0 to D7 and A0 to A7 are multiplexed.
• When the input level on BYTE pin is low (16-bit data bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.
External buses connecting to a multiplexed bus are allocated to only the even addresses of the micro-
computer. Odd addresses cannot be accessed.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 1.7.1
shows the PM06 and PM11 bit set values and address bus widths.
Table 1.7.1. PM06 and PM11 Bits Set Value and Address Bus Width
Set value(Note) Pin function Address bus wide
PM11=1 P34 to P37
12 bits
PM06=1 P40 to P43
PM11=0 A12 to A15
16 bits
PM06=1 P40 to P43
PM11=0 A12 to A15
20 bits
PM06=0 A16 to A19
Note 1: No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address
bus is indeterminate until any external area is accessed.

(2) Data Bus

When input on the BYTE pin is high(data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.

(3) Chip Select Signal

______ ______
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins.
_____
These pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 1.7.1 shows the CSR register.
______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______ ______ ______
from the CSi pin. During 4 Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to
______
“Memory space expansion function”. Figure 1.7.2 shows the example of address bus and CSi signal
output in 1 Mbyte mode.

Chip select control register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
CSR 000816 000000012

Bit symbol Bit name Function RW

CS0 CS0 output enable bit RW
0 : Chip select output disabled
CS1 CS1 output enable bit (functions as I/O port) RW
CS2 CS2 output enable bit 1 : Chip select output enabled RW
CS3 CS3 output enable bit RW
CS0W CS0 wait bit RW
0 : With wait state
CS1W CS1 wait bit 1 : Without wait state RW
CS2W CS2 wait bit (Note 1, Note 2, Note 3) RW
CS3W CS3 wait bit RW

Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set
the CSiW bit to “0” (Wait state).
Note 2: If the PM17 bit in the PM1 register is set to “1” (with wait state), the external area indicated by CS0 to
CS3 is always accessed with one wait state even when the CSiW bit is “1” (without wait state).
Note 3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be
selected using the CSEi1W to CSEi0W bits in the CSE register.

Figure 1.7.1. CSR Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

Example 1 Example 2
To access the external area indicated by CSj in the next cycle after To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi accessing the external area indicated by CSi

The address bus and the chip select signal both change state between The chip select signal changes state but the address bus does not
these two cycles. change state

Access to the external Access to the external Access to the external Access to the internal
area indicated by CSi area indicated by CSj area indicated by CSi ROM or internal RAM

BCLK BCLK

Read signal Read signal

Data bus Data Data Data bus Data

Address bus Address Address Address bus Address

CSi CSi

CSj

Example 3 Example 4
To access the external area indicated by CSi in the next cycle after Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by the same CSi accessing the external area indicated by CSi

The address bus changes state but the chip select signal does not Neither the address bus nor the chip select signal changes state between
change state these two cycles

Access to the external Access to the same Access to the external No access
area indicated by CSi external area area indicated by CSi

BCLK BCLK

Read signal Read signal

Data bus Data Data Data bus Data

Address bus Address Address Address bus Address

CSi CSi

Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.

Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)

______
Figure 1.7.2. Example of Address Bus and CSi Signal Output in 1 Mbyte Mode

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

(4) Read and Write Signals

_____
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
________ ______ _____ ________ ________
BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
_____ ______ ________
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
_____ ________ _________
Table 1.7.2 shows the operation of RD, WRL, and WRH signals. Table 1.7.3 shows the operation of
_____ ______ ________
operation of RD, WR, and BHE signals.

_____ ________ _________

Table 1.7.2. Operation of RD, WRL and WRH Signals
Data bus width RD WRL WRH Status of external data bus
L H H Read data
16-bit
( BYTE pin input H L H Write 1 byte of data to an even address
= “L”) H H L Write 1 byte of data to an odd address
H L L Write data to both even and odd addresses

_____ ______ ________

Table 1.7.3. Operation of RD, WR and BHE Signals
Data bus width RD WR BHE A0 Status of external data bus
H L L H Write 1 byte of data to an odd address
L H L H Read 1 byte of data from an odd address
16-bit H L H L Write 1 byte of data to an even address
(BYTE pin input L H H L Read 1 byte of data from an even address
= “L”)
H L L L Write data to both even and odd addresses
L H L L Read data from both even and odd addresses
8-bit (BYTE pin H L (Note) H or L Write 1 byte of data
input = “H”) L H (Note) H or L Read 1 byte of data
Note : Do not use.

(5) ALE Signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.

When BYTE pin input = “H” When BYTE pin input = “L”

ALE ALE

A0/D0 to A7/D7
A0 Address
Address Data

A1/D0 to A8/D7 Address Data

A8 to A19 Address (Note)

A9 to A19 Address

Note : If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.

Figure 1.7.3. ALE Signal, Address Bus, Data Bus

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

________
(6) The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.

______ ______ ______ ________ ________ ______ ________ __________

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA

________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the
________ ________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________ ________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.

In an instance of separate bus

BCLK

RD

CSi
(i=0 to 3)
AAAAA
RDY
tsu(RDY - BCLK)

Accept timing of RDY signal

In an instance of multiplexed bus

BCLK

RD

CSi
(i=0 to 3)
AAAAAA
RDY
tsu(RDY - BCLK)

AA
AA
: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits in the CSE register are “002” (one wait state).

________
Figure 1.7.4. Example in which Wait State was Inserted into Read Cycle by RDY Signal

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

(7) Hold Signal

This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
__________
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
__________
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
__________
which time the HLDA pin outputs a low-level signal.
Table 1.7.4 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.

__________
HOLD > DMAC > CPU
Figure 1.7.5. Bus-using Priorities

Table 1.7.4. Microcomputer Status in Hold State

Item Status
BCLK Output
_______ _______ _____ ________ _________ _______ _______
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE High-impedance
I/O ports P0, P1, P3, P4(Note 2) High-impedance
P6 to P14(Note 1) Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Undefined
Note 1: P11 to P14 are included in the 128-pin version.
Note 2: When I/O port function is selected.
Note 3: The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count
source for the watchdog timer is the ring oscillator clock).

(8) BCLK Output

If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to “CPU clock and pheripheral clock”.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

Table 1.7.5. Pin Functions for Each Processor Mode

Memory expansion
Processor mode Memory expansion mode or microprocessor mode mode
002(separate bus) 012(CS2 is for multiplexed bus and 112(multiplexed bus
others are for separate bus) for the entire space)
PM05–PM04 bits
102(CS1 is for multiplexed bus and (Note 1)
others are for separate bus)

Data bus width 8 bits 16 bits 8 bits 16 bits 8 bits

BYTE pin “H” “L” “H” “L” “H”
P00 to P07 D0 to D7 D0 to D7 D0 to D7(Note 4) D0 to D7(Note 4) I/O ports
P10 to P17 I/O ports D8 to D15 I/O ports D8 to D15(Note 4) I/O ports
P20 A0 A0 A0/D0(Note 2) A0 A0/D0
P21 to P27 A1 to A7 A1 to A7 A1 to A7/D1 to D7 A1 to A7/D0 to D6 A1 to A7/D1 to D7
(Note 2) (Note 2)
P30 A8 A8 A8 A8/D7(Note 2) A8
P31 to P33 A9 to A11 I/O ports
P34 to P37 PM11=0 A12 to A15 I/O ports
PM11=1 I/O ports
P40 to P43 PM06=0 A16 to A19 I/O ports
PM06=1 I/O ports
P44 CS0=0 I/O ports
CS0=1 CS0
P45 CS1=0 I/O ports
CS1=1 CS1
P46 CS2=0 I/O ports
CS2=1 CS2
P47 CS3=0 I/O ports
CS3=1 CS3
P50 PM02=0 WR
PM02=1 (Note 3) WRL (Note 3) WRL (Note 3)
P51 PM02=0 BHE
PM02=1 (Note 3) WRH (Note 3) WRH (Note 3)
P52 RD
P53 BCLK
P54 HLDA
P55 HOLD
P56 ALE
P57 RDY
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: To set the PM01 to PM00 bits are set to “012” and the PM05 to PM04 bits are set to “112” (multiplexed bus assigned to the entire CS
space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not rewrite the PM05
to PM04 bits to “112” after reset. If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3: If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
Note 4: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

(9) External Bus Status When Internal Area Accessed

Table 1.7.6 shows the external bus status when the internal area is accessed.

Table 1.7.6. External Bus Status When Internal Area Accessed

Item SFR accessed Internal ROM, RAM accessed

A0 to A19 Address output Maintain status before accessed

address of external area or SFR

D0 to D15 When read High-impedance High-impedance

When write Output data Undefined

RD, WR, WRL, WRH RD, WR, WRL, WRH output Output “H”

BHE BHE output Maintain status before accessed

status of external area or SFR

CS0 to CS3 Output “H” Output “H”

ALE Output “L” Output “L”

(10) Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. Refer
to “Table 1.7.7. Bit and Bus Cycle Related to Software Wait” for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0”(with wait state). Figure 1.7.6
shows the CSE register. Table 1.7.7 shows the software wait related bits and bus cycles. Figure 1.7.7 and
1.7.8 show the typical bus timings using software wait.

Chip select expansion control register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
CSE 001B16 0016

Bit symbol Bit name Function RW

CS0 wait expansion bit b1 b0

CSE00W RW
(Note) 0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
CSE01W RW
1 1: Must not be set

CS1 wait expansion bit b3 b2

CSE10W RW
(Note) 0 0: 1 wait
0 1: 2 waits
CSE11W 1 0: 3 waits RW
1 1: Must not be set

CS2 wait expansion bit b5 b4

CSE20W RW
0 0: 1 wait
(Note) 0 1: 2 waits
CSE21W 1 0: 3 waits RW
1 1: Must not be set

CS3 wait expansion bit b7 b6

CSE30W RW
0 0: 1 wait
(Note)
0 1: 2 waits
CSE31W 1 0: 3 waits RW
1 1: Must not be set
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “
002” before setting it.

Figure 1.7.6. CSE Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

Table 1.7.7. Bit and Bus Cycle Related to Software Wait

CSR register CSE register
CS3W bit (Note 1) CSE31W to CSE30W bit
PM2 register PM1 register CS2W bit (Note 1) CSE21W to CSE20W bit Software wait
Area Bus mode PM20 bit PM17 bit Bus cycle
CS1W bit (Note 1) CSE11W to CSE10W bit
CS0W bit (Note 1) CSE01W to CSE00W bit

SFR 0 2 BCLK cycle (Note 3)

1 No wait 3 BCLK cycle (Note 3)

Internal 0 No wait 1 BCLK cycle (Note 4)

RAM, ROM 1 1 wait 2 BCLK cycles
1 BCLK cycle (read)
0 1 002 No wait
2 BCLK cycles (write)

Separate bus 0 002 1 wait 2 BCLK cycles (Note 4)

0 012 2 waits 3 BCLK cycles
External 0 102 3 waits 4 BCLK cycles
area
1 1 002 1 wait 2 BCLK cycles
0 002 1 wait 3 BCLK cycles

Multiplexed 0 012 2 waits 3 BCLK cycles

bus (Note 2)
0 102 3 waits 4 BCLK cycles
1 0 002 1 wait 3 BCLK cycles
Note 1: To use the RDY signal, set this bit to “0”.
Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
Note 3: When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the PM20 bit in the PM2 register. When using a
16 MHZ or higher PLL clock, be sure to set the PM20 bit to “0” (2 wait cycles).
Note 4: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“0016” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

(1) Separate bus, No wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Data bus Output Input

Address bus Address Address

CS

(2) Separate bus, 1-wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Output Input
Data bus

Address bus Address Address

CS

(3) Separate bus, 2-wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Output Input
Data bus

Address bus Address Address

CS

Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.

Figure 1.7.7. Typical Bus Timings Using Software Wait (1)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus

(1) Separate bus, 3-wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

Data bus Output Input

Address bus Address Address

CS

(2)Multiplexed bus, 1- or 2-wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

ALE

Address bus Address Address

Address bus/ Data output Address

Address Input
Data bus

CS

(3)Multiplexed bus, 3-wait setting

Bus cycle (Note) Bus cycle (Note)

BCLK

Write signal

Read signal

ALE

Address bus Address Address

Address bus/ Data output Address

Address Input
Data bus

CS

Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.

Figure 1.7.8. Typical Bus Timings Using Software Wait (2)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function

Memory Space Expansion Function

The following describes a memory space extension function.
During memory expansion or microprocessor mode, the memory space expansion function allows the
access space to be expanded using the appropriate register bits.
Table 1.8.1 shows the way of setting memory space expansion function, memory spaces.

Table 1.8.1. The Way of Setting Memory Space Expansion Function, Memory Space
Memory space expansion function How to set (PM15 to PM14) Memory space
1 Mbytes mode 002 1 Mbytes (no expansion)
4 Mbytes mode 112 4 Mbytes

(1) 1 Mbyte Mode

In this mode, the memory space is 1 Mbytes. In 1 Mbyte mode, the external area to be accessed is
______ ______
specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 1.8.2 to 1.8.3
_____
show the memory mapping and CS area in 1 Mbyte mode.

(2) 4 Mbyte Mode

In this mode, the memory space is 4 Mbytes. Figure 1.8.1 shows the DBR register. The BSR2 to BSR0
bits in the DBR register select a bank number which is to be accessed to read or write data. Setting the
OFS bit to “1” (with offset) allows the accessed address to be offset by 4000016.

______
In 4 Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed.
Addresses 0400016 to 3FFFF16, C000016 to FFFFF16
______ ______
• The CSi signal is output from the CSi pin (same operation as 1 Mbyte mode. However the last address
_______
of CS1 area is 3FFFF16)
Addresses 4000016 to BFFFF16
______
• The CS0 pin outputs “L”
______ ______
• The CS1 to CS3 pins output the value ofsetting as the BSR2 to BSR0 bits (bank number)

______
Figures 1.8.4 to 1.8.5 show the memory mapping and CS area in 4 Mbyte mode. Note that banks 0 to 6
______
are data-only areas. Locate the program in bank 7 or the CSi area.

Data bank register (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
DBR 000B16 0016

Bit symbol Bit name Description RW

Nothing is assigned. When write, set to “0”. When read, its content is
(b1-b0) “0”.

OFS Offset bit 0: Not offset

1: Offset RW
BSR0 Bank selection bits b5 b4 b3 b5 b4 b3
0 0 0: Bank 0 0 0 1: Bank 1 RW
0 1 0: Bank 2 0 1 1: Bank 3
BSR1 RW
1 0 0: Bank 4 1 0 1: Bank 5
1 1 0: Bank 6 1 1 1: Bank 7
BSR2 RW
Nothing is assigned. When write, set to “0”. When read, its content is
(b7-b6) “0”.

Note : Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).

Figure 1.8.1. DBR Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function

Memory expansion mode Microprocessor mode

0000016

AAAA AAAA
SFR SFR
0040016
Internal RAM Internal RAM

AAAA AAAA
XXXXX16
Reserved area Reserved area
0400016

AAAA AAAA
CS3(16 Kbytes)
0800016 Reserved, External area Reserved, external area CS2(PM10=0: 124 Kbytes)

AAAA AAAA
1000016 CS2 (PM10=1: 92 Kbytes)
2700016 Reserved area Reserved area
2800016

AAAA AAAA
CS1(32 Kbytes)
3000016
External area External area

AAAA AAAA
CS0(Memory expansion mode:640 Kbytes )

AAAA
D000016
Reserved area CS0(Microprocessor mode:832 Kbytes)

AAAA
YYYYY16
Internal ROM
FFFFF16

PM13=0
Internal RAM Internal ROM External area
Capacity Address XXXXX16 Capacity Address YYYYY16 CS0 CS1 CS2 CS3
4 Kbytes 013FF16 48 Kbytes F400016 Memory expansion mode 2800016– When PM10=0 0400016–
5 Kbytes 017FF16 64 Kbytes F000016 3000016–CFFFF16 2FFFF16 0800016–26FFF16 07FFF16
10 Kbytes 02BFF16 96 Kbytes E800016 Microprocessor mode When PM10=1
12 Kbytes 033FF16 128 Kbytes E000016 3000016–FFFFF16 1000016–26FFF16
16 Kbytes 03FFF16(Note) 192 Kbytes D000016
20 Kbytes 03FFF16(Note) 256 Kbytes D000016(Note)
24 Kbytes 03FFF16(Note) 320 Kbytes D000016(Note)
31 Kbytes 03FFF16(Note) 384 Kbytes D000016(Note)
512 Kbytes D000016(Note)

Note : If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
______
Figure 1.8.2. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=0)

Memory expansion mode Microprocessor mode

0000016
SFR SFR
0040016
Internal RAM Internal RAM
XXXXX16

AAAAA AAAAA
Reserved area

AAAAA AAAAA
0800016 Reserved, external area Reserved, external area CS2(PM10=0: 124 Kbytes)
1000016 CS2 (PM10=1: 92 Kbytes)

AAAAA AAAAA
2700016 Reserved area Reserved area
2800016

AAAAA AAAAA
CS1(32 Kbytes)
3000016
External

AAAAA AAAAA
area
External area CS0(Memory expansion mode:320 Kbytes )

8000016

YYYYY16

FFFFF16
Reserved area

Internal ROM
AAAAA
AAAAA
CS0(Microprocessor mode:832 Kbytes)

PM13=1
Internal RAM Internal ROM External area
Capacity Address XXXXX16 Capacity Address YYYYY16 CS0 CS1 CS2 CS3
4 Kbytes 013FF16 48 Kbytes F400016 Memory expansion mode 2800016– When PM10=0 No area
5 Kbytes 017FF16 64 Kbytes F000016 3000016–7FFFF16 2FFFF16 0800016–26FFF16
10 Kbytes 02BFF16 96 Kbytes E800016 Microprocessor mode When PM10=1
12 Kbytes 033FF16 128 Kbytes E000016 3000016–FFFFF16 1000016–26FFF16
16 Kbytes 043FF16 192 Kbytes D000016
20 Kbytes 053FF16 256 Kbytes C000016
24 Kbytes 063FF16 320 Kbytes B000016
31 Kbytes 07FFF16 384 Kbytes A000016
512 Kbytes 8000016

______
Figure 1.8.3. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=1)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function

Memory expansion mode Microprocessor mode

0000016
SFR SFR
0040016

AAAAA AAAAA
Internal RAM Internal RAM
XXXXX16
Reserved area Reserved area

AAAAA AAAAAA
0400016
CS3(16 Kbytes)
0800016 Reserved, external area

AAAAA AAAAAA
Reserved, external area CS2(PM10=0: 124 Kbytes)
1000016 CS2 (PM10=1: 92 Kbytes)
2700016

AAAAA AAAAAA
Reserved area Reserved area
2800016
CS1(96 Kbytes)

AAAAA AAAAAA
4000016
External area External area Other than the CS area (512 Kbytes X 8 banks)

AAAAA AAAAAA
C000016
CS0(Memory expansion mode:64 Kbytes )

AAAAAA
D000016
Reserved area CS0(Microprocessor mode:256 Kbytes)
YYYYY16

AAAAAA
Internal ROM
FFFFF16

PM13=0
Internal RAM Internal ROM External area
Capacity Address XXXXX16 Capacity Address YYYYY16 CS0 CS1 CS2 CS3 Other than the CS area (Note 1)
4 Kbytes 013FF16 48 Kbytes F400016 Memory expansion mode 2800016– When PM10=0
5 Kbytes 017FF16 64 Kbytes F000016 C000016–CFFFF16 3FFFF16 0800016–26FFF16 0400016– 4000016–BFFFF16
10 Kbytes 02BFF16 96 Kbytes E800016 Microprocessor mode When PM10=1 07FFF16
12 Kbytes 033FF16 128 Kbytes E000016 C000016–FFFFF16 1000016–26FFF16
16 Kbytes 03FFF16(Note2) 192 Kbytes D000016
20 Kbytes 03FFF16(Note2) 256 Kbytes D000016(Note2)
24 Kbytes 03FFF16(Note2) 320 Kbytes D000016(Note2)
31 Kbytes 03FFF16(Note2) 384 Kbytes D000016(Note2)
512 Kbytes D000016(Note2)
Note 1: The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

______
Figure 1.8.4. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=0)

Memory expansion mode Microprocessor mode

0000016
SFR SFR
0040016
Internal RAM Internal RAM
XXXXX16

Reserved area Reserved area

0800016

AAAAA
Reserved, external area

AAAAA Reserved, external area CS2(PM10=0: 124 Kbytes)

AAAAA AAAAA
1000016 CS2 (PM10=1: 92 Kbytes)
2700016 Reserved area Reserved area

AAAAA AAAAA
2800016
CS1(96 Kbytes)
4000016

AAAAA AAAAA
External area External area
Other than the CS area (Memory expansion mode:256 Kbytes X 8 banks)*
*Two 256 Kbytes X 8 banks can be used by changing the offset.

AAAAA
8000016 Other than the CS area(Microprocessor mode:512 Kbytes X 8 banks)
C000016

AAAAA
Reserved area

YYYYY16 CS0(Microprocessor mode:256 Kbytes)

Internal ROM
FFFFF16

PM13=1
Internal RAM Internal ROM External area
Capacity Address XXXXX16 Capacity Address YYYYY16 CS0 CS1 CS2 CS3 Other than the CS area (Note)
4 Kbytes 013FF16 48 Kbytes F400016 Microprocessor mode 2800016– When PM10=0 No area Memory expansion mode
5 Kbytes 017FF16 64 Kbytes F000016 C000016–FFFFF16 3FFFF16 0800016–26FFF16 4000016–7FFFF16
10 Kbytes 02BFF16 96 Kbytes E800016 When PM10=1 Microprocessor mode
12 Kbytes 033FF16 128 Kbytes E000016 1000016–26FFF16 4000016–BFFFF16
16 Kbytes 043FF16 192 Kbytes D000016
20 Kbytes 053FF16 256 Kbytes C000016
24 Kbytes 063FF16 320 Kbytes B000016
31 Kbytes 07FFF16 384 Kbytes A000016
512 Kbytes 8000016
Note : The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.

______
Figure 1.8.5. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=1)

46
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function

Figure 1.8.6 shows the external memory connect example in 4 Mbyte mode.
_____ _______
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte
_______ _______ _______
ROM address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of micro-
computer, respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Fig-
ures 1.8.7 to 1.8.9 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer
for the case of a connection example in Figure 1.8.6.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is “0”,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to “1”(offset) allows the
accessed address to be offset by 4000016, so that even the data overlapping a bank boundary can be
accessed in succession.
In memory expansion mode where the PM13 bit is “1”, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them over with the OFS bit.
____ _______
Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 =“L”, CS0
_______ _____ ____
and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept
____ _______ _______
“H” active and “L” active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the
chip.

8
D0 to D7 DQ0 to DQ7
17
A0 to A16 AD0 to AD16
A17 AD17
4M bytes ROM

A19 AD18
Microcomputer

CS1 AD19
CS2 AD20
CS3 AD21
RD OE
CS0 CS

WR DQ0 to DQ7
128K bytes SRAM

AD0 to AD16

OE
S2
(Note)
S1
W

Note: If only one chip select pin (S1 or S2) is present,

decoding by use of an external circuit is required.

Figure 1.8.6. External Memory Connect Example in 4M Byte Mode

47
48

Memory Space Expansion Function

Figure 1.8.7. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (1)
Memory expansion mode where PM13 =0

AAAA
ROM address Microcomputer address

AAAA
OFS bit of the DBR register=0 OFS bit of the DBR register=1

00000016 4000016

AAAA
Output from the microcomputer pins
Bank Access
OFS CS output Address output bank 0

AAAA
number area
CS3 CS2 CS1 A19 A18 A17 A16 A15–A0
04000016 (512 Kbytes) 4000016
4000016

AAAA
0 0 0 0 1 0 0 000016 00000016
0
BFFFF16 0 0 0 1 0 1 1 FFFF16 07FFFF16 BFFFF16 bank 0

AAAA
0
4000016 0 0 0 1 0 0 0 000016 04000016 08000016 4000016 (512 Kbytes)
1 0 0 1 0 1 1 1 FFFF16

AAAA
BFFFF16 0BFFFF16
0 0 1 0 1 0 0 bank 1 BFFFF16
4000016 000016 08000016

AAAA
0 (512 Kbytes) 4000016
BFFFF16 0 0 1 1 0 1 1 FFFF16 0FFFFF16 0C000016
1
4000016

AAAA
0 0 1 1 0 0 0 0C000016
1
000016 BFFFF16 bank 1
BFFFF16 0 1 0 0 1 1 1 FFFF16 13FFFF16 (512 Kbytes)
10000016 4000016

AAAA
4000016 0 1 0 0 1 0 0
000016 10000016
0 bank 2 BFFFF16

AAAA
BFFFF16 0 1 0 1 0 1 1 FFFF16 17FFFF16
2
4000016 0 1 0 1 0 0 0 000016 14000016 14000016 (512 Kbytes) 4000016

AAAA
1
BFFFF16 0 1 1 0 1 1 1 FFFF16 1BFFFF16
BFFFF16 bank 2

AAAA
4000016 0 1 1 0 1 0 0 000016 18000016
0 18000016 4000016 (512 Kbytes)
BFFFF16 0 1 1 1 0 1 1 FFFF16 1FFFFF16

AAAA
3 0 1 1 1 0 0 0
4000016 000016 1C000016 Data bank 3 BFFFF16
1

AAAA
BFFFF16 1 0 0 0 1 1 1 FFFF16 23FFFF16 1C000016 (512 Kbytes) 4000016
4000016 1 0 0 0 1 0 0 000016 20000016

AAAA
0
BFFFF16 1 0 0 1 0 1 1 FFFF16 27FFFF16 BFFFF16 bank 3
4

AAAA
4000016 1 0 0 1 0 0 0 000016 24000016 20000016 4000016 (512 Kbytes)
1 1 0 1 0 1 1 1 FFFF16
BFFFF16 2BFFFF16

AAAA
bank 4 BFFFF16
4000016 1 0 1 0 1 0 0 000016 28000016 (512 Kbytes)
0 24000016 4000016

AAAA
BFFFF16 1 0 1 1 0 1 1 FFFF16 2FFFFF16
5
4000016 1 0 1 1 0 0 0 000016 2C000016 BFFFF16 bank 4

AAAA
1
BFFFF16 1 1 0 0 1 1 1 FFFF16 33FFFF16 28000016 4000016 (512 Kbytes)

AAAA

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

4000016 1 1 0 0 1 0 0 000016 30000016
0 1 1 0 1 0 1 1 FFFF16 bank 5 BFFFF16
BFFFF16 37FFFF16

AAAA
6
4000016 1 1 0 1 0 0 0 2C000016 (512 Kbytes) 4000016
000016 34000016
1

AAAA
BFFFF16 1 1 1 0 1 1 1 FFFF16 3BFFFF16 BFFFF16 bank 5
1 1 1 0 1 0 0 38000016

AAAA
4000016 000016 30000016 4000016 (512 Kbytes)
7FFFF16 1 1 1 0 1 1 1 FFFF16 3BFFFF16

AAAA
8000016 1 1 1 1 0 0 0 000016 3C000016 bank 6 BFFFF16
BFFFF16 1 1 1 1 0 1 1 FFFF16 34000016 (512 Kbytes)

AAAA
3FFFFF16 4000016
7 0
1 1 1 1 1 0 0 000016 3C000016

M16C / 62P Group

C000016
BFFFF16 bank 6
CFFFF16 1 1 1 1 1 0 0 FFFF16 3CFFFF16

Renesas microcomputers
38000016 4000016 (512 Kbytes)
D000016 Internal ROM access Program or data bank 7
DFFFF16 Internal ROM access (512 Kbytes) BFFFF16
D000016 Internal ROM access 3C000016
DFFFF16 Internal ROM access Program or data
A21 A20 A19 A18 N.C. A17 A16 A15–A0 Address input for 4- 3FFFFF16 BFFFF16
Address input for 4-Mbyte ROM Mbyte ROM

N.C.: No connected
 Memory Space Expansion Function
Figure 1.8.8. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (2)

Memory expansion mode where PM13 =1

AAA
ROM address Microcomputer address

AAA
OFS bit of the DBR register=0 OFS bit of the DBR register=1

Output from the microcomputer pins 00000016 4000016

AAA
Bank Access bank 0
OFS CS output Address output (256 Kbytes)
number area
7FFFF16

AAA
CS3 CS2 CS1 A19 A18 A17 A16 A15–A0
4000016 04000016 4000016
0 0 0 0 1 0 0 000016 00000016 bank 0

AAA
0
7FFFF16 0 0 0 0 1 1 1 FFFF16 03FFFF16 (256 Kbytes)
0 7FFFF16

AAA
4000016 0 0 0 1 0 0 0 000016 04000016 08000016
1 4000016
7FFFF16 0 0 0 1 0 1 1 FFFF16 bank 1
07FFFF16

AAA
(256 Kbytes)
4000016 0 0 1 0 1 0 0 000016 08000016 7FFFF16
0

AAA
7FFFF16 0 0 1 0 1 1 1 FFFF16 0BFFFF16 0C000016 bank 1
4000016
1
4000016 (256 Kbytes)

AAA
0 0 1 1 0 0 0 000016 0C000016
1 7FFFF16
7FFFF16 0 0 1 1 0 1 1 FFFF16 0FFFFF16 4000016
10000016

AAA
bank 2
4000016 0 1 0 0 1 0 0 000016 10000016
0 (256 Kbytes)

AAA
7FFFF16 0 1 0 0 1 1 1 FFFF16 13FFFF16 7FFFF16
2 14000016
4000016 0 1 0 1 0 0 0 000016 14000016 4000016

AAA
1 bank 2
7FFFF16 0 1 0 1 0 1 1 FFFF16 17FFFF16 (256 Kbytes)
7FFFF16

AAA
4000016 0 1 1 0 1 0 0 000016 18000016 18000016 4000016
0 bank 3
7FFFF16

AAA
0 1 1 0 1 1 1 FFFF16 1BFFFF16
3 (256 Kbytes)
4000016 0 1 1 1 0 0 0 000016 1C000016 Data 7FFFF16

AAA
1 1C000016 4000016
7FFFF16 0 1 1 1 0 1 1 FFFF16 1FFFFF16 bank 3
(256 Kbytes

AAA
4000016 1 0 0 0 1 0 0 000016 20000016
0 7FFFF16
7FFFF16 1 0 0 0 1 1 1 FFFF16 23FFFF16 4000016

AAA
4 20000016 bank 4
4000016 1 0 0 1 0 0 0 000016 24000016 (256 Kbytes)
1

AAA
7FFFF16 1 0 0 1 0 1 1 FFFF16
27FFFF16 7FFFF16
4000016 24000016 4000016

AAA
1 0 1 0 1 0 0 000016 28000016 bank 4
0 (256 Kbytes)
7FFFF16 1 0 1 0 1 1 1 FFFF16 2BFFFF16 7FFFF16

AAA
5
4000016 1 0 1 1 0 0 0 000016 2C000016 28000016 4000016
1 bank 5

AAA
7FFFF16 1 0 1 1 0 1 1 FFFF16 2FFFFF16 (256 Kbytes)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

4000016 30000016 7FFFF16

AAA
1 1 0 0 1 0 0 000016
0 1 1 0 0 1 1 1 FFFF16 2C000016 4000016
7FFFF16 33FFFF16 bank 5
6

AAA
4000016 (256 Kbytes)
1 1 0 1 0 0 0 000016 34000016 7FFFF16
1
7FFFF16 1 1 0 1 0 1 1 FFFF16

AAA
37FFFF16 30000016 4000016
bank 6
4000016 1 1 1 0 1 0 0 000016 38000016 (256 Kbytes)

AAA
7FFFF16 1 1 1 0 1 1 1 FFFF16 3BFFFF16 7FFFF16
7 0 34000016 4000016

AAA
8000016 Internal ROM access bank 6
(256 Kbytes)
FFFFF16 Internal ROM access
7FFFF16

M16C / 62P Group

4000016 1 1 1 1 0 0 0 000016 3C000016 38000016 4000016

Renesas microcomputers
bank 7
7FFFF16 1 1 1 1 0 1 1 FFFF16 3FFFFF16 Program or data
(256 Kbytes)
7 1
8000016 Internal ROM access 7FFFF16
3C000016 4000016
FFFFF16 Internal ROM access bank 7
Program or data
A21 A20 A19 A18 N.C. A17 A16 A15–A0 Address input for 4- (256 Kbytes)
Mbyte ROM
3FFFFF16 7FFFF16
Address input for 4-Mbyte ROM
N.C.: No connected
49
50

Memory Space Expansion Function

Figure 1.8.9. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (3)

Microprocessor mode

AAA
ROM address Microcomputer address

AAA
OFS bit of the DBR register=0 OFS bit of the DBR register=1

00000016 4000016

AAA
Output from the microcomputer pins
Bank Access
number OFS area
CS output Address output bank 0

AAA
CS3 CS2 CS1 A19 A18 A17 A16 A15–A0 (512 Kbytes)
04000016 4000016

AAA
4000016 0 0 0 0 1 0 0 000016 00000016
0 BFFFF16 bank 0
BFFFF16 0 0 0 1 0 1 1 FFFF16 07FFFF16

AAA
0 08000016 (512 Kbytes)
4000016 0 0 0 1 0 0 0 000016 04000016 4000016
1

AAA
BFFFF16 0 0 1 0 1 1 1 FFFF16 0BFFFF16 bank 1 BFFFF16

AAA
4000016 0 0 1 0 1 0 0 000016 08000016 0C000016 (512 Kbytes) 4000016
0
BFFFF16 0 0 1 1 0 1 1 FFFF16 0FFFFF16

AAA
1 BFFFF16 bank 1
4000016 0 0 1 1 0 0 0 000016 0C000016
1 10000016 4000016 (512 Kbytes)

AAA
BFFFF16 0 1 0 0 1 1 1 FFFF16 13FFFF16
bank 2 BFFFF16

AAA
4000016 0 1 0 0 1 0 0 000016 10000016
0
BFFFF16 0 1 0 1 0 1 1 FFFF16 17FFFF16 14000016 (512 Kbytes) 4000016
2

AAA
4000016 0 1 0 1 0 0 0 000016 14000016
1 BFFFF16 bank 2

AAA
BFFFF16 0 1 1 0 1 1 1 FFFF16 1BFFFF16
18000016 4000016 (512 Kbytes)
4000016 18000016

AAA
0 1 1 0 1 0 0 000016
0 bank 3
BFFFF16 0 1 1 1 0 1 1 FFFF16 1FFFFF16 Data BFFFF16
3

AAA
1C000016 (512 Kbytes) 4000016
4000016 0 1 1 1 0 0 0 000016 1C000016
1
BFFFF16

AAA
1 0 0 0 1 1 1 FFFF16 23FFFF16
BFFFF16 bank 3
4000016 1 0 0 0 1 0 0 000016 20000016 (512 Kbytes)

AAA
0 20000016 4000016
BFFFF16 1 0 0 1 0 1 1 FFFF16 27FFFF16
4

AAA
bank 4 BFFFF16
4000016 1 0 0 1 0 0 0 000016 24000016
1 24000016 (512 Kbytes)
BFFFF16 1 0 1 0 1 1 1 FFFF16 4000016

AAA
2BFFFF16
4000016 1 0 1 0 1 0 0 000016 28000016 BFFFF16 bank 4

AAA
0
BFFFF16 1 0 1 1 0 1 1 FFFF16 2FFFFF16 28000016 4000016 (512 Kbytes)
5

AAA
2C000016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

4000016 1 0 1 1 0 0 0 000016
1 bank 5 BFFFF16
BFFFF16 1 1 0 0 1 1 1 FFFF16

AAA
33FFFF16 (512 Kbytes)
2C000016 4000016
4000016 1 1 0 0 1 0 0 000016 30000016

AAA
0
BFFFF16 1 1 0 1 0 1 1 FFFF16
37FFFF16 BFFFF16 bank 5
6 (512 Kbytes)

AAA
4000016 1 1 0 1 0 0 0 000016 34000016 30000016 4000016
1
BFFFF16 1 1 1 0 1 1 1 FFFF16 3BFFFF16

AAA
bank 6 BFFFF16
4000016 1 1 1 0 1 0 0 000016 38000016 (512 Kbytes)
34000016

AAA
4000016
7FFFF16 1 1 1 0 1 1 1 FFFF16 3BFFFF16
bank 6

M16C / 62P Group

8000016 1 1 1 1 0 0 0 000016 3C000016 BFFFF16
7 0 (512 Kbytes)

Renesas microcomputers
BFFFF16 1 1 1 1 0 1 1 FFFF16 38000016 4000016
3FFFFF16 Program or data bank 7
C000016 1 1 1 1 1 0 0 000016 3C000016 (512 Kbytes) 7FFFF16 BFFFF16
FFFFF16 1 1 1 1 1 1 1 FFFF16 3FFFFF16 3C000016 C000016
A21 A20 A19 A18 N.C. A17 A16 A15–A0 Address input for 4- Program or data
Address input for 4-Mbyte ROM Mbyte ROM FFFFF16
3FFFFF16
N.C.: No connected
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Clock Generation Circuit

The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) Ring oscillator
(4) PLL frequency synthesizer

Table 1.9.1 lists the clock generation circuit specifications. Figure 1.9.1 shows the clock generation circuit.
Figures 1.9.2 to 1.9.6 show the clock-related registers.

Table 1.9.1. Clock Generation Circuit Specifications

Item Main clock Sub clock Ring oscillator PLL frequency

oscillation circuit oscillation circuit synthesizer
Use of clock • CPU clock source •CPU clock source • CPU clock source • CPU clock source
• Peripheral function • Timer A, B's clock • Peripheral function clock source • Peripheral function clock
clock source source • CPU and peripheral function source
clock sources when the main
clock stops oscillating
Clock frequency 0 to 16 MHz 32.768 kHz About 1 MHz 10 to 24 MHz

Usable oscillator • Ceramic oscillator • Crystal oscillator

• Crystal oscillator
Pins to connect XIN, XOUT XCIN, XCOUT
oscillator

Oscillation stop, Presence Presence Presence Presence

restart function

Oscillator status Oscillating Stopped Stopped Stopped

after reset

Other Externally derived clock can be input

51
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

CM01–CM00=002
A
AAA
Sub-clock I/O ports
generating circuit PM01–PM00=002, CM01–CM00=012
CLKOUT
XCIN XCOUT PM01–PM00=002, CM01–CM00=102
PM01–PM00=002,
fC32 CM01–CM00=112
CM04 1/32

AA
AAA
f1
PCLK0=1
Sub-clock
f2
PCLK0=0

AAAA
fC
f8

AAAA
Ring
CM21 Ring oscillator
oscillator f32
clock
fAD

AA
Oscillation f1SIO
stop, re- PCLK1=1
oscillation
detection f2SIO
PCLK1=0
circuit
f8SIO

AAAA
CM10=1(stop mode) S Q PLL
XIN XOUT frequency f32SIO

AAA
A AA
AAAA AAAA
R
synthesizer e b c
CM07=0 D4INT clock
a d

AAAA
PLL CM21=1
clock
Divider CPU clock
Main 1
clock
Main clock 0 CM21=0 fC BCLK
generating circuit CM11
CM05 CM07=1

CM02

S Q

WAIT instruction R

e b c
a 1/2 1/2 1/2 1/2 1/2
1/32
RESET 1/2 1/4 1/8 1/16
Software reset CM06=0
CM17–CM16=112
NMI CM06=1
CM06=0
Interrupt request level judgment output CM17–CM16=102
d
CM02, CM04, CM05, CM06, CM07: CM0 register bits CM06=0
CM10, CM11, CM16, CM17: CM1 register bits CM17–CM16=012
PCLK0, PCLK1: PCLK register bits
CM21, CM27 : CM2 register bits CM06=0
CM17–CM16=002 Details of divider

Oscillation stop, re-oscillation detection circuit

Reset
Pulse generation CM27=0 generating Oscillation stop
circuit for clock Charge, circuit detection reset
Main edge detection discharge
clock and charge, circuit
Oscillation stop, Oscillation stop,
discharge control re-oscillation re-oscillation
CM27=1
detection interrupt detection signal
generating circuit

CM21 switch signal

PLL frequency synthesizer

Programmable
Voltage 1/2 PLL clock
counter
Phase Charge control
comparator pump oscillator
(VCO)
Main clock

Internal low-
pass filter

Figure 1.9.1. Clock Generation Circuit

52
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

System clock control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
CM0 000616 010010002

Bit symbol Bit name Function RW

b1 b0
CM00 Clock output function 0 0 : I/O port P57 RW
select bit 0 1 : fC output
(Valid only in single-chip 1 0 : f8 output
CM01 mode) RW
1 1 : f32 output
CM02 WAIT peripheral function 0 : Do not stop peripheral function clock in wait mode
clock stop bit (Note 10) 1 : Stop peripheral function clock in wait mode (Note 8) RW
XCIN-XCOUT drive capacity 0 : LOW
CM03 RW
select bit (Note 2) 1 : HIGH
Port XC select bit 0 : I/O port P86, P87
CM04
1 : XCIN-XCOUT generation function(Note 9)
RW
(Note 2)
CM05 Main clock stop bit 0 : On
(Notes 3, 10, 12, 13) 1 : Off (Note 4, Note5)
RW

CM06 Main clock division select 0 : CM16 and CM17 valid

bit 0 (Notes 7, 13, 14) 1 : Division by 8 mode RW

CM07 System clock select bit 0 : Main clock, PLL clock, or ring oscillator clock
(Notes 6, 10, 11, 12) 1 : Sub-clock
RW

Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: The CM03 bit is set to “1” (high) when the CM04 bit is set to “0” (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode
is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to “1” (Sub-clock select) or the CM21 bit of CM2 register to “1” (Ring oscillator select) with the sub-clock
stably oscillating.
(2) Set the CM20 bit of CM2 register to “0” (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to “1” (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the sub clock is not
chosen as a CPU clock.
Note 5: When CM05 bit is set to “1, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the CM06
bit is set to “1” (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to “1”. Also make sure ports P86 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to “1”, set the CM07 bit to “0”(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to “0” (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to “0”.
Note 13: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1”
(divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
Note 14: To return from ring oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits both to “1”.

Figure 1.9.2. CM0 Register

53
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

System clock control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 Symbol Address After reset

CM1 000716 001000002

Bit symbol Bit Function RW

name
All clock stop control bit 0 : Clock on
CM10 RW
(Notes 4, 6) 1 : All clocks off (stop mode)
CM11 System clock select bit 1 0 : Main clock
(Notes 6, 7) RW
1 : PLL clock (Note 5)

(b4-b2) Reserved bit Must set to “0” RW

CM15 XIN-XOUT drive capacity 0 : LOW RW

select bit (Note 2) 1 : HIGH
b7 b6
CM16 Main clock division 0 0 : No division mode RW
select bit 1 (Note 3) 0 1 : Division by 2 mode
CM17 1 0 : Division by 4 mode
1 1 : Division by 16 mode RW

Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit of CM2 register is
set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Note 5: After setting the PLC07 bit in PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
“1” (PLL clock).
Note 6: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is ring oscillator clock), writing to the CM10 bit
has no effect.
Note 7: Effective when CM07 bit is “0” and CM21 bit is “0” .

Figure 1.9.3. CM1 Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Oscillation stop detection register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 0 000C16
CM2 0X0000002(Note 11)

Bit symbol Bit name Function RW

Oscillation stop, re- 0: Oscillation stop, re-oscillation
CM20
oscillation detection bit detection function disabled
(Notes 7, 9, 10, 11) 1: Oscillation stop, re-oscillation RW
detection function enabled

CM21 System clock select bit 2 0: Main clock or PLL clock

(Notes 2, 3, 6, 8, 11, 12) 1: Ring oscillator clock
RW
(Ring oscillator oscillating)

CM22 Oscillation stop, re- 0: Main clock stop, re-oscillation

oscillation detection flag not detected RW
(Note 4) 1: Main clock stop, re-oscillation
detected

XIN monitor flag 0: Main clock oscillating

CM23 1: Main clock turned off RO
(Note 5)
Reserved bit Must set to “0” RW
(b5-b4)
Nothing is assigned. When write, set to “0”. When read, its
(b6) content is indeterminate.

CM27 Operation select bit 0: Oscillation stop detection reset

(when an oscillation stop, 1: Oscillation stop, re-oscillation RW
re-oscillation is detected) detection interrupt
(Note 11)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to “1” (ring oscillator clock) if the main clock stop is detected.
Note 3: If the CM20 bit is “1” and the CM23 bit is “1” (main clock turned off), do not set the CM21 bit to “0”.
Note 4: This flag is set to “1” when the main clock is detected to have stopped and when the main clock is
detected to have restarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop or
an oscillation restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate
the causes of interrupts between the oscillation stop and oscillation restart detection interrupts and the
watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in a program. (Writing a “1” has no
effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart detection interrupt request
acknowledged.)
If when the CM22 bit = 1 an oscillation stoppage or an oscillation restart is detected, no oscillation
stop and oscillation restart detection interrupts are generated.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 6: Effective when the CM07 bit of CM0 register is “0”.
Note 7: When the PM21 bit of PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
effect.
Note 8: Where the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is “1” (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is “0”
under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to “1” (ring oscillator clock) inside the interrupt
routine.
Note 9: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to “1” (enable).
Note 10: Set the CM20 bit to “0” (disable) before setting the CM05 bit of CM0 register.
Note 11: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 12: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM0
6 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).

Figure 1.9.4. CM2 Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Peripheral clock select register (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset
PCLKR 025E16 000000112
0 0 0 0 0 0

Bit symbol Bit name Function RW

PCLK0 Timers A, B clock select bit
0 : f2
(Clock source for the RW
1 : f1
timers A, B, and the dead
timer)
PCLK1 SI/O clock select bit 0 : f2SIO
(Clock source for UART0 1 : f1SIO RW
to UART2, SI/O3, SI/O4)

Reserved bit Must set to “0”

(b7-b2) RW
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).

Processor mode register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
PM2 001E16 XXX000002
0 0

Bit symbol Bit name Function RW

PM20 Specifying wait when
0 : 2 waits
accessing SFR at PLL RW
(Note 2) 1 : 1 wait
operation
PM21 System clock protective 0 : Clock is protected by PRCR
bit register RW
(Note 3, Note 4) 1 : Clock modification disabled
PM22 WDT count source 0 : CPU clock is used for the
protective bit watchdog timer count source RW
(Note 3, Note 5) 1 : Ring oscillator clock is used
for the watchdog timer count
source
Reserved bit Must set to “0”
RW
(b4-b3)
Nothing is assigned. When write, set to “0”. When read, its
(b7-b5) content is indeterminate.

Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is “0” (PLL turned off). Also, to select a 16 MHz or higher PLL
clock, set this bit to “0” (2 waits). Note that if the clock source for the CPU clock is to be changed from the PLL
clock to another, the PLC07 bit must be set to “0” before setting the PM20 bit.
Note 3: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 4: If the PM21 bit is set to “1”, writing to the following bits has no effect:
CM02 bit of CM0 register
CM05 bit in the CM0 register (main clock does not stop)
CM07 bit in the CM0 register (clock source for the CPU clock does not change)
CM10 bit of CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (clock source for the CPU clock does not change)
CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits of PLC0 register (PLL frequency synthesizer settings do not change)
Be aware that the WAIT instruction cannot be executed when the PM21 bit = 1.
Note 5: Setting the PM22 bit to “1” results in the following conditions:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode or hold state.

Figure 1.9.5. PCLKR Register and PM2 Register

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Clock Generation Circuit

PLL control register 0 (Note 1, Note 2)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 0 1 PLC0 001C16 0001 X0102

Bit
symbol Bit name Function RW

PLL multiplying factor b2 b1b0

PLC00 0 0 0: Do not set RW
select bit (Note 3) 0 0 1: Multiply by 2
0 1 0: Multiply by 4
PLC01 0 1 1: Multiply by 6 RW
1 0 0: Multiply by 8
1 0 1:
PLC02 1 1 0: Do not set RW
1 1 1:

Nothing is assigned. When write, set to “0”.

(b3) When read, its content is indeterminate.

Reserved bit Must set to “1” RW

(b4)

Reserved bit Must set to “0” RW

(b6-b5)

Operation enable bit 0: PLL Off

PLC07 RW
(Note 4) 1: PLL On
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the PM21 bit of PM2 register is “1” (clock modification disable), writing to this register has no effect.
Note 3: These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
cannot be modified.
Note 4: Before setting this bit to “1” , set the CM07 bit to “0” (main clock), set the CM17 to CM16 bits to “002”
(main clock undivided mode), and set the CM06 bit to “0” (CM16 and CM17 bits enable).

Figure 1.9.6. PLC0 Register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

The following describes the clocks generated by the clock generation circuit.
(1) Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as
the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured
by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a
feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the
amount of power consumed in the chip. The main clock oscillator circuit may also be configured by
feeding an externally generated clock to the XIN pin. Figure 1.9.7 shows the examples of main clock
connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or ring
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor. Note that if an externally generated clock is fed into
the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1”, unless the sub clock is
chosen as a CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.

Microcomputer Microcomputer
(Built-in feedback resistor) (Built-in feedback resistor)
XIN XOUT XIN XOUT
Open
(Note)
Rd
Externally derived clock

CIN VCC1
COUT
Vss

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.

Figure 1.9.7. Examples of Main Clock Connection Circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

(2) Sub Clock

The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 1.9.8 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscilla-
tor circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.

Microcomputer Microcomputer
(Built-in feedback resistor) (Built-in feedback resistor)
XCIN XCOUT XCIN XCOUT
Open
(Note)
RCd
Externally derived clock

CCIN CCOUT VCC1

Vss

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.

Figure 1.9.8. Examples of Sub Clock Connection Circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

(3) Ring Oscillator Clock

This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (ring oscillator
clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer
(Refer to “watchdog timer • Count source protective mode”.
After reset, the ring oscillator is turned off. It is turned on by setting the CM21 bit of CM2 register to “1”
(ring oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in place
of the main clock. If the main clock stops oscillating when the CM20 bit of CM2 register is “1” (oscillation
stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation
detection interrupt), the ring oscillator automatically starts operating, supplying the necessary clock for
the microcomputer.

(4) PLL Clock

The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the
CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 1.9.9 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits PLC0 register
(However, 10 MHz ≤ PLL clock frequency ≤ 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 1.9.2 shows the example for setting PLL
clock frequencies.

Table 1.9.2. Example for Setting PLL Clock Frequencies

XIN PLC02 PLC01 PLC00 Multiplying factor PLL clock
(MHz) (MHz)(Note)
10 0 0 1 2
5 0 1 0 4
3.33 0 1 1 6 20
2.5 1 0 0 8
12 0 0 1 2
6 0 1 0 4
4 0 1 1 6 24
3 1 0 0 8
Note: 10MHz≤PLL clock frequency≤24MHz.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Using the PLL clock as the clock source for the CPU

Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “002”(main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled). (Note)

Set the PLC02 to PLC00 bits (multiplying factor).

(To select a 16 MHz or higher PLL clock)

Set the PM20 bit to “0” (2-wait states).

Set the PLC07 bit to “1” (PLL operation).

Wait until the PLL clock becomes stable (tsu(PLL)).

Set the CM11 bit to “1” (PLL clock for the CPU clock source).

END

Note : PLL operation mode can be entered from high speed mode.

Figure 1.9.9. Procedure to Use PLL Clock as CPU Clock Source

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Clock Generation Circuit

CPU Clock and Peripheral Function Clock

Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or
the PLL clock.
If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “002” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator
low power dissipation mode, or when the CM05 bit of CM0 register is set to “1” (main clock turned off) in
low-speed mode, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode).
(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or ring oscillator clock by
dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32
clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D
converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.

Clock Output Function

During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to
CM00 bits of CM0 register to select.

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Clock Generation Circuit

Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.

(1) Normal Operation Mode

Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
ring oscillator or ring oscillator low power dissipation mode. Nor can operation modes be changed directly
from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation
mode. Where the CPU clock source is changed from the ring oscillator to the main clock, change the
operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the
CM06 bit of CM0 register was set to “1”) in the ring oscillator mode.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• PLL Operation Mode
The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (ring oscillator turned off), and the ring oscillator clock is
used when the CM21 bit is set to “1” (ring oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.

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Clock Generation Circuit

• Ring Oscillator Mode

The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32
can be used as the count source for timers A and B.
• Ring Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected
as in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function
clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. When the
operation mode is returned to the high and medium speed modes, set the CM06 bit to “1” (divided by
8 mode).
Table 1.9.3. Setting Clock Related Bit and Modes
CM2 register CM1 register CM0 register
Modes
CM21 CM11 CM17, CM16 CM07 CM06 CM05 CM04
PLL operation mode 0 1 002 0 0 0
High-speed mode 0 0 002 0 0 0
Medium- divided by 2 0 0 012 0 0 0
speed divided by 4 0 0 102 0 0 0
mode
divided by 8 0 0 0 1 0
divided by 16 0 0 112 0 0 0
Low-speed mode 1 0 1
Low power dissipation mode 1 1(Note 1) 1(Note 1) 1
Ring divided by 1 1 002 0 0 0
oscillator divided by 2 1 012 0 0 0
mode
divided by 4 1 102 0 0 0
divided by 8 1 0 1 0
divided by 16 1 112 0 0 0
Ring oscillator low power 1 (Note 2) 0 (Note 2) 1
dissipation mode
Note 1: When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode.

(2) Wait Mode

In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit of PM2 register is “1” (ring oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock, ring oscillator
clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = “1” (CPU clock source is the PLL clock), be sure to clear the CM11 bit to “0”
(CPU clock source is the main clock) before going to wait mode. The power consumption of the chip
can be reduced by clearing the PLC07 bit to “0” (PLL stops).
• Pin Status During Wait Mode
Table 1.9.4 lists pin status during wait mode
• Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-
ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait

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Clock Generation Circuit

mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral func-
tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked
by external signals can be used to exit wait mode.

Table 1.9.4. Pin Status During Wait Mode

Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
A0 to A19, D0 to D15, CS0 to CS3, Retains status before wait mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH “H”
__________
HLDA,BCLK “H”
ALE “H”
I/O ports Retains status before wait mode Retains status before wait mode
CLKOUT When fC selected Does not stop
When f8, f32 selected Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is main-
tained.

Table 1.9.5. Interrupts to Exit Wait Mode

Interrupt CM02=0 CM02=1
NMI interrupt Can be used Can be used
Serial I/O interrupt Can be used when operating Can be used when operating
with internal or external clock with external clock
key input interrupt Can be used Can be used
A-D conversion Can be used in one-shot mode (Do not use)
interrupt or single sweep mode
Timer A interrupt Can be used in all modes Can be used in event counter
Timer B interrupt mode or when the count
source is fC32

INT interrupt Can be used Can be used

Table 1.9.5 lists the interrupts to exit wait mode.

If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.

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(3) Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc1 and Vcc2 pins is VRAM or more,
the internal RAM is retained. When applying 2.7 or less voltage to Vcc1 and Vcc2 pins, make sure
Vcc1≥Vcc2≥VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• Voltage down detection interrupt (refer to “voltage down detection interrupt” for an operating condition)
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disable).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
• Pin Status in Stop Mode
Table 1.9.6 lists pin status during stop mode
• Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph-
eral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
If the CPU clock before entering stop mode was derived from the ring oscillator clock: ring oscillator
clock divide-by-8

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Table 1.9.6. Pin Status in Stop Mode

Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
A0 to A19, D0 to D15, CS0 to CS3, Retains status before stop mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH “H”
__________
HLDA, BCLK “H”
ALE “H”
I/O ports Retains status before stop mode Retains status before stop mode
CLKOUT When fc selected “H”
When f8, f32 selected Retains status before stop mode

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Clock Generation Circuit

Figure 1.9.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure
1.9.11 shows the state transition in normal operation mode.
Table 1.9.7 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.

Reset

WAIT
All oscillators stopped CM10=1 instruction CPU operation stopped
(Note 3)
Medium-speed mode
Stop mode (divided-by-8 mode) Wait mode
Interrupt Interrupt

Interrupt WAIT
CM07=0 instruction
CM06=1 (Note 3)
CM05=0 High-speed, medium-
CM11=0
Stop mode Wait mode
speed mode Interrupt
CM10=1 CM10=1
(Note 5)
When Notes 1, 2
low power When
dissipation low-
mode speed PLL operation
mode mode WAIT
CM10=1 instruction
(Note 3)
Stop mode Low-speed, low power
dissipation mode
Wait mode
Interrupt
Interrupt
WAIT
instruction
CM10=1 Ring oscillator, Ring oscillator (Note 3)
Stop mode dissipation mode Interrupt
Wait mode
Interrupt
(Note 4)

Normal mode

Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
Note 3: When the PM21 bit = 0 (system clock protective function unused).
Note 4: The ring oscillator clock divided by 8 provides the CPU clock.
Note 5: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (ring oscillator turned off).
Note 6: Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “0” (oscillation stop and oscillation restart detection
function disabled).

Figure 1.9.10. State Transition to Stop Mode and Wait Mode

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Clock Generation Circuit

Main clock oscillation

Ring oscillator clock
oscillation
Middle-speed mode Ring oscillator low power
PLL operation mode Middle-speed mode Middle-speed mode Middle-speed mode Ring oscillator mode
PLC07=1 (divide by 4) dissipation mode
High-speed mode (divide by 2) (divide by 8) (divide by 16)
CM11=1
CPU clock: f(PLL) CM21=0 CPU clock CPU clock
(Note 6) CPU clock: f(XIN) CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16 CM05=0
CM07=0 (Note 8) f(Ring) f(Ring)
CM07=0 CM07=0 CM07=0 CM07=0 f(Ring)/2 f(Ring)/2
CM06=0 CM07=0
CM06=0 CM06=0 CM06=0 CM06=0 f(Ring)/4 f(Ring)/4
CM17=0 f(Ring)/8 f(Ring)/8
PLC07=0 CM17=0 CM17=0 CM17=1 CM17=1 CM05=1
CM16=0 CM06=1 CM21=1 f(Ring)/16 f(Ring)/16
CM11=0 CM16=0 CM16=1 CM16=0 CM16=1 (Note 1)
(Note 7)

CM04=1 CM04=0 CM04=1 CM04=0 CM04=1 CM04=0 CM04=1 CM04=0

Ring oscillator
PLL operation Ring oscillator low power
Middle-speed mode Middle-speed mode Middle-speed mode Middle-speed mode
mode mode dissipation mode
PLC07=1 High-speed mode (divide by 2) (divide by 4) (divide by 8) (divide by 16)
CPU clock: f(PLL) CM11=1 CM21=0 CPU clock CPU clock
(Note 6) CPU clock: f(XIN) CPU clock: f(XIN)/2 CPU clock: f(XIN)/4 CPU clock: f(XIN)/8 CPU clock: f(XIN)/16 (Note 8) CM05=0
M
M0
CM07=0 f(Ring) f(Ring)
CM07=0 CM07=0 CM07=0 CM07=0 f(Ring)/2 f(Ring)/2
CM06=0 CM07=0
CM06=0 CM06=0 CM06=0 CM06=0 f(Ring)/4 f(Ring)/4
CM17=0 PLC07=0 f(Ring)/8 f(Ring)/8
CM17=0 CM17=0 CM17=1 CM17=1
CM16=0 CM11=0 CM06=1 CM21=1 f(Ring)/16 f(Ring)/16
(Note 7) CM16=0 CM16=1 CM16=0 CM16=1
CM05=1
(Note 1)

CM07=1 CM07=0
(Note 3) (Note 2, Note 4)

Low-speed mode CM21=0 Low-speed mode

CPU clock: f(XCIN) CPU clock: f(XCIN)

CM07=0 CM07=0
CM21=1

CM05=1 CM05=0
(Note 1, Note 9)

Low power dissipation mode

CPU clock: f(XCIN)

CM07=0
CM06=1
CM15=1

Sub clock oscillation

Notes:
1: Avoid making a transition when the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over.
3: Switch clock after oscillation of sub-clock is sufficiently stable.
4: Change CM17 and CM16 before changing CM06.
5: Transit in accordance with arrow.
6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.
To select a 16 MHz or higher PLL clock, set the PM20 bit to “0” (SFR accessed with two wait states) before setting PLC07 to “1” (PLL operation).
7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to “0” (PLL turned off)
before setting the PM20 bit to “1” (SFR accessed with one wait state).
8: Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
9: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).

Figure 1.9.11. State Transition in Normal Mode

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit

Table 1.9.7. Allowed Transition and Setting

State after transition
Ring oscillator
High-speed mode, Low-speed mode2 Low power PLL operation Ring oscillator
low power Stop mode
middle-speed mode dissipation mode mode2 mode Wait mode
dissipation mode
High-speed mode,
8 (9)7 -- (13)3 (15) -- (16)1 (17)
middle-speed mode See Table A
Low-speed mode2 (11)1, 6 (16)1
(8) -- -- -- (17)
Low power dissipation
mode -- (10) -- -- -- (16)1 (17)
Current state

PLL operation mode2 (12)3 -- -- -- -- -- --

Ring oscillator mode (14)4 -- -- -- See Table A
8 (11)1 (16)1 (17)
Ring oscillator
(16)1
low power dissipation -- -- -- -- (10) See Table A8 (17)
mode
Stop mode (18)5 (18) (18) -- (18)5 (18)5 --
Wait mode
(18) (18) (18) -- (18) (18) --
Notes: --: Cannot transit
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Ring oscillator clock oscillates and stops in low-speed mode. In this mode, the ring oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.

Sub clock oscillating Sub clock turned off

No Divided Divided Divided Divided No Divided Divided Divided Divided
division by 2 by 4 by 8 by 16 division by 2 by 4 by 8 by 16
No division (4) (5) (7) (6) (1) -- -- -- --
Divided by 2 (3) (5) (7) (6) -- (1) -- -- --
oscillating
Sub clock

Divided by 4 (3) (4) (7) (6) -- -- (1) -- --

Divided by 8 (3) (4) (5) (6) -- -- -- (1) --
Divided by 16 (3) (4) (5) (7) -- -- -- -- (1)
No division (2) -- -- -- -- (4) (5) (7) (6)
Divided by 2 -- (2) -- -- -- (3) (5) (7) (6)
Sub clock
turned off

Divided by 4 -- -- (2) -- -- (3) (4) (7) (6)

Divided by 8 -- -- -- (2) -- (3) (4) (5) (6)
Divided by 16 -- -- -- -- (2) (3) (4) (5) (7)
9. ( ) : setting method. Refer to following table. --: Cannot transit

Setting Operation

(1) CM04 = 0 Sub clock turned off

CM04, CM05, CM06, CM07 : bit of CM0 register
CM10, CM11, CM16, CM17 : bit of CM1 register
(2) CM04 = 1 Sub clock oscillating
CM20, CM21 : bit of CM2 register
CM06 = 0, PLC07 : bit of PLC0 register
(3) CM17 = 0 , CM16 = 0 CPU clock no division mode
CM06 = 0,
(4) CM17 = 0 , CM16 = 1
CPU clock division by 2 mode
CM06 = 0,
(5) CM17 = 1 , CM16 = 0
CPU clock division by 4 mode
CM06 = 0,
(6) CM17 = 1 , CM16 = 1
CPU clock division by 16 mode

(7) CM06 = 1 CPU clock division by 8 mode

Main clock, PLL clock,
(8) CM07 = 0
or ring oscillator clock selected
(9) CM07 = 1 Sub clock selected

(10) CM05 = 0 Main clock oscillating

(11) CM05 = 1 Main clock turned off

PLC07 = 0,
(12) CM11 = 0
Main clock selected
PLC07 = 1,
(13) CM11 = 1
PLL clock selected

(14) CM21 = 0 Main clock or PLL clock selected

(15) CM21 = 1 Ring oscillator clock selected

(16) CM10 = 1 Transition to stop mode

(17) wait instruction Transition to wait mode

(18) Hardware interrupt Exit stop mode or wait mode

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Clock Generation Circuit

System Clock Protective Function

When the main clock is selected for the CPU clock source, this function disables the clock against modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register

Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit of CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for the
CPU clock source):
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is “1”.

Oscillation Stop and Re-oscillation Detect Function

The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re-
oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit of CM2
register. The oscillation stop detection function can be enabled and disabled by the CM20 bit in the CM2
register. Table 1.9.8 lists an specification overview of the oscillation stop and re-oscillation detect function.

Table 1.9.8. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop, Set CM20 bit to “1”(enable)
re-oscillation detection function
Operation at oscillation stop, •Reset occurs (when CM27 bit =0)
re-oscillation detection •Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1)

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Clock Generation Circuit

(1) Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)

Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to “SFR”,
“Reset”).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)
(2) Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The ring oscillator starts oscillation, and the ring oscillator clock becomes the clock source for CPU clock
and peripheral functions in place of the main clock.
• CM21 bit = 1 (ring oscillator clock for CPU clock source)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)

Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(ring oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged

Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from
the stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged

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Clock Generation Circuit

How to Use Oscillation Stop and Re-oscillation Detect Function

• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-
rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read
the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and periph-
eral functions must be switched to the main clock in the program. Figure 1.9.12 shows the procedure for
switching the clock source from the ring oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-
comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-
abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-
tion detection interrupt request is generated. At the same time, the ring oscillator starts oscillating. In
this case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred,
the peripheral function clocks now are derived from the ring oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function dis-
abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.

Main clock switch

Inspect the CM23 bit

1(Main clock stop)
0(Main clock oscillation)

Do this check a number of times

The main clock is confirmed to be active a number of times.

Set the CM22 bit to 0 (main clock stop,

re-oscillation not detected).

Set the CM21 bit to 0

(main clock for the CPU clock source)(Note)

All of CM21-23 are the CM2 register bits

End

Note: If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation
mode after set to high-speed mode.

Figure 1.9.12. Procedure to Switch Clock Source From Ring Oscillator to Main Clock

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Protection

Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 1.10.1 shows the PRCR register. The following lists the registers protected
by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0 and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by PRC2 bit: PD9, S3C and S4C registers
• Registers protected by PRC3 bit: VCR2 and D4INT registers

Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.

Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 0 PRCR 000A16 XX0000002

Bit symbol Bit name Function RW

PRC0 Protect bit 0 Enable write to CM0, CM1, CM2,

PLC0 and PCLKR registers
RW
0 : Write protected
1 : Write enabled

Enable write to PM0, PM1, PM2,

PRC1 Protect bit 1 TB2SC, INVC0 and INVC1
registers
RW
0 : Write protected
1 : Write enabled (Note)

Enable write to PD9, S3C and

PRC2 Protect bit 2 S4C registers
RW
0 : Write protected
1 : Write enabled

Enable write to VCR2 and D4INT

PRC3 Protect bit 3 registers
RW
0 : Write protected
1 : Write enabled

Reserved bit Must set to “0” RW

(b5-b4)

Nothing is assigned. When write, set to “0”. When read, its

(b7-b6) content is indeterminate.

Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.

Figure 1.10.1. PRCR Register

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Interrupts

Type of Interrupts
Figure 1.11.1 shows types of interrupts.


 Undefined instruction (UND instruction)
 Software  Overflow (INTO instruction)
 (Non-maskable interrupt)
 BRK instruction
  INT instruction

  _______

  NMI
________
Interrupt   DBC (Note 2)
  Watchdog timer
  Special

  Oscillation stop and re-oscillation
 (Non-maskable interrupt)
   detection
Hardware
  Single step (Note 2)
  Address match

 Peripheral function (Note 1)
(Maskable interrupt)

Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.

Figure 1.11.1. Interrupts

• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.

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Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.

• Undefined Instruction Interrupt

An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.

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Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
_______
• NMI Interrupt
_______ _______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______
about the NMI interrupt, refer to the section "NMI interrupt".
________
• DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
• Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop and re-oscillation detection function, refer to the section "clock generating circuit".
• Voltage Down Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the
section "voltage detection circuit".
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or
AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt en-
abled). For details about the address match interrupt, refer to the section "address match interrupt".

(2) Peripheral Function Interrupts

Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in “Table 1.11.2.
Relocatable Vector Tables”. For details about the peripheral functions, refer to the description of each
peripheral function in this manual.

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Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 1.11.2 shows the interrupt vector.

Vector address (L)

AAAAAAAAA
AAAAAAAAA
MSB
Low address
LSB

AAAAAAAAA
AAAAAAAAA 0000
Mid address

High address

Vector address (H)

AAAAAAAAA 0000 0000

Figure 1.11.2. Interrupt Vector

• Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.11.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to the section "flash memory
rewrite disabling function".

Table 1.11.1. Fixed Vector Tables

Interrupt source Vector table addresses Remarks Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction serise software
BRK instruction FFFE416 to FFFE716 If the contents of address maual
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
Address match FFFE816 to FFFEB16 Address match interrupt
Single step (Note) FFFEC16 to FFFEF16
Watchdog timer FFFF016 to FFFF316 Watchdog timer
Oscillation stop and
re-oscillation detection Clock generating circuit
Voltage down
detection Voltage detection circuit
________
DBC (Note) FFFF416 to FFFF716
_______ _______
NMI FFFF816 to FFFFB16 NMI interrupt
Reset FFFFC16 to FFFFF16 Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.

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• Relocatable Vector Tables

The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 1.11.2 lists the relocatable vector tables. Setting an even address in the INTB regis-
ter results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 1.11.2. Relocatable Vector Tables

Interrupt source Vector address (Note 1) Software interrupt Reference

Address (L) to address (H) number

BRK instruction (Note 5) +0 to +3 (000016 to 000316) 0 M16C/60, M16C/20

series software
(Reserved) 1 to 3 manual
INT3 +16 to +19 (001016 to 001316) 4 INT interrupt
Timer B5 +20 to +23 (001416 to 001716) 5 Timer
(Note 4, 6) 6
Timer B4, UART1 bus collision detect +24 to +27 (001816 to 001B16) Timer
(Note 4, 6) Serial I/O
Timer B3, UART0 bus collision detect +28 to +31 (001C16 to 001F16) 7

SI/O4, INT5 (Note 2) +32 to +35 (002016 to 002316) 8

INT interrupt
SI/O3, INT4 (Note 2) +36 to +39 (002416 to 002716) 9 Serial I/O
UART 2 bus collision detection (Note 6) +40 to +43 (002816 to 002B16) 10 Serial I/O
DMA0 +44 to +47 (002C16 to 002F16) 11
DMAC
DMA1 +48 to +51 (003016 to 003316) 12
Key input interrupt +52 to +55 (003416 to 003716) 13 Key input interrupt

A-D +56 to +59 (003816 to 003B16) 14 A-D convertor

UART2 transmit, NACK2 (Note 3) +60 to +63 (003C16 to 003F16) 15
UART2 receive, ACK2 (Note 3) +64 to +67 (004016 to 004316) 16
UART0 transmit, NACK0 (Note 3) +68 to +71 (004416 to 004716) 17
Serial I/O
UART0 receive, ACK0 (Note 3) +72 to +75 (004816 to 004B16) 18

UART1 transmit, NACK1(Note 3) +76 to +79 (004C16 to 004F16) 19

UART1 receive, ACK1 (Note 3) +80 to +83 (005016 to 005316) 20

Timer A0 +84 to +87 (005416 to 005716) 21
Timer A1 +88 to +91 (005816 to 005B16) 22

Timer A2 +92 to +95 (005C16 to 005F16) 23

Timer A3 +96 to +99 (006016 to 006316) 24
Timer
Timer A4 +100 to +103 (006416 to 006716) 25

Timer B0 +104 to +107 (006816 to 006B16) 26

Timer B1 +108 to +111 (006C16 to 006F16) 27
Timer B2 +112 to +115 (007016 to 007316) 28

INT0 +116 to +119 (007416 to 007716) 29

INT1 +120 to +123 (007816 to 007B16) 30 INT interrupt
INT2 +124 to +127 (007C16 to 007F16) 31

+128 to +131 (008016 to 008316) 32 M16C/60, M16C/20

Software interrupt (Note 5) to to series software
+252 to +255 (00FC16 to 00FF16) 63 manual
Note 1: Address relative to address in INTB.
Note 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Note 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Note 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Note 5: These interrupts cannot be disabled using the I flag.
Note 6: Bus collision detection : During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I2C mode, however, a start condition or a stop condition detection constitutes
the cause of an interrupt.

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Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable
the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 1.11.3 shows the interrupt control registers.

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Interrupt control register (Note 2)

Symbol Address After reset
TB5IC 004516 XXXXX0002
TB4IC/U1BCNIC (Note 3) 004616 XXXXX0002
TB3IC/U0BCNIC (Note 3) 004716 XXXXX0002
BCNIC 004A16 XXXXX0002
DM0IC, DM1IC 004B16, 004C16 XXXXX0002
KUPIC 004D16 XXXXX0002

AAA
A
AA
ADIC 004E16 XXXXX0002
S0TIC to S2TIC 005116, 005316, 004F16 XXXXX0002
b7 b6 b5 b4 b3 b2 b1 b0 S0RIC to S2RIC 005216, 005416, 005016 XXXXX0002

AAA
AA
A
TA0IC to TA4IC 005516 to 005916 XXXXX0002
TB0IC to TB2IC 005A16 to 005C16 XXXXX0002

Bit symbol Bit name Function RW

ILVL0 Interrupt priority level
b2 b1 b0
select bit RW
000: Level 0 (interrupt disabled)
001: Level 1
ILVL1 010: Level 2
011: Level 3 RW
100: Level 4
101: Level 5
ILVL2 110: Level 6
111: Level 7 RW

IR Interrupt request bit 0 : Interrupt not requested RW

1 : Interrupt requested (Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
(b7-b4) when read are indeterminate.
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Note 3: Use the IFSR2A register to select.

AAA Symbol Address After reset

A
AA
INT3IC (Note 4) 004416 XX00X0002
b7 b6 b5 b4 b3 b2 b1 b0 S4IC/INT5IC 004816 XX00X0002
0 S3IC/INT4IC 004916 XX00X0002
INT0IC to INT2IC 005D16 to 005F16 XX00X0002

Bit symbol Bit name Function RW

ILVL0 Interrupt priority level
b2 b1 b0
select bit RW
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
ILVL1 0 1 0 : Level 2
0 1 1 : Level 3
RW
1 0 0 : Level 4
1 0 1 : Level 5
ILVL2 1 1 0 : Level 6
1 1 1 : Level 7 RW

IR Interrupt request bit 0: Interrupt not requested RW

1: Interrupt requested (Note 1)
POL Polarity select bit 0 : Selects falling edge (Notes 3, 5)
1 : Selects rising edge RW

Reserved bit Must always be set to “0” RW

(b5)
No functions are assigned.
(b7-b6) When writing to these bits, write “0”. The values in these bits RW
when read are indeterminate.

Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is “1” (both edges), set the INTiIC register’s POL bit to “0” (falling edge).
Note 4: When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the
LVL2 to ILVL0 bits in the INT5IC to INT3IC registers to “0002” (interrupts disabled).
Note 5: Set the S3IC or S4IC register’s POL bit to “0” (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.

Figure 1.11.3. Interrupt Control Registers

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I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.

IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.

ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt priority
levels enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag = “1”
· IR bit = “1”
· interrupt priority level > IPL

The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.

Table 1.11.3. Settings of Interrupt Priority Table 1.11.4. Interrupt Priority Levels
Levels Enabled by IPL

Interrupt priority Priority

ILVL2 to ILVL0 bits level order IPL Enabled interrupt priority levels

0002 Level 0 (interrupt disabled) 0002 Interrupt levels 1 and above are enabled

0012 Level 1 Low 0012 Interrupt levels 2 and above are enabled

0102 Level 2 0102 Interrupt levels 3 and above are enabled

0112 Level 3 0112 Interrupt levels 4 and above are enabled

1002 Level 4 1002 Interrupt levels 5 and above are enabled

1012 Level 5 1012 Interrupt levels 6 and above are enabled

1102 Level 6 1102 Interrupt levels 7 and above are enabled

1112 Level 7 High 1112 All maskable interrupts are disabled

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Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 1.11.4 shows time required for
executing the interrupt sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not re-
quested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register(Note 1).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.

Note: This register cannot be used by user.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CPU clock

Address bus Address Indeterminate (Note 1) SP-2 SP-4 vec vec+2 PC

000016
Data bus Interrupt SP-2 SP-4 vec vec+2
information Indeterminate (Note 1) contents contents contents contents

RD Indeterminate (Note 1)

WR
(Note 2)

Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.

Figure 1.11.4. Time Required for Executing Interrupt Sequence

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Interrupt Response Time

Figure 1.11.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 1.11.5) and a time during which the interrupt
sequence is executed ((b) in Figure 1.11.5).

Interrupt request generated Interrupt request acknowledged

Time

Instruction Interrupt sequence Instruction in

interrupt routine
(a) (b)

Interrupt response time

(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).

(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.

Interrupt vector address SP value 16-Bit bus, without wait 8-Bit bus, without wait
Even Even 18 cycles 20 cycles
Even Odd 19 cycles 20 cycles
Odd Even 19 cycles 20 cycles
Odd Odd 20 cycles 20 cycles

Figure 1.11.5. Interrupt response time

Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 1.11.5 is set in the IPL. Shown in Table 1.11.5 are the IPL values of software and special
interrupts when they are accepted.
Table 1.11.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources Level that is set to IPL
_______
Watchdog timer, NMI, Oscillation stop and re-oscillation detection, 7
voltage down detection
_________
Software, address match, DBC, single-step Not changed

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Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
1.11.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.

Address Stack Address Stack

MSB LSB MSB LSB

[SP]
m–4 m–4 PC New SP value
L

m–3 m–3 PC
M

m–2 m–2 FLGL

m–1 m–1 FLGH PCH

[SP]
SP value before
m Content of previous stack m Content of previous stack
interrupt request is
accepted.
m+1 Content of previous stack m+1 Content of previous stack

Stack status before interrupt request Stack status after interrupt request
is acknowledged is acknowledged

Figure 1.11.6. Stack Status Before and After Acceptance of Interrupt Request

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The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 1.11.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.

(1) SP contains even number

Address Stack Sequence in which order
registers are saved

[SP] – 5 (Odd)

[SP] – 4 (Even) PCL

(2) Saved simultaneously,
[SP] – 3(Odd) PCM all 16 bits

[SP] – 2 (Even) FLGL

(1) Saved simultaneously,
FLGH PCH all 16 bits
[SP] – 1(Odd)

[SP] (Even)
Finished saving registers
in two operations.

(2) SP contains odd number

Address Stack Sequence in which order
registers are saved

[SP] – 5 (Even)

[SP] – 4(Odd) PCL (3)

[SP] – 3 (Even) PCM

(4)
Saved, 8 bits at a time
[SP] – 2(Odd) FLGL
(1)

[SP] – 1 (Even) FLGH PCH (2)

[SP] (Odd)
Finished saving registers
in four operations.

Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.

Figure 1.11.7. Operation of Saving Register

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Returning from an Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt re-
quest.
Return the other registers saved by a program within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.

Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.11.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.

Reset High

NMI

DBC

Oscillation stop and re-oscillation

detection,
voltage down detection

Peripheral function

Single step
Low
Address match

Figure 1.11.8. Hardware Interrupt Priority

Interrupt Priority Resolution Circuit

The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 1.11.9 shows the circuit that judges the interrupt priority level.

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Priority level of each interrupt

Level 0 (initial value)
INT1
Highest
Timer B2

Timer B0

Timer A3

Timer A1

Timer B4, UART1 bus collision

INT3

INT2

INT0

Timer B1

Timer A4

Timer A2

Timer B3, UART0 bus collision

Timer B5

UART1 reception, ACK1

UART0 reception, ACK0

Priority of peripheral function interrupts
(if priority levels are same)
UART2 reception, ACK2

A-D conversion

DMA1

UART 2 bus collision

SI/O4, INT5

Timer A0

UART1 transmission, NACK1

UART0 transmission, NACK0

UART2 transmission, NACK2

Key input interrupt

DMA0
Lowest
SI/O3, INT4

IPL Interrupt request level resolution output to clock

generating circuit (Fig.1.11.1. Interrupts)

I flag Interrupt
request
Address match accepted

Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection

DBC

NMI

Figure 1.11.9. Interrupts Priority Select Circuit

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______
INT Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
_______ _______
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
_______ _______ _______
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the
_______
IFSR register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested)
before enabling the interrupt.
Figure 1.11.10 shows the IFSR and IFSR2A registers.

AAA
AAAA
Interrupt request cause select register

AAAA
AAA
b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address After reset

IFSR 035F16 0016

Bit symbol Bit name Function RW

IFSR0 INT0 interrupt polarity 0 : One edge
switching bit 1 : Both edges (Note 1) RW

IFSR1 INT1 interrupt polarity 0 : One edge

switching bit 1 : Both edges (Note 1) RW

IFSR2 INT2 interrupt polarity 0 : One edge

switching bit 1 : Both edges (Note 1) RW

IFSR3 INT3 interrupt polarity 0 : One edge

switching bit 1 : Both edges (Note 1) RW

IFSR4 INT4 interrupt polarity 0 : One edge

switching bit 1 : Both edges (Note 1) RW
IFSR5 INT5 interrupt polarity 0 : One edge
switching bit 1 : Both edges (Note 1) RW
IFSR6 Interrupt request cause 0 : SI/O3 (Note 3)
select bit (Note 2) 1 : INT4 RW
IFSR7 Interrupt request cause 0 : SI/O4
select bit (Note 2) 1 : INT5 RW

Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: During memory expansion and microprocessor modes, set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).

AAA
AAAA
Interrupt request cause select register 2

AAAA
AAA
b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address After reset

IFSR2A 035E16 00XXXXXX2

Bit symbol Bit name Function RW

Nothing is assigned. When write, set to “0”.
(b5-b0) When read, their contents are indeterminate.
IFSR26 Interrupt request cause 0 : Timer B3
select bit (Note 1) 1 : UART0 bus collision RW
detection
IFSR27 Interrupt request cause 0 : Timer B4
select bit (Note 2) 1 : UART1 bus collision RW
detection
Note 1: Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using the
timer B3 interrupt, clear the IFSR26 bit to “0” (timer B3). When using UART0 bus collision detection, set the
IFSR26 bit to “1”.
Note 2: Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using the
timer B4 interrupt, clear the IFSR27 bit to “0” (timer B4). When using UART1 bus collision detection, set the
IFSR27 bit to “1”.

Figure 1.11.10. IFSR Register and IFSR2A Register

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______
NMI Interrupt
_______ _______ ______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI
interrupt is a non-maskable interrupt.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
This pin cannot be used as an input port.

Key Input Interrupt

Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be
used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure
1.11.11 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which
has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port
are not detected as interrupts.

PUR2 register's PU25 bit

Pull-up KUPIC register

transistor PD10 register's
PD10_7 bit

PD10 register's PD10_7 bit

KI3

Pull-up PD10 register's

transistor PD10_6 bit
Key input interrupt
KI2 Interrupt control circuit
request

Pull-up
transistor PD10 register's
PD10_5 bit

KI1

Pull-up PD10 register's

transistor PD10_4 bit

KI0

Figure 1.11.11. Key Input Interrupt

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Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 1.11.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for external
areas.
Figure 1.11.12 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.

Table 1.11.6. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Value of the PC that is
Instruction at the address indicated by the RMADi register saved to the stack area

• 16-bit op-code instruction The address

• Instruction shown below among 8-bit operation code instructions indicated by the
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest RMADi register +2
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest
STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (However, dest=A0 or A1)

The address
Instructions other than the above indicated by the
RMADi register +1
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.

Table 1.11.7. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0 AIER0 RMAD0
Address match interrupt 1 AIER1 RMAD1
Address match interrupt 2 AIER20 RMAD2
Address match interrupt 3 AIER21 RMAD3

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Address match interrupt enable register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
AIER 000916 XXXXXX002

AAAAAAAAAAAAAA
Bit symbol Bit name Function RW

AAAAAAAAAAAAAA
AIER0 Address match interrupt 0 0 : Interrupt disabled
enable bit 1 : Interrupt enabled RW

AAAAAAAAAAAAAA
AIER1 Address match interrupt 1 0 : Interrupt disabled
enable bit RW
1 : Interrupt enabled
Nothing is assigned.
(b7-b2) When write, set to “0”.
When read, their contents are indeterminate.

Address match interrupt enable register 2

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset

AAAAAAAAAAAAAA
AIER2 01BB16 XXXXXX002

AAAAAAAAAAAAAA
Bit symbol Bit name Function RW
AIER20 Address match interrupt 2 0 : Interrupt disabled RW

AAAAAAAAAAAAAA
enable bit 1 : Interrupt enabled

AIER21 Address match interrupt 3 0 : Interrupt disabled

AAAAAAAAAAAAAA
enable bit 1 : Interrupt enabled RW

Nothing is assigned.
(b7-b2) When write, set to “0”.
When read, their contents are indeterminate.

Address match interrupt register i (i = 0 to 3)

(b23) (b19) (b16)(b15) (b8) Symbol Address After reset
b7 b3 b0 b7 b0 b7 b0
RMAD0 001216 to 001016 X0000016
RMAD1 001616 to 001416 X0000016
RMAD2 01BA16 to 01B816 X0000016
RMAD3 01BE16 to 01BC16 X0000016
Function Setting range RW
Address setting register for address match interrupt 0000016 to FFFFF16 RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.

Figure 1.11.12. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers

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Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot be
set to “0” (watchdog timer interrupt) in a program. Refer to “Watchdog Timer Reset” for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, ring oscillator clock, PLL clock, the divide-by-N
value for the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide-
by-N value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer
can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.

With main clock source chosen for CPU clock, ring oscillator clock, PLL clock

Prescaler dividing (16 or 128) X Watchdog timer count (32768)

Watchdog timer period =
CPU clock

With sub-clock chosen for CPU clock

Prescaler dividing (2) X Watchdog timer count (32768)

Watchdog timer period =
CPU clock

For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.

The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is re-
sumed from the held value when the modes or state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.

• Count source protective mode

In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit of PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit of PM2 register to “1” (ring oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).

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Setting the PM22 bit to “1” results in the following conditions

• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count
source.
Watchdog timer count (32768)
Watchdog timer period =
ring oscillator clock
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode or hold state.

Prescaler
CM07 = 0
WDC7 = 0
1/16
PM12 = 0
CPU CM07 = 0 Watchdog timer
WDC7 = 1 PM22 = 0 interrupt request
clock
1/128
HOLD
Watchdog timer
CM07 = 1 PM22 = 1
1/2
PM12 = 1
Reset

Ring oscillator clock

Set to
Write to WDTS register “7FFF16”

RESET

Figure 1.12.1. Watchdog Timer Block Diagram

Watchdog timer control register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 WDC 000F16 00XXXXXX2(Note 2)

Bit symbol Bit name Function RW

(b4-b0) High-order bit of watchdog timer RO

Cold start / warm start 0 : Cold start
WDC5 RW
discrimination flag (Note 1) 1 : Warm start

Reserved bit Must set to “0” RW

(b6)
WDC7 Prescaler select bit 0 : Divided by 16
RW
1 : Divided by 128

Note 1: Writing to the WDC register causes the WDC5 bit to be set to “1” (warm start).
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set
to “0” when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register
is set to “1” (RAM retention limit detection circuit enable).

Watchdog timer start register (Note)

b7 b0
Symbol Address After reset
WDTS 000E16 Indeterminate

Function RW

The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16” WO
regardless of whatever value is written.

Note : Write to the WDTS register after the watchdog timer interrupt occurs.

Figure 1.12.2. WDC Register and WDTS Register

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DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 1.13.1 shows the block diagram of the DMAC. Table 1.13.1
shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the DMAC-related registers.

AAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA AA
AAA
A
Address bus

AAA A AAA
AAA A AA
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)

AAA A AA AA
AA
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)

AA
A A AA
A AA
DMA0 forward address pointer (20) (Note)

AA
A A AAAA A AA
DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20)

AAAA AA AA AA
(addresses 002916, 002816) (addresses 003216 to 003016)

AA
A A AA AA
DMA0 transfer counter TCR0 (16) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)

AA
A A A AA
DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note)

A A AA
(addresses 003916, 003816)

AA
DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits

Data bus low-order bits AA

AA
Data bus high-order bits

Note: Pointer is incremented by a DMA request.

Figure 1.13.1. DMAC Block Diagram

A DMA request is generated by a write to the DMiSL register (i = 0–1)’s DSR bit, as well as by an interrupt
request which is generated by any function specified by the DMiSL register’s DMS and DSEL3–DSEL0 bits.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the
interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be
accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,
the interrupt control register’s IR bit does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =
“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.

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Table 1.13.1. DMAC Specifications

Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space • From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________
DMA request factors Falling edge of INT0 or
________
INT1
________
(Note 1, Note 2) Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority DMA0 > DMA1 (DMA0 takes precedence)
Transfer unit 8 bits or 16 bits
Transfer address direction forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode •Single transfer Transfer is completed when the DMAi transfer counter (i = 0–1)
underflows after reaching the terminal count.
•Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
DMA shutdown •Single transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
•Repeat transfer When the DMAE bit is set to “0” (disabled)
Reload timing for forward ad- When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
dress pointer and transfer
SARi or the DARi pointer whichever is specified to be in the forward
counter
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016–003F16) are accessed by the DMAC.

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DMA0 request cause select register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
DM0SL 03B816 0016

Bit symbol Bit name Function RW

DSEL0 DMA request cause Refer to note RW
select bit
DSEL1 RW

DSEL2 RW
DSEL3 RW
Nothing is assigned. When write, set to “0”.
(b5-b4) When read, its content is “0”.

DMA request cause 0: Basic cause of request

DMS RW
expansion select bit 1: Extended cause of request

Software DMA A DMA request is generated by

request bit setting this bit to “1” when the DMS
DSR bit is “0” (basic cause) and the RW
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .

Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 02 Falling edge of INT0 pin –
0 0 0 12 Software trigger –
0 0 1 02 Timer A0 –
0 0 1 12 Timer A1 –
0 1 0 02 Timer A2 –
0 1 0 12 Timer A3 –
0 1 1 02 Timer A4 Two edges of INT0 pin
0 1 1 12 Timer B0 Timer B3
1 0 0 02 Timer B1 Timer B4
1 0 0 12 Timer B2 Timer B5
1 0 1 02 UART0 transmit –
1 0 1 12 UART0 receive –
1 1 0 02 UART2 transmit –
1 1 0 12 UART2 receive –
1 1 1 02 A-D conversion –
1 1 1 12 UART1 transmit –

Figure 1.13.2. DM0SL Register

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DMA1 request cause select register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
DM1SL 03BA16 0016

Bit symbol Bit name Function RW

DSEL0 DMA request cause Refer to note RW
DSEL1 select bit RW
DSEL2 RW
DSEL3 RW

Nothing is assigned. When write, set to “0”.

(b5-b4) When read, its content is “0”.

DMS DMA request cause 0: Basic cause of request

expansion select bit RW
1: Extended cause of request
Software DMA A DMA request is generated by
request bit setting this bit to “1” when the DMS
DSR bit is “0” (basic cause) and the RW
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .

Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 02 Falling edge of INT1 pin –
0 0 0 12 Software trigger –
0 0 1 02 Timer A0 –
0 0 1 12 Timer A1 –
0 1 0 02 Timer A2 –
0 1 0 12 Timer A3 SI/O3
0 1 1 02 Timer A4 SI/O4
0 1 1 12 Timer B0 Two edges of INT1
1 0 0 02 Timer B1 –
1 0 0 12 Timer B2 –
1 0 1 02 UART0 transmit –
1 0 1 12 UART0 receive/ACK0 –
1 1 0 02 UART2 transmit –
1 1 0 12 UART2 receive/ACK2 –
1 1 1 02 A-D conversion –
1 1 1 12 UART1 receive/ACK1 –

DMAi control register(i=0,1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
DM0CON 002C16 00000X002
DM1CON 003C16 00000X002

Bit symbol Bit name Function RW

DMBIT Transfer unit bit select bit 0 : 16 bits

1 : 8 bits RW

DMASL Repeat transfer mode 0 : Single transfer RW

select bit 1 : Repeat transfer

DMA request bit 0 : DMA not requested RW

DMAS
1 : DMA requested (Note 1)

DMAE DMA enable bit 0 : Disabled

RW
1 : Enabled
Source address direction 0 : Fixed
DSD select bit (Note 2) RW
1 : Forward
Destination address 0 : Fixed
DAD RW
direction select bit (Note 2) 1 : Forward

Nothing is assigned. When write, set to “0”. When

(b7-b6)
read, its content is “0”.
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).

Figure 1.13.3. DM1SL Register, DM0CON Register, and DM1CON Registers

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DMAi source pointer (i = 0, 1) (Note)

(b23) (b19) (b16)(b15) (b8)
b7 b3 b0 b7 b0 b7 b0 Symbol Address After reset
SAR0 002216 to 002016 Indeterminate
SAR1 003216 to 003016 Indeterminate

Function Setting range RW

Set the source address of transfer 0000016 to FFFFF16 RW

Nothing is assigned. When write, set “0”. When read, these contents
are “0”.

Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.

DMAi destination pointer (i = 0, 1)(Note)

(b23) (b19) (b16)(b15) (b8)
b7 b3 b0 b7 b0 b7 b0
Symbol Address After reset
DAR0 002616 to 002416 Indeterminate
DAR1 003616 to 003416 Indeterminate

Function Setting range RW

Set the destination address of transfer 0000016 to FFFFF16 RW

Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.

DMAi transfer counter (i = 0, 1)

(b15) (b8)
b7 b0 b7 b0
Symbol Address After reset
TCR0 002916, 002816 Indeterminate
TCR1 003916, 003816 Indeterminate

Function Setting range RW

Set the transfer count minus 1. The written value

is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
000016 to FFFF16 RW
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.

Figure 1.13.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers

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1. Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory extension and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.

(a) Effect of Source and Destination Addresses

If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.

(b) Effect of BYTE Pin Level

During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-
bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.

(c) Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.

_______
(d) Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area
________ ________
are affected by the RDY signal. Refer to “RDY signal”.

Figure 1.13.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units using an 8-bit bus ((2) in Figure 1.13.5), two source read bus cycles and two destination write bus
cycles are required.

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(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

BCLK

Address Dummy
CPU use Source Destination CPU use
bus cycle

RD signal

WR signal

Data Dummy
CPU use Source Destination CPU use
bus cycle

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used

BCLK

Address Dummy
CPU use Source Source + 1 Destination CPU use
bus cycle

RD signal

WR signal

Data CPU use Source Source + 1 Dummy

Destination CPU use
bus cycle

(3) When the source read cycle under condition (1) has one wait state inserted

BCLK

Address Destination
Dummy
CPU use Source cycle CPU use
bus

RD signal

WR signal

Data Dummy
CPU use Source Destination CPU use
bus cycle

(4) When the source read cycle under condition (2) has one wait state inserted

BCLK

Address Dummy
CPU use Source Source + 1 Destination cycle CPU use
bus

RD signal

WR signal

Data Dummy
CPU use Source Source + 1 Destination CPU use
bus cycle

Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Transfer Cycles for Source Read

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2. DMA Transfer Cycles

Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMA transfer cycles. Table 1.13.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

Table 1.13.2. DMA Transfer Cycles

Single-chip mode
Memory expansion mode
Transfer unit Bus width Access address Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1 1 1 1
8-bit transfers (BYTE= “L”) Odd 1 1 1 1
(DMBIT= “1”) 8-bit Even — — 1 1
(BYTE = “H”) Odd — — 1 1
16-bit Even 1 1 1 1
16-bit transfers (BYTE = “L”) Odd 2 2 2 2
(DMBIT= “0”) 8-bit Even — — 2 2
(BYTE = “H”) Odd — — 2 2

Table 1.13.3. Coefficient j, k

Internal area External area
Internal ROM, RAM SFR Separate bus Multiplex bus
No wait With wait 1-wait2 2-wait2 No wait With wait1 With wait1
1 wait 2 waits 3 waits 1wait 2 waits 3 waits
j 1 2 2 3 1 2 3 4 3 3 4
k 1 2 2 3 2 2 3 4 3 3 4
Notes:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in PM2 register.

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3. DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.

If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.

4. DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 1.13.4 shows the
timing at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.

Table 1.13.4. Timing at Which the DMAS Bit Changes State

DMAS bit of the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
Software trigger When the DSR bit of DMiSL • Immediately before a data transfer starts
register is set to “1” • When set by writing “0” in a program
Peripheral function When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiSL register
has its IR bit set to “1”

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DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Channel Priority and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 1.13.6 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 1.13.6, occurs more than one time, the DMAS bit is set to “0” as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to “(7) Hold Signal in Bus Control” for details about bus arbitration between the CPU and DMA.

An example where DMA requests for external causes are detected active at the same

AAAA
BCLK

DMA0
AAAAAAAA
AAAAAA
AA AA AAAAA
AA
DMA1 Bus
arbitration

AAAAAA AA AAAAA
AA AA
CPU

INT0

DMA0
request bit

INT1

DMA1
request bit

Figure 1.13.6. DMA Transfer by External Factors

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Timers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function
as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 1.14.1 and 1.14.2 show block diagrams of timer A and
timer B configuration, respectively.

f2 PCLK0 bit = 0
1/2 Clock prescaler
• Main clock f1 f1 or f2
• PLL clock XCIN 1/32 fC32
• Ring oscillator PCLK0 bit = 1
1/8 f8 Reset
clock Set the CPSR bit of CPSRF
1/4 f32 register to “1” (= prescaler
reset)
f1 or f2 f8 f32 fC32

• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Timer A0
TA0IN Noise
filter • Event counter mode

• Timer mode
• One-shot timer mode
• PWM mode
Timer A1 interrupt
Timer A1
Noise
TA1IN filter
• Event counter mode

• Timer mode
• One-shot timer mode
• PWM mode
Timer A2 interrupt
Noise
Timer A2
TA2IN filter • Event counter mode

• Timer mode
• One-shot timer mode
• PWM mode
Timer A3 interrupt
Timer A3
Noise
TA3IN filter • Event counter mode

• Timer mode
• One-shot timer mode
• PWM mode
Timer A4 interrupt
Timer A4
Noise
TA4IN filter
• Event counter mode

Timer B2 overflow or underflow

Note: Be aware that TA0IN shares the pin with RxD2 and TB5IN.

Figure 1.14.1. Timer A Configuration

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f2 PCLK0 bit = 0
1/2 Clock prescaler
• Main clock f1 f1 or f2
• PLL clock XCIN 1/32 fC32
• Ring oscillator PCLK0 bit = 1
1/8 f8 Reset
clock Set the CPSR bit of CPSRF
1/4 f32 register to “1” (= prescaler
reset)
f1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B0 interrupt
Noise Timer B0
TB0IN filter
• Event counter mode

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B1 interrupt
TB1IN Noise
filter Timer B1
• Event counter mode

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode Timer B2 interrupt
Noise
TB2IN filter Timer B2
• Event counter mode

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode Timer B3 interrupt
Noise
TB3IN filter Timer B3
• Event counter mode

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode Timer B4 interrupt
TB4IN Noise
filter Timer B4
• Event counter mode

• Timer mode
• Pulse width measuring mode,
pulse period measuring mode Timer B5 interrupt
Noise
TB5IN filter Timer B5
• Event counter mode

Note: Be aware that TB5IN shares the pin with RxD2 and TA0IN.

Figure 1.14.2. Timer B Configuration

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Timers (Timer A) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A
Figure 1.14.3 shows a block diagram of the timer A. Figures 1.14.4 to 1.14.6 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.

Data bus high-order bits

AAAA
Clock source Data bus low-order bits
selection • Timer
f1 or f2 • One shot Low-order High-order

A
• PWM
f8 8 bits 8 bits
f32 • Timer Reload register

A
(gate function)
fC32
Clock selection
• Event counter
Polarity Counter
selection Up-count/down-count
TAiIN
(i = 0 to 4) Always counts down except
TABSR register
Clock selection in event counter mode

TAi Addresses TAj TAk

(Note) Timer A0 038716 - 038616 Timer A4 Timer A1
TB2 overflow To external Timer A1 038916 - 038816 Timer A0 Timer A2
(Note) trigger circuit Timer A2 038B16 - 038A16 Timer A1 Timer A3
TAj overflow Down count Timer A3 038D16 - 038C16 Timer A2 Timer A4
(j = i – 1. Note, however, that j = 4 when i = 0) Timer A4 038F16 - 038E16 Timer A3 Timer A0
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)

TAiOUT Pulse output

(i = 0 to 4)
Toggle flip-flop

Note: Overflow or underflow

Figure 1.14.3. Timer A Block Diagram

Timer Ai mode register (i=0 to 4)

Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0
TA0MR to TA4MR 039616 to 039A16 0016

Bit symbol Bit name Function RW

TMOD0 b1 b0
Operation mode select bit 0 0 : Timer mode RW
0 1 : Event counter mode
TMOD1 1 0 : One-shot timer mode
1 1 : Pulse width modulation RW
(PWM) mode
MR0 RW
Function varies with each
MR1 operation mode RW
MR2 RW
MR3 RW
TCK0 Count source select bit Function varies with each RW
TCK1 operation mode RW

Figure 1.14.4. TA0MR to TA4MR Registers

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Timer Ai register (i= 0 to 4) (Note 1)

Symbol Address After reset
(b15) (b8)
b7 b0 b7 b0 TA0 038716, 038616 Indeterminate
TA1 038916, 038816 Indeterminate
TA2 038B16, 038A16 Indeterminate
TA3 038D16, 038C16 Indeterminate
TA4 038F16, 038E16 Indeterminate
Mode Function Setting range RW
Timer Divide the count source by n + 1 where n = 000016 to FFFF16 RW
mode set value
Event Divide the count source by FFFF16 – n + 1 000016 to FFFF16
counter where n = set value when counting up or RW
mode by n + 1 when counting down (Note 5)
One-shot Divide the count source by n where n = set 000016 to FFFF16 WO
timer mode value and cause the timer to stop (Notes 2, 4)
Pulse width Modify the pulse width as follows: 000016 to FFFE16
modulation PWM period: (216 – 1) / fj (Note 3, 4)
mode High level PWM pulse width: n / fj WO
(16-bit PWM) where n = set value, fj = count source
frequency
Pulse width Modify the pulse width as follows: 0016 to FE16
modulation PWM period: (28 – 1) x (m + 1)/ fj (High-order address)
mode High level PWM pulse width: (m + 1)n / fj 0016 to FF16
(Low-order address) WO
(8-bit PWM) where n = high-order address set value,
m = low-order address set value, fj = (Note 3, 4)
count source frequency

Note 1: The register must be accessed in 16 bit units.

Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TABSR 038016 0016

Bit symbol Bit name Function RW

TA0S Timer A0 count start flag 0 : Stops counting RW

TA1S Timer A1 count start flag 1 : Starts counting RW

TA2S Timer A2 count start flag RW

TA3S Timer A3 count start flag RW

AAAAAAAAAAAAAA
TA4S Timer A4 count start flag RW

AAAAAAAAAAAAAA
TB0S Timer B0 count start flag RW

TB1S Timer B1 count start flag RW

AAAAAAAAAAAAAA
TB2S Timer B2 count start flag RW

Up/down flag (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
UDF 038416 0016

Bit symbol Bit name Function RW

TA0UD Timer A0 up/down flag 0 : Down count RW
1 : Up count
TA1UD Timer A1 up/down flag RW
Enabled by setting the TAiMR
TA2UD Timer A2 up/down flag register’s MR2 bit to “0” RW
(= switching source in UDF RW
TA3UD Timer A3 up/down flag register) during event counter
TA4UD Timer A4 up/down flag mode. RW

TA2P Timer A2 two-phase pulse 0 : two-phase pulse signal WO

signal processing select bit processing disabled
1 : two-phase pulse signal
TA3P Timer A3 two-phase pulse processing enabled
WO
signal processing select bit (Notes 2, 3)

TA4P Timer A4 two-phase pulse

WO
signal processing select bit

Note 1: Use MOV instruction to write to this register.

Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to
“0” (input mode).
Note 3: When not using the two-phase pulse signal processing function, set the bit corresponding to
timer A2 to timer A4 to “0”.

Figure 1.14.5. TA0 to TA4 Registers, TABSR Register, and UDF Register

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One-shot start flag

Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0 ONSF 038216 0016

Bit symbol Bit name Function RW

TA0 Timer A0 one-shot start flag The timer starts counting by setting RW
OS this bit to “1” while the TMOD1 to
TA1 Timer A1 one-shot start flag TMOD0 bits of TAiMR register (i = RW
OS
TA2OS Timer A2 one-shot start flag 0 to 4) = ‘102’ (= one-shot timer RW
mode) and the MR2 bit of TAiMR
TA3 Timer A3 one-shot start flag register = “0” (=TAiOS bit enabled). RW
OS When read, its content is “0”.
TA4 Timer A4 one-shot start flag RW
OS
0 : Z-phase input disabled
TA4 Z-phase input enable bit RW
OS 1 : Z-phase input enabled
b7 b6
TA0 Timer A0 event/trigger RW
TGL select bit 0 0 : Input on TA0IN is selected (Note 1)
0 1 : TB2 overflow is selected (Note 2)
TA0 1 0 : TA4 overflow is selected (Note 2) RW
TGH
1 1 : TA1 overflow is selected (Note 2)
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TRGSR 038316 0016

Bit symbol Bit name Function RW

TA1TGL Timer A1 event/trigger b1 b0
select bit 0 0 : Input on TA1IN is selected (Note) RW
0 1 : TB2 is selected
TA1TGH 1 0 : TA0 is selected
RW
1 1 : TA2 is selected

TA2TGL Timer A2 event/trigger b3 b2

0 0 : Input on TA2IN is selected (Note) RW
select bit
0 1 : TB2 is selected
TA2TGH 1 0 : TA1 is selected
RW
1 1 : TA3 is selected
Timer A3 event/trigger b5 b4
TA3TGL RW
select bit 0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 is selected
TA3TGH 1 0 : TA2 is selected RW
1 1 : TA4 is selected
Timer A4 event/trigger b7 b6
TA4TGL 0 0 : Input on TA4IN is selected (Note) RW
select bit
0 1 : TB2 is selected
TA4TGH 1 0 : TA3 is selected
RW
1 1 : TA0 is selected

Note : Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
CPSRF 038116 0XXXXXXX2

Bit symbol Bit name Function RW

Nothing is assigned.

AAAAAAAAAAAAAAA
When write, set to “0”. When read, their contents are
(b6-b0) indeterminate.

AAAAAAAAAAAAAAA
CPSR Clock prescaler reset flag Setting this bit to “1” initializes the
prescaler for the timekeeping clock. ( RW
When read, its content is “0”.)

Figure 1.14.6. ONSF Register, TRGSR Register, and CPSRF Register

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1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.14.1). Figure 1.14.7
shows TAiMR register in timer mode.

Table 1.14.1. Specifications in Timer Mode

Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio 1/(n+1) n: set value of TAiMR register (i= 0 to 4) 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TAiIN pin function I/O port or gate input
TAiOUT pin function I/O port or pulse output
Read from timer Count value can be read by reading TAi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.

Timer Ai mode register (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 0 0 TA0MR to TA4MR 039616 to 039A16 0016

Bit symbol Bit name Function RW

TMOD0 Operation mode b1 b0 RW
select bit 0 0 : Timer mode
TMOD1 RW
MR0 Pulse output function 0 : Pulse is not output
select bit (TAiOUT pin is a normal port pin)
RW
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1 Gate function select bit b4 b3
0 0 : Gate function not available
01:
} (TAiIN pin functions as I/O port) RW
1 0 : Counts while input on the TAiIN pin
MR2 is low (Note 2)
1 1 : Counts while input on the TAiIN pin RW
is high (Note 2)
MR3 Must be set to “0” in timer mode RW
b7 b6
TCK0 Count source select bit
0 0 : f1 or f2 RW
0 1 : f8
TCK1 1 0 : f32 RW
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).

Figure 1.14.7. Timer Ai Mode Register in Timer Mode

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2. Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 1.14.2 lists specifica-
tions in event counter mode (when not processing two-phase pulse signal). Table 1.14.3 lists specifica-
tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 1.14.8 shows TAiMR register in event counter mode (when not processing two-phase pulse sig-
nal). Figure 1.14.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-
phase pulse signal with the timers A2, A3 and A4).

Table 1.14.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item Specification
Count source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
Count operation • Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function I/O port or count source input
TAiOUT pin function I/O port, pulse output, or up/down-count select input
Read from timer Count value can be read by reading TAi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.

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Timer Ai mode register (i=0 to 4)

(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 0 1 TA0MR to TA4MR 039616 to 039A16 0016

Bit symbol Bit name Function RW

R W
TMOD0 Operation mode select bit b1 b0 RW
TMOD1 0 1 : Event counter mode (Note 1) RW
MR0 Pulse output function 0 : Pulse is not output
select bit (TAiOUT pin functions as I/O port)
RW
1 : Pulse is output (Note 2)
(TAiOUT pin functions as pulse output pin)
MR1 Count polarity 0 : Counts external signal's falling edge RW
select bit (Note 3) 1 : Counts external signal's rising edge
MR2 Up/down switching 0 : UDF register
cause select bit 1 : Input signal to TAiOUT pin (Note 4) RW

MR3 Must be set to “0” in event counter mode RW

TCK0 Count operation type 0 : Reload type
select bit 1 : Free-run type RW

TCK1 Can be “0” or “1” when not using two-phase pulse signal
RW
processing
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: TA0OUT pin is N-channel open drain output.
Note 3: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).

Figure 1.14.8. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)

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Table 1.14.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item Specification
Count source • Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
Count operation • Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio 1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16
Count start condition Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read by reading timer A2, A3 or A4 register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note) • Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.

TAjOUT

TAjIN
(j=2,3) Up- Up- Up- Down- Down- Down-
count count count count count count

• Multiply-by-4 processing operation (timer A3 and timer A4)

If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.

TAkOUT

Count up all edges Count down all edges

TAkIN
(k=3,4)

Count up all edges Count down all edges

• Counter initialization by Z-phase input (timer A3)

The timer count value is initialized to 0 by Z-phase input.
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.

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Timer Ai mode register (i=2 to 4)

(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TA2MR to TA4MR 039816 to 039A16 0016
0 1 0 0 0 1

Bit name Function RW

TMOD0 Operation mode select bit b1 b0
RW
TMOD1 0 1 : Event counter mode
RW
MR0 To use two-phase pulse signal processing, set this bit to “0”. RW

MR1 RW
To use two-phase pulse signal processing, set this bit to “0”.

MR2 To use two-phase pulse signal processing, set this bit to “1”. RW

MR3 To use two-phase pulse signal processing, set this bit to “0”. RW
TCK0 Count operation type 0 : Reload type
select bit RW
1 : Free-run type

TCK1 Two-phase pulse signal

processing operation 0 : Normal processing operation RW
select bit (Note 1)(Note 2) 1 : Multiply-by-4 processing operation

Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiTGH and TAiTGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).

Figure 1.14.9. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)

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• Counter Initialization by Two-Phase Pulse Signal Processing

This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.

This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
_______
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.

Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).

Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.

The counter is initialized at the next count timing after recognizing Z-phase input. Figure 1.14.10
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.

If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.

TA3OUT
(A phase)

TA3IN
(B phase)

Count source

INT2 (Note)
(Z phase)
Input equal to or greater than one clock cycle
of count source
Timer A3 m m+1 1 2 3 4 5

Note: This timing diagram is for the case where the POL bit of INT2IC register = “1” (= rising edge).

Figure 1.14.10. Two-phase Pulse (A phase and B phase) and the Z Phase

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3. One-shot Timer Mode

In one-shot timer mode, the timer is activated only once by one trigger. (See Table 1.14.4.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 1.14.12 shows the
TAiMR register in one-shot timer mode.

Table 1.14.4. Specifications in One-shot Timer Mode

Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count
• When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : set value of TAi register 000016 to FFFF16
However, the counter does not work if the divide-by-n value is set to 000016.
Count start condition TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
Count stop condition • When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
Interrupt request generation timing When the counter reaches “000016”
TAiIN pin function I/O port or trigger input
TAiOUT pin function I/O port or pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function • Pulse output function
The timer outputs a low when not counting and a high when counting.

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Timer Ai mode register (i=0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 1 0 TA0MR to TA4MR 39616 to 039A16 0016

Bit symbol Bit name Function RW

TMOD0 Operation mode select bit b1 b0 RW
1 0 : One-shot timer mode
TMOD1 RW
MR0 Pulse output function 0 : Pulse is not output
select bit (TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 1) RW
(TAiOUT pin functions as a pulse output pin)
MR1 External trigger select 0 : Falling edge of input signal to TAiIN pin (Note 3)
bit (Note 2) 1 : Rising edge of input signal to TAiIN pin (Note 3) RW

MR2 Trigger select bit 0 : TAiOS bit is enabled

1 : Selected by TAiTGH to TAiTGL bits RW

MR3 Must be set to “0” in one-shot timer mode RW

TCK0 Count source select bit b7 b6

RW
0 0 : f1 or f2
0 1 : f8
TCK1 1 0 : f32 RW
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).

Figure 1.14.12. TAiMR Register in One-shot Timer Mode

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4. Pulse Width Modulation (PWM) Mode

In PWM mode, the timer outputs pulses of a given width in succession (see Table 1.14.5). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 1.14.13 shows
TAiMR register in pulse width modulation mode. Figures 1.14.14 and 1.14.15 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.

Table 1.14.5. Specifications in PWM Mode

Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting
16-bit PWM • High level width n / fj n : set value of TAi register (i=o to 4)
• Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32)
8-bit PWM • High level width n x (m+1) / fj n : set value of TAiMR register high-order address
• Cycle time (28-1) x (m+1) / fj m : set value of TAiMR register low-order address
Count start condition • TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
Count stop condition TAiS bit is set to “0” (= stop counting)
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer An indeterminate value is read by reading TAi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)

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Timer Ai mode register (i= 0 to 4)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 1 1 TA0MR to TA4MR 039616 to 039A16 0016

Bit symbol Bit name Function RW

TMOD0 Operation mode
b1 b0 RW
TMOD1 select bit 1 1 : PWM mode
(Note 1) RW
MR0 Must be set to “1” in PWM mode RW
MR1 External trigger select 0: Falling edge of input signal to TAiIN pin(Note 3)
bit (Note 2) RW
1: Rising edge of input signal to TAiIN pin(Note 3)

MR2 Trigger select bit 0 : Write “1” to TAiS bit in the TASF register RW
1 : Selected by TAiTGH to TAiTGL bits

MR3 16/8-bit PWM mode 0: Functions as a 16-bit pulse width modulator RW

select bit 1: Functions as an 8-bit pulse width modulator
b7 b6

TCK0 Count source select bit 0 0 : f1 or f2 RW

0 1 : f8
1 0 : f32
TCK1 RW
1 1 : fC32

Note 1: TA0OUT pin is N-channel open drain output.

Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).

Figure 1.14.13. TAiMR Register in PWM Mode

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16
1 / fi X (2 – 1)

Count source

“H”
Input signal to
TAiIN pin “L”
Trigger is not generated by this signal

1 / fj X n
PWM pulse output “H”
from TAiOUT pin “L”

IR bit of TAiIC “1”

register
“0”

fj : Frequency of count source

(f1, f2, f8, f32, fC32)
Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 4
Note 1: n = 000016 to FFFE16.
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiTGH and TAiTGL bits of
ONSF or TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and
the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).

Figure 1.14.14. Example of 16-bit Pulse Width Modulator Operation

1 / fj X (m + 1) X (2 8 – 1)

Count source (Note1)

Input signal to “H”

TAiIN pin

AAAAAAAAAAAAAAAAA
“L”

1 / fj X (m + 1)

AAAAAAAAAAAAAAAAA
Underflow signal of “H”
8-bit prescaler (Note2) “L”

1 / fj X (m + 1) X n

PWM pulse output “H”

from TAiOUT pin “L”

“1”
IR bit of TAiIC
register “0”

fj : Frequency of count source

(f1, f2, f8, f32, fC32) Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 4

Note 1: The 8-bit prescaler counts the count source.

Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiTGH and TAiTGL bits of ONSF or
TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).

Figure 1.14.15. Example of 8-bit Pulse Width Modulator Operation

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Timers (Timer B) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B
Figure 1.15.1 shows a block diagram of the timer B. Figures 1.15.2 and 1.15.3 show registers related to the
timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.

Data bus high-order bits

Data bus low-order bits

Clock source selection
Low-order 8 bits High-order 8 bits
f1 or f2 • Timer
• Pulse period measuremnet, Reload register
f8 pulse width measurement
f32 Clock selection

fC32 • Event counter Counter

Polarity switching, TABSR register

TBiIN
edge pulse TBSR register
(i = 0 to 5)

Counter reset circuit

Can be selected in only
event counter mode
TBi Address TBj
TBj overflow (Note) Timer B0 039116 - 039016 Timer B2
(j = i – 1, except j = 2 if i = 0, j = 5 if i = 3) Timer B1 039316 - 039216 Timer B0
Timer B2 039516 - 039416 Timer B1
Timer B3 035116 - 035016 Timer B5
Note: Overflow or underflow. Timer B4 035316 - 035216 Timer B3
Timer B5 035516 - 035416 Timer B4

Figure 1.15.1. Timer B Block Diagram

Timer Bi mode register (i=0 to 5)

Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 035B16 to 035D16 00XX00002

Bit symbol Bit name Function RW

TMOD0 Operation mode select bit
b1 b0
0 0 : Timer mode RW
0 1 : Event counter mode
TMOD1 1 0 : Pulse period measurement mode,
pulse width measurement mode RW
1 1 : Must not be set
MR0 RW
Function varies with each operation
MR1 mode RW
MR2 RW
(Note 1)

(Note 2)
MR3 RO
TCK0 Count source select bit Function varies with each operation RW
TCK1 mode RW
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.

Figure 1.15.2. TB0MR to TB5MR Registers

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Timer Bi register (i=0 to 5)(Note 1) Symbol Address After reset

TB0 039116, 039016 Indeterminate
(b15) (b8) TB1 039316, 039216 Indeterminate
b7 b0 b7 b0
TB2 039516, 039416 Indeterminate
TB3 035116, 035016 Indeterminate
TB4 035316, 035216 Indeterminate
TB5 035516, 035416 Indeterminate
Mode Function Setting range RW
Timer mode Divide the count source by n + 1 000016 to FFFF16
RW
where n = set value
Event counter Divide the count source by n + 1 000016 to FFFF16 RW
mode where n = set value (Note 2)
Pulse period Measures a pulse period or width
modulation mode,
RO
Pulse width
modulation mode
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TABSR 038016 0016

AAAAAAAAAAAAAAA
Bit symbol

AAAAAAAAAAAAAAA
TA0S
Bit name
Timer A0 count start flag
Function
0 : Stops counting
RW
RW

AAAAAAAAAAAAAAA
TA1S Timer A1 count start flag 1 : Starts counting RW
TA2S Timer A2 count start flag RW

AAAAAAAAAAAAAAA
TA3S Timer A3 count start flag RW

AAAAAAAAAAAAAAA
TA4S Timer A4 count start flag RW
TB0S Timer B0 count start flag RW

AAAAAAAAAAAAAAA
TB1S Timer B1 count start flag RW
TB2S Timer B2 count start flag RW

Timer B3, B4, B5 count start flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TBSR 034016 000XXXXX2

AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Bit symbol Bit name Function
Nothing is assigned. When write, set to “0”. When read, their
RW

AAAAAAAAAAAAAAA
(b4-b0) contents are indeterminate.
TB3S Timer B3 count start flag 0 : Stops counting RW

AAAAAAAAAAAAAAA
1 : Starts counting
TB4S Timer B4 count start flag RW
TB5S Timer B5 count start flag RW

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
CPSRF 038116 0XXXXXXX2

Bit symbol Bit name Function RW

AAAAAAAAAAAAAAA
Nothing is assigned. When write, set to “0”. When read, their
(b6-b0) contents are indeterminate.

AAAAAAAAAAAAAAA
CPSR Clock prescaler reset flag Setting this bit to “1” initializes the
prescaler for the timekeeping clock. RW
(When read, the value of this bit is “0”.)

Figure 1.15.3. TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register

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1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.15.1). Figure 1.15.4
shows TBiMR register in timer mode.

Table 1.15.1. Specifications in Timer Mode

Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBiMR register (i= 0 to 5) 000016 to FFFF16
Count start condition Set TBiS bit(Note) to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function I/O port
Read from timer Count value can be read by reading TBi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S
bits are assigned to the TBSR register bit 5 to bit 7.

AAA
Timer Bi mode register (i= 0 to 5)
Symbol Address After reset

AAA
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16 00XX00002
0 0
TB3MR to TB5MR 035B16 to 035D16 00XX00002

Bit symbol Bit name Function RW

TMOD0 Operation mode select bit
b1 b0
RW
0 0 : Timer mode
TMOD1 RW
MR0 Has no effect in timer mode RW
MR1 Can be set to “0” or “1” RW
MR2 TB0MR, TB3MR registers
Must be set to “0” in timer mode RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3 When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate. RO

b7 b6
TCK0 Count source select bit
0 0 : f1 or f2 RW
0 1 : f8
TCK1 1 0 : f32 RW
1 1 : fC32

Figure 1.15.4. TBiMR Register in Timer Mode

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2. Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 1.15.2) . Figure 1.15.5 shows TBiMR register in event counter mode.
Table 1.15.2. Specifications in Event Counter Mode
Item Specification
Count source • External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16
Count start condition 1
Set TBiS bit to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function Count source input
Read from timer Count value can be read by reading TBi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.

AA
Timer Bi mode register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 1 TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 035B16 to 035D16 00XX00002

Bit symbol Bit name Function RW

TMOD0 Operation mode select bit b1 b0 RW
0 1 : Event counter mode
TMOD1 RW
b3 b2
MR0 Count polarity select
bit (Note 1) 0 0 : Counts external signal's
RW
falling edges
0 1 : Counts external signal's
rising edges
MR1 1 0 : Counts external signal's
falling and rising edges RW
1 1 : Must not be set
TB0MR, TB3MR registers
MR2 RW
Must be set to “0” in timer mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
MR3 When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate. RO

TCK0 Has no effect in event counter mode.

Can be set to “0” or “1”. RW

TCK1 Event clock select 0 : Input from TBiIN pin (Note 2)

1 : TBj overflow or underflow
RW
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).

Figure 1.15.5. TBiMR Register in Event Counter Mode

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3. Pulse Period and Pulse Width Measurement Mode

In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 1.15.3). Figure 1.15.6 shows TBiMR register in pulse period and pulse width
measurement mode. Figure 1.15.7 shows the operation timing when measuring a pulse period. Figure
1.15.8 shows the operation timing when measuring a pulse width.
Table 1.15.3. Specifications in Pulse Period and Pulse Width Measurement Mode
Item Specification
Count source f1, f2, f8, f32, fC32
Count operation • Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
Count start condition Set TBiS (i=0 to 5) bit3 to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input1
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function Measurement pulse input
Read from timer Contents of the reload register (measurement result) can be read by reading TBi register2
Write to timer Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned
to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
1 0 TB0MR to TB2MR 039B16 to 039D16 00XX00002
TB3MR to TB5MR 035B16 to 035D16 00XX00002

Bit symbol Bit name Function RW

b1 b0
TMOD0 Operation mode RW
1 0 : Pulse period / pulse width
select bit measurement mode
TMOD1 RW
b3 b2
MR0 Measurement mode
0 0 : Pulse period measurement
select bit
(Measurement between a falling edge and the
next falling edge of measured pulse)
RW
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
MR1 rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
RW
a rising edge and the next falling edge)
1 1 : Must not be set.
MR2 TB0MR and TB3MR registers RW
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
MR3 Timer Bi overflow 0 : Timer did not overflow
flag ( Note) 1 : Timer has overflowed RO
b7 b6
TCK0 Count source RW
0 0 : f1 or f2
select bit
0 1 : f8
TCK1 1 0 : f32
1 1 : fC32 RW

Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register's bit 5 to bit 7.

Figure 1.15.6. TBiMR Register in Pulse Period and Pulse Width Measurement Mode

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Count source

“H”
Measurement pulse
“L”
Transfer Transfer
(indeterminate value) (measured value)

Reload register counter

transfer timing
(Note 1) (Note 1) (Note 2)

Timing at which counter

reaches “000016”

“1”
TBiS bit
“0”

TBiIC register's “1”

IR bit “0”

Set to “0” upon accepting an interrupt request or by writing in

“1” program
TBiMR register's
MR3 bit “0”
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “002” (measure the interval
from falling edge to falling edge of the measurement pulse).

Figure 1.15.7. Operation timing when measuring a pulse period

Count source

“H”
Measurement pulse
“L”
Transfer Transfer Transfer Transfer
(indeterminate (measured value) (measured (measured value)
value) value)
Reload register counter
transfer timing
(Note 1) (Note 1) (Note 1) (Note 1) (Note 2)
Timing at which counter
reaches “000016”

TBiS bit “1”

“0”

“1”
TBiIC register's
IR bit “0”

Set to “0” upon accepting an interrupt request or by

“1” writing in program
TBiMR register's “0”
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).

Figure 1.15.8. Operation timing when measuring a pulse width

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Three-phase Motor Control Timer Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-phase Motor Control Timer Function

Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 1.16.1 lists the
specifications of the three-phase motor control timer function. Figure 1.16.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figure 1.16.2 to Figure
1.16.7.
Table 1.16.1. Three-phase Motor Control Timer FunctionS Specifications
Item ___
Specification
___ ___
Three-phase waveform output pin Six pins (U,_______
U, V, V, W, W)
Forced cutoff input1 Input “L” to NMI pin
Used Timers Timer A4, A1, A2 (used ___
in the one-shot timer mode)
Timer A4: U- and ___ U-phase waveform control
Timer A1: V- and V-phase
___
waveform control
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead timer timer (3 eight-bit timer and shared reload register)
Dead time control
Output waveform Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase
level respectively
Carrier wave cycle Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting
the INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time Count source x p, or no dead time
active disable function p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Active level Eable to select “H” or “L”
Positive and negative-phase concurrent Positive and negative-phases concurrent active disable
function
Positive and negative-phases concurrent active detect func
tion
Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle
basis through 15 times carrier wave cycle-to-cycle basis
Notes: _______
1. Forced cutoff with NMI input _______
is effective when the IVPCR1 bit of TB2SC register _______
is set to “1” (three-phase
output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin when the IVPCR1 bit
is “1”, the related pins go to a high-impedance state regardless of which functions of those pins are being
used.
Related pins P72/CLK2/TA1OUT/V
_________ _________ ___
P73/CTS2/RTS2/TA1IN/V
P74/TA2OUT/W
____
P75/TA2IN/W
P80/TA4OUT/U
___
P81/TA4IN/U

127
128

Three-phase Motor Control Timer Functions

Figure 1.16.1. Three-phase Motor Control Timer Functions Block Diagram
ICTB2 register
INV13 n = 1 to 15

INV01 Interrupt occurrence set circuit

INV00 INV11
1 INV03 D Q
Timer B2 underflow ICTB2 counter RESET R
Timer B2
n = 1 to 15 interrupt request bit NMI
0 INV05
0 INV12
Signal to be Reload register INV14
written to f1 1/2 n = 1 to 255 INV04
timer B2 1
INV07
INV10 Trigger Reverse U
Timer B2 D Q
Trigger Dead time timer control
T
(Timer mode) INV06 n = 1 to 255

U phase output
Timer Ai(i = 1, 2, 4) start trigger signal control circuit
DU1 DU0
Transfer trigger
(Note 1) bit bit
Timer A4 reload control signal U phase output signal
D Q D
Q
TA4 register Reload TA41 register T T
Trigger
Timer A4 counter Three-phase output
Timer A4
(One-shot timer mode) shift register
one-shot pulse DUB1 DUB0 (U phase)
INV11 bit bit
T Q
U phase output signal
Set to 0 when TA4S bit = 0 D Q D Reverse
Q D Q control
U
T T
T

Reverse
Trigger
D Q control V
Trigger Dead time timer

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

T
INV06 n = 1 to 255
V phase output signal
TA1 register Reload TA11 register
V phase output
Trigger V phase output Reverse
Timer A 1 counter control circuit
signal D Q control V
(One-shot timer mode)
T
INV11
T Q Trigger Reverse
D Q control
W
Trigger Dead time timer
Set to 0 when TA1S bit = 0 T
INV06 n = 1 to 255

M16C / 62P Group

W phase output signal
TA2 register Reload TA21 register

Renesas microcomputers
W phase output
Trigger
control circuit Wphase output signal Reverse
Timer A 2 counter W
D Q control
(One-shot timer mode) T
INV11
T Q Diagram for switching to P80, P81 and P72 - P75 is not shown.
Set to 0 when TA2S bit = 0

Note : If the INV06 bit = 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.
 Renesas microcomputers
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Three-phase Motor Control Timer Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-phase PWM control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
INVC0 034816 0016

Bit symbol Bit name Description RW

Effective interrupt output 0: ICTB2 counter incremented by 1 at
INV00 polarity select bit odd-numbered occurrences of a timer
B2 underflow
1: ICTB2 counter incremented by 1 at RW
even-numbered occurrences of a timer
B2 underflow
(Note 3)
Effective interrupt output 0: ICTB2 counter incremented by 1 at a
INV01 specification bit timer B2 underflow RW
(Note 2, Note 3) 1: Selected by INV00 bit
Mode select bit (Note 4) 0: Three-phase motor control timer
INV02 function unused (Note 5) RW
1: Three-phase motor control timer
function
Output control bit (Note 6) 0: Three-phase motor control timer output
INV03 disabled (Note 5)
1: Three-phase motor control timer output
RW
enabled
Positive and negative 0: Simultaneous active output enabled
INV04 phases concurrent output 1: Simultaneous active output disabled RW
disable bit
Positive and negative 0: Not detected yet
INV05 phases concurrent output 1: Already detected (Note 7) RW
detect flag
INV06 Modulation mode select 0: Triangular wave modulation mode (Note 9)
bit (Note 8) 1: Sawtooth wave modulation mode RW

INV07 Software trigger select bit Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated. RW
The value of this bit when read is “0”.

Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that INV00 to INV02,
INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
Note 3: Effective when the INV11 bit is “1” (three-phase mode 1). If INV11 is “0” (three-phase mode 0), the ICTB2 counter is
incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
Note 4: Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
Note 5: All of the U, U, V, V, W and W pins are placed in the high-impedance state by setting the INV02 bit to 1 (three-phase
motor control timer function) and setting the INV03 bit to “0” (three-phase motor control timer output disable).
Note 6: The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active simultaneously while INV04 bit is “1”
• When set to “0” in a program
• When input on the NMI pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when NMI input is
“L”.)
Note 7: Can only be set by writing “0” in a program, and cannot be set to “1”.
Note 8: The effects of the INV06 bit are described in the table below.

Item INV06=0 INV06=1

Mode Triangular wave modulation mode Sawtooth wave modulation mode
Timing at which transferred from IDB0 to Transferred only once synchronously Transferred every transfer trigger
IDB1 registers to three-phase output shift with the transfer trigger after writing to
register the IDB0 to IDB1 registers
Timing at which dead time timer trigger is Synchronous with the falling edge of Synchronous with the transfer
generated when INV16 bit is “0” timer A1, A2, or A4 one-shot pulse trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
INV13 bit Effective when INV11 is “1” and INV06 Has no effect
is “0”
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
Note 9: If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2
reloaded by a timer B2 underflow).

Figure 1.16.2. INVC0 Register

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Three-phase PWM control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 INVC1 034916 0016

Bit symbol Bit name Description RW

Timer A1, A2, A4 start 0: Timer B2 underflow
INV10 trigger signal select bit 1: Timer B2 underflow and write to the RW
TB2 register

Timer A1-1, A2-1, A4-1 0: Three-phase mode 0

INV11 control bit (Note 3) RW
(Note 2) 1: Three-phase mode 1

INV12 Dead time timer count 0 : f1 or f2

source select bit 1 : f1 divided by 2 or f2 divided by 2 RW

Carrier wave detect flag 0: Timer A output at even-numbered occ-

(Note 4) urrences (TA11, TA21, TA41 register
INV13 value counted) RO
1: Timer A output at odd-numbered occ-
urrences (TA1, TA2, TA4 register
value counted)
0 : Output waveform “L” active
INV14 Output polarity control bit RW
1 : Output waveform “H” active
INV15 Dead time invalid bit 0: Dead time timer enabled
1: Dead time timer disabled RW

Dead time timer trigger 0: Falling edge of timer A4, A1 or A2

INV16 select bit one-shot pulse
1: Rising edge of three-phase output shift RW
register (U, V or W phase) output
(Note 5)

Reserved bit This bit should be set to “0”

RW
(b7)

Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that this
register can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: The effects of the INV11 bit are described in the table below.
Item INV11=0 INV11=1
Mode Three-phase mode 0 Three-phase mode 1
TA11, TA21, TA41 registers Not used Used
INV00 bit, INV01 bit Has no effect. ICTB2 counted every time Effect
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
INV13 bit Has no effect Effective when INV11 bit is “1” and
INV06 bit is “0”
Note 3: If the INV06 bit is “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the
INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
Note 4: The INV13 bit is effective only when the INV06 bit is “0” (triangular wave modulation mode) and the INV11 bit
is “1” (three-phase mode 1).
Note 5: If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge
of three-phase output shift register output)
• The INV15 bit is “0” (dead time timer enabled)
• When the INV03 bit is set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U,
V, or W, j: 0 to 1) have always different values (the positive-phase and negative-phase always output
different levels during the period other than dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered

Figure 1.16.3. INVC1 Register

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Three-phase output buffer register i (i=0, 1) (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
IDB0 034A16 0016
IDB1 034B16 0016
Bit Symbol Bit name Function RW

DUi U phase output buffer i Write the output level RW

0: Active level
DUBi U phase output buffer i 1: Inactive level RW

DVi V phase output buffer i When read, these bits show the RW
three-phase output shift register
DVBi V phase output buffer i value. RW
DWi W phase output buffer i RW
DWBi W phase output buffer i RW
Nothing is assigned. When write, set to “0”. When read, its
(b7-b6) content is “0”.
Note: The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The
value written to the IDB0 register after a transfer trigger generates the output signal of each phase, and the
next value written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents
the output signal of each phase.

Dead time timer (Note 1, Note 2)

b7 b0
Symbol Address After reset
DTT 034C16 Indeterminate

Function Setting range RW

Assuming the set value = n, upon a start trigger the 1 to 255

timer starts counting the count source selected by
the INV12 bit and stops after counting it n times. The WO
positive or negative phase whichever is going from
an inactive to an active level changes at the same
time the dead time timer stops.

Note 1: Use MOV instruction to write to this register.

Note 2: Effective when the INV15 bit is “0” (dead time timer enable). If the INV15 bit is “1”, the dead time timer is
disabled and has no effect.

Figure 1.16.4. IDB0 Register, IDB1Register, and DTT Register

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Timer B2 interrupt occurrences frequency set counter

b3 b0
Symbol Address After reset
ICTB2 034D16 Indeterminate

Function Setting range RW

If the INV01 bit is “0” (ICTB2 counter counted every

1 to 15
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow.
If the INV01 bit is “1” (ICTB2 counter count timing WO
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit. (Note)
Nothing is assigned. When write, set to “0”. When read, its content is
indeterminate.

Note : Use MOV instruction to write to this register.

If the INV01 bit = “1”, make sure the TB2S bit also = “0” (timer B2 count stopped) when writing to this register.
If the INV01 bit = “0”, although this register can be written even when the TB2S bit = “1” (timer B2 count start),
do not write synchronously with a timer B2 underflow.

Timer Ai, Ai-1 register (i=1, 2, 4) (Note 1, Note 2, Note 3, Note 4, Note 5, Note 6)
Symbol Address After reset
TA1 038916-038816 Indeterminate
TA2 038B16-038A16 Indeterminate
(b15) (b8) b0
b7 b0 b7 TA4 038F16-038E16 Indeterminate
TA11 034316-034216 Indeterminate
TA21 034516-034416 Indeterminate
TA41 034716-034616 Indeterminate
Function Setting range RW
Assuming the set value = n, upon a start trigger the timer 000016 to FFFF16
starts counting the count source and stops after counting WO
it n times. The positive and negative phases change at
the same time timer A, A2 or A4 stops.

Note 1: The register must be accessed in 16 bit units.

Note 2: When the timer Ai register is set to “000016”, the counter does not operate and a timer Ai interrupt does
not occur.
Note 3: Use MOV instruction to write to these registers.
Note 4: If the INV15 bit is “0” (dead time timer enable), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
Note 5: If the INV11 bit is “0” (three-phase mode 0), the TAi register value is transferred to the reload register by
a timer Ai (i = 1, 2 or 4) start trigger.
If the INV11 bit is “1” (three-phase mode 1), the TAi1 register value is transferred to the reload register
by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the
next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the
reload register alternately.
Note 6: Do not write to these registers synchronously with a timer B2 underflow.
Note 7: Write to the TAi1 register as follows:
(1) Write a value to the TAi1 register.
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.

Timer B2 special mode register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
TB2SC 039E16 XXXXXX002

Bit symbol Bit name Function RW

PWCOM Timer B2 reload timing 0 : Timer B2 underflow
switching bit 1 : Timer A output at odd-numbered RW
occurrences (Note 2)

IVPCR1 Three phase output port 0 : Three-phase output forcible cutoff

NMI control bit 1 by NMI input (high impedance)
(Note 3) disabled RW
1 : Three-phase output forcible cutoff
by NMI input (high impedance)
enabled
Nothing is assigned.
(b7-b2) When write, set to “0”. When read, its content is “0”.

Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: If the INV11 bit is “0” (three-phase mode 0) or the INV06 bit is “1” (triangular wave modulation mode), set
this bit to “0” (timer B2 underflow).
Note 3: Related pins are U(P80), U(P81), V(P72), V(P73), W(P74) and W(P75). If a low-level signal is applied to
the NMI pin when the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of which
functions of those pins are being used. After forced interrupt (cutoff), input “H” to the NMI pin and set
IVPCR1 bit to “0”: this forced cutoff will be reset.

Figure 1.16.5. ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2SC Registers

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Timer B2 register (Note ) Symbol Address After reset

(b15) (b8) b0
b7 b0 b7 TB2 039516-039416 Indeterminate

Function Setting range RW

Divide the count source by n + 1 where n = set value. 000016 to FFFF16
Timer A1, A2 and A4 are started at every occurrence of RW
underflow.
Note : The register must be accessed in 16 bit units.

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
TRGSR 038316 0016

Bit symbol Bit name Function RW

TA1TGL Timer A1 event/trigger To use the V-phase output control RW
select bit circuit, set these bits to “012”(TB2
underflow).
TA1TGH RW

TA2TGL Timer A2 event/trigger To use the W-phase output control

select bit RW
circuit, set these bits to “012”(TB2
underflow).
TA2TGH RW

Timer A3 event/trigger b5 b4
TA3TGL
0 0 : Input on TA3IN is selected (Note 1) RW
select bit
0 1 : TB2 overflow is selected (Note 2)
TA3TGH 1 0 : TA2 overflow is selected (Note 2)
RW
1 1 : TA4 overflow is selected (Note 2)

TA4TGL Timer A4 event/trigger To use the U-phase output control RW

select bit circuit, set these bits to “012”(TB2
underflow).
TA4TGH
RW

Note 1: Set the corresponding port direction bit to “0” (input mode).
Note 2: Overflow or underflow.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
TABSR 038016 0016

Bit symbol Bit name Function RW

TA0S Timer A0 count start flag 0 : Stops counting RW
TA1S Timer A1 count start flag 1 : Starts counting
RW
TA2S Timer A2 count start flag RW

AAAAAAAAAAAAAAAA
TA3S Timer A3 count start flag RW
TA4S Timer A4 count start flag RW

AAAAAAAAAAAAAAAA
TB0S

AAAAAAAAAAAAAAAA
TB1S
TB2S
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
RW
RW
RW

Figure 1.16.6. TB2 Register, TRGSR Register, and TABSR Register

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Timer Ai mode register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
TA1MR 039716 0016
0 1 1 0 TA2MR 039816 0016
TA4MR 039A16 0016
Bit symbol Bit name Function RW
TMOD0 Operation mode Must set to “102” (one-shot timer mode) for RW
select bit the three-phase motor control timer function RW
TMOD1
MR0 Pulse output function Must set to “0” for the three-phase motor
select bit control timer function RW

MR1 External trigger select Has no effect for the three-phase motor
control timer function RW
bit
MR2 Trigger select bit Must set to “1” (selected by TRGSR register)
RW
for the three-phase motor control timer
function
MR3 Must set to “0” for the three-phase motor control timer function RW
TCK0 b7 b6
Count source select bit RW
0 0 : f1 or f2
0 1 : f8
TCK1 1 0 : f32 RW
1 1 : fC32

AAA
Timer B2 mode register

A
AA
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 0 0 TB2MR 039D16 00XX00002

Bit symbol Bit name Function RW

TMOD0 Operation mode select bit Set to “002” (timer mode) for the three- RW
TMOD1 phase motor control timer function RW
MR0 Has no effect for the three-phase motor control timer function. RW
MR1 When write, set to “0”. When read, its content is indeterminate. RW

MR2 Must set to “0” for the three-phase motor control timer function RW

MR3 When write in three-phase motor control timer function, write “0”.
RO
When read, its content is indeterminate.

Count source select bit b7 b6

TCK0 RW
0 0 : f1 or f2
0 1 : f8
TCK1 1 0 : f32
1 1 : fC32 RW

Figure 1.16.7. TA1MR, TA2MR, TA4MR, and TB2MR Registers

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Three-phase Motor Control Timer Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used
__ ___ ___
to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated
dead time timer. Figure 1.16.8 shows the example of triangular modulation waveform and Figure 1.16.9
shows the example of sawtooth modulation waveform.

Carrier wave

Signal wave

TB2S bit of the

TABSR register

Timer B2

Start trigger signal

for timer A4*

Timer A4 m m n n p p
one-shot pulse*
Rewriting IDB0, IDB1 registers

U phase
output signal * Transfer to three-phase
output shift register
U phase
output signal *

U phase
INV14 = 0
(“L” active)
U phase

Dead time
U phase
INV14 = 1
(“H” active)
Dead time

U phase

INV13
(INV11=1(three-phase
mode 1))

* Internal signals. See the block diagram of the three-phase motor control timer function.

Shown here is a typical waveform for the case where INVC0 = 00XX11XX2 (X = set as suitable for the system) and INVC1 = 010XXXX02.
An example for changing PWM outputs is shown below.
(1)When INV11=1(three-phase mode 1) (2)When INV11=0(three-phase mode 0)
· INV01=0, ICTB2=216(timer B2 interrupt is generated at every 2’th · INV01=0, ICTB2=116(timer B2 interrupt is generated at every
occurrence of a timer B2 underflow), or INV01=1, INV00=1, occurrence of a timer B2 underflow)
ICTB2=116(timer B2 interrupt is generated at even-numbered · Initial timer value: TA4 = m. The TA4 register is modified each time
occurrences of a timer B2 underflow). a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n.
· Initial timer value: TA41=m, TA4=m. The TA4 and TA41 registers Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p.
are modified every time a timer B2 interrupt occurs. First time, · Initial values of IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0,
TA41= n, TA4 = n. Second time, TA41 = p, TA4 = p. DUB1=1.The register values are changed to DU0 = 1, DUB0 = 0, DU1=
· Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0, 1 and DUB1 = 0 the sixth time a timer B2 interrupt occurs.
DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1,
DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2
interrupt occurs.
The value written to the TA4 register and TA41 register are inverted at odd-numbered timer A outputs.

Figure 1.16.8. Triangular Wave Modulation Operation

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Carrier wave: sawtooth waveform

Carrier wave

Signal wave

Timer B2

Start trigger signal

for timer A4*

Timer A4
one-shot pulse*

Rewriting IDB0, IDB1 registers

Transfer to three-phase
output shift register
U phase
output signal *

U phase
output signal *

U phase
INV14 = 0
(“L” active) Dead time

U phase

U phase
INV14 = 1
(“H” active) Dead time

U phase

* Internal signals. See the block diagram of the three-phase motor control timer function.

Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the
system) and INVC1 = 010XXX002. An example for changing PWM outputs is shown below.
• ICTB2=n (timer B2 interrupt is generated at every n’th occurrence of a timer B2 underflow)
• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are
changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.

Figure 1.16.9. Sawtooth Wave Modulation Operation

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Serial I/O

Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.

UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 1.17.1 shows the block diagram of UARTi. Figures 1.17.2 shows the block diagram of the UARTi
transmit/receive.

UARTi has the following modes:

• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
• Special mode 4 (SIM mode) : UART2

Figures 1.17.3 to 1.17.8 show the UARTi-related registers.

Refer to tables listing each mode for register setting.

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Serial I/O

PCLK1=0
1/2 f2SIO
f1SIO f1SIO or f2SIO
Main clock, PLL clock, or ring oscillator clock
PCLK1=1
1/8 f8SIO
1/4 f32SIO
(UART0) TxD
RxD polarity polarity
RxD0 reversing circuit reversing TxD0
circuit
Clock source selection UART reception Receive
1/16
Reception clock
CLK1 to CLK0 Clock synchronous
002 control circuit
f1SIO or f2SIO U0BRG type Transmit/
012 Internal CKDIR=0 register receive
f8SIO unit
102 UART transmission Transmit
f32SIO 1 / (n0+1) 1/16
Transmission control clock
External Clock synchronous circuit
CKDIR=1 type
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
CKPOL (when external clock is selected) CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLK
polarity
CLK0 reversing
circuit
CTS/RTS selected CTS/RTS disabled
CRS=1 RTS0
CTS0 / RTS0 “H”
CRS=0
CTS/RTS disabled
RCSP=0 CRD=1 CTS0
CTS0 from UART1 CRD=0
RCSP=1

(UART1) TxD
RxD polarity polarity
RxD1 reversing circuit reversing TxD1
circuit
Clock source selection UART reception
1/16 Receive
CLK1 to CLK0 Reception clock
Clock synchronous control circuit
002 Transmit/
f1SIO or f2SIO U1BRG type
receive
012 Internal CKDIR=0 register
f8SIO unit
102 UART transmission Transmit
f32SIO 1 / (n1+1) 1/16 Transmission clock
Clock synchronous control circuit
External CKDIR=1 type
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
CKPOL (when external clock is selected)
CKDIR=1
CLK Clock synchronous type
polarity (when internal clock is selected)
CLK1 CLKMD0=0
reversing
circuit
CLKMD0=1
Clock output
pin select CTS/RTS selected CTS/RTS disabled
CTS1 / RTS1/ CLKMD1=1 CRS=1 RTS1
CTS0/ CLKS1 CLKMD1=0 CRS=0
“H”
CTS/RTS disabled
RCSP=0 CTS1
CRD=1

CRD=0 CTS0 from UART0

RCSP=1
(UART2) TxD
RxD polarity polarity
RxD2 reversing circuit reversing TxD2
circuit
Clock source selection UART reception Receive
1/16 (Note)
CLK1 to CLK0 Reception clock
Clock synchronous control circuit
002 U2BRG type Transmit/
f1SIO or f2SIO receive
012 Internal CKDIR=0 register
f8SIO unit
102 UART transmission Transmit
f32SIO 1 / (n2+1) 1/16
Transmission clock
Clock synchronous control circuit
External CKDIR=1 type
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKPOL CKDIR=1
Clock synchronous type
CLK (when internal clock is selected)
polarity
CLK2 reversing
circuit
CTS/RTS CTS/RTS disabled
selected
CRS=1 RTS2
CTS2 / RTS2 CRS=0
“H”
CTS/RTS disabled
CRD=1 CTS2
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.

Figure 1.17.1. UARTi Block Diagram

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Serial I/O

No reverse

IOPOL=0
RxD data
RxDi reverse circuit
Reverse IOPOL=1

Clock
synchronous type
UART
1SP PAR (7 bits)
disabled
Clock UART
UART(7 bits) UARTi receive register
synchronous (8 bits)
STPS= 0 PRYE=0 type
SP SP PAR
2SP PRYE=1
STPS= 1 Clock
PAR UART UART
enabled synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)

UiRB register
0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0

Logic reverse circuit + MSB/LSB conversion circuit

Data bus high-order bits

Data bus low-order bits

Logic reverse circuit + MSB/LSB conversion circuit

D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB register

UART
(9 bits) UART
(8 bits)
UART
(9 bits)
Clock
PAR synchronous type
2SP STPS= 1 enabled PRYE=1 UART
SP SP PAR
STPS PRYE=0
=0 UART UARTi transmit register
Clock
(7 bits)
1SP PAR UART UART(7 bits)
synchronous
disabled type (8 bits)
“0”
Clock
synchronous type
i=0 to 2 Error signal output
disable No reverse
SP: Stop bit UiERE=0 IOPOL=0
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
Error signal TxD data TxDi
output circuit reverse circuit
UiERE=1 IOPOL=1
UiERE: UiC1 register's bit Error signal output Reverse
enable

Figure 1.17.2. UARTi Transmit/Receive Unit

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UARTi transmit buffer register (i=0 to 2)(Note)

(b15) (b8) Symbol Address After reset
b7 b0 b7 b0 U0TB 03A316-03A216 Indeterminate
U1TB 03AB16-03AA16 Indeterminate
U2TB 037B16-037A16 Indeterminate

Function RW
Transmit data WO

Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

Note: Use MOV instruction to write to this register.

UARTi receive buffer register (i=0 to 2)

(b15) (b8) Symbol Address After reset
b7 b0 b7 b0
U0RB 03A716-03A616 Indeterminate
U1RB 03AF16-03AE16 Indeterminate
U2RB 037F16-037E16 Indeterminate

Bit Function
Bit name RW
symbol

(b7-b0) Receive data (D7 to D0) RO

(b8) Receive data (D8) RO

Nothing is assigned.
(b10-b9) In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

ABT Arbitration lost detecting 0 : Not detected

flag (Note 2) 1 : Detected RW

OER Overrun error flag (Note 1) 0 : No overrun error

1 : Overrun error found RO

FER Framing error flag (Note 1) 0 : No framing error RO

1 : Framing error found

PER Parity error flag (Note 1) 0 : No parity error

RO
1 : Parity error found

SUM Error sum flag (Note 1) 0 : No error

1 : Error found RO

Note 1: When the UiMR register’s SMD2 to SMD0 bits = “0002” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)

UARTi baud rate generation register (i=0 to 2)(Notes 1, 2)

b7 b0 Symbol Address After reset
U0BRG 03A116 Indeterminate
U1BRG 03A916 Indeterminate
U2BRG 037916 Indeterminate

Function Setting range RW

Assuming that set value = n, UiBRG divides the count source 0016 to FF16 WO
by n + 1

Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.

Figure 1.17.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register

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Serial I/O

UARTi transmit/receive mode register (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
U0MR to U2MR 03A016, 03A816, 037816 0016

Bit
Bit name Function RW
symbol
b2 b1 b0
SMD0 Serial I/O mode select bit 0 0 0 : Serial I/O disabled RW
(Note 2) 0 0 1 : Clock synchronous serial I/O mode
SMD1 0 1 0 : I2C mode (Note 3)
1 0 0 : UART mode transfer data 7 bits long RW
1 0 1 : UART mode transfer data 8 bits long
SMD2 1 1 0 : UART mode transfer data 9 bits long
Must not be set except above RW

CKDIR Internal/external clock 0 : Internal clock

select bit 1 : External clock (Note 1) RW

STPS Stop bit length select bit 0 : One stop bit

1 : Two stop bits RW

PRY Odd/even parity select bit Effective when PRYE = 1

0 : Odd parity RW
1 : Even parity
PRYE Parity enable bit 0 : Parity disabled RW
1 : Parity enabled
IOPOL TxD, RxD I/O polarity 0 : No reverse
reverse bit 1 : Reverse RW

Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).

UARTi transmit/receive control register 0 (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
U0C0 to U2C0 03A416, 03AC16, 037C16 000010002

Bit
Bit name Function RW
symbol
b1 b0
CLK0 BRG count source 0 0 : f1SIO or f2SIO is selected RW
select bit 0 1 : f8SIO is selected
CLK1 1 0 : f32SIO is selected RW
1 1 : Must not be set

CRS CTS/RTS function Effective when CRD = 0

select bit 0 : CTS function is selected (Note 1) RW
(Note 4) 1 : RTS function is selected

TXEPT Transmit register empty 0 : Data present in transmit register (during transmission)
flag 1 : No data present in transmit register RO
(transmission completed)

CRD CTS/RTS disable bit 0 : CTS/RTS function enabled

1 : CTS/RTS function disabled RW
(P60, P64 and P73 can be used as I/O ports)

Data output select bit 0 : TxDi/SDAi and SCLi pins are CMOS output
NCH 1 : TxDi/SDAi and SCLi pins are N-channel open-drain output RW
(Note 2)

CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge RW
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
UFORM Transfer format select bit 0 : LSB first RW
(Note 3) 1 : MSB first

Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).

Figure 1.17.4. U0MR to U2MR Register and U0C0 to U2C0 Register

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UARTi transmit/receive control register 1 (i=0, 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
U0C1, U1C1 03A516,03AD16 000000102

Bit Function
Bit name RW
symbol

TE Transmit enable bit 0 : Transmission disabled

1 : Transmission enabled RW

TI Transmit buffer 0 : Data present in UiTB register RO

empty flag 1 : No data present in UiTB register
RE Receive enable bit 0 : Reception disabled RW
1 : Reception enabled
RI Receive complete flag 0 : No data present in UiRB register
1 : Data present in UiRB register RO

Nothing is assigned.
(b5-b4) When write, set “0”. When read, these contents are “0”.
UiLCH Data logic select bit 0 : No reverse
1 : Reverse RW

UiERE Error signal output 0 : Output disabled

RW
enable bit 1 : Output enabled

UART2 transmit/receive control register 1

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
U2C1 037D16 000000102

Bit Function
Bit name RW
symbol

TE Transmit enable bit 0 : Transmission disabled

1 : Transmission enabled RW

TI Transmit buffer 0 : Data present in U2TB register

empty flag 1 : No data present in U2TB register RO

RE Receive enable bit 0 : Reception disabled

1 : Reception enabled RW

RI Receive complete flag 0 : No data present in U2RB register RO

1 : Data present in U2RB register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1) RW
cause select bit 1 : Transmit is completed (TXEPT = 1)

U2RRM UART2 continuous 0 : Continuous receive mode disabled

RW
receive mode enable bit 1 : Continuous receive mode enabled

U2LCH Data logic select bit 0 : No reverse

1 : Reverse RW

U2ERE Error signal output 0 : Output disabled

enable bit 1 : Output enabled RW

Figure 1.17.5. U0C1 to U2C1 Registers

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UART transmit/receive control register 2

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
UCON 03B016 X00000002

Bit Function
Bit RW
symbol
name
U0IRS UART0 transmit 0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit 1 : Transmission completed (TXEPT = 1) RW

U1IRS UART1 transmit 0 : Transmit buffer empty (Tl = 1)

interrupt cause select bit 1 : Transmission completed (TXEPT = 1) RW

U0RRM UART0 continuous 0 : Continuous receive mode disabled RW

receive mode enable bit 1 : Continuous receive mode enable
U1RRM UART1 continuous 0 : Continuous receive mode disabled
RW
receive mode enable bit 1 : Continuous receive mode enabled
CLKMD0 UART1 CLK/CLKS Effective when CLKMD1 = “1”
select bit 0 0 : Clock output from CLK1 RW
1 : Clock output from CLKS1
CLKMD1 UART1 CLK/CLKS 0 : CLK output is only CLK1
select bit 1 (Note) 1 : Transfer clock output from multiple pins function RW
selected
RCSP Separate UART0 0 : CTS/RTS shared pin RW
CTS/RTS bit 1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)

Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)

UARTi special mode register (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
0 Symbol Address After reset
U0SMR to U2SMR 036F16, 037316, 037716 X00000002

Bit Function
Bit RW
symbol
name
IICM I2C mode select bit 0 : Other than I2C mode RW
1 : I2C mode

ABC Arbitration lost detecting 0 : Update per bit

RW
flag control bit 1 : Update per byte

BBS Bus busy flag 0 : STOP condition detected RW

1 : START condition detected (busy) (Note1)

Reserved bit Set to “0” RW

(b3)

ABSCS Bus collision detect 0 : Rising edge of transfer clock RW

sampling clock select bit 1 : Underflow signal of timer Aj (Note 2)

ACSE Auto clear function 0 : No auto clear function

select bit of transmit 1 : Auto clear at occurrence of bus collision RW
enable bit

SSS Transmit start condition 0 : Not synchronized to RXDi

select bit 1 : Synchronized to RXDi (Note 3) RW

Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)

Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).

Figure 1.17.6. UCON Register and U0SMR to U2SMR Registers

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UARTi special mode register 2 (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
U0SMR2 to U2SMR2 036E16, 037216, 037616 X00000002

Bit
Bit name Function RW
symbol

IICM2 I 2C mode select bit 2 Refer to “Table 1.20.4. I2C Mode Functions”
RW

CSC Clock-synchronous bit 0 : Disabled

1 : Enabled RW

SWC SCL wait output bit 0 : Disabled

1 : Enabled RW

ALS SDA output stop bit 0 : Disabled

RW
1 : Enabled

STAC UARTi initialization bit 0 : Disabled

RW
1 : Enabled
SWC2 SCL wait output bit 2 0: Transfer clock
RW
1: “L” output
SDHI SDA output disable bit 0: Enabled
RW
1: Disabled (high impedance)
Nothing is assigned. When write, set “0”. When read, its content is
(b7) indeterminate.

UARTi special mode register 3 (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
U0SMR3 to U2SMR3 036D16, 037116, 037516 000X0X0X2

Bit
Bit name Function RW
symbol

Nothing is assigned.
(b0) When write, set “0”. When read, its content is indeterminate.
CKPH Clock phase set bit 0 : Without clock delay
RW
1 : With clock delay
Nothing is assigned.
(b2) When write, set “0”. When read, its content is indeterminate.
NODC Clock output select bit 0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output RW

Nothing is assigned.
(b4) When write, set “0”. When read, its content is indeterminate.
DL0 SDAi digital delay b7 b6 b5
RW
setup bit 0 0 0 : Without delay
(Note 1, Note 2) 0 0 1 : 1 to 2 cycle(s) of UiBRG count source
DL1 0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source RW
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
DL2 1 1 0 : 6 to 7 cycles of UiBRG count source RW
1 1 1 : 7 to 8 cycles of UiBRG count source
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.

Figure 1.17.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers

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UARTi special mode register 4 (i=0 to 2)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
U0SMR4 to U2SMR4 036C16, 037016, 037416 0016

Bit
Bit name Function RW
symbol

STAREQ Start condition 0 : Clear RW

generate bit (Note) 1 : Start

RSTAREQ Restart condition 0 : Clear

RW
generate bit (Note) 1 : Start

STPREQ Stop condition 0 : Clear

generate bit (Note) 1 : Start RW

STSPSEL SCL,SDA output 0 : Start and stop conditions not output RW

select bit 1 : Start and stop conditions output
ACKD ACK data bit 0 : ACK
RW
1 : NACK

ACKC ACK data output 0 : Serial I/O data output

RW
enable bit 1 : ACK data output
SCLHI SCL output stop 0 : Disabled
enable bit 1 : Enabled RW

SWC9 SCL wait bit 3 0 : SCL “L” hold disabled

1 : SCL “L” hold enabled RW

Note: Set to “0” when each condition is generated.

Figure 1.17.8. U0SMR4 to U2SMR4 Registers

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Serial I/O (Clock Synchronous Serial I/O)

Clock Synchronous serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.18.1
lists the specifications of the clock synchronous serial I/O mode. Table 1.18.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.

Table 1.18.1. Clock Synchronous Serial I/O Mode Specifications

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit = “1” (external clock) : Input from CLKi pin
_______ _______ _______ _______
Transmission, reception control • Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______ _______
_ If CTS function is selected, input on the CTSi pin = “L”
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
Interrupt request • For transmission, one of the following conditions can be selected
generation timing _ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from

the UARTi transmit register

• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function • CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.

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Serial I/O (Clock Synchronous Serial I/O)

Table 1. 18. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register Bit Function
UiTB(Note3) 0 to 7 Set transmission data
UiRB(Note3) 0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR(Note3) SMD2 to SMD0 Set to “0012”
CKDIR Select the internal clock or external clock
IOPOL Set to “0”
UiC0 CLK1 to CLK0 Select the count source for the UiBRG register
_______ _______
CRS Select CTS or RTS to use
TXEPT Transmit register empty flag
_______ _______
CRD Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode (Note 2)
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to “1” to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 1) Select the source of UART2 transmit interrupt
U2RRM (Note 1) Set this bit to “1” to use continuous receive mode
UiLCH Set this bit to “1” to use inverted data logic
UiERE Set to “0”
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 2 Set to “0”
NODC Select clock output mode
4 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0 Select the transfer clock output pin when CLKMD1 = 1
CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins
_________
RCSP Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to “0”
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Clock Synchronous Serial I/O)

Table 1.18.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
1.18.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 1.18.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)

Table 1.18.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name Function Method of selection
TxDi (i = 0 to 2) Serial data output (Outputs dummy data when performing reception only)
(P63, P67, P70)

RxDi Serial data input PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(P62, P66, P71) (Can be used as an input port when performing transmission only)
CLKi Transfer clock output UiMR register’s CKDIR bit=0
(P61, P65, P72)
Transfer clock input UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
CTSi/RTSi CTS input UiC0 register’s CRD bit=0
(P60, P64, P73) UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1

I/O port UiC0 register’s CRD bit=1

Table 1.18.4. P64 Pin Functions

Pin function Bit set value
U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 CLKMD0 PD6_4
P64 1 0 0 Input: 0, Output: 1
CTS1 0 0 0 0 0
RTS1 0 1 0 0
CTS0(Note1) 0 0 1 0 0
CLKS1 1(Note 2) 1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Clock Synchronous Serial I/O)

(1) Example of transmit timing (when internal clock is selected)

Tc

Transfer clock

“1”
UiC1 register
TE bit “0” Write data to the UiTB register

UiC1 register “1”

TI bit “0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi TCLK
“L”
Stopped pulsing because CTSi = “H” Stopped pulsing because the TE bit = “0”

CLKi

TxDi D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7

UiC0 register “1”

TXEPT bit “0”

SiTIC register “1”

IR bit “0”

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4

(2) Example of receive timing (when external clock is selected)

“1”
UiC1 register
RE bit “0”

“1”
UiC1 register
TE bit “0” Write dummy data to UiTB register
“1”
UiC1 register
TI bit “0”
Transferred from UiTB register to UARTi transmit register
“H”
RTSi Even if the reception is completed, the RTS
“L” does not change. The RTS becomes “L”
1 / fEXT when the RI bit changes to “0” from “1”.

CLKi
Receive data is taken in

RxDi D 0 D1 D 2 D3 D 4 D5 D6 D 7 D0 D 1 D 2 D3 D4 D5

Transferred from UARTi receive register Read out from UiRB register
“1” to UiRB register
UiC1 register
RI bit “0”

SiRIC register “1”

IR bit “0”

Cleared to “0” when interrupt request is

accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input
as follows: to the CLKi pin before receiving data is high:
• UiMR register CKDIR bit = 1 (external clock) • UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected) • UiC0 register RE bit = 1 (Receive enabled)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive • Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock

Figure 1.18.1. Transmit and Receive Operation

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Clock Synchronous Serial I/O)

(a) CLK Polarity Select Function

Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 1.18.2 shows
the polarity of the transfer clock.

(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)

CLKi (Note 2)

TXDi D0 D1 D2 D3 D4 D5 D6 D7

RXDi D0 D1 D2 D3 D4 D5 D6 D7

(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)

CLKi (Note 3)

TXDi D0 D1 D2 D3 D4 D5 D6 D7

R XD i D0 D1 D2 D3 D4 D5 D6 D7

Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2

Figure 1.18.2. Transfer Clock Polarity

(b) LSB First/MSB First Select Function

Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 1.18.3 shows the
transfer format.

(1) When UiC0 register's UFORM bit = 0 (LSB first)

CLKi

TXDi D0 D1 D2 D3 D4 D5 D6 D7

R XD i D0 D1 D2 D3 D4 D5 D6 D7

(2) When UiC0 register's UFORM bit = 1 (MSB first)

CLKi

TXDi D7 D6 D5 D4 D3 D2 D1 D0

R XD i D7 D6 D5 D4 D3 D2 D1 D0

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2

Figure 1.18.3. Transfer Format

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Clock Synchronous Serial I/O)

(c) Continuous Receive Mode

When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.

(d) Serial Data Logic Switching Function

When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register. Figure 1.18.4 shows serial data logic.

(1) When the UiC1 register's UiLCH bit = 0 (no reverse)

“H”
Transfer clock
“L”

TxDi “H”
D0 D1 D2 D3 D4 D5 D6 D7
(no reverse) “L”

(2) When the UiC1 register's UiLCH bit = 1 (reverse)

“H”
Transfer clock
“L”

TxDi “H”
(reverse) D0 D1 D2 D3 D4 D5 D6 D7
“L”

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Figure 1.18.4. Serial Data Logic Switching

(e) Transfer Clock Output From Multiple Pins (UART1)

Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
(See Figure 1.18.5.) This function can be used when the selected transfer clock for UART1 is an
internal clock.

Microcomputer

TXD1 (P67)

CLKS1 (P64)

CLK1 (P65) IN IN
CLK CLK

Transfer enabled Transfer enabled

when the UCON when the UCON
register's register's
CLKMD0 bit = 0 CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).

Figure 1.18.5. Transfer Clock Output From Multiple Pins

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Serial I/O (Clock Synchronous Serial I/O)

_______ _______
(f) CTS/RTS Separate Function (UART0)
_______ _______ _______ _______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.

Microcomputer IC
TXD0 (P63) IN
RXD0 (P62) OUT
CLK0 (P61) CLK

RTS0 (P60) CTS

CTS0 (P64) RTS

_______ _______
Figure 1.18.6. CTS/RTS Separat Function

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (UART)

Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.1 lists the specifications of the UART mode.
Table 1.19.1. UART Mode Specifications
Item Specification
Transfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock • UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16
_______ _______ _______ _______
Transmission, reception control • Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______ _______
_ If CTS function is selected, input on the CTSi pin = “L”

Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection

Interrupt request • For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
generation timing
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from

the UARTi transmit register

• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function • LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.

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Serial I/O (UART)

Table 1. 19. 2. Registers to Be Used and Settings in UART Mode

Register Bit Function
UiTB 0 to 8 Set transmission data (Note 1)
UiRB 0 to 8 Reception data can be read (Note 1)
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
IOPOL Select the TxD/RxD input/output polarity
UiC0 CLK0, CLK1 Select the count source for the UiBRG register
_______ _______
CRS Select CTS or RTS to use
TXEPT Transmit register empty flag
_______ _______
CRD Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode (Note 2)
CKPOL Set to “0”
UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 2) Select the source of UART2 transmit interrupt
U2RRM (Note 2) Set to “0”
UiLCH Set this bit to “1” to use inverted data logic
UiERE Set to “0”
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1 Set to “0”
_________
RCSP Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to “0”
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2

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Serial I/O (UART)

Table 1.19.3 lists the functions of the input/output pins during UART mode. Table 1.19.4 lists the P64 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin
is in a high-impedance state.)

Table 1.19.3. I/O Pin Functions

Pin name Function Method of selection
TxDi (i = 0 to 2) Serial data output (Outputs dummy data when performing reception only)
(P63, P67, P70)

RxDi Serial data input PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(P62, P66, P71) (Can be used as an input port when performing transmission only)
CLKi Input/output port UiMR register’s CKDIR bit=0
(P61, P65, P72)
Transfer clock input UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
CTSi/RTSi CTS input UiC0 register’s CRD bit=0
(P60, P64, P73) UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1

Input/output port UiC0 register’s CRD bit=1

Table 1.19.4. P64 Pin Functions

Pin function Bit set value
U1C0 register UCON register PD6 register
CRD CRS RCSP CLKMD1 PD6_4
P64 1 0 0 Input: 0, Output: 1
CTS1 0 0 0 0 0
RTS1 0 1 0 0
CTS0 (Note) 0 0 1 0 0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).

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Serial I/O (UART)

(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc

Transfer clock
UiC1 register “1”
TE bit
“0” Write data to the UiTB register
UiC1 register
TI bit “1”

“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
“L”
Stopped pulsing
Start Parity Stop because the TE bit
bit bit bit = “0”
TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1

UiC0 register “1”

TXEPT bit
“0”

SiTIC register “1”

IR bit “0”

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

The above timing diagram applies to the case where the register bits are set Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
as follows: fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 1 (parity enabled) fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 0 (1 stop bit) n : value set to UiBRG
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
i: 0 to 2
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4

(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc

Transfer clock

“1”
UiC1 register
TE bit “0” Write data to the UiTB register

UiC1 register “1”

TI bit
“0”
Transferred from UiTB register to UARTi
transmit register
Start Stop Stop
bit bit bit
TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1

UiC0 register “1”

TXEPT bit
“0”

SiTIC register “1”

IR bit “0”

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

The above timing diagram applies to the case where the register bits are set Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
as follows: fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 0 (parity disabled) fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 1 (2 stop bits) n : value set to UiBRG
• UiC0 register CRD bit = 1 (CTS/RTS disabled) i: 0 to 2
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4

Figure 1.19.1. Transmit Operation

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Serial I/O (UART)

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

UiBRG count
source
UiC1 register “1”
RE bit “0”
Stop bit
RxDi Start bit D0 D1 D7
Sampled “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock Transferred from UARTi receive
UiC1 register “1” is generated by falling edge of start bit register to UiRB register
RI bit “0”
“H”
RTSi
“L”
SiRIC register “1”
IR bit “0”

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2

Figure 1.19.2. Receive Operation

(a) LSB First/MSB First Select Function

As shown in Figure 1.19.3, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.

(1) When UiC0 register's UFORM bit = 0 (LSB first)

CLKi

TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP

RXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP

(2) When UiC0 register's UFORM bit = 1 (MSB first)

CLKi

TXDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP

RXDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 ( ST : Start bit
transmit data output at the falling edge and the receive data taken P : Parity bit
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH SP : Stop bit
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and i = 0 to 2
UiMR register's PRYE bit = 1 (parity enabled).

Figure 1.19.3. Transfer Format

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Serial I/O (UART)

(b) Serial Data Logic Switching Function

The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 1.19.4 shows serial data
logic.

(1) When the UiC1 register's UiLCH bit = 0 (no reverse)

“H”
Transfer clock
“L”

TxDi “H”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(no reverse) “L”

(2) When the UiC1 register's UiLCH bit = 1 (reverse)

“H”
Transfer clock
“L”

TxDi “H”
(reverse)
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“L”

Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 ( ST : Start bit
transmit data output at the falling edge of the transfer clock), the P : Parity bit
UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's SP : Stop bit
STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity i = 0 to 2
enabled).

Figure 1.19.4. Serial Data Logic Switching

(c) TxD and RxD I/O Polarity Inverse Function

This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 1.19.5 shows the TXD
pin output and RXD pin input polarity inverse.

(1) When the UiMR register's IOPOL bit = 0 (no reverse)

“H”
Transfer clock
“L”

TxDi “H”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(no reverse) “L”

RxDi “H” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(no reverse) “L”

(2) When the UiMR register's IOPOL bit = 1 (reverse)

Transfer clock “H”
“L”

TxDi “H”
(reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“H”
RxDi “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(reverse)

Note: This applies to the case where the UiC0 register's UFORM bit = 0 ST : Start bit
(LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the P : Parity bit
SP : Stop bit
UiMR register's PRYE bit = 1 (parity enabled). i = 0 to 2

Figure 1.19.5. TXD and RXD I/O Polarity Inverse

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_______ _______
(d) CTS/RTS Separate Function (UART0)
_______ _______ _______ _______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______ _______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.

Microcomputer IC
TXD0 (P63) IN
RXD0 (P62) OUT

RTS0 (P60) CTS

CTS0 (P64) RTS

_______ _______
Figure 1.19.6. CTS/RTS Separate Function

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Special Mode 1 (I2C mode)

I2C mode is provided for use as a simplified I2C interface compatible mode. Table 1.20.1 lists the speci-
fications of the I2C mode. Table 1.20.2 lists the registers used in the I2C mode and the register values
set. Figure 1.20.1 shows the block diagram for I2C mode. Figure 1.20.2 shows SCLi timing.

As shown in Table 1.20.3, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to
‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.

Table 1.20.1. I2C Mode Specifications

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
CKDIR bit = “1” (external clock) : Input from SCLi pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
Interrupt request When start or stop condition is detected, acknowledge undetected, and acknowledge
generation timing detected
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
Select function • Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.

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Start and stop condition generation block

SDAi DMA0, DMA1 request
STSPSEL=1 (UART1: DMA0 only)
Delay SDASTSP
circuit SCLSTSP
STSPSEL=0 IICM2=1
Transmission UARTi transmit,
register NACK interrupt
ACK=1 ACK=0
UARTi IICM=1 and request
IICM2=0
SDHI
ACKD register ALS

D Q DMA0
Arbitration
(UART0, UART2)
Noise T
Filter
IICM2=1
Reception register UARTi receive,
ACK interrupt request,
UARTi
IICM=1 and DMA1 request
IICM2=0
Start condition
detection
S
Q Bus
R busy

Stop condition NACK

detection

D Q
T
Falling edge
detection
SCLi D Q
T ACK
IICM=0 R Port register
I/O port Q (Note) 9th bit
STSPSEL=0 Internal clock
Start/stop condition detection
IICM=1 UARTi SWC2 CLK
interrupt request
STSPSEL=1 External control
Noise clock
Filter UARTi

R 9th bit falling edge

S SWC

This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM : UiSMR register bit
IICM2, SWC, ALS, SWC2, SDHI : UiSMR2 register bit
STSPSEL, ACKD, ACKC : UiSMR4 register bit

i=0 to 2
Note: If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).

Figure 1.20.1. I2C Mode Block Diagram

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Table 1. 20. 2. Registers to Be Used and Settings in I2C Mode (1) (Continued)
Register Bit Function
Master Slave
UiTB3 0 to 7 Set transmission data Set transmission data
UiRB3 0 to 7 Reception data can be read Reception data can be read
8 ACK or NACK is set in this bit ACK or NACK is set in this bit
ABT Arbitration lost detection flag Invalid
OER Overrun error flag Overrun error flag
UiBRG 0 to 7 Set a transfer rate Invalid
UiMR3 SMD2 to SMD0 Set to ‘0102’ Set to ‘0102’
CKDIR Set to “0” Set to “1”
IOPOL Set to “0” Set to “0”
UiC0 CLK1, CLK0 Select the count source for the UiBRG Invalid
register
CRS Invalid because CRD = 1 Invalid because CRD = 1
TXEPT Transmit buffer empty flag Transmit buffer empty flag
CRD Set to “1” Set to “1”
NCH Set to “1”2 Set to “1”2
CKPOL Set to “0” Set to “0”
UFORM Set to “1” Set to “1”
UiC1 TE Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI Transmit buffer empty flag Transmit buffer empty flag
RE Set this bit to “1” to enable reception Set this bit to “1” to enable reception
RI Reception complete flag Reception complete flag
U2IRS1 Invalid Invalid
U2RRM1, Set to “0” Set to “0”
UiLCH, UiERE
UiSMR IICM Set to “1” Set to “1”
ABC Select the timing at which arbitration-lost Invalid
is detected
BBS Bus busy flag Bus busy flag
3 to 7 Set to “0” Set to “0”
UiSMR2 IICM2 Refer to “Table 1.20.4. I2C Mode Functions” Refer to “Table 1.20.4. I2C Mode Functions”
CSC Set this bit to “1” to enable clock Set to “0”
synchronization
SWC Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9th
bit of clock bit of clock
ALS Set this bit to “1” to have SDAi output Set to “0”
stopped when arbitration-lost is detected
STAC Set to “0” Set this bit to “1” to initialize UARTi at
start condition detection
SWC2 Set this bit to “1” to have SCLi output Set this bit to “1” to have SCLi output
forcibly pulled low forcibly pulled low
SDHI Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output
7 Set to “0” Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0” Set to “0”
CKPH Refer to “Table 1.20.4. I2C Mode Functions” Refer to “Table 1.20.4. I2C Mode Functions”
DL2 to DL0 Set the amount of SDAi digital delay Set the amount of SDAi digital delay
i=0 to 2
Notes:
1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.

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Table 1. 20. 3. Registers to Be Used and Settings in I2C Mode (2) (Continued)
Register Bit Function
Master Slave
UiSMR4 STAREQ Set this bit to “1” to generate start Set to “0”
condition
RSTAREQ Set this bit to “1” to generate restart Set to “0”
condition
STPREQ Set this bit to “1” to generate stop Set to “0”
condition
STSPSEL Set this bit to “1” to output each condition Set to “0”
ACKD Select ACK or NACK Select ACK or NACK
ACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK data
SCLHI Set this bit to “1” to have SCLi output Set to “0”
stopped when stop condition is detected
SWC9 Set to “0” Set this bit to “1” to set the SCLi to “L”
hold at the falling edge of the 9th bit of
clock
IFSR2A IFSR26, ISFR27 Set to “1” Set to “1”
UCON U0IRS, U1IRS Invalid Invalid
2 to 7 Set to “0” Set to “0”
i=0 to 2

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Table 1.20.4. I2C Mode Functions

Function Clock synchronous serial I/O I2C mode (SMD2 to SMD0 = 0102, IICM = 1)
mode (SMD2 to SMD0 = 0012, IICM2 = 0 IICM2 = 1
IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt)
CKPH = 0 CKPH = 1 CKPH = 0 CKPH = 1
(No clock delay) (Clock delay) (No clock delay) (Clock delay)
Factor of interrupt number Start condition detection or stop condition detection
6, 7 and 10 (Note 1, 5, 7) (Refer to “Table 1.20.5. STSPSEL Bit Functions”)

Factor of interrupt number UARTi transmission No acknowledgment UARTi transmission UARTi transmission
15, 17 and 19 (Note 1, 6) Transmission started or detection (NACK) Rising edge of Falling edge of SCLi
completed (selected by UiIRS) Rising edge of SCLi 9th bit SCLi 9th bit next to the 9th bit
Factor of interrupt number UARTi reception Acknowledgment detection UARTi reception
16, 18 and 20 (Note 1, 6) When 8th bit received (ACK) Falling edge of SCLi 9th bit
CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit
CKPOL = 1 (falling edge)
Timing for transferring data CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit Falling edge of Falling and rising
from the UART reception CKPOL = 1 (falling edge) SCLi 9th bit edges of SCLi 9th
shift register to the UiRB bit
register
UARTi transmission output Not delayed Delayed
delay
Functions of P63, P67 and TxDi output SDAi input/output
P70 pins
Functions of P62, P66 and RxDi input SCLi input/output
P71 pins
Functions of P61, P65 and CLKi input or output selected (Cannot be used in I2C mode)
P72 pins
Noise filter width 15ns 200ns
Read RxDi and SCLi pin Possible when the Always possible no matter how the corresponding port direction bit is set
levels corresponding port direction bit
=0
Initial value of TxDi and CKPOL = 0 (H) The value set in the port register before setting I2C mode (Note 2)
SDAi outputs CKPOL = 1 (L)
Initial and end values of H L H L
SCLi
DMA1 factor (Refer to Fig UARTi reception Acknowledgment detection UARTi reception
1.20.2) (ACK) Falling edge of SCLi 9th bit
Store received data 1st to 8th bits are stored in 1st to 8th bits are stored in 1st to 7th bits are stored in UiRB register
UiRB register bit 0 to bit 7 UiRB register bit 7 to bit 0 bit 6 to bit 0, with 8th bit stored in UiRB
register bit 8

1st to 8th bits are

stored in UiRB
register bit 7 to bit 0
(Note 3)
Read received data UiRB register status is read Read UiRB register
directly as is Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)

i = 0 to 2
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to “precautions for interrupts” of the Usage Notes Reference Book.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
Note 2: Set the initial value of SDAi output while the UiMR register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
Note 3: Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
Note 4: First data transfer to UiRB register (Falling edge of SCLi 9th bit)
Note 5: Refer to “Figure 1.20.4. STSPSEL Bit Functions”.
Note 6: Refer to “Figure 1.20.2. Transfer to UiRB Register and Interrupt Timing”.
Note 7: When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART1 bus collision).

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(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)

ACK interrupt (DMA1 request),

NACK interrupt

Transfer to UiRB register

b15 b9 b8 b7 b0

••• D8 D7 D6 D5 D4 D3 D2 D1 D0

UiRB register

(2) IICM2= 0, CKPH= 1 (clock delay)

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)

ACK interrupt (DMA1 request),

NACK interrupt

Transfer to UiRB register

b15 b9 b8 b7 b0

••• D8 D7 D6 D5 D4 D3 D2 D1 D0

UiRB register

(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)

Receive interrupt Transmit interrupt

(DMA1 request)

Transfer to UiRB register

b15 b9 b8 b7 b0

••• D0 D7 D6 D5 D4 D3 D2 D1

UiRB register

(4) IICM2= 1, CKPH= 1

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)

Receive interrupt Transmit interrupt

(DMA1 request)

Transfer to UiRB register Transfer to UiRB register

b15 b9 b8 b7 b0 b15 b9 b8 b7 b0

••• D0 D7 D6 D5 D4 D3 D2 D1 ••• D8 D7 D6 D5 D4 D3 D2 D1 D0

UiRB register UiRB register

i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)

Figure 1.20.2. Transfer to UiRB Register and Interrupt Timing

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• Detection of Start and Stop Condtion

Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.

3 to 6 cycles < duration for setting-up (Note)

3 to 6 cycles < duration for holding (Note)

Duration for Duration for

setting up holding
SCLi

SDAi
(Start condition)
SDA i
(Stop condition)

i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.

Figure 1.20.3. Detection of Start and Stop Condition

• Output of Start and Stop Condition

A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 1.20.5 and Figure 1.20.4.

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Table 1.20.5. STSPSEL Bit Functions

Function STSPSEL = 0 STSPSEL = 1
Output of SCLi and SDAi pins Output of transfer clock and Output of a start/stop condition
data according to the STAREQ,
Output of start/stop condition is RSTAREQ and STPREQ bit
accomplished by a program
using ports (not automatically
generated in hardware)
Star/stop condition interrupt Start/stop condition detection Finish generating start/stop condi-
request generation timing tion

(1) When slave

CKDIR=1 (external clock)
STSPSEL bit 0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi

SDAi

Start condition Stop condition

detection interrupt detection interrupt

(2) When master

CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STSPSEL bit

Set to “1” in Set to “0” in Set to “1” in Set to “0” in

a program a program a program a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi

SDAi

Set STAREQ=1 Set STPREQ=1

(start) (start) Stop condition
Start condition
detection interrupt
detection interrupt

Figure 1.20.4. STSPSEL Bit Functions

• Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising
edge of SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT
bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC
bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring
the next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).

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• Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 1.20.4.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi)
and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchro-
nization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the
internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in
the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low,
counting stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi
pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st
bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a
low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s
CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.

• SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR
register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).

• SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit
7 to bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit
6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing
the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB
register after the rising edge of the corresponding clock pulse of 9th bit.

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• ACK and NACK

If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the
UiSMR4 register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low
at the rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.

• Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O
operates as described below.
- The transmit shift register is initialized, and the content of the UiTB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UARTi output value does not change state and remains the same
as when a start condition was detected until the first bit of data is output synchronously with the input
clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.

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Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 1.20.6 lists the specifications of Special Mode 2. Table 1.20.7 lists the registers used in
Special Mode 2 and the register values set. Figure 1.20.5 shows communication control example for
Special Mode 2.

Table 1.20.6. Special Mode 2 Specifications

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • Master mode
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Transmit/receive control Controlled by input/output ports
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition • Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
Interrupt request • For transmission, one of the following conditions can be selected
generation timing _ The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data

from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from

the UARTi transmit register

• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection • Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function • Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.

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P13
P12

P93
P72(CLK2) P72(CLK2)
P71(RxD2) P71(RxD2)
P70(TxD2) P70(TxD2)

Microcomputer Microcomputer
(Master) (Slave)

P93
P72(CLK2)
P71(RxD2)
P70(TxD2)

Microcomputer
(Slave)

Figure 1.20.5. Serial Bus Communication Control Example (UART2)

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Serial I/O (Special Modes)

Table 1. 20. 7. Registers to Be Used and Settings in Special Mode 2

Register Bit Function
UiTB(Note3) 0 to 7 Set transmission data
UiRB(Note3) 0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set a transfer rate
UiMR(Note3) SMD2 to SMD0 Set to ‘0012’
CKDIR Set this bit to “0” for master mode or “1” for slave mode
IOPOL Set to “0”
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because CRD = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxDi pin output format(Note 2)
CKPOL Clock phases can be set in combination with the UiSMR3 register's CKPH bit
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 1) Select UART2 transmit interrupt cause
U2RRM(Note 1), Set to “0”
U2LCH, UiERE
UiSMR 0 to 7 Set to “0”
UiSMR2 0 to 7 Set to “0”
UiSMR3 CKPH Clock phases can be set in combination with the UiC0 register's CKPOL bit
NODC Set to “0”
0, 2, 4 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
UCON U0IRS, U1IRS Select UART0 and UART1 transmit interrupt cause
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
i = 0 to 2

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Serial I/O (Special Modes)

• Clock Phase Setting Function

One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.

(a) Master (Internal Clock)

Figure 1.20.6 shows the transmission and reception timing in master (internal clock).

(b) Slave (External Clock)

Figure 1.20.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 1.20.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).

Clock output "H"

(CKPOL=0, CKPH=0) "L"

Clock output "H"

(CKPOL=1, CKPH=0) "L"

Clock output "H"

(CKPOL=0, CKPH=1) "L"

Clock output "H"

(CKPOL=1, CKPH=1) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
"L"

Data input timing

Figure 1.20.6. Transmission and Reception Timing in Master Mode (Internal Clock)

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"H"
Slave control input
"L"

Clock input "H"

(CKPOL=0, CKPH=0) "L"

Clock input "H"

(CKPOL=1, CKPH=0) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
(Note) "L"

Data input timing Indeterminate

Note :UART2 output is an N-channel open drain and must be pulled-up externally.

Figure 1.20.7. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)

"H"
Slave control input
"L"

Clock input "H"

(CKPOL=0, CKPH=1) "L"

Clock input "H"

(CKPOL=1, CKPH=1) "L"

Data output timing "H"

D0 D1 D2 D3 D4 D5 D6 D7
(Note) "L"

Data input timing

Note :UART2 output is an N-channel open drain and must be pulled-up externally.

Figure 1.20.8. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)

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Serial I/O (Special Modes)

Special Mode 3 (IE mode)

In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 1.20.8 lists the registers used in IE mode and the register values set. Figure 1.20.9 shows the
functions of bus collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect
function.

Table 1. 20. 8. Registers to Be Used and Settings in IE Mode

Register Bit Function
UiTB 0 to 8 Set transmission data
UiRB(Note3) 0 to 8 Reception data can be read
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set to ‘1102’
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Invalid because PRYE=0
PRYE Set to “0”
IOPOL Select the TxD/RxD input/output polarity
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because CRD=1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TxDi pin output mode (Note 2)
CKPOL Set to “0”
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS (Note 1) Select the source of UART2 transmit interrupt
UiRRM (Note 1), Set to “0”
UiLCH, UiERE
UiSMR 0 to 3, 7 Set to “0”
ABSCS Select the sampling timing at which to detect a bus collision
ACSE Set this bit to “1” to use the auto clear function of transmit enable bit
SSS Select the transmit start condition
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
IFSR2A IFSR26, IFSR27 Set to “1”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because CLKMD1 = 0
CLKMD1,RCSP,7 Set to “0”
Note 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
i= 0 to 2

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Serial I/O (Special Modes)

(1) UiSMR register ABSCS bit (bus collision detect sampling clock select) (i=0 to 2)

If ABSCS=0, bus collision is determined at the rising edge of the transfer clock

Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

TxDi

RxDi
Input to TAjIN

Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2

(2) UiSMR register ACSE bit (auto clear of transmit enable bit)

Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

TxDi

RxDi

UiBCNIC register If ACSE bit = 1 (automatically

IR bit (Note) clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
UiC1 register the UiBCNIC register’s IR bit = 1
TE bit (unmatching detected).

Note: BCNIC register when UART2.

(3) UiSMR register SSS bit (Transmit start condition select)

If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.

Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

TxDi

Transmission enable condition is met

If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi

CLKi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

TxDi (Note 2)

RxDi

Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).

Figure 1.20.9. Bus Collision Detect Function-Related Bits

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Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 1.20.9 lists the specifications of SIM mode. Table 1.20.10 lists the registers used in the SIM mode
and the register values set.

Table 1.20.9. SIM Mode Specifications

Item Specification
Transfer data format • Direct format
• Inverse format
Transfer clock • U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register 0016 to FF16
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)

Reception start condition • Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register= 1 (reception enabled)
_ Start bit detection

Interrupt request • For transmission

generation timing When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
(Note 2) • For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection • Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode,
be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.

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Table 1. 20. 10. Registers to Be Used and Settings in SIM Mode

Register Bit Function
U2TB(Note) 0 to 7 Set transmission data
U2RB(Note) 0 to 7 Reception data can be read
OER,FER,PER,SUM Error flag
U2BRG 0 to 7 Set a transfer rate
U2MR SMD2 to SMD0 Set to ‘1012’
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Set this bit to “1” for direct format or “0” for inverse format
PRYE Set to “1”
IOPOL Set to “0”
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD=1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Set to “0”
CKPOL Set to “0”
UFORM Set this bit to “0” for direct format or “1” for inverse format
U2C1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS Set to “1”
U2RRM Set to “0”
U2LCH Set this bit to “0” for direct format or “1” for inverse format
U2ERE Set to “1”
U2SMR(Note) 0 to 3 Set to “0”
U2SMR2 0 to 7 Set to “0”
U2SMR3 0 to 7 Set to “0”
U2SMR4 0 to 7 Set to “0”
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.

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(1) Transmission
Tc

Transfer clock

U2C1 register “1”

TE bit “0” Write data to U2TB register

U2C1 register “1”

TI bit
“0”

Transferred from U2TB register to UART2 transmit register

Start Parity Stop

bit bit bit
TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
Parity error signal sent
back from receiver An “L” level returns due to the
occurrence of a parity error.
RxD2 pin level
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P
(Note)
The level is detected by the SP
interrupt routine.
U2C0 register “1” The level is
TXEPT bit “0” detected by the
interrupt routine.
The IR bit is set to “1” at the
S2TIC register “1” falling edge of transfer clock
IR bit
“0”

The above timing diagram applies to the case where data is Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit) Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
• U2MR register PRY bit = 1 (even) fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• U2C0 register UFORM bit = 0 (LSB first) fEXT : frequency of U2BRG count source (external clock)
• U2C1 register U2LCH bit = 0 (no reverse) n : value set to U2BRG
• U2C1 register U2IRSCH bit = 1 (transmit is completed)

Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal
sent back from receiver.

(1) Reception
Tc

Transfer clock

U2C1 register “1”

RE bit
“0”

Transmitter's Start ParityStop

transmit waveform bit bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP

TxD2
An “L” level is output from TxD2 due to
the occurrence of a parity error
RxD2 pin level
(Note) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP

U2C0 register “1”

RI bit
“0”
Read the U2RB register Read the U2RB register
S2RIC register “1”
IR bit
“0”

The above timing diagram applies to the case where data is Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit) Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
• U2MR register PRY bit = 1 (even)
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse) fEXT : frequency of U2BRG count source (external clock)
• U2C1 register U2IRSCH bit = 1 (transmit is completed) n : value set to U2BRG

Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.

Figure 1.20.10. Transmit and Receive Timing in SIM Mode

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Figure 1.20.11 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.

Microcomputer
SIM card

TxD2

RxD2

Figure 1.20.11. SIM Interface Connection

(a) Parity Error Signal Output

The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 1.20.12. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.

Transfer “H”
clock “L”

“H”
RxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“L”

“H”
TxD2 (Note)
“L”

U2C1 register “1”

RI bit “0”
This timing diagram applies to the case where the direct format is ST : Start bit
implemented. P : Even Parity
Note: The output of microcomputer is in the high-impedance state SP : Stop bit
(pulled up externally).

Figure 1.20.12. Parity Error Signal Output Timing

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(b) Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH
bit to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 1.20.13 shows the SIM interface format.

(1) Direct format

“H”
Transfer
clcck “L”

TxD2 “H”
D0 D1 D2 D3 D4 D5 D6 D7 P
“L”

P : Even parity

(2) Inverse format

“H”
Transfer
clcck “L”

“H”
TxD2
“L” D7 D6 D5 D4 D3 D2 D1 D0 P
P : Odd parity

Figure 1.20.13. SIM Interface Format

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SI/O3, SI/O4

SI/O3 and SI/O4

SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 1.21.1 shows the block diagram of SI/O3 and SI/O4, and Figure 1.21.2 shows the SI/O3 and SI/O4-
related registers.
Table 1.21.1 shows the specifications of SI/O3 and SI/O4.

Clock source select

f2SIO PCLK1=0 SMi1 to SMi0
1/2
Main clock, 002 Data bus
f1SIO
PLL clock,
PCLK1=1 f8SIO 012
or ring oscillator clock 1/8
f32SIO 102
1/4
Synchronous
circuit 1/2 1/(n+1)
SMi4 SMi3 SiBRG register
CLK SMi6 SMi6
polarity SI/Oi
CLKi reversing
SI/O counter i
interrupt request
circuit

SMi2
SMi3
SMi5 LSB MSB
SOUTi

SINi SiTRR register

Note: i = 3, 4.
n = A value set in the SiBRG register.

Figure 1.21.1. SI/O3 and SI/O4 Block Diagram

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SI/O3, SI/O4

S I/Oi control register (i = 3, 4) (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
S3C 036216 010000016
S4C 036616 010000016
Bit Bit name Description RW
symbol
b1 b0
SMi0 Internal synchronous 0 0 : Selecting f1SIO or f2SIO RW
clock select bit 0 1 : Selecting f8SIO
SMi1 1 0 : Selecting f32SIO
RW
1 1 : Must not be set.
SMi2 SOUTi output disable bit 0 : SOUTi output
(Note 4) RW
1 : SOUTi output disable(high impedance)
SMi3 S I/Oi port select bit 0 : Input/output port
RW
1 : SOUTi output, CLKi function
CLK polarity select bit 0 : Transmit data is output at falling edge of
SMi4
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of RW
transfer clock and receive data is input at
falling edge

SMi5 Transfer direction select 0 : LSB first

RW
bit 1 : MSB first
SMi6 Synchronous clock 0 : External clock (Note 2)
RW
select bit 1 : Internal clock (Note 3)
SMi7 SOUTi initial value Effective when SMi3 = 0
set bit 0 : “L” output RW
1 : “H” output
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 3: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 4: When the SMi2 bit is set to “1”, the target pin goes to a high-impedance state regardless of which function of the
pin is being used.

SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)

b7 b0 Symbol Address After reset
S3BRG 036316 Indeterminate
S4BRG 036716 Indeterminate

Description Setting range RW

Assuming that set value = n, BRGi divides the count 0016 to FF16 WO
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.

SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)

b7 b0 Symbol Address After reset
S3TRR 036016 Indeterminate
S4TRR 036416 Indeterminate

Description RW
Transmission/reception starts by writing transmit data to this register. After
RW
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).

Figure 1.21.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers

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SI/O3, SI/O4

Table 1.21.1. SI/O3 and SI/O4 Specifications

Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register 0016 to FF16.
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
Transmission/reception • Before transmission/reception can start, the following requirements must be met
start condition Write transmit data to the SiTRR register (Notes 2, 3)
Interrupt request • When SiC register's SMi4 bit = 0
generation timing The rising edge of the last transfer clock pulse (Note 4)
• When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
CLKi pin fucntion I/O port, transfer clock input, transfer clock output
SOUTi pin function I/O port, transmit data output, high-impedance
SINi pin function I/O port, receive data input
Select function • LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not tranmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-
fore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SI/O3, SI/O4

(a) SI/Oi Operation Timing

Figure 1.21.3 shows the SI/Oi operation timing

1.5 cycle (max) (Note 3)

"H"
SI/Oi internal clock "L"

CLKi output "H"

"L"

Signal written to the "H"

SiTRR register "L"

(Note 2)
SOUTi output "H"
"L"
D0 D1 D2 D3 D4 D5 D6 D7

"H"
SINi input
"L"

SiIC register "1"

IR bit "0"

i= 3, 4

Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.

Figure 1.21.3. SI/Oi Operation Timing

(b) CLK Polarity Selection

The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.21.4 shows
the polarity of the transfer clock.

(1) When SiC register's SMi4 bit = “0”

CLKi (Note 2)

SINi D0 D1 D2 D3 D4 D5 D6 D7

SOUTi D0 D1 D2 D3 D4 D5 D6 D7

(2) When SiC register's SMi4 bit = “1”

CLKi (Note 3)

SINi D0 D1 D2 D3 D4 D5 D6 D7

SOUTi D0 D1 D2 D3 D4 D5 D6 D7
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.

Figure 1.21.4. Polarity of Transfer Clock

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SI/O3, SI/O4

(c) Functions for Setting an SOUTi Initial Value

If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. Figure 1.21.5 shows the timing chart for setting an SOUTi initial value and how to set it.

(Example) When “H” selected for SOUTi initial value (Note 1)

Setting of the initial value of SOUTi

Signal written to
output and starting of transmission/
SiTRR register
reception

SMi7 bit
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)

SMi3 bit

Set the SMi7 bit to “1”

(SOUTi initial value = “H”)
D0
SOUTi (internal)

Set the SMi3 bit to “1”

Port output D0 (SOUTi pin functions as SOUTi output)
SOUTi pin output
Initial value = “H” (Note 3) “H” level is output
(i = 3, 4) from the SOUTi pin
Setting the SOUTi Port selection switching
initial value to “H” (I/O port SOUTi) Write to the SiTRR register
(Note 2)

Note 1: This diagram applies to the case where the SiC register bits are set as follows:
Serial transmit/reception starts
SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)
Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC
register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or
in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.

Figure 1.21.5. SOUTi’s Initial Value Setting

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D Converter
The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95,
___________
P96, P00 to P07, and P20 to P27. Similarly, ADTRG input shares the pin with P97. Therefore, when using
these inputs, make sure the corresponding port direction bits are set to “0” (= input mode).
When not using the A-D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7).
Table 1.22.1 shows the performance of the A-D converter. Figure 1.22.1 shows the block diagram of the
A-D converter, and Figures 1.22.2 and 1.22.3 show the A-D converter-related registers.
Table 1.22.1. Performance of A-D Converter
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC1)
Operating clock φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
Resolution 8-bit or 10-bit (selectable)
Integral nonlinearity error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±3LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±7LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±5LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±7LSB
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN00 to AN07)
+ 8 pins (AN20 to AN27)
A-D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
• External trigger___________
(retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Operation clock frequency (φAD frequency) must be 10 MHz or less.
A case without sample and hold function turn (φAD frequency) into 250kHz or more .
A case with the sample and hold function turn (φAD frequency) into 1MHz or more.
Note 3: If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D conversion rate

selection
CKS1=1
CKS2=0
CKS0=1 øAD
1/2 1/2 CKS1=0
fAD 1/3 CKS0=0
CKS2=1

TRG=0
Software trigger
A-D trigger
ADTRG
TRG=1

VREF
VCUT=0 Resistor ladder
AVSS
VCUT=1

Successive conversion register

ADCON1 register

ADCON0 register

AD0 register (16)

AD1 register (16)
AD2 register (16)
AD3 register (16) Decoder
for A-D register
AD4 register (16)
AD5 register (16)
AD6 register (16)
AD7 register (16)

Data bus high-order

Data bus low-order ADCON2 register

(address 03D416)
PM00
PM01 Vref
(Note)
Decoder
for channel
selection
Comparator
VIN

Port P10 group CH2 to CH0

=0002
AN0 ADGSEL1 to ADGSEL0=002
=0012 OPA1 to OPA0=002
AN1 =0102
Port P0 group AN2
CH2 to CH0 =0112
AN3 =1002
=0002
AN00 AN4
=0012 =1012 PM01 to PM00=002
AN01 AN5 =1102
=0102 ADGSEL1 to ADGSEL0=102
AN02 AN6
=0112 =1112 OPA1 to OPA0=002
AN03 AN7
=1002
AN04
AN05 =1012
=1102
AN06
AN07 =1112 PM01 to PM00=002
ADGSEL1 to ADGSEL0=112
OPA1 to OPA0=002
Port P2 group CH2 to CH0
=0002
AN20 =0012
AN21 =0102
AN22 =0112 ADGSEL1 to ADGSEL0=002
AN23 =1002 OPA1 to OPA0=112
AN24 =1012
AN25 =1102 PM01 to PM00=002
AN26 =1112 ADGSEL1 to ADGSEL0=102
AN27 OPA1 to OPA0=112

PM01 to PM00=002
ADGSEL1 to ADGSEL0=112
OPA1 to OPA0=112 OPA1 to OPA0
ANEX0 OPA0=1 =012

OPA1=1 OPA1=1
ANEX1

Note: Port P0 group (AN00 to AN07) can be used as analog input pins even when PM01
to PM00 bits are set to “012” (memory expansion mode) and PM05 to PM04 bits are
set to “112” (multiplex bus allocated to the entire CS space).

Figure 1.22.1. A-D Converter Block Diagram

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

CH0 Analog input pin select bit Function varies with each operation mode RW

CH1 RW

CH2 RW
b4 b3
A-D operation mode 0 0 : One-shot mode
MD0 RW
select bit 0 0 1 : Repeat mode
1 0 : Single sweep mode
MD1 1 1 : Repeat sweep mode 0 or RW
Repeat sweep mode 1
TRG Trigger select bit 0 : Software trigger
1 : ADTRG trigger RW

ADST A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started RW

CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW

Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
ADCON1 03D716 0016

Bit symbol Bit name Function RW

A-D sweep pin select bit Function varies with each operation mode
SCAN0 RW

SCAN1
RW

A-D operation mode 0 : Any mode other than repeat sweep

MD2 select bit 1 mode 1 RW
1 : Repeat sweep mode 1
8/10-bit mode select bit 0 : 8-bit mode
BITS RW
1 : 10-bit mode

CKS1 Frequency select bit 1 See Note 3 for the ADCON2 register RW

VCUT Vref connect bit (Note 2) 0 : Vref not connected

RW
1 : Vref connected
External op-amp Function varies with each operation mode
OPA0 RW
connection mode bit

OPA1 RW

Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.2. ADCON0 to ADCON1 Registers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D control register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 ADCON2 03D416 0016

Bit symbol Bit name Function RW

A-D conversion method 0 : Without sample and hold
SMP RW
select bit 1 : With sample and hold
b2 b1
ADGSEL0 A-D input group select bit 0 0 : Port P10 group is selected RW
0 1 : Must not be set
1 0 : Port P0 group is selected (Note 3)
ADGSEL1 1 1 : Port P2 group is selected RW

(b3) Reserved bit Must always be set to “0” RW

Frequency select bit 2 0: Selects fAD, fAD divided by 2, or fAD

CKS2 divided by 4. RW
(Note 3)
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.

Nothing is assigned. In an attempt to write to these bits, write “0”.

(b7-b5) The value, if read, turns out to be “0”.
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
Note 3: The ØAD frequency must be 10 MHz or less. The selected ØAD frequency is determined by a combination of
the ADCON0 register's CKS0 bit, ADCON1 register's CKS1 bit, and ADCON2 register's CKS2 bit.

CKS2 CKS1 CKS0 ØAD

0 0 0 Divide-by-4 of fAD
0 0 1 Divide-by-2 of fAD
0 1 0 fAD
0 1 1
1 0 0 Ddivide-by-12 of fAD
1 0 1 Divide-by-6 of fAD
1 1 0 Divide-by-3 of fAD
1 1 1

A-D register i (i=0 to 7) Symbol Address After reset

AD0 03C116 to 03C016 Indeterminate
AD1 03C316 to 03C216 Indeterminate
AD2 03C516 to 03C416 Indeterminate
AD3 03C716 to 03C616 Indeterminate
AD4 03C916 to 03C816 Indeterminate
AD5 03CB16 to 03CA16 Indeterminate
AD6 03CD16 to 03CC16 Indeterminate
AD7 03CF16 to 03CE16 Indeterminate
(b15) (b8)
b7 b0 b7 b0

Function
When the ADCON1 register's When the ADCON1 register's RW
BITS bit is “1” (10-bit mode) BITS bit is “0” (8-bit mode)
Eight low-order bits of A-D conversion result
A-D conversion result RO

Two high-order bits of When read, the content is

A-D conversion result indeterminate RO
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.

Figure 1.22.3. ADCON2 Register, and AD0 to AD7 Registers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

(1) One-shot Mode

In this mode, the input voltage on one selected pin is A-D converted once. Table 1.22.2 shows the
specifications of one-shot mode. Figure 1.22.4 shows the ADCON0 to ADCON1 registers in one-shot
mode.
Table 1.22.2. One-shot Mode Specifications
Item Specification
Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted once.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition • Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A-D conversion
Analog input pin (Note) Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: If VCC2 < VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 0 ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

b2 b1 b0
CH0 Analog input pin select
bit 0 0 0 : AN0 is selected RW
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
CH1 0 1 1 : AN3 is selected RW
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
CH2 1 1 0 : AN6 is selected (Note 2) RW
1 1 1 : AN7 is selected (Note 3)
MD0 A-D operation mode b4 b3
RW
0 0 : One-shot mode (Note 3)
MD1 select bit 0 RW
Trigger select bit 0 : Software trigger
TRG RW
1 : ADTRG trigger
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started RW
CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.

A-D control register 1 (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 0 ADCON1 03D716 0016

Bit symbol Bit name Function RW

SCAN0 A-D sweep pin Invalid in one-shot mode RW
select bit
SCAN1 RW
MD2 A-D operation mode Set to “0” when one-shot mode is selected RW
select bit 1

BITS 8/10-bit mode select bit 0 : 8-bit mode RW

1 : 10-bit mode

CKS1 Frequency select bit1 See Note 3 for the ADCON2 register RW

VCUT Vref connect bit (Note 2) 1 : Vref connected RW

b7 b6
OPA0 External op-amp
connection mode bit 0 0 : ANEX0 and ANEX1 are not used RW
0 1 : ANEX0 input is A-D converted
OPA1 1 0 : ANEX1 input is A-D converted RW
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.4. ADCON0 Register and ADCON1 Register (One-shot Mode)

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A-D Converter

(2) Repeat mode

In this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 1.22.3 shows the
specifications of repeat mode. Figure 1.22.5 shows the ADCON0 to ADCON1 registers in repeat mode.

Table 1.22.3. Repeat Mode Specifications

Item Specification
Function The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted repeatdly.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pin (Note) Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: If VCC2 < VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.

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A-D Converter

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
0 1 ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

b2 b1 b0
Analog input pin
CH0 0 0 0 : AN0 is selected RW
select bit
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
CH1 0 1 1 : AN3 is selected RW
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
CH2 1 1 0 : AN6 is selected (Note 2) RW
1 1 1 : AN7 is selected (Note 3)
MD0 A-D operation mode
b4 b3
RW
select bit 0 0 1 : Repeat mode (Note 3)
MD1 RW
TRG Trigger select bit 0 : Software trigger
1 : ADTRG trigger
RW

ADST A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started RW

CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 0 ADCON1 03D716 0016

Bit symbol Bit name Function RW

SCAN0 A-D sweep pin Invalid in repeat mode RW
select bit
SCAN1 RW
A-D operation mode Set to “0” when this mode is selected
MD2 RW
select bit 1
8/10-bit mode select bit 0 : 8-bit mode
BITS 1 : 10-bit mode
RW

CKS1 Frequency select bit 1 See Note 3 for the ADCON2 register RW

VCUT Vref connect bit (Note 2) 1 : Vref connected RW

OPA0 External op-amp b7 b6
0 0 : ANEX0 and ANEX1 are not used RW
connection mode bit
0 1 : ANEX0 input is A-D converted
OPA1 1 0 : ANEX1 input is A-D converted RW
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.5. ADCON0 Register and ADCON1 Register (Repeat Mode)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

(3) Single Sweep Mode

In this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 1.22.4 shows
the specifications of single sweep mode. Figure 1.22.6 shows the ADCON0 to ADCON1 registers in
single sweep mode.

Table 1.22.4. Single Sweep Mode Specifications

Item Specification
Function The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D con-
verted, one pin at a time.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition • Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A-D conversion
Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.

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A-D Converter

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 0 ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

CH0 Analog input pin Invalid in single sweep mode
RW
select bit
CH1 RW

CH2 RW
b4 b3
MD0 A-D operation mode RW
1 0 : Single sweep mode
select bit 0
MD1 RW

TRG Trigger select bit 0 : Software trigger

RW
1 : ADTRG trigger
A-D conversion start flag 0 : A-D conversion disabled
ADST RW
1 : A-D conversion started
CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 0 ADCON1 03D716 0016

Bit symbol Bit name Function RW

SCAN0 A-D sweep pin select bit When single sweep mode is selected RW
b1 b0
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
SCAN1 1 0 : AN0 to AN5 (6 pins) RW
1 1 : AN0 to AN7 (8 pins) (Note 2)
A-D operation mode Set to “0” when single sweep mode is selected
MD2 select bit 1 RW

8/10-bit mode select bit 0 : 8-bit mode

BITS RW
1 : 10-bit mode
CKS1 Frequency select bit 1 See Note 3 for the ADCON2 register RW
VCUT Vref connect bit (Note 3) 1 : Vref connected RW
b7 b6
OPA0 External op-amp
connection mode 0 0 : ANEX0 and ANEX1 are not used RW
bit 0 1 : Must not be set
OPA1 1 0 : Must not be set RW
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.6. ADCON0 Register and ADCON1 Register (Single Sweep Mode)

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A-D Converter

(4) Repeat Sweep Mode 0

In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 1.22.5 shows the
specifications of repeat sweep mode 0. Figure 1.22.7 shows the ADCON0 to ADCON1 registers in repeat
sweep mode 0.

Table 1.22.5. Repeat Sweep Mode 0 Specifications

Item Specification
Function The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D con-
verted repeatdly.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 1 ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

CH0 Analog input pin Invalid in repeat sweep mode 0 RW
select bit
CH1 RW

CH2 RW
b4 b3
MD0 A-D operation mode RW
1 1 : Repeat sweep mode 0 or
select bit 0 Repeat sweep mode 1
MD1 RW

TRG Trigger select bit 0 : Software trigger

1 : ADTRG trigger
RW
A-D conversion start flag 0 : A-D conversion disabled
ADST RW
1 : A-D conversion started

CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 0 ADCON1 03D716 0016

Bit symbol Bit name Function RW

A-D sweep pin select bit When repeat sweep mode 0 is selected
SCAN0 RW
b1 b0

0 0 : AN0, AN1 (2 pins)

0 1 : AN0 to AN3 (4 pins)
SCAN1 1 0 : AN0 to AN5 (6 pins) RW
1 1 : AN0 to AN7 (8 pins) (Note 2)
A-D operation mode Set to “0” when repeat sweep mode 0 is
MD2 select bit 1 selected RW

BITS 8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode
RW

CKS1 Frequency select bit 1 See Note 3 for the ADCON2 register RW

VCUT Vref connect bit (Note 3) 1 : Vref connected RW

b7 b6
OPA0 External op-amp 0 0 : ANEX0 and ANEX1 are not used RW
connection mode 0 1 : Must not be set
bit 1 0 : Must not be set
OPA1 RW
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.7. ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)

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A-D Converter

(5) Repeat Sweep Mode 1

In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the se-
lected pins. Table 1.22.6 shows the specifications of repeat sweep mode 1. Figure 1.22.8 shows the
ADCON0 to ADCON1 registers in repeat sweep mode 1.

Table 1.22.6. Repeat Sweep Mode 1 Specifications

Item Specification
Function The input voltages on all pins selected by the ADCON2 register's ADGSEL1 to
ADGSEL0 bits are A-D converted repeatdly, with priority given to pins se-
lected by the ADCON1 register's SCAN1 to SCAN0 bits and ADGSEL1 to
ADGSEL0 bits.
Example : If AN0 selected, input voltages are A-D converted in order of
AN0 AN1 AN0 AN2 AN0 AN3, and so on.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pins to be given Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3
priority when A-D converted (4 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 1 ADCON0 03D616 00000XXX2

Bit symbol Bit name Function RW

CH0 Analog input pin Invalid in repeat sweep mode 1
RW
select bit
CH1 RW

CH2 RW
b4 b3
MD0 A-D operation mode 1 1 : Repeat sweep mode 0 or RW
select bit 0 Repeat sweep mode 1
MD1 RW
TRG Trigger select bit 0 : Software trigger RW
1 : ADTRG trigger
A-D conversion start flag 0 : A-D conversion disabled
ADST RW
1 : A-D conversion started

CKS0 Frequency select bit 0 See Note 3 for the ADCON2 register RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
1 1 ADCON1 03D716 0016

Bit symbol Bit name Function RW

SCAN0 A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0 RW
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
SCAN1 1 0 : AN0 to AN2 (3 pins) RW
1 1 : AN0 to AN3 (4 pins) (Note 2)
A-D operation mode Set to “1” when repeat sweep mode 1 is
MD2 select bit 1 RW
selected

BITS 8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode
RW

CKS1 Frequency select bit 1 See Note 3 for the ADCON2 register RW

VCUT Vref connect bit (Note 3) 1 : Vref connected RW

b7 b6
OPA0 External op-amp
connection mode 0 0 : ANEX0 and ANEX1 are not used RW
bit 0 1 : Must not be set
OPA1 1 0 : Must not be set RW
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADCON2 register’s
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.

Figure 1.22.8. ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1)

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A-D Converter

(a) Resolution Select Function

The desired resolution can be selected using the ADCON1 register’s BITS bit. If the BITS bit is set to “1”
(10-bit conversion accuracy), the A-D conversion result is stored in the ADi register (i = 0 to 7)'s bit 0 to bit
9. If the BITS bit is set to “0” (8-bit conversion accuracy), the A-D conversion result is stored in the ADi
register's bit 0 to bit 7.
(b) Sample and Hold
If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is
increased to 28 ØAD cycles for 8-bit resolution or 33 ØAD cycles for 10-bit resolution. Sample-and-hold is
effective in all operation modes. Select whether or not to use the sample-and-hold function before starting
A-D conversion.
(c) Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the
ADCON1 register’s OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1.
The A-D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
(d) External Operation Amp Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the ADCON1 register’s OPA1 OPA0 bits to ‘112’ (external op-amp connection mode). The inputs from
ANi (i = 0 to 7) (Note 1) are output from the ANEX0 pin. Amplify this output with an external op-amp before
sending it back to the ANEX1 pin. The A-D conversion result is stored in the corresponding ADi register.
The A-D conversion speed depends on the response characteristics of the external op-amp. Note that the
ANXE0 and ANEX1 pins cannot be directly connected to each other. Figure 1.22.9 is an example of how
to connect the pins in external operation amp.

Note: AN0i and AN2i can be used the same as ANi. However, if VCC2 < VCC1, do not use AN0i and AN2i as
analog input pins.

Microcomputer
ADCON2 register's ADGSEL1 to ADGSEL0 bits=002
AN0
AN1 Resistor ladder
AN2
AN3
AN4
AN5 Successive conversion
AN6 register
AN7
ADGSEL1 to ADGSEL0 bits=102

AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
ADGSEL1 to ADGSEL0 bits=112

AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
ANEX0

ANEX1

Comparator
External op-
amp

Figure 1.22.9. External Op-amp Connection

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A-D Converter

(e) Current Consumption Reducing Function

When not using the A-D converter, its resistor ladder and reference voltage input pin (VREF) can be
separated using the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin
into the resistor ladder, helping to reduce the power consumption of the chip.
To use the A-D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s
ADST bit to “1” (A-D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A-D conversion.
Note that this does not affect VREF for the D-A converter (irrelevant).
(f) Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 1.22.10 shows analog input pin and external sensor equivalent circuit example.

Microcomputer

Sensor equivalent
circuit
R0 R (7.8kΩ)

VIN
C (1.5pF) Sampling time
3
VC Sample-and-hold function enabled:
fAD
2
Sample-and-hold function disabled:
fAD

Figure 1.22.10. Analog Input Pin and External Sensor Equivalent Circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter

D-A Converter
This is an 8-bit, R-2R type D-A converter. These are two independent D-A converters.
D-A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set
the DACON register’s DAiE bit to “1” (output enabled). Before D-A conversion can be used, the correspond-
ing port direction bit must be cleared to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from
the corresponding port.
Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.23.1 lists the performance of the D-A converter. Figure 1.23.1 shows the block diagram of the D-A
converter. Figure 1.23.2 shows the D-A converter related registers. Figure 1.23.3 shows the D-A converter
equivalent circuit.

Table 1.23.1. D-A Converter Performance

Item Performance
D-A conversion method R-2R method
Resolution 8 bits
Analog output pin 2 (DA0 and DA1)

Data bus low-order

DA0 register

R-2R resistor ladder

DA0E bit
AAAA DA0

DA1 register

R-2R resistor ladder

DA1E bit
AAAA DA1

Figure 1.23.1. D-A Converter Block Diagram

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D-A Converter

D-A control register (Note)

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
DACON 03DC16 0016

Bit symbol Bit name Function RW

DA0E D-A0 output enable bit 0 : Output disabled

1 : Output enabled RW

DA1E D-A1 output enable bit 0 : Output disabled

1 : Output enabled
RW

Nothing is assigned. In an attempt to write to these bits, write “0”.

(b7-b2) The value, if read, turns out to be “0”
Note: When not using the D-A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to ‘0016’ to prevent current from
flowing into the R-2R resistor ladder.

D-Ai register (Note) (i= 0 to 1)

Symbol Address After reset
b7 b0
DA0 03D816 Indeterminate
DA1 03DA16 Indeterminate

Function RW
R W
Output value of D-A conversion RW

Note: When not using the D-A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to ‘0016’ to prevent current from
flowing into the R-2R resistor ladder.

Figure 1.23.2. DACON Register, DA0 Register, and DA1 Register

DAiE bit
“0”
R R R R R R R R 2R
DAi
“1”

2R 2R 2R 2R 2R 2R 2R 2R

MSB LSB

DAi register
“0” “1”

AVSS
VREF

Note: The above diagram shows an instance in which the DA0 register is assigned “2A16”.

Figure 1.23.3. D-A Converter Equivalent Circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation

CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses
a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8
bit units. After the initial value is set in the CRCD register, the CRC code is set in that register each time one
byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two
cycles.
Figure 1.24.1 shows the block diagram of the CRC circuit. Figure 1.24.2 shows the CRC-related registers.
Figure 1.24.3 shows the calculation example using the CRC operation.

Data bus high-order

AAAAA AAAAAAA
Data bus low-order

AAAAAAAAAAA
Eight low-order bits Eight high-order bits

AAAAAAAAAAA
AAAAAAAAAAA
CRCD register

AAAAAAAAAAA CRC code generating circuit

AAAAAAAAAAA
x16 + x12 + x5 + 1

AAAAAA
AAAAAA CRCIN register

Figure 1.24.1. CRC Circuit Block Diagram

CRC data register

(b15) (b8)
b7 b0 b7 b0 Symbol Address After reset
CRCD 03BD16 to 03BC16 Indeterminate

Function Setting range RW

When data is written to the CRCIN register after setting 000016 to FFFF16 RW
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.

CRC input register

b7 b0 Symbo Address After reset
CRCIN 03BE16 Indeterminate

Function Setting range RW

Data input 0016 to FF16 RW

Figure 1.24.2. CRCD Register and CRCIN Register

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CRC Calculation

Setup procedure and CRC operation when generating CRC code “80C416”

(a) CRC operation performed by the M16C

CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 00012)

(b) Setting procedure

(1) Reverse the bit positions of the value “80C416” bytewise in a program.
“8016” → “0116”, “C416” → “2316”

b15 b0
(2) Write 000016 (initial value) CRCD register

b7 b0
(3) Write 0116 CRCIN register
Two cycles later, the CRC code for “8016,” i.e.,
918816, has its bit positions reversed to become
“118916” which is stored in the CRCD register.

b15 b0

118916 CRCD register

b7 b0

(4) Write 2316 CRCIN register

Two cycles later, the CRC code for “80C416,” i.e.,
825016, has its bit positions reversed to become
“0A4116” which is stored in the CRCD register.

b15 b0
0A4116 CRCD register

(c) Details of CRC operation

In the case of (3) above, the value written to the CRCIN register “0116 (000000012)” has its bit positions reversed to
become “100000002.” The value “1000 0000 0000 0000 0000 00002” derived from that by adding 16 digits and the
CRCD register’s initial value “000016” are added, the result of which is divided by the generator polynomial using
modulo-2 arithmetic.
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001 1000 0000 0000 0000 Data 0+0=0
0000 0000
1000 1000 0001 0000 1 0+1=1
Generator polynomial 1000 0001 0000 1000 0 1+0=1
1000 1000 0001 0000 1 1+1=0
-1 = 1
1001 0001 1000 1000

CRC code

The value “0001 0001 1000 10012 (118916)” derived from the remainder “1001 0001 1000 10002 (918816)” by
reversing its bit positions may be read from the CRCD register.

If operation (4) above is performed subsequently, the value written to the CRCIN register “2316 (001000112)” has its bit
positions reversed to become “110001002. The value “1100 0100 0000 0000 0000 00002” derived from that by adding
16 digits and the remainder in (3) “1001 0001 1000 10002” which is left in the CRCD register are added, the result of
which is divided by the generator polynomial using modulo-2 arithmetic.
The value “0000 1010 0100 00012 (0A4116)” derived from the remainder by reversing its bit positions may be read
from the CRCD register.

Figure 1.24.3. CRC Calculation

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Programmable I/O Ports SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Ports

The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 87 lines P0 to
P10 (except P85) for the 100-pin version, or 113 lines P0 to P14 (except P85) for the 128-pin version. Each
port can be set for input or output every line by using a direction register, and can also be chosen to be or
not be pulled high every 4 lines. P85 is an input-only port and does not have a pull-up resistor. Port P85
_______ ______
shares the pin with NMI, so that the NMI input level can be read from the P8 register P8_5 bit.
Figures 1.25.1 to 1.25.4 show the I/O ports. Figure 1.25.5 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input or D-A converter output pin, set the direction bit for that pin to “0” (input
mode). Any pin used as an output pin for peripheral functions other than the D-A converter is directed for
output no matter how the corresponding direction bit is set.
When using any pin as a bus control pin, refer to “Bus Control.”
P0 to P5, P12, and P13 are capable of VCC2-level input/output; P6 to P11 and P14 are capable of VCC1-
level input/output.
(1) Port Pi Direction Register (PDi Register, i = 0 to 13)
Figure 1.25.6 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______ _______ _______ _________ ______ __________________ _________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 0 to 13)
Figure 1.25.7 and 1.25.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______ _______ _______ _________ ______ __________________ _________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 1.25.9 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high
in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory
extension and microprocessor modes. Although the register contents can be modified, no pull-up resis-
tors are connected.
(4) Port Control Register
Figure 1.25.10 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.

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Pull-up selection

Direction register
P00 to P07, P20 to P27 (inside dotted-line
included)

Data bus Port latch

P30 to P37, P40 to P47,
P50 to P54, P56,
(Note 1)
P110 to P117(Note 2), (inside dotted-line
P120 to P127(Note 2), not included)
P130 to P137(Note 2),
P140, P141(Note 2)

Analog input

Pull-up selection

P10 to P14 Direction register

Port P1 control register

Data bus Port latch

(Note 1)

Pull-up selection

Direction register
P15 to P17

Port P1 control register

Data bus Port latch

(Note 1)

Input to respective peripheral functions

Pull-up selection
Direction
P57, P60, P64, P73 to P76, register
"1"
P80, P81, P90, P92
Output
Data bus Port latch

(Note 1)

Input to respective peripheral functions

Note 1: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Note 2: Available in only the 128-pin version.

Figure 1.25.1. I/O Ports (1)

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Pull-up selection
Direction
P61, P65, P72 register
"1"

Output
Data bus Port latch

Switching (Note 1)
between
CMOS and
Nch

Input to respective peripheral functions

Pull-up selection
P82 to P84
Direction register

Data bus Port latch

(Note 1)

Input to respective peripheral functions

Pull-up selection

Direction register
P55, P77, P91, P97

Data bus Port latch

(Note 1)

Input to respective peripheral functions

Note 1: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Note 2: Available in only the 128-pin version.

Figure 1.25.2. I/O Ports (2)

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Pull-up selection

Direction register
P62, P66

Data bus Port latch

(Note 1)
Switching
between
CMOS and Nch

Input to respective peripheral functions

Pull-up selection

Direction register
P63, P67
“1”

Output
Data bus Port latch

(Note 1)

Switching between CMOS and Nch

P85
Data bus

NMI interrupt input (Note 1)

Direction register
P70, P71
“1”

Output
Data bus Port latch

(Note 2)

Input to respective peripheral functions

Note 1: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Note 2: symbolizes a parasitic diode.

Figure 1.25.3. I/O Ports (3)

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Pull-up selection
P100 to P103
(inside dotted-line
Direction register
not included)
P104 to P107
(inside dotted-line
included)
Data bus Port latch
(Note)

Analog input
Input to respective peripheral functions

Pull-up selection
D-A output enabled
Direction register
P93, P94

Data bus Port latch

(Note)

Input to respective peripheral functions

Analog output
D-A output enabled

Pull-up selection

P96 Direction register

“1”

Output
Data bus Port latch

(Note)

Analog input

Pull-up selection

Direction register
P95 “1”

Output
Data bus Port latch
(Note)

Input to respective peripheral functions

Analog input

Note: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.

Figure 1.25.4. I/O Ports (4)

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Pull-up selection

Direction register
P87

Data bus Port latch

(Note)

fc

Rf

Pull-up selection

Rd
Direction register
P86
"1"

Output
Data bus Port latch
(Note)

Note: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.
VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.

Figure 1.25.5. I/O Ports (5)

BYTE (Note 2)
BYTE signal input
(Note 1)

CNVSS (Note 2)
CNVSS signal input
(Note 1)

RESET
RESET signal input
(Note 1)

Note 1: symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC1.
Note 2: A parasitic diode on the VCC1 side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed VCC1.

Figure 1.25.6. I/O Pins

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Port Pi direction register (i=0 to 7 and 9 to 13) (Note 1, 2, 3)

Symbol Address After reset
PD0 to PD3 03E216, 03E316, 03E616, 03E716 0016
b7 b6 b5 b4 b3 b2 b1 b0
PD4 to PD7 03EA16, 03EB16, 03EE16, 03EF16 0016
PD9 to PD12 03F316, 03F616, 03F716, 03FA16 0016
PD13 03FB16 0016
Bit symbol Bit name Function RW
PDi_0 Port Pi0 direction bit RW
PDi_1 Port Pi1 direction bit 0 : Input mode
RW
(Functions as an input port)
PDi_2 Port Pi2 direction bit 1 : Output mode RW
PDi_3 Port Pi3 direction bit (Functions as an output port) RW
PDi_4 Port Pi4 direction bit (i = 0 to 7 and 9 to 13) RW
PDi_5 Port Pi5 direction bit RW
PDi_6 Port Pi6 direction bit RW
PDi_7 Port Pi7 direction bit RW
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register’s PRC2 bit to “1” (write enabled).
Note 2: During memory extension and microprocessor modes, the PD register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 pins are placed in the high-impedance state.

Port P8 direction register

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PD8 03F216 00X000002

Bit symbol Bit name Function RW

PD8_0 Port P80 direction bit RW
PD8_1 Port P81 direction bit 0 : Input mode
(Functions as an input port) RW
PD8_2 Port P82 direction bit 1 : Output mode RW
PD8_3 Port P83 direction bit (Functions as an output port) RW
PD8_4 Port P84 direction bit RW
Nothing is assigned. In an attempt to write to this bit, write “0”.
(b5) The value, if read, turns out to be indeterminate.

PD8_6 Port P86 direction bit 0 : Input mode RW

(Functions as an input port)
1 : Output mode
PD8_7 Port P87 direction bit (Functions as an output port) RW

Figure 1.25.7. PD0 to PD13 Registers

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Port Pi register (i=0 to 7 and 9 to 13) (Note 2, 3)

Symbol Address After reset
b7 b6 b5 b4 b3 b2 b1 b0
P0 to P3 03E016, 03E116, 03E416, 03E516 Indeterminate
P4 to P7 03E816, 03E916, 03EC16, 03ED16 Indeterminate
P9 to P12 03F116, 03F416, 03F516, 03F816 Indeterminate
P13 03F916 Indeterminate
Bit symbol Bit name Function RW
Pi_0 Port Pi0 bit The pin level on any I/O port which is RW
set for input mode can be read by
Pi_1 Port Pi1 bit RW
reading the corresponding bit in this
Pi_2 Port Pi2 bit register. RW
Pi_3 Port Pi3 bit The pin level on any I/O port which is RW
set for output mode can be controlled
Pi_4 Port Pi4 bit by writing to the corresponding bit in RW
Pi_5 Port Pi5 bit this register RW
0 : “L” level
Pi_6 Port Pi6 bit
1 : “H” level (Note 1)
RW
Pi_7 Port Pi7 bit (i = 0 to 7 and 9 to 13) RW
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 registers are cleared to ‘0016’ and the P11 to P14 pins are
placed in the high-impedance state.

Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
P8 03F016 Indeterminate

Bit symbol Bit name Function RW

P8_0 Port P80 bit RW
The pin level on any I/O port which is
P8_1 Port P81 bit set for input mode can be read by RW
P8_2 Port P82 bit reading the corresponding bit in this RW
register.
P8_3 Port P83 bit The pin level on any I/O port which is RW
P8_4 Port P84 bit set for output mode can be controlled RW
by writing to the corresponding bit in
P8_5 Port P85 bit
this register (except for P85)
RO
P8_6 Port P86 bit 0 : “L” level RW
P8_7 Port P87 bit 1 : “H” level RW

Figure 1.25.8. P0 to P13 Registers

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Port P14 control register (128-pin package)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PC14 03DE16 XX00XXXX2

Bit symbol Bit name Function RW

The pin level on any I/O port which is
P140 Port P140 bit set for input mode can be read by RW
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
P141 Port P141 bit by writing to the corresponding bit in RW
this register
0 : “L” level
1 : “H” level
Nothing is assigned. In an attempt to write to this bit, write “0”. The
(b3-b2) value, if read, turns out to be indeterminate.

PD140 Port P140 direction bit 0 : Input mode RW

(Functions as an input port)
1 : Output mode
PD141 Port P141 direction bit (Functions as an output port) RW

Nothing is assigned. In an attempt to write to this bit, write “0”. The

(b7-b6) value, if read, turns out to be indeterminate.

Pull-up control register 3 (128-pin package)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUR3 03DF16 0016

Bit symbol Bit name Function RW

PU30 P110 to P113 pull-up 0 : Not pulled high RW
PU31 P114 to P117 pull-up 1 : Pulled high (Note 1) RW
PU32 P120 to P123 pull-up RW
PU33 P124 to P127 pull-up RW
PU34 P130 to P133 pull-up RW
PU35 P134 to P137 pull-up RW
PU36 P140, P141 pull-up RW

PU37 P11 to P14 enabling bit 0 : Unusable (Note 2)

1 : Usable RW

Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 2: If the PU37 bit is set to “0” (unusable), the P11 to P14 pins are placed in the high-impedance state and
the P11 to P14 registers are cleared to “0”.

Figure 1.25.9. PC14 Register and PUR3 Register

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Pull-up control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUR0 03FC16 0016

Bit symbol Bit name Function RW

PU00 P00 to P03 pull-up RW
0 : Not pulled high
PU01 P04 to P07 pull-up 1 : Pulled high (Note 2) RW
PU02 P10 to P13 pull-up RW
PU03 P14 to P17 pull-up RW
PU04 P20 to P23 pull-up RW
PU05 P24 to P27 pull-up RW
PU06 P30 to P33 pull-up RW
PU07 P34 to P37 pull-up RW
Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their
corresponding register contents can be modified.
Note 2: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.

Pull-up control register 1

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset(Note 5)
PUR1 03FD16 000000002
000000102
Bit symbol Bit name Function RW
PU10 P40 to P43 pull-up (Note 2) 0 : Not pulled high RW
PU11 P44 to P47 pull-up (Note 4) 1 : Pulled high (Note 3) RW
PU12 P50 to P53 pull-up (Note 2) RW
PU13 P54 to P57 pull-up (Note 2) RW
PU14 P60 to P63 pull-up RW
PU15 P64 to P67 pull-up RW
PU16 P72 to P73 pull-up (Note 1) RW
PU17 P74 to P77 pull-up RW
Note 1: The P70 and P71 pins do not have pull-ups.
Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents
of these bits can be modified.
Note 3: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 4: If the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor mode) in a
program during single-chip mode, the PU11 bit becomes “1”.
Note 5: The values after hardware reset 1 and 2 are as follows:
• 000000002 when input on CNVss pin is “L“
• 000000102 when input on CNVss pin is “H“
The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows:
• 000000002 when PM 01 to PM00 bits of PM0 register are “002“ (single-chip mode)
• 000000102 when PM 01 to PM00 bits of PM0 register are “012“ (memory expansion mode) or
“112“ (microprocessor mode)

Pull-up control register 2

b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address After reset
PUR2 03FE16 0016

Bit symbol Bit name Function RW

PU20 P80 to P83 pull-up 0 : Not pulled high RW
PU21 P84 to P87 pull-up (Note 2) 1 : Pulled high (Note 1) RW
PU22 P90 to P93 pull-up RW
PU23 P94 to P97 pull-up RW
PU24 P100 to P103 pull-up RW
PU25 P104 to P107 pull-up RW
Nothing is assigned. In an attempt to write to these bits, write
(b7-b6) “0”. The value, if read, turns out to be “0”.
Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 2: The P85 pin does not have pull-up.

Figure 1.25.10. PUR0 to PUR2 Registers

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Port control register

b7 b6 b5 b4 b3 b2 b1 b0
Symbpl Address After reset
PCR 03FF16 0016

Bit symbol Bit name Function RW

PCR0 Port P1 control bit Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17 RW
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
Nothing is assigned. In an attempt to write to these bits,
(b7-b1) write “0”. The value, if read, turns out to be “0”.

Figure 1.25.11. PCR Register

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Table 1.25.1. Unassigned Pin Handling in Single-chip Mode

Pin name Connection

Ports P0 to P7, P80 to P84, After setting for input mode, connect every pin to VSS via a resistor(pull-down);
P86 to P87, P9 to P14 or after setting for output mode, leave these pins open. (Note 1, 2 ,3)

XOUT (Note 4) Open

NMI Connect via resistor to VCC1 (pull-up)

AVCC Connect to VCC1

AVSS, VREF, BYTE Connect to VSS

Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 4: With external clock input to XIN pin.
Note 5: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3 register’s
PU37 bit to “0” (P11 to P14 unusable) without causing any problem.

Table 1.25.2. Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin name Connection

Ports P0 to P7, P80 to P84, After setting for input mode, connect every pin to VSS via a resistor (pull-down);
P86 to P87, P9 to P14 or after setting for output mode, leave these pins open. (Note 1, 2, 3, 4)

P45 / CS1 to P47 / CS3 Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
corresponding direction bit for CSi (i=1 to 3) to “0” (input mode) and the CSR
register’s CSi bit to “0” (chip select disabled).

BHE, ALE, HLDA, XOUT(Note 5), Open

BCLK (Note 6)

HOLD, RDY Connect via resistor to VCC2 (pull-up)

NMI (P85) Connect via resistor to VCC1 (pull-up)

AVCC Connect to VCC1

AVSS, VREF Connect to VSS

Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become
indeterminate, causing the power supply current to increase while they remain set for input ports.
Note 4: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 5: With external clock input to XIN pin.
Note 6: If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC2 via a resistor
(pulled high).
Note 7: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3 register’s
PU37 bit to “0” (P11 to P14 unusable) without causing any problem.

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Microcomputer Microcomputer
Port P0 to P14 (except for P85) Port P6 to P14 (except for P85)
(Note 2) (Note 2)
(Input mode) (Input mode)
· ·· · ··
· ·
· · · ·
(Input mode) (Input mode)
(Output mode) Open (Output mode) Open VCC1
VCC1 VCC2
NMI
NMI Port P45 / CS1 BHE
XOUT Open to P47 / CS3 HLDA
ALE Open
VCC1
XOUT VCC2
AVCC BCLK (Note)
BYTE HOLD VCC1

AVSS RDY

VREF AVCC
AVSS
VREF

VSS VSS
In single-chip mode In memory expansion mode or
in microprocessor mode

Note 1: If the PM0 register’s PM07 bit is set to “1” (BCLK not output), connect this pin to VCC2 via a resistor
(pulled high).
Note 2: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3
register’s PU37 bit to “0” (P11 to P14 unusable) without causing any problem.

Figure 1.25.12. Unassigned Pins Handling

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Electrical Characteristics

Electrical Characteristics
Table 1.26.1. Absolute Maximum Ratings
Symbol Parameter Condition Rated value Unit
VCC1, VCC2 Supply voltage VCC1=AVCC -0.3 to 6.5 V
VCC2 Supply voltage VCC2 -0.3 to VCC1+0.1 V
AVCC Analog supply voltage VCC1=AVCC -0.3 to 6.5 V
Input RESET, CNVSS, BYTE,
voltage P60 to P67, P72 to P77, P80 to P87,
P90 to P97, P100 to P107, P110 to P117, -0.3 to VCC1+0.3 V
P140, P141,
VI VREF, XIN
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57, -0.3 to VCC2+0.3 V
P120 to P127, P130 to P137
P70, P71 -0.3 to 6.5 V
Output P60 to P67, P72 to P77, P80 to P84,
voltage P86, P87, P90 to P97, P100 to P107,
-0.3 to VCC1+0.3 V
P110 to P117, P140, P141,
XOUT
VO
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57, -0.3 to VCC2+0.3 V
P120 to P127, P130 to P137
P70, P71 -0.3 to 6.5 V
Pd Power dissipation Topr=25 C 300 mW
Topr Operating ambient temperature -20 to 85 / -40 to 85 C
Tstg Storage temperature -65 to 150 C

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Electrical Characteristics

Table 1.26.2. Recommended Operating Conditions (Note 1)

Standard
Symbol Parameter Min. Typ. Max. Unit
VCC1, VCC2 Supply voltage(VCC1≥VCC2) 2.7 5.0 5.5 V
AVcc Analog supply voltage VCC1 V
Vss Supply voltage 0 V
AVss Analog supply voltage 0 V
HIGH input P31 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 0.8VCC2 VCC2 V
voltage P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) 0.8VCC2 VCC2 V
P00 to P07, P10 to P17, P20 to P27, P30
VIH 0.5VCC2 VCC2 V
(data input during memory expansion and microprocessor modes)
P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107,
P110 to P117, P140, P141, 0.8VCC1 VCC1 V
XIN, RESET, CNVSS, BYTE
P70 , P71 0.8VCC1 6.5 V
LOW input P31 to P37, P40 to P47, P50 to P57, P120 to P127, P130 to P137 0 0.2VCC2 V
voltage
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) 0 0.2VCC2 V
VIL P00 to P07, P10 to P17, P20 to P27, P30 0 0.16VCC2
(data input during memory expansion and microprocessor modes) V

P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107,
V
P110 to P117, P140, P141, 0 0.2VCC1
XIN, RESET, CNVSS, BYTE
HIGH peak output P00 to P07, P10 to P17, P20 to P27,P30 to P37,
I OH (peak) current P40 to P47, P50 to P57, P60 to P67,P72 to P77, -10.0 mA
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117, P120 to P127, P130 to P137, P140, P141
HIGH average P00 to P07, P10 to P17, P20 to P27,P30 to P37,
I OH (avg) output current P40 to P47, P50 to P57, P60 to P67,P72 to P77, -5.0 mA
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117, P120 to P127, P130 to P137, P140, P141
LOW peak output P00 to P07, P10 to P17, P20 to P27,P30 to P37,
I OL (peak) current P40 to P47, P50 to P57, P60 to P67,P70 to P77, 10.0 mA
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117, P120 to P127, P130 to P137, P140, P141
LOW average P00 to P07, P10 to P17, P20 to P27,P30 to P37,
I OL (avg) output current P40 to P47, P50 to P57, P60 to P67,P70 to P77, 5.0 mA
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117, P120 to P127, P130 to P137, P140, P141
Main clock input oscillation frequency VCC1=3.0 to 5.5V 0 16 MHz
f (XIN)
(Note 4) VCC1=2.7 to 3.0V 0 20 X VCC1-44 MHz
f (XCIN) Sub-clock oscillation frequency 32.768 50 kHz
f (Ring) Ring oscillation frequency 1 MHz
f (PLL) PLL clock oscillation frequency (Note 4) VCC1=3.0 to 5.5V 10 24 MHz
VCC1=2.7 to 3.0V 10 46.67 X VCC1- MHz
116
f (BCLK) CPU operation clock 0 24 MHz
TSU(PLL) PLL frequency synthesizer stabilization wait time VCC1=5.0V 20 ms
VCC1=3.0V 50 ms
Note 1: Referenced to VCC = VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P140 and P141 must be 80mA max. The total IOL (peak)
for ports P3, P4, P5, P6, P7, P80 to P84, P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2
must be -40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for
ports P6, P7, and P80 to P84 must be -40mA max. The total IOH (peak) for ports P86, P87, P9, P10, P11, P140, and P141
must be -40mA max.
Note 4: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
f(XIN) operating maximum frequency [MHZ]

f(PLL) operating maximum frequency [MHZ]

AAAAAA
Main clock input oscillation frequency PLL clock oscillation frequency
46.67 x VCC1-116MHZ

AAAAAA
20 x VCC1-44MHZ 24.0

16.0
AAAAAA
AAAAAA
AAAAAA
AAAAAA
10.0
AAAAAA
AAAAAA
10.0
AAAAAA
0.0
AAAAAA
AAAAAA
2.7 3.0 5.5
0.0
2.7 3.0 5.5
VCC1[V] (main clock: no division) VCC1[V] (PLL clock oscillation)

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Electrical Characteristics

Table 1.26.3. A-D Conversion Characteristics (Note 1)

Standard
Symbol Parameter Measuring condition Unit
Min. Typ. Max.
– Resolution VREF =VCC1 10 Bits
AN0 to AN7 input ±3 LSB
VREF= ANEX0, ANEX1 input
VCC1= External operation amp
Integral 5V ±7 LSB
INL non- connection mode
10 bit
linearity AN00 to AN07 input
error AN20 to AN27 input

AN0 to AN7 input ±5 LSB

VREF=
VCC1= ANEX0, ANEX1 input
3.3V External operation amp
connection mode ±7 LSB
AN00 to AN07 input
AN20 to AN27 input

8 bit VREF =VCC1=3.3V ±2 LSB

AN0 to AN7 input ±3 LSB
VREF= ANEX0, ANEX1 input
VCC1= External operation amp
5V connection mode ±7 LSB
– Absolute 10 bit AN00 to AN07 input
accuracy AN20 to AN27 input

AN0 to AN7 input ±5 LSB

VREF=
VCC1= ANEX0, ANEX1 input
3.3V External operation amp
connection mode ±7 LSB
AN00 to AN07 input
AN20 to AN27 input

8 bit VREF =VCC1=3.3V ±2 LSB

DNL Differential non-linearity error ±1 LSB
– Offset error ±3 LSB
– Gain error ±3 LSB
RLADDER Ladder resistance VREF =VCC1 10 40 kΩ
tCONV Conversion time(10bit), Sample & hold VREF =VCC1=5V, øAD=10MHz 3.3 µs
function available
tCONV Conversion time(8bit), Sample & hold VREF =VCC1=5V, øAD=10MHz 2.8 µs
function available
tSAMP Sampling time 0.3 µs
VREF Reference voltage 2.0 VCC1 V
VIA Analog input voltage 0 VREF V
Note 1: Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: If VCC1 > VCC2, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
Note 3: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC1 is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 4: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 3.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 3.

Table 1.26.4. D-A Conversion Characteristics (Note 1)

Standard
Symbol Parameter Measuring condition Unit
Min. Typ. Max.
– Resolution 8 Bits
– Absolute accuracy 1.0 %
tsu Setup time 3 µs
RO Output resistance 4 10 20 kΩ
IVREF Reference power supply input current (Note 2) 1.5 mA
Note 1: Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The
A-D converter’s ladder resistance is not included. Also, when D-A register contents are not “0016”, the current
IVREF always flows even though Vref may have been set to be unconnected by the A-D control register.

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Electrical Characteristics

Table 1.26.5. Flash Memory Version Electrical Characteristics (Note 1) 100 times guarantee article

Symbol Standard
Parameter Measuring condition Unit
Min. Typ. Max
– Word program time 30 200 µs
– Block erase time 1 4 s
– Erase all unlocked blocks time 1Xn 4Xn s
– Lock bit program time 30 200 µs
tPS Flash memory circuit stabilization wait time 15 µs
Note 1: Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C unless otherwise specified.
Note 2: n denotes the number of block erases.

Table 1.26.6. Flash Memory Version Electrical Characteristics (Note 1) 10000 times guarantee article
(block1 and block A(Note 3))

Symbol Standard
Parameter Measuring condition Unit
Min. Typ. Max
– Word program time 30 T.B.D µs
– Block erase time 1 T.B.D s
– Erase all unlocked blocks time 1Xn T.B.D s
– Lock bit program time 30 T.B.D µs
tPS Flash memory circuit stabilization wait time 15 µs
Note 1: Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C unless otherwise specified.
Note 2: n denotes the number of block erases.
Note 3: Shown here are the rated values for block 1 and block A when they have been programmed and erased more
than 1,000 times. The rated values up to 1,000 times of programming and erasure are the same for all blocks
as those products that are guaranteed of 100 times of programming and erasure.

Table 1.26.7. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60oC)
Flash program, erase voltage Flash read operation voltage
VCC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V VCC1=2.7 to 5.5 V

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Electrical Characteristics

Table 1.26.8. Low Voltage Detection Circuit Electrical Characteristics (Note 1)

Symbol Parameter Measuring condition Standard
Unit
Min. Typ. Max.
Vdet4 Voltage down detection voltage (Note 1) 3 .3 3 .8 4 .4 V
Vdet3 Reset level detection voltage (Notes 1, 2) 2 .2 2 .8 3 .6 V

Vdet3s Low voltage reset retention voltage VCC1=0.8 to 5.5V 0 .8 V

Vdet3r Low voltage reset release voltage (Note 3) 2 .2 2 .9 4 .0 V
Vdet2 RAM retention limit detection voltage (Note 1) 1.4 2 .0 2 .7 V
Note 1: Vdet4 > Vdet3 > Vdet2
Note 2: Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the
operation at f(BCLK) ≤ 10MHz is guaranteed.
Note 3: Vdet3r > Vdet3 is not guaranteed.

Table 1.26.9. Power Supply Circuit Timing Characteristics

Symbol Parameter Measuring condition Standard
Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during powering-on 2 ms
td(R-S) STOP release time 150 µs
VCC1=2.7 to 5.5V
td(W-S) Low power dissipation mode wait mode release time 150 µs
td(M-L) Time for internal power supply stabilization when main clock oscillation starts 50 µs
td(S-R) Hardware reset 2 release wait time VCC1=Vdet3r to 5.5V 6 (Note) 20 ms
td(E-A) Low voltage detection circuit operation start time VCC1=2.7 to 5.5V 20 µs
Note : When VCC1 = 5V

VCC1 Vdet3r

td(S-R)

Interrupt for
stop mode
release

CPU clock

td(R-S)

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Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Table 1.26.10. Electrical Characteristics (Note 1)
Symbol Parameter Measuring condition Standard
Unit
Min. Typ. Max.
HIGH output P60 to P67,P72 to P77,P80 to P84,P86,P87,P90 to P97,
voltage IOH=-5mA VCC1-2.0 VCC1
P100 to P107,P110 to P117,P140,P141
VOH V
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
IOH=-5mA(Note 2) VCC2-2.0 VCC2
P40 to P47,P50 to P57,P120 to P127,P130 to P137
HIGH output P60 to P67,P72 to P77,P80 to P84,P86,P87,P90 to P97, VCC1-0.3
IOH=-200µA VCC1
voltage P100 to P107,P110 to P117,P140,P141
VOH V
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
IOH=-200µA(Note 2) VCC2-0.3
P40 to P47,P50 to P57,P120 to P127,P130 to P137 VCC2
HIGHPOWER IOH=-1mA VCC1-2.0 VCC1
HIGH output voltage XOUT V
VOH
LOWPOWER IOH=-0.5mA VCC1-2.0 VCC1
HIGH output voltage XCOUT HIGHPOWER With no load applied 2.5 V
LOWPOWER With no load applied 1 .6
LOW output P60 to P67,P70 to P77,P80 to P84,P86,P87,P90 to P97,
IOL=5mA 2 .0
voltage P100 to P107,P110 to P117,P140,P141
VOL V
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
IOL=5mA(Note 2) 2 .0
P40 to P47,P50 to P57,P120 to P127,P130 to P137
LOW output P6 0 t o P6 7,P 7 0 t o P 7 7, P8 0 t o P8 4 ,P8 6 ,P 8 7,P9 0 t o P9 7 ,
IOL=200µA 0.45
voltage P100 to P107,P110 to P117,P140,P141
VOL V
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
IOL=200µA(Note 2) 0.45
P40 to P47,P50 to P57,P120 to P127,P130 to P137
HIGHPOWER IOL=1mA 2 .0
VOL LOW output voltage XOUT V
LOWPOWER IOL=0.5mA 2 .0
HIGHPOWER With no load applied 0
LOW output voltage XCOUT V
LOWPOWER With no load applied 0
Hysteresis HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
VT+-VT-
ADTRG, CTS0 to CTS2, SCL, SDA, 0.2 1.0 V
CLK0 to CLK4,TA2OUT to TA4OUT,
KI0 to KI3, RxD0 to RxD2, SIN3, SIN4
VT+-VT- Hysteresis RESET 0.2 2.2 V
HIGH input P00 to P07,P10 to P17,P20 to P27,P30 to P37,
current P40 to P47,P50 to P57,P60 to P67,P70 to P77,
II H P80 to P87,P90 to P97,P100 to P107,P110 to P117, VI=5V 5 .0 µA
P120 to P127,P130 to P137,P140,P141,
XIN, RESET, CNVss, BYTE

LOW input P00 to P07,P10 to P17,P20 to P27,P30 to P37,

current P40 to P47,P50 to P57,P60 to P67,P70 to P77,
IIL P80 to P87,P90 to P97,P100 to P107,P110 to P117, VI=0V -5.0 µA
P120 to P127,P130 to P137,P140,P141,
XIN, RESET, CNVss, BYTE

RPULLUP Pull-up P00 to P07,P10 to P17,P20 to P27,P30 to P37,

resistance P40 to P47,P50 to P57,P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107, VI=0V 30 50 170 kΩ
P110 to P117,P120 to P127,P130 to P137,P140,P141
RfXIN Feedback resistance XIN 1.5 MΩ
RfXCIN Feedback resistance XCIN 15 MΩ
VRAM RAM retention voltage At stop mode 2 .0 V

Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.
Note 2: Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on the VCC2 port side.

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Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Table 1.26.11. Electrical Characteristics (2) (Note 1)
Symbol Parameter Measuring condition Standard
Unit
Min. Typ. Max.
In single-chip mode, the output Mask ROM f(BCLK)=24MHz,
14 20 mA
pins are open and other pins are No division, PLL operation
VSS No division, Ring oscillation
1 mA

Flash memory f(BCLK)=24MHz,

18 27 mA
No division, PLL operation

No division, Ring oscillation 1.8 mA

Flash memory f(BCLK)=10MHz,
15 mA
Program VCC1=5.0V
Flash memory f(BCLK)=10MHz,
25 mA
Erase VCC1=5.0V
Mask ROM f(XCIN)=32kHz,
25 µA
Low power dissipation mode,
ICC Power supply current ROM(Note 3)
(VCC1=4.0 to 5.5V)
f(BCLK)=32kHz,
Flash memory
Low power dissipation mode, 25 µA
RAM(Note 3)
f(BCLK)=32kHz
Low power dissipation mode, 420 µA
Flash memory(Note 3)
Ring oscillation,
50 µA
Wait mode
f(BCLK)=32kHz,
7.5 µA
Wait mode (Note 2),
Mask ROM Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode(Note 2), 2 .0 µA
Oscillation capacity Low
Stop mode,
0.8 3.0 µA
Topr=25°C
Idet4 Voltage down detection dissipation current (Note 4) 0.7 4 µA
Idet3 Reset area detection dissipation current (Note 4) 1 .2 8 µA
Idet2 RAM retention limit detection dissipation current (Note 4) 1 .1 6 µA

Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.
Note 2: With one timer operated using fC32.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.12. External Clock Input (XIN input)

Standard
Symbol Parameter Unit
Min. Max.
tc External clock input cycle time 62.5 ns
tw(H) External clock input HIGH pulse width 25 ns
tw(L) External clock input LOW pulse width 25 ns
tr External clock rise time 15 ns
tf External clock fall time 15 ns

Table 1.26.13. Memory Expansion Mode and Microprocessor Mode

Standard
Symbol Parameter Unit
Min. Max.
tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns
tac2(RD-DB) Data input access time (for setting with wait) (Note 2) ns
tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns
tsu(DB-RD) Data input setup time 40 ns
tsu(RDY-BCLK ) RDY input setup time 30 ns
tsu(HOLD-BCLK ) HOLD input setup time 40 ns
th(RD-DB) Data input hold time 0 ns
th(BCLK -RDY) RDY input hold time 0 ns
th(BCLK-HOLD ) HOLD input hold time 0 ns
td(BCLK-HLDA ) HLDA output delay time 40 ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 45
f(BCLK) [ns]

Note 2: Calculated according to the BCLK frequency as follows:

(n–0.5) X 109
– 45 n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
f(BCLK) [ns]
setting.
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 45
f(BCLK) [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.14. Timer A Input (Counter Input in Event Counter Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 100 ns
tw(TAH) TAiIN input HIGH pulse width 40 ns
tw(TAL) TAiIN input LOW pulse width 40 ns

Table 1.26.15. Timer A Input (Gating Input in Timer Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 400 ns
tw(TAH) TAiIN input HIGH pulse width 200 ns
tw(TAL) TAiIN input LOW pulse width 200 ns

Table 1.26.16. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 200 ns
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.26.17. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol Parameter Unit
Min. Max.
tw(TAH) TAiIN input HIGH pulse width 100 ns
tw(TAL) TAiIN input LOW pulse width 100 ns

Table 1.26.18. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(UP) TAiOUT input cycle time 2000 ns
tw(UPH) TAiOUT input HIGH pulse width 1000 ns
tw(UPL) TAiOUT input LOW pulse width 1000 ns
tsu(UP-TIN) TAiOUT input setup time 400 ns
th(TIN-UP) TAiOUT input hold time 400 ns

Table 1.26.19. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 800 ns
tsu(TAIN-TAOUT) TAiOUT input setup time 200 ns
tsu(TAOUT-TAIN) TAiIN input setup time 200 ns

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.20. Timer B Input (Counter Input in Event Counter Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 100 ns
tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns
tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 ns
tc(TB) TBiIN input cycle time (counted on both edges) 200 ns
tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns
tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns

Table 1.26.21. Timer B Input (Pulse Period Measurement Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.26.22. Timer B Input (Pulse Width Measurement Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input HIGH pulse width 200 ns
tw(TBL) TBiIN input LOW pulse width 200 ns

Table 1.26.23. A-D Trigger Input

Standard
Symbol Parameter Unit
Min. Max.
tc(AD) ADTRG input cycle time (trigger able minimum) 1000 ns
tw(ADL) ADTRG input LOW pulse width 125 ns

Table 1.26.24. Serial I/O

Standard
Symbol Parameter Unit
Min. Max.
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input HIGH pulse width 100 ns
tw(CKL) CLKi input LOW pulse width 100 ns
td(C-Q) TxDi output delay time 80 ns
th(C-Q) TxDi hold time 0 ns
tsu(D-C) RxDi input setup time 30 ns
th(C-D) RxDi input hold time 90 ns

_______
Table 1.26.25. External Interrupt INTi Input
Standard
Symbol Parameter Unit
Min. Max.
tw(INH) INTi input HIGH pulse width 250 ns
tw(INL) INTi input LOW pulse width 250 ns

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.26. Memory Expansion and Microprocessor Modes (for setting with no wait)
Measuring condition
Standard
Symbol Parameter Min. Max. Unit
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) 0 ns
th(WR-AD) Address output hold time (refers to WR) (Note 2) ns
td(BCLK-CS) Chip select output delay time 25 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
td(BCLK-ALE) ALE signal output delay time 25 ns
th(BCLK-ALE) ALE signal output hold time –4 ns
Figure 1.26.1
td(BCLK-RD) RD signal output delay time 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns
th(BCLK-DB) Data output hold time (refers to BCLK)(Note 3) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 1) ns
th(WR-DB) Data output hold time (refers to WR)(Note 3) (Note 2) ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 40
f(BCLK) [ns] f(BCLK) is 12.5MHZ or less.
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 10
f(BCLK) [ns]

Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
R
(pull-down) resistance value.
Hold time of data bus is expressed in DBi
t = –CR X ln (1 – VOL / VCC2) C
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.

P0
P1
P2 30pF
P3
P4
P5
P6
P7
P8
P9
P10

Figure 1.26.1. Ports P0 to P10 Measurement Circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.27. Memory Expansion and Microprocessor Modes

(for 1- to 3-wait setting and external area access)

Measuring condition
Standard
Symbol Parameter Min. Max. Unit
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) 0 ns
th(WR-AD) Address output hold time (refers to WR) (Note 2) ns
td(BCLK-CS) Chip select output delay time 25 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
td(BCLK-ALE) ALE signal output delay time 25 ns
th(BCLK-ALE) ALE signal output hold time Figure 1.26.1 –4 ns
td(BCLK-RD) RD signal output delay time 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns
th(BCLK-DB) Data output hold time (refers to BCLK)(Note 3) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 1) ns
th(WR-DB) Data output hold time (refers to WR)(Note 3) (Note 2) ns
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109 n is “1” for 1-wait setting, “2” for 2-wait
– 40
f(BCLK) [ns] setting and “3” for 3-wait setting.
When n=1, f(BCLK) is 12.5MHZ or less.

Note 2: Calculated according to the BCLK frequency as follows:

0.5 X 109
– 10
f(BCLK) [ns]

Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
R
(pull-down) resistance value.
Hold time of data bus is expressed in DBi
t = –CR X ln (1 – VOL / VCC2) C
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.28. Memory Expansion and Microprocessor Modes

(for 2- to 3-wait setting, external area access and multiplex bus selection)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) (Note 1) ns
th(WR-AD) Address output hold time (refers to WR) (Note 1) ns
td(BCLK-CS) Chip select output delay time 25 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
th(RD-CS) Chip select output hold time (refers to RD) (Note 1) ns
th(WR-CS) Chip select output hold time (refers to WR) (Note 1) ns
td(BCLK-RD) RD signal output delay time 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
Figure 1.26.1
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns
th(BCLK-DB) Data output hold time (refers to BCLK) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 2) ns
th(WR-DB) Data output hold time (refers to WR) (Note 1) ns
td(BCLK-ALE) ALE signal output delay time (refers to BCLK) 25 ns
th(BCLK-ALE) ALE signal output hold time (refers to BCLK) –4 ns
td(AD-ALE) ALE signal output delay time (refers to Address) (Note 3) ns
th(ALE-AD) ALE signal output hold time (refers to Adderss) (Note 4) ns
td(AD-RD) RD signal output delay from the end of Adress 0 ns
td(AD-WR) WR signal output delay from the end of Adress 0 ns
tdZ(RD-AD) Address output floating start time 8 ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
–10
f(BCLK) [ns]

Note 2: Calculated according to the BCLK frequency as follows:

(n–0.5) X 109
–40
f(BCLK) [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

Note 3: Calculated according to the BCLK frequency as follows:

0.5 X 109
–25
f(BCLK) [ns]

Note 4: Calculated according to the BCLK frequency as follows:

0.5 X 109
–15
f(BCLK) [ns]

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
tc(TA)
tw(TAH)

TAiIN input
tw(TAL)

tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)

TAiOUT input
(Up/down input)

During event counter mode

TAiIN input
(When count on falling th(TIN–UP) tsu(UP–TIN)
edge is selected)

TAiIN input
(When count on rising
edge is selected)

Two-phase pulse input in

event counter mode tc(TA)

TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)

tc(TB)
tw(TBH)

TBiIN input
tw(TBL)

tc(AD)
tw(ADL)

ADTRG input

Figure 1.26.2. Timing Diagram (1)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V

tc(CK)
tw(CKH)

CLKi
tw(CKL)
th(C–Q)

TxDi
td(C–Q) tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)

Figure 1.26.3. Timing Diagram (2)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)

BCLK

RD
(Separate bus)

WR, WRL, WRH

(Separate bus)

RD
(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input
tsu(RDY–BCLK) th(BCLK–RDY)

(Common to setting with wait and setting without wait)

BCLK

tsu(HOLD–BCLK) th(BCLK–HOLD)

HOLD input

HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2, Hi–Z
P3, P4,
P50 to P52

Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.

Measuring conditions :
• VCC1=VCC2=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V

Figure 1.26.4. Timing Diagram (3)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing

BCLK
td(BCLK-CS) th(BCLK-CS)
25ns.max 4ns.min

CSi
tcyc

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
25ns.max -4ns.min 0ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
25ns.max 0ns.min

RD
tac1(RD-DB)
(0.5 X tcyc-45)ns.max

Hi-Z
DB
tSU(DB-RD) th(RD-DB)
40ns.min 0ns.min

Write timing
BCLK
td(BCLK-CS) th(BCLK-CS)
25ns.max 4ns.min

CSi

tcyc

td(BCLK-AD) th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(WR-AD)
25ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
25ns.max 0ns.min
WR,WRL,
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min
Hi-Z
DBi

td(DB-WR) th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 1.26.5. Timing Diagram (4)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS) th(BCLK-CS)
25ns.max 4ns.min

CSi

tcyc

td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
25ns.max -4ns.min 0ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
25ns.max 0ns.min

RD
tac2(RD-DB)
(1.5 X tcyc-45)ns.max
Hi-Z
DB
th(RD-DB)
tSU(DB-RD) 0ns.min
40ns.min

Write timing
BCLK
td(BCLK-CS) th(BCLK-CS)
25ns.max 4ns.min

CSi

tcyc

td(BCLK-AD) th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(WR-AD)
25ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
25ns.max 0ns.min
WR,WRL,
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min
Hi-Z
DBi

td(DB-WR) th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)

Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 1.26.6. Timing Diagram (5)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access )
Read timing
tcyc

BCLK

th(BCLK-CS)
td(BCLK-CS) 4ns.min
25ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(RD-AD)
25ns.max th(BCLK-ALE)
-4ns.min 0ns.min

ALE

td(BCLK-RD) th(BCLK-RD)
25ns.max 0ns.min

RD

tac2(RD-DB)
(2.5 X tcyc-45)ns.max

DBi Hi-Z

tSU(DB-RD) th(RD-DB)
40ns.min 0ns.min

Write timing
tcyc

BCLK

td(BCLK-CS) th(BCLK-CS)
4ns.min
25ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(WR-AD)
25ns.max th(BCLK-ALE) (0.5 X tcyc-10)ns.min
-4ns.min

ALE

th(BCLK-WR)
td(BCLK-WR) 0ns.min
25ns.max
WR, WRL
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min

DB Hi-Z

td(DB-WR) th(WR-DB)
(1.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)

Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V

Figure 1.26.7. Timing Diagram (6)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc

BCLK

th(BCLK-CS)
td(BCLK-CS) 4ns.min
25ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min

ADi
BHE
td(BCLK-ALE)
25ns.max th(BCLK-ALE) th(RD-AD)
-4ns.min 0ns.min

ALE

td(BCLK-RD) th(BCLK-RD)
25ns.max 0ns.min

RD

tac2(RD-DB)
(3.5 X tcyc-45)ns.max

DBi Hi-Z

tSU(DB-RD) th(RD-DB)
40ns.min 0ns.min

Write timing
tcyc

BCLK

td(BCLK-CS) th(BCLK-CS)
25ns.max 4ns.min

CSi

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min

ADi
BHE
td(BCLK-ALE) th(WR-AD)
25ns.max th(BCLK-ALE) (0.5 X tcyc-10)ns.min
-4ns.min

ALE

td(BCLK-WR) th(BCLK-WR)
25ns.max 0ns.min

WR, WRL
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min

DB Hi-Z

td(DB-WR) th(WR-DB)
(2.5 X tcyc-40)ns.min
(0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 1.26.8. Timing Diagram (7)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)

Read timing

BCLK
th(BCLK-CS)
td(BCLK-CS) th(RD-CS) 4ns.min
tcyc
25ns.max (0.5 X tcyc-10)ns.min

CSi
td(AD-ALE)
(0.5 X tcyc-25)ns.min th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi Address Data input Address
/DBi tdZ(RD-AD)
8ns.max th(RD-DB)
tac3(RD-DB) tSU(DB-RD) 0ns.min
(1.5 X tcyc-45)ns.max
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
25ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
25ns.max 0ns.min

RD

Write timing

BCLK
td(BCLK-CS) th(BCLK-CS)
tcyc th(WR-CS) 4ns.min
25ns.max (0.5 X tcyc-10)ns.min

CSi
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min

ADi Address Data output Address

/DBi
td(DB-WR) th(WR-DB)
td(AD-ALE) (1.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
(0.5 X tcyc-25)ns.min

td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) td(AD-WR) th(WR-AD)
25ns.max -4ns.min 0ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
25ns.max 0ns.min
WR,WRL,
WRH

1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 1.26.9. Timing Diagram (8)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)

VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc

BCLK
th(RD-CS)
(0.5 X tcyc-10)ns.min th(BCLK-CS)
td(BCLK-CS) 4ns.min
25ns.max
CSi
td(AD-ALE)
(0.5 X tcyc-25)ns.min
th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi
/DB Address Data input
tdZ(RD-AD) th(RD-DB)
td(BCLK-AD) td(AD-RD) 8ns.max tac3(RD-DB) tSU(DB-RD) 0ns.min
th(BCLK-AD)
25ns.max (2.5 X tcyc-45)ns.max 40ns.min 4ns.min
0ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max th(RD-AD)
th(BCLK-ALE) (0.5 X tcyc-10)ns.min
-4ns.min

ALE

th(BCLK-RD)
td(BCLK-RD) 0ns.min
25ns.max
RD

Write timing
tcyc

AAAA
BCLK

th(WR-CS) th(BCLK-CS)
td(BCLK-CS) (0.5 X tcyc-10)ns.min
4ns.min
25ns.max

CSi
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min
ADi
Address Data output
/DB
td(AD-ALE)
td(DB-WR) th(WR-DB)
(0.5 X tcyc-25)ns.min
(0.5 X tcyc-10)ns.min
(2.5 X tcyc-40)ns.min
td(BCLK-AD) th(BCLK-AD)
25ns.max 4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE) th(BCLK-ALE)
25ns.max -4ns.min
th(WR-AD)
(0.5 X tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE

th(BCLK-WR)
td(BCLK-WR) 0ns.min
25ns.max
WR, WRL
WRH

1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 1.26.10. Timing Diagram (9)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Table 1.26.29. Electrical Characteristics (Note)
Measuring condition Standard
Symbol Parameter Unit
Min. Typ. Max.
HIGH output P00 to P07,P10 to P17,P20 to P27,P30 to P37,
VOH voltage P40 to P47,P50 to P57,P60 to P67,P72 to P77,
IOH=-1mA VCC-0.5 VC C V
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117,P120 to P127,P130 to P137,P140,P141
HIGHPOWER IOH=-0.1mA VCC-0.5 VC C
HIGH output voltage XOUT V
VOH LOWPOWER IOH=-50µA VCC-0.5 VC C

HIGH output voltage XCOUT HIGHPOWER With no load applied 2 .5

V
LOWPOWER With no load applied 1.6
LOW output P00 to P07,P10 to P17,P20 to P27,P30 to P37,
voltage P40 to P47,P50 to P57,P60 to P67,P70 to P77,
VOL IOL=1mA 0 .5 V
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P117,P120 to P127,P130 to P137,P140,P141
HIGHPOWER IOL=0.1mA 0 .5
VOL LOW output voltage XOUT V
LOWPOWER IOL=50µA 0 .5
HIGHPOWER With no load applied 0
LOW output voltage XCOUT V
LOWPOWER With no load applied 0
Hysteresis HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
VT+-VT-
ADTRG, CTS0 to CTS2, SCL, SDA, 0.2 0.8 V
CLK0 to CLK4, TA2OUT to TA4OUT,
KI0 to KI3, RxD0 to RxD2, SIN3,SIN4
VT+-VT- Hysteresis RESET 0 .2 (0.7) 1.8 V
HIGH input P00 to P07,P10 to P17,P20 to P27,P30 to P37,
current P40 to P47,P50 to P57,P60 to P67,P70 to P77,
IIH P80 to P87,P90 to P97,P100 to P107,P110 to P117, VI=3V 4.0 µA
P120 to P127,P130 to P137,P140,P141,
XIN, RESET, CNVss, BYTE

LOW input P00 to P07,P10 to P17,P20 to P27,P30 to P37,

current P40 to P47,P50 to P57,P60 to P67,P70 to P77,
IIL P80 to P87,P90 to P97,P100 to P107,P110 to P117, VI=0V -4.0 µA
P120 to P127,P130 to P137,P140,P141,
XIN, RESET, CNVss, BYTE
RPULLUP Pull-up P00 to P07,P10 to P17,P20 to P27,P30 to P37,
resistance P40 to P47,P50 to P57,P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107, VI=0V 50 100 500 kΩ
P110 to P117,P120 to P127,P130 to P137,P140,P141
RfXIN Feedback resistance XIN 3.0 MΩ
RfXCIN Feedback resistance XCIN 25 MΩ
VRAM RAM retention voltage At stop mode 2.0 V

Note 1 : Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2 : VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Table 1.26.30. Electrical Characteristics (2) (Note 1)
Symbol Parameter Measuring condition Standard
Min. Typ. Max. Unit
In single-chip mode, the output Mask ROM f(BCLK)=10MHz,
8 11 mA
pins are open and other pins are No division
VSS No division, Ring oscillation 1 mA

Flash memory f(BCLK)=10MHz,

No division 8 13 mA

No division, Ring oscillation

1.8 mA
Flash memory f(BCLK)=10MHz,
Program 12 mA
Vcc1=3.0V
Flash memory f(BCLK)=10MHz,
Erase 22 mA
Vcc1=3.0V
Mask ROM f(XCIN)=32kHz,
25 µA
Low power dissipation mode,
ICC Power supply current ROM(Note 3)
(VCC1=2.7 to 3.6V)
Flash memory f(BCLK)=32kHz,
Low power dissipation mode, 25 µA
RAM(Note 3)
f(BCLK)=32kHz,
Low power dissipation mode, 420 µA
Flash memory(Note 3)
Ring oscillation, µA
Wait mode 45
f(BCLK)=32kHz,
Wait mode (Note 2), 6.0 µA
Mask ROM Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode (Note 2), 1.8 µA
Oscillation capacity Low
Stop mode,
0.7 3.0 µA
Topr=25°C
Idet4 Voltage down detection dissipation current (Note 4) 0.6 4 µA
Idet3 Reset level detection dissipation current (Note 4) 0 .4 2 µA
Idet2 RAM retention limit detection dissipation current (Note 4) 0.9 4 µA

Note 1: Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.31. External Clock Input (XIN input)

Standard
Symbol Parameter Unit
Min. Max.
tc External clock input cycle time 100 ns
tw(H) External clock input HIGH pulse width 40 ns
tw(L) External clock input LOW pulse width 40 ns
tr External clock rise time 18 ns
tf External clock fall time 18 ns

Table 1.26.32. Memory Expansion and Microprocessor Modes

Standard
Symbol Parameter Unit
Min. Max.
tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns
tac2(RD-DB) Data input access time (for setting with wait) (Note 2) ns
tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns
tsu(DB-RD) Data input setup time 50 ns
tsu(RDY-BCLK ) RDY input setup time 40 ns
tsu(HOLD-BCLK ) HOLD input setup time 50 ns
th(RD-DB) Data input hold time 0 ns
th(BCLK -RDY) RDY input hold time 0 ns
th(BCLK-HOLD ) HOLD input hold time 0 ns
td(BCLK-HLDA ) HLDA output delay time 40 ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 60
f(BCLK) [ns]

Note 2: Calculated according to the BCLK frequency as follows:

(n–0.5) X 109
– 60 n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
f(BCLK) [ns]
setting.
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 60
f(BCLK) [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.33. Timer A Input (Counter Input in Event Counter Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 150 ns
tw(TAH) TAiIN input HIGH pulse width 60 ns
tw(TAL) TAiIN input LOW pulse width 60 ns

Table 1.26.34. Timer A Input (Gating Input in Timer Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 600 ns
tw(TAH) TAiIN input HIGH pulse width 300 ns
tw(TAL) TAiIN input LOW pulse width 300 ns

Table 1.26.35. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 300 ns
tw(TAH) TAiIN input HIGH pulse width 150 ns
tw(TAL) TAiIN input LOW pulse width 150 ns

Table 1.26.36. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol Parameter Unit
Min. Max.
tw(TAH) TAiIN input HIGH pulse width 150 ns
tw(TAL) TAiIN input LOW pulse width 150 ns

Table 1.26.37. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(UP) TAiOUT input cycle time 3000 ns
tw(UPH) TAiOUT input HIGH pulse width 1500 ns
tw(UPL) TAiOUT input LOW pulse width 1500 ns
tsu(UP-TIN) TAiOUT input setup time 600 ns
th(TIN-UP) TAiOUT input hold time 600 ns

Table 1.26.38. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol Parameter Unit
Min. Max.
tc(TA) TAiIN input cycle time 2 µs
tsu(TAIN -TAOUT ) TAiOUT input setup time 500 ns
tsu(TAOUT -TAIN) TAiIN input setup time 500 ns

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.39. Timer B Input (Counter Input in Event Counter Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 150 ns
tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 ns
tw(TBL) TBiIN input LOW pulse width (counted on one edge) 60 ns
tc(TB) TBiIN input cycle time (counted on both edges) 300 ns
tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 120 ns
tw(TBL) TBiIN input LOW pulse width (counted on both edges) 120 ns

Table 1.26.40. Timer B Input (Pulse Period Measurement Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 600 ns
tw(TBH) TBiIN input HIGH pulse width 300 ns
tw(TBL) TBiIN input LOW pulse width 300 ns

Table 1.26.41. Timer B Input (Pulse Width Measurement Mode)

Standard
Symbol Parameter Unit
Min. Max.
tc(TB) TBiIN input cycle time 600 ns
tw(TBH) TBiIN input HIGH pulse width 300 ns
tw(TBL) TBiIN input LOW pulse width 300 ns

Table 1.26.42. A-D Trigger Input

Standard
Symbol Parameter Unit
Min. Max.
tc(AD) ADTRG input cycle time (trigger able minimum) 1500 ns
tw(ADL) ADTRG input LOW pulse width 200 ns

Table 1.26.43. Serial I/O

Standard
Symbol Parameter Unit
Min. Max.
tc(CK) CLKi input cycle time 300 ns
tw(CKH) CLKi input HIGH pulse width 150 ns
tw(CKL) CLKi input LOW pulse width 150 ns
td(C-Q) TxDi output delay time 160 ns
th(C-Q) TxDi hold time 0 ns
tsu(D-C) RxDi input setup time 50 ns
th(C-D) RxDi input hold time 90 ns

_______
Table 1.26.44. External Interrupt INTi Input
Standard
Symbol Parameter Unit
Min. Max.
tw(INH) INTi input HIGH pulse width 380 ns
tw(INL) INTi input LOW pulse width 380 ns

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.45. Memory Expansion, Microprocessor Modes (for setting with no wait)
Measuring condition
Standard
Symbol Parameter Min. Max. Unit
td(BCLK-AD) Address output delay time 30 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) 0 ns
th(WR-AD) Address output hold time (refers to WR) (Note 2) ns
td(BCLK-CS) Chip select output delay time 30 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
td(BCLK-ALE) ALE signal output delay time 30 ns
th(BCLK-ALE) ALE signal output hold time Figure 1.26.11 –4 ns
td(BCLK-RD) RD signal output delay time 30 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 30 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns
th(BCLK-DB) Data output hold time (refers to BCLK)(Note 3) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 1) ns
th(WR-DB) Data output hold time (refers to WR)(Note 3) (Note 2) ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 40
f(BCLK) [ns]
f(BCLK) is 12.5MHZ or less.

Note 2: Calculated according to the BCLK frequency as follows:

0.5 X 109
– 10
f(BCLK) [ns]

Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
R
(pull-down) resistance value.
Hold time of data bus is expressed in DBi
t = –CR X ln (1 – VOL / VCC2) C
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.

P0
P1
P2 30pF
P3
P4
P5
P6
P7
P8
P9
P10

Figure 1.26.11. Ports P0 to P10 Measurement Circuit

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 1.26.46. Memory expansion and Microprocessor Modes

(for 1- to 3-wait setting and external area access)

Measuring condition
Standard
Symbol Parameter Min. Max. Unit
td(BCLK-AD) Address output delay time 30 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) 0 ns
th(WR-AD) Address output hold time (refers to WR) (Note 2) ns
td(BCLK-CS) Chip select output delay time 30 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
td(BCLK-ALE) ALE signal output delay time Figure 1.26.11 30 ns
th(BCLK-ALE) ALE signal output hold time –4 ns
td(BCLK-RD) RD signal output delay time 30 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 30 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 40 ns
th(BCLK-DB) Data output hold time (refers to BCLK)(Note 3) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 1) ns
th(WR-DB) Data output hold time (refers to WR)(Note 3) (Note 2) ns
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109 n is “1” for 1-wait setting, “2” for 2-wait setting
– 40
f(BCLK) [ns] and “3” for 3-wait setting.
When n=1, f(BCLK) is 12.5MHZ or less.

Note 2: Calculated according to the BCLK frequency as follows:

0.5 X 109
– 10
f(BCLK) [ns]

Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
R
(pull-down) resistance value.
Hold time of data bus is expressed in DBi
t = –CR X ln (1 – VOL / VCC2) C
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.

248
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC, unless otherwise specified)

Table 1.26.47. Memory expansion and Microprocessor Modes

(for 2- to 3-wait setting, external area access and multiplex bus selection)
Standard
Symbol Parameter Measuring condition Unit
Min. Max.
td(BCLK-AD) Address output delay time 50 ns
th(BCLK-AD) Address output hold time (refers to BCLK) 4 ns
th(RD-AD) Address output hold time (refers to RD) (Note 1) ns
th(WR-AD) Address output hold time (refers to WR) (Note 1) ns
td(BCLK-CS) Chip select output delay time 50 ns
th(BCLK-CS) Chip select output hold time (refers to BCLK) 4 ns
th(RD-CS) Chip select output hold time (refers to RD) (Note 1) ns
th(WR-CS) Chip select output hold time (refers to WR) (Note 1) ns
td(BCLK-RD) RD signal output delay time 40 ns
th(BCLK-RD) RD signal output hold time 0 ns
Figure 1.26.11
td(BCLK-WR) WR signal output delay time 40 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (refers to BCLK) 50 ns
th(BCLK-DB) Data output hold time (refers to BCLK) 4 ns
td(DB-WR) Data output delay time (refers to WR) (Note 2) ns
th(WR-DB) Data output hold time (refers to WR) (Note 1) ns
td(BCLK-ALE) ALE signal output delay time (refers to BCLK) 40 ns
th(BCLK-ALE) ALE signal output hold time (refers to BCLK) –4 ns
td(AD-ALE) ALE signal output delay time (refers to Address) (Note 3) ns
th(ALE-AD) ALE signal output hold time (refers to Adderss) (Note 4) ns
td(AD-RD) RD signal output delay from the end of Address 0 ns
td(AD-WR) WR signal output delay from the end of Address 0 ns
tdZ(RD-AD) Address output floating start time 8 ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
–10
f(BCLK) [ns]

Note 2: Calculated according to the BCLK frequency as follows:

(n–0.5) X 109
–50
f(BCLK) [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

Note 3: Calculated according to the BCLK frequency as follows:

0.5 X 109
–40
f(BCLK) [ns]

Note 4: Calculated according to the BCLK frequency as follows:

0.5 X 109
–15 [ns]
f(BCLK)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
tc(TA)
tw(TAH)

TAiIN input
tw(TAL)

tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)

TAiOUT input
(Up/down input)

During event counter mode

TAiIN input
(When count on falling th(TIN–UP) tsu(UP–TIN)
edge is selected)

TAiIN input
(When count on rising
edge is selected)

Two-phase pulse input in

event counter mode tc(TA)

TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)

tc(TB)
tw(TBH)

TBiIN input
tw(TBL)

tc(AD)
tw(ADL)

ADTRG input

Figure 1.26.12. Timing Diagram (1)

250
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
tc(CK)
tw(CKH)

CLKi
tw(CKL)
th(C–Q)

TxDi
td(C–Q) tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)

Figure 1.26.13. Timing Diagram (2)

251
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)

VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)

BCLK

RD
(Separate bus)

WR, WRL, WRH

(Separate bus)

RD
(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input
tsu(RDY–BCLK) th(BCLK–RDY)

(Common to setting with wait and setting without wait)

BCLK

tsu(HOLD–BCLK) th(BCLK–HOLD)

HOLD input

HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2, Hi–Z
P3, P4,
P50 to P52

Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit of PM0 register and PM11 bit of PM1 register.

Measuring conditions :
• VCC1=VCC2=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 1.26.14. Timing Diagram (3)

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing

BCLK
td(BCLK-CS) th(BCLK-CS)
30ns.max 4ns.min

CSi
tcyc

td(BCLK-AD) th(BCLK-AD)
30ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
30ns.max -4ns.min 0ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
30ns.max 0ns.min

RD
tac1(RD-DB)
(0.5 X tcyc-60)ns.max

Hi-Z
DB
tSU(DB-RD) th(RD-DB)
50ns.min 0ns.min

Write timing
BCLK
td(BCLK-CS) th(BCLK-CS)
30ns.max 4ns.min

CSi
tcyc

td(BCLK-AD) th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(WR-AD)
30ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
30ns.max 0ns.min
WR,WRL,
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min
Hi-Z
DBi

td(DB-WR) th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.15. Timing Diagram (4)

253
 Renesas microcomputers
M16C / 62P Group
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS) th(BCLK-CS)
30ns.max 4ns.min

CSi
tcyc

td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
30ns.max -4ns.min 0ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
30ns.max 0ns.min

RD
tac2(RD-DB)
(1.5 X tcyc-60)ns.max

Hi-Z
DB
th(RD-DB)
tSU(DB-RD) 0ns.min
50ns.min

Write timing
BCLK
td(BCLK-CS) th(BCLK-CS)
30ns.max 4ns.min

CSi
tcyc

td(BCLK-AD) th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(WR-AD)
30ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
30ns.max 0ns.min
WR,WRL,
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min
Hi-Z
DBi

td(DB-WR) th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)

Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.16. Timing Diagram (5)

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc

BCLK

th(BCLK-CS)
td(BCLK-CS) 4ns.min
30ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
30ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(RD-AD)
30ns.max th(BCLK-ALE)
-4ns.min 0ns.min

ALE

td(BCLK-RD) th(BCLK-RD)
30ns.max 0ns.min

RD

tac2(RD-DB)
(2.5 X tcyc-60)ns.max

DBi Hi-Z

tSU(DB-RD) th(RD-DB)
50ns.min 0ns.min

Write timing
tcyc

BCLK

td(BCLK-CS) th(BCLK-CS)
4ns.min
30ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
30ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(WR-AD)
30ns.max th(BCLK-ALE) (0.5 X tcyc-10)ns.min
-4ns.min

ALE

th(BCLK-WR)
td(BCLK-WR) 0ns.min
30ns.max
WR, WRL
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min

DB Hi-Z

td(DB-WR) th(WR-DB)
(1.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.17. Timing Diagram (6)

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M16C / 62P Group
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc

BCLK

th(BCLK-CS)
td(BCLK-CS) 4ns.min
30ns.max

CSi

td(BCLK-AD) th(BCLK-AD)
30ns.max 4ns.min
ADi
BHE
td(BCLK-ALE)
30ns.max th(BCLK-ALE) th(RD-AD)
-4ns.min 0ns.min

ALE

td(BCLK-RD) th(BCLK-RD)
30ns.max 0ns.min

RD

tac2(RD-DB)
(3.5 X tcyc-60)ns.max

DBi Hi-Z

tSU(DB-RD) th(RD-DB)
50ns.min 0ns.min

Write timing
tcyc

BCLK

td(BCLK-CS) th(BCLK-CS)
30ns.max 4ns.min

CSi

td(BCLK-AD) th(BCLK-AD)
30ns.max 4ns.min

ADi
BHE
td(BCLK-ALE) th(WR-AD)
30ns.max th(BCLK-ALE)
-4ns.min (0.5 X tcyc-10)ns.min

ALE

td(BCLK-WR) th(BCLK-WR)
30ns.max 0ns.min

WR, WRL
WRH
td(BCLK-DB) th(BCLK-DB)
40ns.max 4ns.min

DB Hi-Z

td(DB-WR) th(WR-DB)
(2.5 X tcyc-40)ns.min
(0.5 X tcyc-10)ns.min
1
tcyc=
f(BCLK)

Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.18. Timing Diagram (7)

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing

BCLK
th(BCLK-CS)
td(BCLK-CS) th(RD-CS) 4ns.min
tcyc
40ns.max (0.5 X tcyc-10)ns.min

CSi
td(AD-ALE)
(0.5 X tcyc-40)ns.min th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi Address Data input Address
/DBi tdZ(RD-AD)
8ns.max th(RD-DB)
tac3(RD-DB) tSU(DB-RD) 0ns.min
(1.5 X tcyc-60)ns.max 50ns.min

td(AD-RD)
td(BCLK-AD) 0ns.min th(BCLK-AD)
40ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
40ns.max -4ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-RD) th(BCLK-RD)
40ns.max 0ns.min

RD

Write timing

BCLK
td(BCLK-CS) tcyc th(BCLK-CS)
th(WR-CS)
4ns.min
40ns.max (0.5 X tcyc-10)ns.min

CSi
td(BCLK-DB) th(BCLK-DB)
50ns.max 4ns.min

ADi Address Data output Address

/DBi
td(DB-WR) th(WR-DB)
td(AD-ALE)
(1.5 X tcyc-50)ns.min (0.5 X tcyc-10)ns.min
(0.5 X tcyc-40)ns.min

td(BCLK-AD) th(BCLK-AD)
40ns.max 4ns.min
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(WR-AD)
td(AD-WR)
40ns.max -4ns.min 0ns.min (0.5 X tcyc-10)ns.min

ALE
td(BCLK-WR) th(BCLK-WR)
40ns.max 0ns.min
WR,WRL,
WRH

1
tcyc=
f(BCLK)

Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.19. Timing Diagram (8)

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Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)

Read timing
tcyc

BCLK
th(RD-CS)
(0.5 X tcyc-10)ns.min th(BCLK-CS)
td(BCLK-CS) 6ns.min
40ns.max
CSi
td(AD-ALE)
(0.5 X tcyc-40)ns.min th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi Address Data input
/DB th(RD-DB)
tdZ(RD-AD)
td(BCLK-AD) td(AD-RD) 8ns.max tac3(RD-DB) tSU(DB-RD)
0ns.min
th(BCLK-AD)
40ns.max 0ns.min (2.5 X tcyc-60)ns.max 50ns.min 4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max th(RD-AD)
th(BCLK-ALE) (0.5 X tcyc-10)ns.min
-4ns.min
ALE

th(BCLK-RD)
td(BCLK-RD) 0ns.min
40ns.max
RD

Write timing
tcyc

BCLK

th(WR-CS)
th(BCLK-CS)
td(BCLK-CS) (0.5 X tcyc-10)ns.min 4ns.min
40ns.max

CSi
td(BCLK-DB) th(BCLK-DB)
50ns.max 4ns.min

ADi
Address Data output
/DB
td(AD-ALE) td(DB-WR)
(0.5 X tcyc-40)ns.min th(WR-DB)
(2.5 X tcyc-50)ns.min (0.5 X tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE) th(BCLK-ALE)
40ns.max -4ns.min th(WR-AD)
(0.5 X tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE

th(BCLK-WR)
td(BCLK-WR) 0ns.min
40ns.max
WR, WRL
WRH

1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 1.26.20. Timing Diagram (9)

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Flash Memory Version

Flash Memory Version

Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally con-
tains flash memory.
The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/
output modes—in which its internal flash memory can be operated on.
Table 1.27.1 shows the outline performance of flash memory version (refer to “Table 1.1.1. Performance
outline of M16C/62P group” for the items not listed in Table 1.27.1.).

Table 1.27.1. Flash Memory Version Specifications

Item Specification

Flash memory operating mode 3 modes (CPU rewrite, standard serial I/O, parallel I/O)
User ROM area Refer to “Figure 1.27.1. Flash Memory Block Diagram”
Erase block
Boot ROM area 1 block (4 Kbytes) (Note 1)
Method for program In units of word, in units of byte (Note 2)
Method for erasure Collective erase, block erase
Program, erase control method Program and erase controlled by software command
Protect method Protected for each block by lock bit
Number of commands 8 commands
Number of program and erasure 100 times, 1,000 times/10,000 times (option) (Note 3, 4)
Data Retention 10 years
ROM code protection Parallel I/O and standard serial I/O modes are supported.
Note 1: The boot ROM area contains a standard serial I/O mode rewrite control program which is stored in it when
shipped from the factory. This area can only be rewritten in parallel input/output mode.
Note 2: Can be programmed in byte units in only parallel input/output mode.
Note 3: Block 1 and block A are guaranteed of 10,000 times of programming and erasure. All other blocks are
guaranteed of 1,000 times of programming and erasure. (Under development; mass production scheduled to
start in the 3rd quarter of 2003)
Note 4: Definition of programming and erasure times
The programming and erasure times are defined to be per-block erasure times. For example, assume
a case where a 4K-byte block A is programmed in 2,048 operations by writing one word at a time and
erased thereafter.
In this case, the block is reckoned as having been programmed and erased once.
If a product is guaranteed of 100 times of programming and erasure, each block in it can be erased up to
100 times. When guaranteed of 10,000 times of programming and erasure, block 1 and block A can each
be erased up to 10,000 times. All other blocks can each be erased up to 1,000 times.

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Flash Memory Version

Table 1.27.2. Flash Memory Rewrite Modes Overview

Flash memory CPU rewrite mode (Note 1) Standard serial I/O mode Parallel I/O mode
rewrite mode
Function The user ROM area is rewrit- The user ROM area is rewrit- The boot ROM and user
ten by executing software ten by using a dedicated se- ROM areas are rewritten by
commands from the CPU. rial programmer. using a dedicated parallel
EW0 mode: Standard serial I/O mode 1: programmer.
Can be rewritten in any Clock sync serial I/O
area other than the flash Standard serial I/O mode 2:
memory (Note 2) UART
EW1 mode:
Can be rewritten in the
flash memory
Areas which User ROM area User ROM area User ROM area
can be rewritten Boot ROM area
Operation Single chip mode Boot mode Parallel I/O mode
mode Memory expansion mode
(EW0 mode)
Boot mode (EW0 mode)
ROM None Serial programmer Parallel programmer
programmer
Note 1: The PM13 bit remains set to “1” while the FMR0 register FMR01 bit = 1 (CPU rewrite mode enabled).
The PM13 bit is reverted to its original value by clearing the FMR01 bit to “0” (CPU rewrite mode
disabled). However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not
reflected until after the FMR01 bit is cleared to “0”.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM or in an external area that is enabled for
use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode,
the extended accessible area (4000016 to BFFFF16) cannot be used.

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Flash Memory Version

1. Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 1.27.1 shows the block diagram of flash momoery. The user ROM area has a 4K-byte block A, in
addition to the area that stores a program for microcomputer operation during singe-chip or memory expan-
sion mode.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial
input/output, and parallel input/output modes. Block A is enabled for use by setting the PM1 register’s
PM10 bit to “1” (block A enabled, CS2 area at addresses 1000016 to 26FFF16).
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in
parallel input/output mode. After a hardware reset that is performed by applying a high-level signal to the
CNVSS and P50 pins and a low-level signal to the P55 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the
user ROM area is executed (but the boot ROM area cannot be read).

00F00016
Block A :4K bytes
00FFFF16

08000016

Block 12 : 64K bytes

08FFFF16
09000016

Block 11 : 64K bytes

09FFFF16
0A000016

Block 10 : 64K bytes

0AFFFF16
0B000016

Block 9 : 64K bytes

0BFFFF16
0C000016 0F000016

Block 8 : 64K bytes

0CFFFF16
Block 5 : 32K bytes
0D000016

Block 7 : 64K bytes

0DFFFF16 0F7FFF16
0E000016 0F800016
Block 4 : 8K bytes
Block 6 : 64K bytes 0F9FFF16
0FA00016
Block 3 : 8K bytes
0EFFFF16 0FBFFF16
0F000016 0FC00016
Block 2 : 8K bytes
Block 0 to Block 5 (32+8+8+8 0FDFFF16
+4+4)K bytes 0FE00016 Block 1 : 4K bytes
0FEFFF16
0FF00016 Block 0 : 4K bytes 0FF00016 4K bytes
0FFFFF16 0FFFFF16 0FFFFF16
User ROM area Boot ROM area

Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Note 4: Block A can be made usable by setting the PM1 register’s PM10 bit to “1” (block A enabled, CS2 area allocated at addresses 1000016 to 26FFF16).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it.

Figure 1.27.1. Flash Memory Block Diagram

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Flash Memory

Boot Mode
After a hardware reset which is performed by applying a low-level signal to the P55 pin and a high-level
signal to the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the pro-
gram in the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0
register.
The boot ROM area contains a standard serial input/output mode based rewrite control program which was
stored in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite
control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the
system.

Functions To Prevent Flash Memory from Rewriting

To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM
code protect and standard serial input/output mode has an ID code check function.

• ROM Code Protect Function

The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
input/output mode. Figure 1.27.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM
code protect function is enabled by clearing one or both of two ROMCP1 bits to “0” when the ROMCR bits
are not ‘002,’ with the flash memory thereby protected against reading or rewriting. Conversely, when the
ROMCR bits are ‘002’ (ROM code protect removed), the flash memory can be read or rewritten. Once the
ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel input/output
mode. Therefore, use standard serial input/output or other modes to rewrite the flash memory.

• ID Code Check Function

Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes
sent from the programmer and the ID codes written in the flash memory are compared to see if they
match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316,
0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes
are preset at these addresses and write it in the flash memory.

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Flash Memory

ROM code protect control address

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address Value when shipped
1 1 1 1 ROMCP 0FFFFF16 FF16 (Note 4)

Bit symbol Bit name Function RW

Reserved bit Set this bit to “1” RW

Reserved bit Set this bit to “1” RW

Reserved bit Set this bit to “1” RW

Reserved bit Set this bit to “1” RW

b5 b4
ROMCR ROM code protect reset RW
00: Removes protect
bit (Note 2, Note 4)
01:

11:
}
10: Enables ROOMCP1 bit
RW

b7 b6
ROMCP1 ROM code protect level
00: RW
1 set bit
(Note 1, Note 3, Note 4) 01:
10:
}
Protect enabled

11: Protect disabled RW

Note 1: If the ROMCR bits are set to other than ‘002’ and the ROMCP1 bits are set to other than ‘112’ (
ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to ‘002’ when the ROMCR bits are other than ‘002’ and the ROMCP1
bits are other than ‘112,’ ROM code protect level 1 is removed. However, because the ROMCR
bits cannot be modified during parallel input/output mode, they need to be modified in standard
serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘012,’ ‘102,’ or ‘112.’
Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to ‘FF16.’

Figure 1.27.2. ROMCP Register

Address
0FFFDF16 to 0FFFDC16 ID1 Undefined instruction vector

0FFFE316 to 0FFFE016 ID2 Overflow vector

0FFFE716 to 0FFFE416 BRK instruction vector

0FFFEB16 to 0FFFE816 ID3 Address match vector

0FFFEF16 to 0FFFEC16 ID4 Single step vector

0FFFF316 to 0FFFF016 ID5 Watchdog timer vector

0FFFF716 to 0FFFF416 ID6 DBC vector

0FFFFB16 to 0FFFF816 ID7 NMI vector

0FFFFF16 to 0FFFFC16 ROMCP Reset vector

4 bytes

Figure 1.27.3. Address for ID Code Stored

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Flash Memory

CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 1.27.1 can be rewritten and the boot ROM
area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on
each block in the user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase
Write 1 (EW1) mode. Table 1.27.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1
(EW1) modes.
Table 1.27.3. EW0 Mode and EW1 Mode
Item EW0 mode EW1 mode
Operation mode • Single chip mode Single chip mode
• Memory expansion mode
• Boot mode
Areas in which a • User ROM area User ROM area
rewrite control • Boot ROM area
program can be located
Areas in which a Must be transferred to any area other Can be executed directly in the user
rewrite control than the flash memory (e.g., RAM) ROM area
program can be executed before being executed (Note 2)
Areas which can be User ROM area User ROM area
rewritten However, this does not include the area
in which a rewrite control program
exists
Software command None • Program, Block Erase command
limitations Cannot be executed on any block in
which a rewrite control program exists
• Erase All Unlocked Block command
Cannot be executed when the lock bit
for any block in which a rewrite control
program exists is set to “1” (unlocked)
or the FMR0 register’s FMR02 bit is set
to “1” (lock bit disabled)
• Read Status Register command
Cannot be executed
Modes after Program or Read Status Register mode Read Array mode
Erase
CPU status during Auto Operating Hold state (I/O ports retain the state in
Write and Auto Erase which they were before the command
was executed)(Note 1)
Flash memory status • Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
detection FMR06, and FMR07 bits in a FMR06, and FMR07 bits in a program
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
_______
Note 1: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13
bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended accessible area
(4000016 to BFFFF16) cannot be used.

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Flash Memory

• EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit
= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
• EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.

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Flash Memory

Figure 1.27.4 shows the FIDR, FMR0 and FMR1 registers.

FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or
Lock Bit program is running; otherwise, the bit is “1”.
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode). During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to
the description of the data protect function.) The lock bits set are enabled by setting the FMR02 bit to “0”.
The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status
flag). However, if the Erase command is executed while the FMR02 bit is set to “1”, the lock bit data
changes state from “0” (locked) to “1” (unlocked) after Erase is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. Setting the FMSTP bit to “1” makes the internal flash memory
inaccessible. Therefore, make sure the FMSTP bit is modified in other than the flash memory area.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00
bit not reset to “1” (ready))
• When entering low power mode or ring low power mode
Figure 1.27.7 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power
for the internal flash memory is automatically turned off and is turned back on again after returning from
stop or wait mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area
(for read, write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase
error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.

Figure 1.27.5 and 1.27.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
FMR11 Bit
Setting this bit to “1” places the microcomputer in EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.

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Flash Memory

Flash identification register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
FIDR 01B416 XXXXXX002

Bit symbol Bit name Function RW

FIDR0 Flash module type b1 b0 RO

identification value 0 0: M16C/62N, M3062GF8N type flash module
1 0: M16C/62P type flash module
FIDR1 1 1: M16C/62M, M16C/62A type flash module RO
Nothing is assigned.
(b7-b2) When write, set to “0”. When read, their contents are indeterminate.
Note: This register identifies on-chip flash module type of M16C/62 group. Note, however, no chip version is known
by this register. Follow the procedure described below for the identification.
(1) Write FF16 to FIDR register
(2) Read FIDR register
(3) Check two low-order bits of read value
Make sure no access to external memories or other SFRs or no interrupts or DMA transfers will occur between
the above two instructions no. 1 and no. 2.

Flash memory control register 0

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 FMR0 01B716 XX0000012

Bit symbol Bit name Function RW

FMR00 RY/BY status flag 0: Busy (being written or erased)
RO
1: Ready

FMR01 CPU rewrite mode select bit 0: Disables CPU rewrite mode
(Note 1) 1: Enables CPU rewrite mode RW

FMR02 Lock bit disable select bit 0: Enables lock bit

(Note 2) 1: Disables lock bit RW

Flash memory stop bit 0: Enables flash memory operation

FMSTP
(Note 3, Note 5)) 1: Stops flash memory operation
(placed in low power mode, RW
flash memory initialized)

(b4) Reserved bit Must always be set to “0” RW

FMR05 User ROM area select bit 0: Boot ROM area is accessed
(Note 3) 1: User ROM area is accessed RW
(Effective in only boot mode)
FMR06 Program status flag (Note 4) 0: Terminated normally
1: Terminated in error RO

FMR07 Erase status flag (Note 4) 0: Terminated normally

1: Terminated in error RO
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, write to this bit from
a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Note 6: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.

Flash memory control register 1

b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset
0 0 0 0 FMR1 01B516 0X00XX0X2

Bit symbol Bit name Function RW

(b0) Reserved bit The value in this bit when read is RO

indeterminate.
FMR11 EW1 mode select bit ( 0: EW0 mode
Note) 1: EW1 mode RW

Reserved bit The value in this bit when read is

(b3-b2) indeterminate.
RO

(b5-b4) Reserved bit Must always be set to “0” RW

FMR06 Lock bit status flag 0: Lock
RO
1: Unlock

(b7) Reserved bit Must always be set to “0” RW

Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.

Figure 1.27.4. FIDR Register and FMR0 and FMR1 Registers

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Flash Memory

EW0 mode operation procedure

Rewrite control program

Single-chip mode, memory expansion For only boot mode

mode, or boot mode set the FMR05 bit to “1” (user ROM area access)

Set CM0, CM1, and PM1 registers (Note 1) Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)

Transfer a CPU rewrite mode based rewrite control

Execute software commands
program to any area other than the flash memory
(Note 5)

Jump to the rewrite control program which has been Execute the Read Array command
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory) Write “0” to the FMR01 bit
(CPU rewrite mode disabled)

For only boot mode

Write “0” to the FMR05 bit (Boot ROM area
accessed) (Note 4)

Jump to a specified address in the flash memory

Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits.
Also, set the PM1 register’s PM17 bit to “1” (with wait state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA
transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is
“H” level.
Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to “1”.
Note 5: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the
PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended
accessible area (4000016 to BFFFF16) cannot be used.

Figure 1.27.5. Setting and Resetting of EW0 Mode

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Flash Memory

EW1 mode operation procedure

Program in ROM

Single-chip mode (Note 1)

Set CM0, CM1, and PM1 registers (Note 2)

Set the FMR01 bit by writing “0” and then “1” (CPU
rewrite mode enabled)
Set the FMR11 bit by writing “0” and then “1” (EW1
mode) (Note 3)

Execute software commands

Write “0” to the FMR01 bit

(CPU rewrite mode disabled)

Note 1: In EW1 mode, do not set the microcomputer in memory expansion or boot mode.
Note 2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait
state).
Note 3: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Also write only when the NMI pin is “H” level.

Figure 1.27.6. Setting and Resetting of EW1 Mode

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Flash Memory

Low power dissipation

mode program

Transfer a low power dissipation mode program Set the FMR01 bit by writing “0” and then “1”
to any area other the flash memory (CPU rewrite mode enabled)

Jump to the low power dissipation mode program Set FMSTP bit to “1”
which has been transferred to any area other the (flash memory stopped. Low power state)(Note 1)
flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.) Switch the clock source for CPU clock.
Turn main clock off. (Note 2)

Process of low power dissipation mode or

ring oscillator low power dissipation mode

Turn main clock on wait until oscillation stabilizes

switch the clock source for CPU clock (Note 2)

Set the FMSTP bit to “0” (flash memory operation)

Write “0” to the FMR01 bit

(CPU rewrite mode disabled)

Wait until the flash memory circuit stabilizes (tPS)

(Note 3)

Jump to a specified address in the flash memory

Note 1: Set the FMSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).
Note 2: Before the clock source for CPU clock can be changed to
main clock or sub clock, the clock to which to be changed
must be stable.
Note 3: Insert a tPS wait time in a program. The flash memory
cannot be accessed during this wait time.

Figure 1.27.7. Processing Before and After Low Power Dissipation Mode

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Flash Memory

Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using
the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17
bit in the PM1 register to “1” (with wait state).

(2) Instructions to Prevent from Using

The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruc-
tion.

(3) Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.

(4) How to Access

To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.

(5) Writing in the User ROM Space

EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.

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(6) DMA Transfer

In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).

(7) Writing Command and Data

Write the command code and data at even addresses.

(8) Wait Mode

When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.

(9) Stop Mode

When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after returning from stop mode

(10) Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program

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Software Commands
Software commands are described below. The command code and data must be read and written in 16-
bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-
order bits (D1t–D8) are ignored.

Table 1.27.4. Software Commands

First bus cycle Second bus cycle
Command Data Data
Mode Address (D0 to D7) Mode Address (D0 to D7)
Read array Write X xxFF16
Read status register Write X xx7016 Read X SRD
Clear status register Write X xx5016
Program Write WA xx4016 Write WA WD
Block erase Write X xx2016 Write BA xxD016
Erase all unlocked block(Note) Write X xxA716 Write X xxD016
Lock bit program Write BA xx7716 Write BA xxD016
Read lock bit status Write X xx7116 Write BA xxD016
Note: It is only blocks 0 to 12 that can be erased by the Erase All Unlocked Block command.
Block A cannot be erased. Use the Block Erase command to erase block A.
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address
as the write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
xx: High-order 8 bits of command code (ignored)

Read Array Command (FF16)

This command reads the flash memory.
Writing ‘xxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16-bit units.
Because the microcomputer remains in read array mode until another command is written, the con-
tents of multiple addresses can be read in succession.

Read Status Register Command (7016)

This command reads the status register.
Write ‘xx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
to “Status Register.”) When reading the status register too, specify an even address in the user ROM
area.
Do not execute this command in EW1 mode.

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Clear Status Register Command (5016)

This command clears the status register to “0”.
Write ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to
SR5 in the status register will be cleared to “0”.

Program Command (4016)

This command writes data to the flash memory in 1 word (2 byte) units.
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is
“0” during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check.”)
Note that each block can be disabled from being programmed by a clock bit (Refer to “Data Protect
Function”). Be careful not to write over the already programmed addresses.

In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto program-
ming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to
“0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In
this case, the microcomputer remains in read status register mode until a read command is written
next. The result of auto programming can be known by reading the status register after auto program-
ming has finished.

Start

Write the command code ‘xx4016’

to the write address

Write data to the write address

NO
FMR00=1?

YES
Full status check

Program
completed

Note: Write the command code and data at even number.

Figure 1.27.8. Program Command

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Flash Memory

Block Erase
Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known. (Refer to “Full Status Check.”)
Figure 1.27.9 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
Writing over already programmed addresses is inhibited.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.

Start

Write the command code ‘xx2016’

Write ‘xxD016’ to the uppermost

block address

NO
FMR00=1?

YES
Full status check

Block erase completed

Note: Write the command code and data at even number.

Figure 1.27.9. Block Erase Command

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Flash Memory

Erase All Unlocked Block

Write ‘xxA716’ in the first bus cycle and write ‘xxD016’ in the second bus cycle, and all blocks except
block A will be erased successively, one block at a time.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The result of the auto erase
operation can be known by inspecting the FMR0 register’s FMR07 bit.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the
rewrite control program is stored, or when the FMR0 register’s FMR02 bit = 1 (lock bit disabled).
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Note that only blocks 0 to 12 can be erased by the Erase All Unlocked Block command. Block A
cannot be erased. Use the Block Erase command to erase block A.

Lock Bit Program Command (7716/D016)

This command sets the lock bit for a specified block to “0” (locked).
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Figure 1.27.10 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can
be read using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
For details about the lock bit function, and on how to set the lock bit to “1”, refer to “Data Protect
Function.”

Start

Write command code ‘xx7716’ to

the uppermost block address

Write ‘xxD016’ to the uppermost

block address

NO
FMR00=1?

YES
Full status check

Lock bit program completed

Note: Write the command code and data at even number.

Figure 1.27.10. Lock Bit Program Command

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Flash Memory

Read Lock Bit Status Command (7116)

This command reads the lock bit status of a specified block.
Write ‘xx7116’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the
FMR1 register’s FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1”
(ready).
Figure 1.27.11 shows an example of a read lock bit status flowchart.

Start

Write the command code ‘xx7116’

Write ‘xxD016’ to the uppermost

block address

NO
FMR00=1?

YES

NO
FMR16=0?

YES

Block locked Blocks not locked

Note: Write the command code and data at even number.

Figure 1.27.11. Read Lock Bit Status Command

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Flash Memory

Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit =
0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program-
ming and erasure. This helps to prevent data from inadvertently written to or erased from the flash
memory. The following shows the relationship between the lock bit and the block status.

• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased.

The lock bit is cleared to “0” (locked) by executing the Lock Bit Program command, and is set to “1”
(unlocked) by erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command

The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function
(lock bit data retained).
If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target
block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to “1”
after completion of erasure.
For details about the commands, refer to “Software Commands.”

Status Register
The status register indicates the operating status of the flash memory and whether an erase or program-
ming operation terminated normally or in error. The status of the status register can be known by reading
the FMR0 register’s FMR00, FMR06, and FMR07 bits.
Table 1.27.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register
command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,
Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array
command.

Sequencer Status (SR7 and FMR00 Bits )

The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation
finishes.

Erase Status (SR5 and FMR07 Bits)

Refer to “Full Status Check.”

Program Status (SR4 and FMR06 Bits)

Refer to “Full Status Check.”

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Table 1.27.5. Status Register

Status FMR0 Contents Value
register register Status name after
bit bit "0" "1" reset
SR7 (D7) FMR00 Sequencer status Busy Ready 1
SR6 (D6) Reserved - -
SR5 (D5) FMR07 Erase status Terminated normally Terminated in error 0
SR4 (D4) FMR06 Program status Terminated normally Terminated in error 0
SR3 (D3) Reserved - -
SR2 (D2) Reserved - -
SR1 (D1) Reserved - -
SR0 (D0) Reserved - -
• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to “0” by executing the Clear Status Register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked Block,
and Lock Bit Program commands are not accepted.

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Full Status Check

When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check). Table 1.27.6 lists errors and FMR0 register status. Figure 1.27.12 shows a full status
check flowchart and the action to be taken when each error occurs.

Table 1.27.6. Errors and FMR0 Register Status

FRM00 register
(status register)
status Error Error occurrence condition
FMR07 FMR06
(SR5) (SR4)
1 1 Command • When any command is not written correctly
sequence error • When invalid data was written other than those that can be writ-
ten in the second bus cycle of the Lock Bit Program, Block Erase,
or Erase All Unlocked Block command (i.e., other than ‘xxD016’ or
‘xxFF16’) (Note 1)
1 0 Erase error • When the Block Erase command was executed on locked blocks
(Note 2)
• When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not auto-
matically erased correctly
0 1 Program error • When the Block Erase command was executed on locked blocks
(Note 2)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not pro-
grammed correctly
Note 1: Writing ‘xxFF16’ in the second bus cycle of these commands places the microcomputer in read array
mode, and the command code written in the first bus cycle is nullified.
Note 2: When the FMR02 bit = 1 (lock bit disabled), no error will occur under this condition.

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Full status check

FMR06 =1 YES
and Command (1) Execute the Clear Status Register command to set
FMR07=1? sequence error these status flags to “0”.
(2) Reexecute the command after checking that it is
entered correctly.
NO

NO (1) Execute the Clear Status Register command to set

FMR07= Erase error the erase status flag to “0”.
0?
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
YES the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Block Erase or Erase All Unlocked
Block command.
Note 1: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.

[During programming]
NO (1) Execute the Clear Status Register command to set
FMR06= Program error the program status flag to “0”.
0? (2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
YES the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During lock bit programming]
(1) Execute the Clear Status Register command to set
the program status flag to “0”.
(2) Set the FMR0 register’s FMR02 bit to “1”.
(3) Execute the Block Erase command to erase the
block in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error
Full status check completed cannot be used.

Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Erase All Unlocked
Block, Lock Bit Program, or Read Lock Bit Status command is not accepted.
Execute the Clear Status Register command before executing those commands.

Figure 1.27.12. Full Status Check and Handling Procedure for Each Error

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Standard Serial I/O Mode

In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer suitable for the M16C/62P group. For more information
about serial programmers, contact the manufacturer of your serial programmer. For details on how to use,
refer to the user’s manual included with your serial programmer.
Table 1.27.7 lists pin functions (flash memory standard serial input/output mode). Figures 1.27.13 to
1.27.15 show pin connections for standard serial input/output mode.

ID Code Check Function

This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to the description of the functions to inhibit rewriting flash memory version.)

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Table 1.27.7. Pin Functions (Flash Memory Standard Serial I/O Mode)
Power
Pin Name I/O supply Description

Apply the voltage guaranteed for Program and Erase to VCC1 pin and
VCC1, VCC2, Power input VCC2 to the VCC2 pin. The VCC apply condition is that VCC2 ≤ VCC1.
VSS
Apply 0 V to VSS pin.

CNVSS CNVSS I VCC1 Connect to VCC1 pin.

RESET Reset input I VCC1 Reset input pin. While RESET pin is "L" level, input a 20 cycle or
longer clock to XIN pin.

XIN Clock input I VCC1 Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
XOUT Clock output O VCC1 and open XOUT pin.

BYTE BYTE I VCC1 Connect this pin to VCC1 or Vss.

AVCC, AVSS Analog power supply input Connect AVss to Vss and AVcc to VCC1, respectively.

VREF Reference voltage input I Enter the reference voltage for AD from this pin.

P00 to P07 Input port P0 I VCC2 Input "H" or "L" level signal or open.

P10 to P17 Input port P1 I VCC2 Input "H" or "L" level signal or open.

P20 to P27 Input port P2 I VCC2 Input "H" or "L" level signal or open.

P30 to P37 Input port P3 I VCC2 Input "H" or "L" level signal or open.

P40 to P47 Input port P4 I VCC2 Input "H" or "L" level signal or open.
P51 to P54,
Input port P5 I VCC2 Input "H" or "L" level signal or open.
P56, P57

P50 CE input I VCC2 Input "H" level signal.

P55 EPM input I VCC2 Input "L" level signal.

P60 to P63 Input port P6 I VCC1 Input "H" or "L" level signal or open.

P64/RTS1 BUSY output O VCC1 Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
P65/CLK1 SCLK input I VCC1 Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P66/RXD1 RxD input I VCC1 Serial data input pin.

P67/TXD1 TxD output O VCC1 Serial data output pin. (Note 1)

P70 to P77 Input port P7 I VCC1 Input "H" or "L" level signal or open.
P80 to P84, P86, Input port P8 I VCC1 Input "H" or "L" level signal or open.
P87
P85/NMI NMI input I VCC1 Connect this pin to VCC1.

P90 to P97 Input port P9 I VCC1 Input "H" or "L" level signal or open. (Note 2)

P100 to P107 Input port P10 I VCC1 Input "H" or "L" level signal or open. (Note 2)

P110 to P117 Input port P11 I VCC1 Input "H" or "L" level signal or open. (Note 2)

P120 to P127 Input port P12 I VCC2 Input "H" or "L" level signal or open. (Note 2)

P130 to P137 Input port P13 I VCC2 Input "H" or "L" level signal or open. (Note 2)

P140 to P147 Input port P14 I VCC1 Input "H" or "L" level signal or open. (Note 2)
___________
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET
pin is pulled low. Therefore, connect this pin to VCC1 via a resistor. Because this pin is directed for
data output after reset, adjust the pull-up resistance value in the system so that data transfers will
not be affected.
Note 2: Available in only the 128-pin version.

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VCC2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46 CE
86 45
87 44
88 43
89 42
90 M16C/62P Group 41 EPM
91 40
92
93
(Flash memory version) 39
38
94 37
95 36
96 35
97 34 BUSY
98 33 SCLK
99 32 RxD
100 31 TxD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Vss

Connect
oscillator Mode setup method
circuit. Signal Value
CNVss VCC1
RESET

EPM Vss
RESET Vss to VCC1
CE VCC2
CNVss

VCC1

Package: 100P6S-A

Figure 1.27.13. Pin Connections for Serial I/O Mode (1)

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VCC2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

76 50
77 49
78 48
79 47
80 46
81 45
82 44 CE
83 43
84 42
85 41
86 40
87
88
M16C/62P Group 39
38
EPM

89
90
(Flash memory version) 37
36
91 35
92 34
93 33
94 32 BUSY
95 31 SCLK
96 30 RXD
97 29 TXD
98 28
99 27
100 26

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

VSS

Connect
oscillator Mode setup method
circuit. Signal Value
CNVss VCC1
RESET

EPM Vss
RESET Vss to VCC1
CE VCC2
CNVSS

VCC1

Package: 100P6Q-A

Figure 1.27.14. Pin Connections for Serial I/O Mode (2)

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VCC2
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103 64
104 63
105 62
106 61 CE
107 60
108 59
109 58
110 57
111 56
112 55
113 54
114 M16C/62P Group 53
52
115 EPM
116
117
(Flash memory version) 51
50
118 49
119 48
120 47
121 46
122 45
123 44
124 43
125 42
126 41 BUSY
127 40 SCLK
128 39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Vss
RESET

RxD
TxD

Mode setup method

Connect Signal Value
oscillator CNVss VCC1
circuit. EPM Vss
RESET Vss to VCC1
CE VCC2
CNVss

VCC1

Package: 128P6Q-A

Figure 1.27.15. Pin Connections for Serial I/O Mode (3)

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Example of Circuit Application in the Standard Serial I/O Mode

Figure 1.27.16 and 1.27.17 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.

Microcomputer

SCLK input P65/CLK1

P50(CE)
TXD output P67/TXD1 P55(EPM)

BUSY output P64/RTS1

RXD input P66/RXD1 CNVss

Reset input RESET

User reset P85/NMI

signal

(1) Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
(3) If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.

Figure 1.27.16. Circuit Application in Standard Serial I/O Mode 1

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Microcomputer

P65/CLK1 P50(CE)
TXD output P67/TXD1 P55(EPM)

Monitor output P64/RTS1

RXD intput P66/RXD1 CNVss

P85/NMI

(1) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.

Figure 1.27.17. Circuit Application in Standard Serial I/o Mode 2

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Parallel I/O Mode

In parallel input/output mode, the user ROM and boot ROM areas can be rewritten by using a parallel
programmer suitable for the M16C/62 group (M16C/62P). For more information about parallel program-
mers, contact the manufacturer of your parallel programmer. For details on how to use, refer to the user’s
manual included with your parallel programmer.

User ROM and Boot ROM Areas

In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area
contains a standard serial input/output mode based rewrite control program which was written in it when
shipped from the factory. Therefore, when using a serial programmer, be careful not to rewrite the boot
ROM area.
When in parallel output mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other
than the addresses 0FF00016 to 0FFFFF16.)

ROM Code Protect Function

The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)

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Package Dimensions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Package Dimensions
100P6S-A MMP Plastic 100pin 14✕20mm body QFP
EIAJ Package Code JEDEC Code Weight(g) Lead Material
QFP100-P-1420-0.65 – 1.58 Alloy 42 MD

e
HD
D

ME
100 81

b2
1 80

I2

Recommended Mount Pad

Dimension in Millimeters
Symbol
Min Nom Max
HE
E

A – – 3.05
A1 0 0.1 0.2
A2 – 2.8 –
b 0.25 0.3 0.4
c 0.13 0.15 0.2
D 13.8 14.0 14.2
30 51 E 19.8 20.0 20.2
e – 0.65 –
31 50 HD 16.5 16.8 17.1
A
L1 HE 22.5 22.8 23.1
L 0.4 0.6 0.8
L1 – 1.4 –
A2

x – – 0.13
y – – 0.1
c

F 0° – 10°
e b2 – 0.35 –
A1

b x M L
Detail F I2 1.3 – –
y MD – 14.6 –
ME – 20.6 –

100P6Q-A MMP Plastic 100pin 14✕14mm body LQFP

EIAJ Package Code JEDEC Code Weight(g) Lead Material MD
LQFP100-P-1414-0.50 – 0.63 Cu Alloy
e

HD ME
b2

D
100 76
l2
Recommended Mount Pad
1 75
Dimension in Millimeters
Symbol
Min Nom Max
A – – 1.7
A1 0 0.1 0.2
HE

– 1.4 –
E

A2
b 0.13 0.18 0.28
c 0.105 0.125 0.175
D 13.9 14.0 14.1
E 13.9 14.0 14.1
25 51
e – 0.5 –
HD 15.8 16.0 16.2
26 50 HE 15.8 16.0 16.2
A L 0.3 0.5 0.7
L1
F L1 – 1.0 –
e Lp 0.45 0.6 0.75
A3 – 0.25 –
A2

A3

x – – 0.08
y – – 0.1
0° – 10°
A1

b x y L
c

M b2 – 0.225 –
Lp I2 0.9 – –
Detail F
MD – 14.4 –
ME – 14.4 –

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Package Dimensions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

128P6Q-A MMP Plastic 128pin 14✕20mm body LQFP

EIAJ Package Code JEDEC Code Weight(g) Lead Material MD
LQFP128-P-1420-0.50 – – Cu Alloy

e
HD

ME
D

b2
128 103

1 102 l2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min Nom Max
A 1.4 1.5 1.7
A1 0.05 0.125 0.2
HE
E

A2 – 1.4 –
b 0.17 0.22 0.27
c 0.105 0.125 0.175
D 13.9 14.0 14.1
E 19.9 20.0 20.1
e – 0.5 –
38 65
HD 15.8 16.0 16.2
HE 21.8 22.0 22.2
39 64
L1 L 0.35 0.5 0.65
A
L1 – 1.0 –
F
Lp 0.45 0.6 0.75
e A3 – 0.25 –

A3
A2

x – – 0.08
y – – 0.1
0° – 8°
A1

L b2 – 0.225 –
y b x M Detail F Lp I2 – 1.0 –
MD – 14.4 –
ME – 20.4 –

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Differences Between M16C/62P and M16C/62A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Differences Between M16C/62P and M16C/62A

Differences in Mask ROM Version and Flash Memory Version (1) (Note)
Item M16C/62P M16C/62A
Shortest instruction 41.7ns (f(BCLK)=24MHZ, VCC1=3.0 to 5.5V) 62.5ns (f(XIN)=16MHZ, VCC=4.2V to 5.5V)
execution time 100ns (f(BCLK)=10MHZ, VCC1=2.7 to 5.5V) 100ns (f(XIN)=10MHZ, VCC=2.7V to 5.5V
with software one-wait)
Supply voltage VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1 4.2V to 5.5V (f(XIN)=16MHZ, without
(f(BCLK)=24MHZ) software wait)
VCC1=VCC2=2.7 to 5.5V 2.7V to 5.5V (f(XIN)=10MHZ, with software
(f(BCLK)=10MHZ) one-wait)
I/O power supply Double (VCC1, VCC2) Single (VCC)
Package 100-pin, 128-pin plastic mold QFP 80-pin, 100-pin plastic mold QFP
Voltage detection Built-in None
circuit Vdet2, Vdet3, Vdet4 detect
Voltage down detect interrupt
Hardware reset 2
Clock Generating PLL, XIN, XCIN, ring oscillator XIN, XCIN
Circuit When placed in low power mode, a divide- When placed in low power mode, the
by-8 value is used for these clocks. The XIN divide-by-n value for the main clock
drive capability is set to HIGH. does not change. Nor does the XIN
drive capability change.

System clock Built-in None

protective function (protected by protect register)
Oscillation stop, Built-in None
re-oscillation detection
function
Low power 18mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 32.5mA (VCC=5V, f(XIN)=16MHz)
consumption 8mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 8.5mA (VCC=3V, f(XCIN)=10MHz with
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, software one-wait)
when wait mode) 0.9µA (VCC=3V, f(XCIN)=32kHz,
when wait mode)
Memory area Memory area expandable 1 Mbytes fixed
(4 Mbytes)
External device 0400016–07FFF16(PM13=0) 0400016–05FFF16(PM13=0)
connect area 0800016–0FFFF16(PM10=0) 0600016–CFFFF16
1000016–26FFF16 D000016–FFFFF16(Microprocessor mode)
2800016–7FFFF16
8000016–CFFFF16(PM13=0)
D000016–FFFFF16(Microprocessor mode)
Upper address in P40 to P43 (A16 to A19), P34 to P37 (A12 to P40 to P43 (A16 to A19) : Switchable between
memory expansion A15) : Switchable between address bus and address bus and I/O port
mode and I/O port A12 to A15 : No switchable
microprocessor mode
Access to SFR Variable (1 to 2 waits) 1 wait fixed
Software wait to Variable (0 to 3 waits) Variable (0 to 1 wait)
external area
Protect Can be set for PM0, PM1, PM2, CM0, Can be set for PM0, PM1, CM0, CM1,
CM1, CM2, PLC0, INVC0, INVC1, PD9, S3 PD9, S3C, S4C registers
C, S4C, TB2SC, PCLKR, VCR2, D4INT
registers
Watchdog timer Watchdog timer interrupt or watchdog Watchdog timer interrupt
timer reset is selected No count source protective mode
Count source protective mode is available
Address match 4 2
interrupt
Note: About the details and the electric characteristics, refer to data sheet.

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Differences Between M16C/62P and M16C/62A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Differences in Mask ROM version and Flash memory version (2) (Note)
Item M16C/62P M16C/62A
Timers A, B count Selectable: f1, f2, f8, f32, fC32 Selectable: f1, f8, f32, fC32
source
Timer A two-phase Function Z-phase (counter reset) input No function Z-phase (counter reset) input
pulse signal
processing
Timer functions for Function protect by protect register Function protect by protect register
three-phase motor Count source is selected: Count source is selected:
control f1, f2, f8, f32, fC32 f1, f8, f32, fC32
Dead time timer count source is selected: Dead time timer count source is fixed at f1/2
f1, f1 divided by 2, f2 , f2 divided by 2
Three-phase output forcible shutoff function
based on output polarity change, carrier
wave phase detection and NMI input is
available.

Serial I/O (UART, clock synchronous, I2C bus, IE bus) (UART, clock synchronous,) x 2
(UART0 to UART2) x3 (UART, clock synchronous, IIC bus, IE bus)
x1
UART0 to UART2, Select from f1SIO, f2SIO, f8SIO, f32SIO Select from f1, f8, f32
SI/O3, SI/O4 count
source
Serial I/O RTS timing Assert low when receive buffer is read Assert low when reception is completed

CTS/RTS separate Have None

function
UART2 data transmit After data was written, transfer starts at the After data was written, transfer starts at the
timing 2nd BRG overflow timing 1st BRG overflow timing
(same as UART0 and UART1) (Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Serial I/O sleep None Have
function
Serial I/O I2C mode Start condition, stop condition: Start condition, stop condition:
Auto-generationable Not auto-generationable
Serial I/O I2C mode Only digital delay is selected as SDA delay Analog or digital delay is selected as SDA
SDA delay SDA digital delay count source: BRG delay
SDA digital delay count source: 1/ f(XIN)
SI/O3, SI/O4 clock Selectable Fixed
polarity
A-D converter 10 bits X 8 channels 10 bits X 8 channels
Expandable up to 26 channels Expandable up to 10 channels
A-D converter Selectable: fAD, fAD divided by 2, 3, 4, 6, 12 Selectable: fAD, fAD/2, fAD/4
operation clock

A-D converter Select from ports P0, P2, P10 Fixed at port P10
input pin
Note: About the details and the electric characteristics, refer to data sheet.

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Differences Between M16C/62P and M16C/62A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Differences in Flash memory version(Note)

Item M16C/62P M16C/62A
User ROM blocks 14 blocks: 4 Kbytes x 3, 8 Kbytes x 3, 7 blocks: 8 Kbytes x 2, 16 Kbytes x1,
32 Kbytes x1, 64 Kbytes x 7 32 Kbytes x 1, 64 Kbytes x 3
(Flash memory: max. 512 Kbytes) (Flash memory: max. 256 Kbytes)
Program manner Word Page
Program command Page program command: none Page program command: have
(software command) Program command: have Program command: none
(program method: in units of word, in units (program method: in units of page)
of byte)
Block status after None Have
program function

CPU rewrite EW1 mode is available No EW1 mode

mode

Note: About the details and the electric characteristics, refer to data sheet.

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Register Index SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Register Index

A I
AD0 to AD7 190 ICTB2 132
ADCON0 189 IDB0 131
ADCON1 189 IDB1 131
ADCON2 190 IFSR 89
ADIC 81 IFSR2A 89
AIER 92 INT0IC to INT5IC 81
AIER2 92 INVC0 129
INVC1 130
B
K
BCNIC 81
KUPIC 81
C
O
CM0 53
CM1 54 ONSF 109
CM2 55
P
CPSRF 109, 122
CRCD 205 P0 to P13 214
CRCIN 205 PC14 215
CSE 40 PCLKR 56
CSR 34 PCR 217
PD0 to PD13 213
D
PLC0 57
D4INT 25 PM0 30
DA0 204 PM1 31
DA1 204 PM2 56
DACON 204 PRCR 74
DAR0 99 PUR0 to PUR2 216
DAR1 99 PUR3 215
DBR 44
R
DM0CON 98
DM0IC to DM1IC 81 RMAD0 to RMAD3 92
DM0SL 97 ROMCP 263
DM1CON 98
S
DM1SL 98
DTT 131 S0RIC to S2RIC 81
S0TIC to S2TIC 81
F S3BRG 183
FIDR 267 S3C 183
FMR0 267 S3IC to S4IC 81
FMR1 267 S3TRR 183
S4BRG 183

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S4C 183 UCON 143

S4TRR 183 UDF 108
SAR0 99
V
SAR1 99
VCR1 25
T
VCR2 25
TA0 to TA4 108
W
TA0IC to TA4IC 81
TA0MR to TA4MR 107 WDC 24, 94
TA1 132 WDTS 94
TA11 132
TA1MR 134
TA2 132
TA21 132
TA2MR 134
TA4 132
TA41 132
TA4MR 134
TABSR 108, 122, 133
TB0 to TB5 122
TB0IC to TB5IC 81
TB0MR to TB5MR 121
TB2 133
TB2MR 134
TB2SC 132
TBSR 122
TCR0 99
TCR1 99
TRGSR 109, 133

U
U0BCNIC to U1BCNIC 81
U0BRG to U2BRG 140
U0C0 to U2C0 141
U0C1 to U2C1 142
U0MR to U2MR 141
U0RB to U2RB 140
U0SMR to U2SMR 143
U0SMR2 to U2SMR2 144
U0SMR3 to U2SMR3 144
U0SMR4 to U2SMR4 145
U0TB to U2TB 140

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 REVISION HISTORY M16C/62 GROUP (M16C/62P) Group Hardware Manual

Rev. Date Description

Page Summary
1.0 Jan/31/Y03 1 Applications are partly revised.
(Continued) 2 Table 1.1.1 is partly revised.
5 Table 1.1.3 is partly revised.
5 Figure 1.1.2 is partly revised.
11 Explanation of “Memory” is partly revised.
20 Explanation of “Hardware Reset 1” is partly revised.
21 Figure 1.5.1 is partly revised.
22 Figure 1.5.2 is partly revised.
24 Figure 1.5.4 is partly revised.
25 VCR2 Register in Figure 1.5.6 is partly revised.
26 Figure 1.5.6 is partly revised.
27 Explanation of “Power Supply Down Detection Interrupt” is partly revised.
30 Figure 1.6.1 is partly revised.
31 Figure 1.6.2 is partly revised.
39 Table 1.7.5 is partly revised.
41 Table 1.7.7 is partly revised.
43 Figure 1.7.8 is partly revised.
44 Explanation of “4 Mbyte Mode” is partly revised.
53 Notes 12 and 13 in Figure 1.9.2 is partly revised.
54 Notes 2 and 5 in Figure 1.9.3 is partly revised.
55 Figure 1.9.4 is partly revised.
57 Note 4 in Figure 1.9.6 is partly revised.
60 Explanation of “PLL Clock” is partly revised.
61 Figure 1.9.9 is partly revised.
62 Explanation of “CPU Clock and BCLK” is partly revised.
63 Explanation of “Low-speed Mode” is partly revised.
63 Explanation of “Low Power Dissipation Mode” is partly revised.
64 Explanation of “Ring Oscillator Low Power Dissipation Mode” is partly revised.
64 Table 1.9.3 is partly revised.
65 Table 1.9.5 is partly revised.
68 Figure 1.9.10 is partly revised.
69 Figure 1.9.11 is partly revised.
70 Table 1.9.7 is added.
71 Explanation of “System Clock Protective Function” is partly revised.
77 Explanation of “Power Supply Down Detection Interrupt” is partly revised.
78 Table 1.11.1 is partly revised.
88 Figure 1.11.9 is partly revised.
96 WDTS Register in Figure 1.12.2 is partly revised.
99 Figure 1.13.2 is partly revised.
100 Figure 1.13.3 is partly revised.
103 Figure 1.13.5 is partly revised.
104 Table 1.13.3 is partly revised.
105 Explanation of “DMA Enable” is partly revised.
109 Figure 1.14.3 is partly revised.
115 Table 1.14.3 is partly revised.
117 Explanation of “Counter Initialization by Two-Phase Pulse Signal Processing” is
partly revised.
117 Figure 1.14.10 is partly revised.
122 Figure 1.14.14 is partly revised.
122 Figure 1.14.15 is partly revised.

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Rev. Date Description

Page Summary
1.0 Jan/31/Y03 124 Figure 1.15.3 is partly revised.
(Continued) 128 Figure 1.15.7 is partly revised.
128 Figure 1.15.8 is partly revised.
130 Figure 1.16.1 is partly revised.
132 Figure 1.16.3 is partly revised.
134 Note 7 is added to TAi, TAi1 Register in Figure 1.16.5.
137 Figure 1.16.8 is partly revised.
146 UiSMR2 Register in Figure 1.17.7 is partly revised.
163 Figure 1.20.1 is partly revised.
164, 165 Table 1.20.2 and Table 1.20.3 are partly revised.
169 Figure 1.20.4 is partly revised.
169 Explanation of “Arbitration” is partly revised.
170 Explanation of “Transfer Clock” is partly revised.
171 Explanation of “ACK and NACK” is partly revised.
179 Explanation of “Special Mode 4 (SIM Mode)” is partly revised.
179 Table 1.20.9 is partly revised.
184 Figure 1.21.1 is partly revised.
187 Figure 1.21.4 is partly revised.
203 Explanation of “External Operation Amp Connection Mode” is partly revised.
205 Explanation of “Caution of Using A-D Converter” is partly revised.
205 Figure 1.22.11 is partly revised
206 Table 1.23.1 is partly revised.
207 Figure 1.23.3 is partly revised.
218 Figure 1.25.9 is partly revised.
223 Table 1.26.1 is partly revised.
224 Table 1.26.2 is partly revised.
225 Note 1 of Table 1.26.3 is partly revised.
225 Note 1 of Table 1.26.4 is partly revised.
225 Table 1.26.6 is partly revised.
227 Note 1 of Table 1.26.9 is partly revised.
228 Note 1 of Table 1.26.10 is partly revised.
229 Measurement conditions of timing requirements are partly revised.
229 Table 1.26.11 is partly revised.
230 Measurement conditions of timing requirements are partly revised.
230 Table 1.26.18 is added.
231 Measurement conditions of timing requirements are partly revised.
232 Measurement conditions of switching characteristics are partly revised.
233 Measurement conditions of switching characteristics are partly revised.
234 Measurement conditions of switching characteristics are partly revised.
235 Figure 1.26.2 is partly revised.
242 Figure 1.26.9 is partly revised.
244 Note of Table 1.26.28 is partly revised.
245 Figure 1.26.29 is partly revised.
246 Measurement conditions of timing requirements are partly revised.
246 Table 1.26.30 is partly revised.
247 Measurement conditions of timing requirements are partly revised.
247 Table 1.26.37 is added.
248 Measurement conditions of timing requirements are partly revised.
249 Measurement conditions of switching characteristics are partly revised.
250 Measurement conditions of switching characteristics are partly revised.

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 REVISION HISTORY M16C/62 GROUP (M16C/62P) Group Hardware Manual

Rev. Date Description

Page Summary
1.0 Jan/31/Y03 251 Measurement conditions of switching characteristics are partly revised.
252 Figure 1.26.12 is partly revised.
255 Figure 1.26.15 is partly revised.
256 Figure 1.26.16 is partly revised.
257 Figure 1.26.17 is partly revised.
258 Figure 1.26.18 is partly revised.
259 Figure 1.26.19 is partly revised.
260 Figure 1.26.20 is partly revised.
262 Explanation of “Memory Map” is partly revised.
263 Explanation of “Boot Mode” is partly revised.
264 Figure 1.27.3 is partly revised.
268 Note of FIDR Register in Figure 1.27.4 is partly revised.
271 Figure 1.27.7 is partly revised.
272 Explanation of “Interrupts” is partly revised.
272 Explanation of “Writing in the User ROM Space” is partly revised.
274 Table 1.27.4 is partly revised.
274 Explanation of “Read Array Command” is partly revised.
278 Explanation of “Program Command” is partly revised.
287 Figure 1.27.15 is partly revised.
293 Partly revised.
1.10 May/28/Y03 2 Table 1.1.1 is partly revised.
(Continued) 4-5 Table 1.1.2 and 1.1.3 is partly revised.
14-19 SFR is partly revised.
Note 1 is partly revised.
20 Explanation of “Hardware Reset 1” is partly revised.
23 Note 1 is added.
24 Figure 1.5.4 is partly revised.
Note 1 of Figure 1.5.5 is partly revised.
26 Figure 1.5.7 is partly revised.
27 Table 1.5.2 is partly revised.
Table 1.5.3 is partly revised.
Explanation of “1. Limitations on Stop Mode” is partly revised.
28 Explanation of “1. Limitations on WAIT instruction” is partly revised.
Figure 1.5.8 is partly revised.
31 Note is added.
33 Explanation of “Multiplexed Bus” is revised.
34 Explanation of “(2) Data Bus” is revised.
38 Explanation of “(7) Hold Signal” is revised.
Note 3 of Table 1.7.4 is added.
39 Note 4 of Table 1.7.5 is added.
40 Explanation of “(10) Software Wait” is revised.
41 Table 1.7.7 is revised.
46 Table of Figure 1.8.5 is revised.
47 Explanation is revised.
48-50 Figures 1.8.7 to 1.8.9 is partly revised.
51 Explanation of “Clock Generation Circuit” is revised.
52 Figure 1.9.1 is revised.
53 Note of Figure 1.9.2 is revised.
55 Note 12 is added.
58 Explanation of “(1) Main clock” is partly revised.

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 REVISION HISTORY M16C/62 GROUP (M16C/62P) Group Hardware Manual

Rev. Date Description

Page Summary
1.10 May/28/Y03 60 Explanation of “(4) PLL Clock” is partly revised.
(Continued) 63 Explanation of “Low power Dissipation Mode” is partly revised.
64 Explanation of “Entering Wait mode” is partly revised.
66 Explanation of “(3) Stop Mode” is partly revised.
69 Note 9 is added.
70 Table 1.9.7 is revised.
75 Figure 1.11.1 is revised.
79 Note 6 is added.
83 Note 2 is added to Figure 1.11.4.
84 Table 1.11.5 is partly revised.
85 Figure 1.11.6 is partly revised.
86 Figure 1.11.8 is partly revised.
89 Notes 1 to 2 is added to IFSR register of Figure 1.11.4.
91 Explanation of “Address Match Interrupt” is partly revised.
Figure 1. 11.12 is changed into Table 1.11.6.
93-94 Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/62P)
USAGE NOTES”).
93 Explanation of “Watchdog Timer” is partly revised.
94 A formula is added.
104 Explanation of “Channel Priority Transfer Timing” is partly revised.
109 TRGSR register of Figure 1.14.6 is partly revised.
116 Table 1.14.4 is partly revised.
117 Figure 1.14.12 is partly revised.
129 Figure 1.16.2 is partly revised.
130 Figure 1.16.3 is partly revised.
143 U0SMR to U2SMR of Figure 1.17.6 is partly revised.
144 U0SMR2 to U2SMR2 of Figure 1.17.7 is partly revised.
154, 162, “-” of UiBRG of Tables 1.19.2, 1.20.2 and 1.20.8 is changed into “0 to 7”.
175
161 Figure 1.20.1 is partly revised.
164 Table 1.20.4 is partly revised. Notes 5 to 7 is added.
166 Explanation of “Output of Start and Stop Condition” is partly revised.
177 Note 2 is added to Table 1.20.9.
178 “-” of U2BRG of Table 1.20.10 is changed into “0 to 7”.
179 Figure 1.20.10 is revised.
183 Note of SiC register of Figure 1.21.2 is partly revised.
187 Note 2 of Table 1.22.1 is revised.
188 Figure 1.22.1 is partly revised.
190 Table of ADCON2 register of Figure 1.22.3 is partly revised.
202 The value of a capacitor of Figure 1.22.10 is changed.
Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/62P)
USAGE NOTES”).
208-212 Note 1 of Figures 1.25.1 to 1.25.5 is partly revised.
218 Table 1.25.1 and 1.25.2 is revised.
219 Figure 1.25.12 is partly revised.
222 Table 1.26.3 is partly revised.
223 Table 1.26.5 is partly revised.
Table 1.26.6 is added.
224 Table 1.26.9 is partly revised.
230 Notes 1 and 2 in Table 1.26.26 is partly revised.

C-4
 REVISION HISTORY M16C/62 GROUP (M16C/62P) Group Hardware Manual

Rev. Date Description

Page Summary
1.10 May/28/Y03 231 Notes 1 in Table 1.26.27 is partly revised.
230-231 Note 3 is added to “Data output hold time (refers to BCLK)” in Table 1.26.26 and
1.26.27.
232 Note 4 is added to “th(ALE-AD)” in Table 1.26.28.
230-232 Switching Characteristics is partly revised.
236-239 th(WR-AD) and th(WR-DB) in Figure 1.26.5 to 1.5.8 is partly revised.
240-241 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.9 to 1.5.10 is
partly revised.
242 Note 2 is added to Table 1.26.29.
247 Notes 1 and 2 in Table 1.26.45 is partly revised.
248 Notes 1 in Table 1.26.46 is partly revised.
247-248 Note 3 is added to “Data output hold time(refers to BCLK)” in Table 1.26.45 and
1.26.46.
249 Note 4 is added to “th(ALE-AD)” in Table 1.26.47.
247-249 Switching Characteristics is partly revised.
253-256 th(WR-AD) and th(WR-DB) in Figure 1.26.15 to 1.5.18 is partly revised.
257-258 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.19 to 1.5.20 is
partly revised.
259 Table 1.27.1 is partly revised. Notes 3 and 4 is added.
260 Notes 1 and 2 is added to Table 1.27.2.
264 Note 2 is added to Table 1.27.3.
267 Notes 1 and 3 of FMR0 register of Table 1.27.4 is partly revised.
268 Figure 1.27.5 is partly revised. Note 2 is added.
270 Figure 1.27.7 is partly revised.
277 Figure 1.27.11 is partly revised.
281 Figure 1.27.12 is partly revised.
283 Table 1.27.7 is partly revised.
284-286 Figures 1.27.13 to 1.27.15 is partly revised.
287-288 Figures 1.27.16 and 1.27.17 is partly revised.
292-293 Difference in Mask ROM Version and Flash Memory Version is revised.
294 Difference in Flash Memory Version is revised.
1.11 June/20/Y03 259 Number of program and erasure in Table 1.26.27 is partly revised.

1.20 Sep/11/Y03 94 Figure 1.12.2 is revised.

C-5
 RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M16C/62 Group (M16C/62P) Rev.1.20

Editioned by
Committee of editing of RENESAS Semiconductor Hardware Manual

This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
 M16C/62 Group (M16C/62P)
Hardware Manual

2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

REJ09B0017-0110Z

M16C/62 Group(M16C/62P)
16 Usage Notes Reference Book

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

M16C FAMILY / M16C/60 SERIES

For the most current Usage Notes Reference Book, please visit our website.

Before using this material, please visit our website to confirm that this is the most
current document available.

Rev. 1.10
Revision date: May. 28, 2003 www.renesas.com
 Keep safety first in your circuit designs!
• Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
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Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the
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he products contained therein.
Preface
The “Usage Notes Reference Book” is a
compilation of usage notes from the
Hardware Manual as well as technical
news related to this product.
 Table of Contents
1. Usage Precaution_______________________________________ 1
1.1 Precautions for External Bus .......................................................................................................... 1

1.2 Precautions for PLL Frequency Synthesizer .................................................................................. 2

1.3 Precautions for Power Control ........................................................................................................ 3

1.4 Precautions for Protect ................................................................................................................... 4

1.5 Precautions for Interrupts ............................................................................................................... 5

1.5.1 Reading address 0000016 ....................................................................................................... 5

1.5.2 Setting the SP .......................................................................................................................... 5

_______
1.5.3 The NMI Interrupt ..................................................................................................................... 5

1.5.4 Changing the Interrupt Generate Factor .................................................................................. 6

______
1.5.5 INT Interrupt ............................................................................................................................. 6

1.5.6 Rewrite the Interrupt Control Register ..................................................................................... 7

1.5.7 Watchdog Timer Interrupt ........................................................................................................ 8

1.6 Precautions for DMAC .................................................................................................................... 9

1.6.1 Write to DMAE Bit in DMiCON Register .................................................................................. 9

1.7 Precautions for Timers .................................................................................................................. 10

1.7.1 Timer A .................................................................................................................................. 10

1.7.1.1 Timer A (Timer Mode).................................................................................................... 10

1.7.1.2 Timer A (Event Counter Mode) ...................................................................................... 11

1.7.1.3 Timer A (One-shot Timer Mode) .................................................................................... 12

1.7.1.4 Timer A (Pulse Width Modulation Mode) ....................................................................... 13

1.7.2 Timer B .................................................................................................................................. 14

1.7.2.1 Timer B (Timer Mode).................................................................................................... 14

1.7.2.2 Timer B (Event Counter Mode) ...................................................................................... 15

1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) ............................................ 16

1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O) ............................................................ 17

1.8.1 Transmission/reception .......................................................................................................... 17

1.8.2 Transmission ......................................................................................................................... 18

1.8.3 Reception ............................................................................................................................... 19

A-1
1.9 Precautions for Serial I/O (UART Mode) ...................................................................................... 20

1.9.1 Special Mode 2 ..................................................................................................................... 20

1.9.2 Special Mode 4 (SIM Mode) ................................................................................................. 20

1.10 Precautions for A-D Converter .................................................................................................... 21

1.11 Precautions for Programmable I/O Ports .................................................................................... 23

1.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ...... 24

1.13 Precautions for Flash Memory Version ....................................................................................... 25

1.13.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite ................................ 25

1.13.2 Precautions for Stop mode .................................................................................................. 25

1.13.3 Precautions for Wait mode .................................................................................................. 25

1.13.4 Precautions for Low power dissipation mode, ring oscillator low power dissipation mode ................. 25

1.13.5 Writing command and data .................................................................................................. 25

1.13.6 Precautions for Program Command .................................................................................... 25

1.13.7 Precautions for Lock Bit Program Command ...................................................................... 26

1.13.8 Operation speed .................................................................................................................. 26

1.13.9 Instructions inhibited against use ......................................................................................... 26

1.13.10 Interrupts ............................................................................................................................ 26

1.13.11 How to access ................................................................................................................... 26

1.13.12 Writing in the user ROM area ............................................................................................ 27

1.13.13 DMA transfer ...................................................................................................................... 27

1.13.14 Regarding Programming/Erasure Times and Execution Time .......................................... 27

2. Differences Made Depending on Manufactured Time ________ 28

2.1 Vdet2 Detection ............................................................................................................................ 28

2.2 RESET Input ................................................................................................................................. 29

2.3 Serial I/O ....................................................................................................................................... 30

A-2
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for External Bus

1. Usage Precaution

1.1 Precautions for External Bus

1. The external ROM version can operate only in the microprocessor mode, connect the CNVSS pin to
VCC1.

2. When resetting CNVss pin with "H" input, contents of internal ROM cannot be read out.

1
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.2 Precautions for PLL Frequency Synthesizer

1.2 Precautions for PLL Frequency Synthesizer

Make the supply voltage stable to use the PLL frequency synthesizer.
For ripple with the supply voltage 5V, keep below 10kHz as frequency, below 0.5V (peak to peak) as
voltage fluctuation band and below 1V/mS as voltage fluctuation rate.
For ripple with the supply voltage 3V, keep below 10kHz as frequency, below 0.3V (peak to peak) as
voltage fluctuation band and below 0.6V/mS as voltage fluctuation rate.

2
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.3 Precautions for Power Control

1.3 Precautions for Power Control

____________
1. When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is
stabilized.

2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, de-
pending on a combination of instruction and an execution timing.

3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.

4. Suggestions to reduce power consumption

(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connec-
tion). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after setting
the VCUT bit to “1” (VREF connection).
(c) D-A converter
When not performing D-A conversion, set the DAiE bit (i=0, 1) of DACON register to “0” (input inhib-
ited) and DAi register to “0016”.
(d) Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
(e) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(f) External clock
When using an external clock input for the CPU clock, set the CM0 register CM05 bit to “1” (stop).
Setting the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the amount
of current drawn in the chip. (When using an external clock input, note that the clock remains fed into
the chip regardless of how the CM05 bit is set.)

3
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Protect

1.4 Precautions for Protect

Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.

4
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Interrupts

1.5 Precautions for Interrupts

1.5.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.

1.5.2 Setting the SP

Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
_______
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
_______
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.

_______
1.5.3 The NMI Interrupt
_______ _______
1. The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a
resistor (pull-up).
_______
2. The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5
_______
bit can only be read when determining the pin level in NMI interrupt routine.
_______
3. Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
_______
NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
_______ _______
4. Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
_______
5. The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.

5
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Interrupts

1.5.4 Changing the Interrupt Generate Factor

If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 1.5.1 shows the procedure for changing the interrupt generate factor.

Changing the interrupt source

Disable interrupts (Note 2, Note 3)

Change the interrupt generate factor (including a mode change of peripheral function)

Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)

Enable interrupts (Note 2, Note 3)

End of change

IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed

Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section 1.1.6, “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.

Figure 1.5.1. Procedure for Changing the Interrupt Generate Factor

______
1.5.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
________ ________
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.

6
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Interrupts

1.5.6 Rewrite the Interrupt Control Register

(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET

Changing the IR bit

Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.

(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue
buffer.

Example 1:Using the NOP instruction to keep the program waiting until
the interrupt control register is modified
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
NOP ;
NOP
FSET I ; Enable interrupts.

The number of NOP instruction is as follows.

PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4.

Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.

Example 3:Using the POPC instruction to changing the I flag

INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
POPC FLG ; Enable interrupts.

7
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Interrupts

1.5.7 Watchdog Timer Interrupt

Initialize the watchdog timer after the watchdog timer interrupt occurs.

8
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.6 Precautions for DMAC

1.6 Precautions for DMAC

1.6.1 Write to DMAE Bit in DMiCON Register

When both of the conditions below are met, follow the steps below.

Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.

Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously(*1).
Step 2: Make sure that the DMAi is in an initial state(*2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.

Notes:
*1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to
“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.

*2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If
the read value is a value in the middle of transfer, the DMAi is not in an initial state.

9
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7 Precautions for Timers

1.7.1 Timer A

1.7.1.1 Timer A (Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.

______
3. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.

10
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.1.2 Timer A (Event Counter Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in the
TAi register while not counting, the set value is read.

______
3. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.

11
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.1.3 Timer A (One-shot Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.

2. When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).

3. Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs between
a trigger input to TAiIN pin and output in one-shot timer mode.

4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.

5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, gener-
ate a second trigger between occurring the previous trigger and operating longer than one cycle of
a timer count source.

______
6. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.1.4 Timer A (Pulse Width Modulation Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.

2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.

3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.

______
4. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.2 Timer B

1.7.2.1 Timer B (Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.

2. A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.2.2 Timer B (Event Counter Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.

2. The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the
TBi register is read after setting a value in it while not counting but before the counter starts count-
ing, the read value is the one that has been set in the register.

15
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for Timers

1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)

1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5)
register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the
TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.

2. The IR bit of TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be deter-
mined by use of the MR3 bit of TBiMR register within the interrupt routine.

3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.

4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).

5. Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.

6. When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.

7. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer
Bi interrupt request may be generated between a count start and an effective edge input.

8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 5) register and the TBi register before setting the TABSR register or TBiS bit in the TBSR
register to “1” (count starts).
Always make sure the TBiMR registe is modified while the TBiS bit remains “0” (count stops) re-
gardless whether after reset or not.

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O)

1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O)

1.8.1 Transmission/reception
_______ ________
1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
________ ________
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
_______
reception data with consistent timing. With the internal clock, the RTS function has no effect.

_______
2. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______ _________
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance
state.

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O)

1.8.2 Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit =
“0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer
clock), the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is
in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register = “0” (data present in UiTB register)
_______ _______
• If CTS function is selected, input on the CTSi pin = “L”

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O)

1.8.3 Reception
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix set-
tings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.

2. When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data to the
UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin.

3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an overrun
error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case, because
the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on
the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit-
ted. Note that when an overrun error occurred, the SiRIC register IR bit does not change state.

4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.

5. When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
• The RE bit of UiC1 register= “1” (reception enabled)
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register= “0” (data present in the UiTB register)

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.9 Precautions for Serial I/O (UART Mode)

1.9 Precautions for Serial I/O (UART Mode)

1.9.1 Special Mode 2
_______
If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = 1 (three-phase output
_______ _________
forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.

1.9.2 Special Mode 4 (SIM Mode)

A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to “0” (no interrupt request) after setting these bits.

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.10 Precautions for A-D Converter

1.10 Precautions for A-D Converter

1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before
a trigger occurs).

2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con-
nected), start A-D conversion after passing 1 µs or longer.

3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7)AN0i, AN2i) each and the
AVSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 1.10.1 is an ex-
ample connection of each pin.

4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the ADTRG pin is set to “0” (input mode).

5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)

6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.

7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.

Microcomputer
VCC1 VCC1
VCC1 AVCC
C4

VSS VREF
C1 C2

VCC2 AVSS
VCC2 C3
C5 ANi
VSS

ANi: ANi, AN 0i, and AN 2i (i=0 to 7)

Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.

Figure 1.10.1. Use of capacitors to reduce noise

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.10 Precautions for A-D Converter

8. If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.

9. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the
ADIC register’s IR bit to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.

10. If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit
to “0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents
of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.

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 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.11 Precautions for Programmable I/O Ports

1.11 Precautions for Programmable I/O Ports

_______
1. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______
output forcible cutoff by input on NMI pin enabled), the P72 to P75, P80 and P81 pins go to a high-
impedance state.

2. Setting the SM32 bit in the S3C register to “1” causes the P92 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P96 pin to go to a high-impedance
state.

3. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers

1.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-
ducted in the flush memory version.

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.13 Precautions for Flash Memory Version

1.13 Precautions for Flash Memory Version

1.13.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite

ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written
in standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.

1.13.2 Precautions for Stop mode

When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after returning from stop mode

1.13.3 Precautions for Wait mode

When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode diabled) before executing the
WAIT instruction.

1.13.4 Precautions for Low power dissipation mode, ring oscillator low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program

1.13.5 Writing command and data

Write the command code and data at even addresses.

1.13.6 Precautions for Program Command

Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.

25
 Renesas microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.13 Precautions for Flash Memory Version

1.13.7 Precautions for Lock Bit Program Command

Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure the
address value specified in the first bus cycle is the same uppermost block address that is specified in the
second bus cycle.

1.13.8 Operation speed

Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the
CM0 register’s CM06 bit and CM1 register’s CM17–6 bits. Also, set the PM1 register’s PM17 bit to 1 (with
wait state).

1.13.9 Instructions inhibited against use

The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

1.13.10 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.

1.13.11 How to access

To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary to
ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when
_______
NMI pin is “H” level.

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.13 Precautions for Flash Memory Version

1.13.12 Writing in the user ROM area

EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.

1.13.13 DMA transfer

In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).

1.13.14 Regarding Programming/Erasure Times and Execution Time

As the number of programming/erasure times increases, so does the execution time for software com-
mands (Program, Block Erase, Erase All Unlock Blocks, and Lock Bit Program). Especially when the
number of programming/erasure times exceeds 1,000, the software command execution time is notice-
ably extended. Therefore, the software command wait time that is set must be greater than the maximum
rated value of electrical characteristics.
_______
The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is aborted by such reset or interrupt, the block that was in process
must be erased before reexecuting the aborted command.

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.1 Vdet2 Detection

2. Differences Made Depending on Manufactured Time

2.1 Vdet2 Detection

The present version of the products may not detect the Vdet2 voltage in the voltage detection circuit prop-
erly. Therefore, the followings should be noted.
(1) When the VC25 bit in the VCR2 register is set to “1” (enabling the RAM retention limit detection
circuit), the present version may not be reset even if the voltage at the Vcc1 input pin drops below
Vdet2.
(2) The WD5 bit in the WDC register may not change properly.

Supplementary Explanation
Normally, during the stop mode, the Vdet3 voltage is not detected, and thus no reset is generated even
when the input voltage at the VCC1 pin drops to Vdet3 or less. Therefore, if the microcomputer is not reset
when the VCC1 voltage drops below Vdet2 due to the reason described in the above No.1, the microcom-
puter cannot get out of the stop mode with Hardware Reset 2.

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 Renesas microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2 RESET Input

2.2 RESET Input

Ensure that pin RESET must hold valid-low state during powering-up.
When using a reset IC, use a CMOS type IC. When using an open-drain type reset IC, insert a capacitor
between the reset input and Vss and a resistor between the input and Vcc respectively. The R-C time
constant of the capacitor and resistor must provide a low state at least 10 times longer than the Vcc rise
time.

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M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.3 Serial I/O

2.3 Serial I/O

For the RXDi input setup time, refer to the rated values shown below, as well as Electrical Characteristics
Table 1.26.23, “Serial I/O,” and Table 1.26.42, “Serial I/O,” in the Hardware Manual.

Table2.3.1. Serial I/O (VCC1=VCC2=5V)

Standard
Symbol Parameter Unit
Min. Max.
tsu(D-C) RxDi input setup time 70 ns
Note: Refer to “Table 1.26.23. Serial I/O of the Electrical Characteristics in the Hardware Manual”.

Table2.3.2. Serial I/O (VCC1=VCC2=3V)

Standard
Symbol Parameter Unit
Min. Max.
tsu(D-C) RxDi input setup time 100 ns
Note: Refer to “Table 1.26.42. Serial I/O of the Electrical Characteristics in the Hardware Manual”.

30
 REVISION HISTORY M16C/62 GROUP (M16C/62P) USAGE NOTES

Rev. Date Description

Page Summary
1.0 Jan/31/Y03 1 Figure 1.1.1 is partly revised.
8 The section “1.3 Precautions for DMAC” is added.
9 The section “1.4.1 Timers A and B” is added.
15 The section “1.4.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode” is
partly revised.
18 The section “1.5.3 Reception” is partly revised.
19 The section “1.6 Precautions for Serial I/O (UART Mode, Special Mode 2)” is partly
revised.
22 The section “1.8 Precautions for Power Control” is partly revised.
25 The section “1.11.1 Precautions for Functions to Inhibit Rewriting Flash Memory
Rewrite” is partly revised.
26 The section “1.11.2 Precautions for Program Command” is partly revised.
38 The section “1.12 Precautions for PLL Frequency Synthesizer” is partly revised.
1.10 May/28/Y03 - A written order is all changed.
5-8 The written order of the section “1.5 Precautions for Interrupt” is changed.
5 The section “1.5.2 Setting the SP” is added.
6 The section “1.5.4 Changing the Interrupt Generate Factor” is added.
Figure 1.5.1 is revised.
______
The section “1.5.5 INT Interrupt” is revised.
7 The section “1.5.6 Rewrite the Interrupt Control Register” is revised.
10 The text of the section “1.7 Precautions for Timers” and the section “1.7.1 Timer A”
is deleted.
10 to 13 “1.” of the section “1.7.1.1 Timer A (Timer Mode)” to “1.7.1.4 Timer A (Pulse Width
Modulation Mode)”is revised.
14 “1.” of the section “1.7.2.1 Timer B (Timer Mode)” is revised.
15 “1.” of the section “1.7.2.2 Timer B (Event Counter Mode)” is added.
16 “1.” of the section “1.7.2.3 Timer B (Pulse Period/Pulse Width Measurement Mode)”
is revised.
20 The section “1.9.2 Special Mode 4 (SIM Mode)” is added.
21 Figure 1.10.1 is revised.
22 A written order is changed.
23 “2.” of the section “1.11 Precautions for Programmable I/O Ports” is revised.
25-27 The written order of the section “1.13 Precautions for Flash Memory Version” is
changed.
27 The section “1.13.14 Regarding Programming/Erasure Times and Execution Time”
is added.
29 The section “2.2 RESET Input” is added.
30 The section “2.3 Serial I/O” is added.

B-1
 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
USAGE NOTES REFERENCE BOOK
M16C/62 Group (M16C/62P) Rev.1.10

Editioned by
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Usage Notes Reference Book

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