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LP VLSI Syllabus

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Pradeep Kumar
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51 views

LP VLSI Syllabus

syllabus

Uploaded by

Pradeep Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LOW POWER VLSI

ECE 414(c) Credits:3


Instruction : 3 periods & 1 Tutorial/Week Sessional Marks:40
End Exam : 3 Hours End Exam Marks:60
Prerequisites: Digital Electronics, VLSI design
Course objectives:
 To make students familiar with power dissipation, power optimization techniques and power
estimation in VLSI circuits.
 To make student design the power efficient VLSI systems by applying low power design
techniques.
Course Outcomes:
By the end of the course, students will be able to
1. Explain the sources of power dissipation in CMOS
2. Classify the special techniques to mitigate the power consumption in VLSI circuits
3. Summarize the power optimization and trade-off techniques in digital circuits.
4. Illustrate the power estimation at logic and circuit level
5. Explain the software design for low power in various level
CO-PO –PSO Mapping

CO PO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
CO1 3 1 1
CO2 3 2 1
CO3 3 3 1
CO4 3 3 1 1
CO5 2 3 3 2 2 1
Correlation levels 1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High)
SYLLABUS
UNIT I 10 Periods
Power Dissipation in CMOS :Sources of power dissipation – Physics of power dissipation in
MOSFET devices: The MIS structure, long channel MOSFET, Submicron MOSFET, gate
induced drain leakage– Power dissipation in CMOS: short circuit dissipation, dynamic
dissipation, load capacitance– Low power VLSI design: Limits – principles of low power design,
hierarchy of limits, fundamental limit, material limit, device limit, system limit.

UNIT II 10 Periods
Power Optimization Using Special Techniques : Power Reduction in Clock Networks:
Clock Gating, Reduced Swing Clock, Oscillator Circuit for Clock Generation, Frequency
Division and Multiplication, Other Clock Power Reduction Techniques - CMOS Floating Node:
Tristate Keeper Circuit, Blocking Gate, Low Power Bus: Low Swing Bus, Charge Recycling
Bus, Delay Balancing - Low Power Techniques for SRAM: SRAM Cell, Memory Bank
Partitioning, Pulsed Word line and Reduced bit line Swing

UNIT III 10 Periods


Design of Low Power Circuits: Transistor and Gate Sizing : Sizing an Inverter Chain,
Transistor and Gate Sizing for Dynamic Power Reduction, Transistor Sizing for Leakage Power
Reduction - Network Restructuring and Reorganization : Transistor Network Restructuring,
Transistor Network Partitioning and Reorganization - Special Latches and Flip-flops : Self-
gating Flip-flop, Combinational Flip-flop, Double Edge Triggered Flip-flop - Low Power Digital
Cell Library : Cell Sizes and Spacing, Varieties of Boolean Functions, Adjustable Device
Threshold Voltage
UNIT IV 10 Periods
Power Estimation: Modeling of signals - signal probability calculation - Statistical techniques -
estimation of glitching power- Sensitivity Analysis-Power estimation using input vector
compaction, power dissipation in Domino logic, circuit reliability, power estimation at the circuit
level, Estimation of maximum power: test generation based approach, steepest descent, generic
based algorithm based approach

UNIT V 10 Periods
Software Design for Low Power: Sources of software power dissipation - software power
estimation: Gate level, architecture level, bus switching activity, instruction level power analysis
- software power optimization: minimizing memory access costs, instruction selection and
ordering, power management - Automated low power code generation – Co-design for low
power.

TEXT BOOKS:
1.Kaushik Roy, S.C.Prasad,“LowpowerCMOSVLSIcircuitdesign”,Wiley,2000
2.A.P. Chandrasekaran, R.W. Broadersen,“Low power digital CMOS design”, Kluwer,1995
3.Gary Yeap,“PracticallowpowerdigitalVLSIdesign”,Kluwer,1998

REFERENCE BOOKS:
1. DimitriosSoudris,ChristiansPignet,CostasGoutis,“DesigningCMOSCircuitsforLowPower”,
Kluwer,2002
2. J.B.Kulo, J.HLou,“Low VoltageCMOSVLSICircuits”,Wiley1999.

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