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MESI Protocol

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KARTHIKA THEVAR
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MESI Protocol

Uploaded by

KARTHIKA THEVAR
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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MESI Protocol

07 April 2024 13:08

 The MESI Cache Consistency Model


1. The MESI (modified-Exclusive-Shared-Invalid) protocol provides a method to maintain cache coherency.
2. The MESI protocol is only for the data cache and the SI protocol for the code cache.
3. Each line in the data cache can be in one of the four MESI states as indicated by two bits stored along
with the tag address.
 Modified
 It indicates that this line in cache has been updated or modified due to a write hit in the cache.
 In this case, when the cache subsystem snoops the system bus and finds a snoop hit, it write the
modifies line back to memory (update the memory).
 Exclusive
 It is the intermediate state between Shared and Modified.
 Shared
 It indicates that this line may be resent in several cache and an exact duplicate of the information exists
in each source (caches and main memory).
 Invalid
 It is the initial state after reset and indicates that the line is not present in the cache.
 During reset, the MESI state bits for the processor’s internal L1 caches and the L2 cache are forced to
the invalid (I) state. Hence, all initial accesses to L1 and L2 cache are cache misses.

MESI PROTOCOL
ØÊÊWriteÊPoliciesÊ/ÊCacheÊConsistencyÊ/ÊCacheÊCoherency
1.ÊThough cache memory has massive speed advantage, it comes with an inherent
drawback. Dur to cache, there are two copies of the same data, one in cache memory and
the other in Main Memory.

2.ÊAsÊlongÊasÊbothÊareÊtheÊsameÊtheÊcacheÊisÊsaidÊtoÊbeÊconsistentÊ(coherent).ÊInconsistencyÊarisesÊ
theÊmomentÊaÊprocessorÊperformsÊaÊwriteÊoperation.

3.ÊThe write will be performed on the cache, as that’s the whole idea of having cache
memory in the first place. This means the same data in the main memory now has an old
(stale/invalid) value. If another bus master (co-processor) accesses the same data from the
Main Memory, it will get stale value. Hence the cache becomes inconsistent. This can be
avoided by having good write policies. There are several policies suggested.

ØÊWriteÊThrough
1.ÊWhen a processor writes into Cache Memory, it must also write in Main Memory.
2.ÊThisÊcompletelyÊsolvesÊtheÊproblemÊofÊinconsistencyÊbutÊmakesÊwritesÊslowÊasÊwritingÊintoÊ
MainÊMemoryÊisÊmuchÊslowerÊasÊcomparedÊtoÊreads.ÊItsÊnotÊallÊthatÊbadÊbecauseÊonÊanÊaverageÊ
majorityÊoperationsÊareÊreadsÊcomparedÊtoÊwrites.

ØÊWriteÊBackÊ(DelayedÊWriteÊ/ÊPostedÊWriteÊ/ÊBufferedÊWrite)

1. Processor will only write into Cache Memory. A Cache Controller (Eg: Intel’s 80385)
keeps a track of all blocks that have been modified in the Cache Memory.
2.ÊWhenÊtheÊprocessorÊisÊidleÊorÊatÊtheÊtimeÊwhenÊthisÊblockÊhasÊtoÊbeÊreplaced,ÊitÊwillÊcopyÊallÊ
modifiedÊinformationÊfromÊCacheÊMemoryÊtoÊMainÊMemory.ÊThisÊmakesÊprocessor’sÊwritesÊveryÊ
fastÊbutÊkeepsÊtheÊMainÊMemoryÊinconsistentÊforÊsometime.

ØÊÊSNOOPINGÊ

1. Processor will only write into Cache Memory. A Cache Controller (Eg: Intel’s 80835)
keeps a track of all blocks that have been modified in the Cache Memory. Additionally the
Cache Controller will “Snoop” activities of other bus masters.

2.ÊIfÊitÊnoticesÊthatÊanotherÊbusÊmasterÊisÊtryingÊtoÊaccessÊaÊlocationÊfromÊMainÊMemoryÊwhichÊ
hasÊbeenÊmodifiedÊinÊtheÊCacheÊMemory,ÊtheÊCacheÊControllerÊwillÊstopÊactivitiesÊofÊallÊbusÊ
masters,ÊcopyÊupdatedÊdataÊfromÊCacheÊMemoryÊtoÊMainÊMemoryÊandÊallowÊtheÊsystemÊtoÊ
resume.ÊThisÊgivesÊtotalÊconsistencyÊandÊalsoÊpreventsÊunnecessaryÊupdatesÊtoÊmainÊmemoryÊ
henceÊgivesÊtheÊbestÊperformance.

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