IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

11, NOVEMBER 2011 3285

On Zero Steady-State Error Voltage Control

of Single-Phase PWM Inverters With
Different Load Types
Dong Dong, Student Member, IEEE, Timothy Thacker, Member, IEEE, Rolando Burgos, Member, IEEE,
Fei Wang, Fellow, IEEE, and Dushan Boroyevich, Fellow, IEEE

Abstract—This paper comprehensively investigates and com-

pares different multiloop linear control schemes for single-phase
pulsewidth modulation inverters, both in stationary and syn-
chronous (d–q) frames, by focusing on their steady-state error
under different loading conditions. Specifically, it is shown how
proportional plus resonant (P + R) control and load current feed-
back (LCF) control can, respectively, improve the steady-state and
transient performance of the inverter, leading to the proposal of
a PID + R + LCF control scheme. Furthermore, the LCF con-
trol and capacitive current feedback control schemes are shown to Fig. 1. Single-phase full-bridge PWM inverter.
be subject to stability issues under second and higher order filter
loads. Additionally, the equivalence between the stationary frame
and d–q frame controllers is discussed depending on the orthogonal terruptable power supplies [1]–[5], dc–ac interfacing of wind
term generation method, and a d–q frame voltage control strategy
is proposed eliminating the need for the generation of this orthogo- and solar renewable energy sources, stand-alone voltage regu-
nal component. This is achieved while retaining all the advantages lators in distributed power systems [6]–[8], as well as in many
of operating in the synchronous d–q frame, i.e., zero steady-state other applications. The major requirement of its control system
error and ease of implementation. All theoretical findings are val- is to achieve ac voltage regulation with fast dynamic response
idated experimentally using a 1.5 kW laboratory prototype. and a taut frequency regulation during transients, all this while
Index Terms—PWM inverter, single phase, stationary frame, maintaining almost zero steady-state error under different types
synchronous frame. of loads [9].
Numerous control schemes have been proposed during the
NOMENCLATURE past decades for this converter, such as deadbeat, repetitive,
PID: Multi-pole-multi-zero compensator. sliding mode, and other controls [2], [10]–[18], as well as many
P + R: Proportional gain plus resonant controller. other nonlinear schemes, such as adaptive and neural networks
PI: Proportional gain plus integrator controller. control [3]–[5], [19]–[23]. It is understandable, however, that
LCF: Load current feedback. many of these control strategies present some sort of short-
CCF Capacitive current feedback. coming, for instance difficulty in modeling, complex design
OGM Orthogonal (imaginary) term generation method. and hardware implementation, sensitivity to system parameters
and loading conditions, slow dynamics, or simply steady-state
I. INTRODUCTION errors. Furthermore, most advanced controls are usually con-
HE full-bridge pulsewidth modulation (PWM) single- cerned only with specific types of loads reducing the scope of
T phase inverter shown in Fig. 1 is widely used in unin- the benefits found.
Regarding the controller structure, the use of a single-voltage
regulator is sufficient for the control of the converter ac volt-
age; however, this is not enough when dealing with more de-
Manuscript received October 18, 2010; revised February 23, 2011; accepted manding applications with higher performance requirements,
May 2, 2011. Date of current version November 18, 2011. Recommended for
publication by Associate Editor P. C. Loh. where normally at least a current loop is required as well.
D. Dong and D. Boroyevich are with the Center for Power Electronics For the latter case, a multiloop current-voltage PID control
Systems, Virginia Tech, Blacksburg, VA 24061 USA (e-mail: [email protected]; scheme can represent a simple solution when designed using
[email protected]).
T. Thacker is with the PowerHub System, Blacksburg, VA 24061 USA frequency-response techniques, providing several advantages in
(e-mail: [email protected]). terms of design and ease of implementation, ultimately achiev-
R. Burgos is with ABB U.S. Corporate Research Center, Raleigh, NC 27606 ing good regulation and a well-defined region of predictable
USA (e-mail: [email protected]).
F. Wang is with The University of Tennessee, Knoxville, TN 37996 USA, stability for the converter operation. The downside of such a
and also with the Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA control approach is that it is subject to steady-state errors due
(e-mail: [email protected]). to its finite loop gain at 60 Hz, and also that it has a vari-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. able dynamic response depending on the loading conditions. To
Digital Object Identifier 10.1109/TPEL.2011.2157361 address these shortfalls, several methods have been proposed
0885-8993/$26.00 © 2011 IEEE
3286 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 2. Small-signal model of a single-phase PWM inverter. Fig. 3. Diagram of an inverter control signal loop.

including the use of LCF [24]–[29], CCF [29]–[33], propor-

tional plus resonant (P + R) controls [28], [29], [34], [36], [37], The small-signal transfer functions from control signal to in-
and single-phase d–q frame controls with orthogonal stationary ductor current GiL , and from control signal to capacitor current
β-axis terms [40]–[46], where only the last two are capable of GiC , can be easily derived from Fig. 2 as shown in (1) and (2),
effectively eliminating the lackluster steady-state error. respectively. Notice that the small-signal transfer functions are
Addressing the previous discussion, this paper presents a de- only valid from dc up to half of the switching frequency due to
tailed small-signal control system model for the converter in the Nyquist sampling effect
question demonstrating that: 1) a mixed PID current loop with
ĩac 1 + sZac Cac
a PID + R + LCF voltage-loop scheme represents the best al- GiL (s) = = Vdc 2 (1)
ternative to achieve zero steady-state error under different load d˜ab s Lac Cac Zac + sLac + Zac
conditions; 2) the LCF/CCF controller is inherently unstable un- ĩc sZac Cac
der certain types of filter loads; 3) LCF should be truly regarded GiL (s) = = Vdc 2 . (2)
˜
dab s Lac ac Zac + sLac + Zac
C
as feedback compensation and not feedforward as claimed so
far; and 4) from the different OGMs, the differentiation method The inductor-current to output-voltage transfer function Gv iL
is the only one that holds the equivalency between the PR volt- shown in (3) on the other hand is derived assuming that the
age regulator and the single-phase d–q frame controller. Fi- inner current loop is effectively closed, and that the inverter
nally, an unbalanced d–q frame controller is proposed where behaves like an ideal current source feeding the Zac −Cac load
the orthogonal terms are simply defined to be zero, eliminating ṽac Zac
all the hassles from this control method while fully retaining Gv iL (s) = = . (3)
ĩac sZac Cac + 1
the benefits of operating in the synchronous d–q frame (zero
steady-state error and simple digital implementation). All the- This transfer function shows how the voltage regulation perfor-
oretical findings are validated experimentally using a 1.5 kW mance of the inverter is highly dependent on the load, which is
120 V rms, and 340 V dc laboratory prototype operating at evinced by the pole dependence on the load impedance Zac . As
20 kHz and controlled by a DSP-field-programmable gate array such, under heavy-load conditions, the load–capacitance prod-
digital control platform. uct in the denominator approaches zero; hence, (3) can be ap-
proximated as in (4)
II. SMALL-SIGNAL MODEL AND CONTROL SYSTEM ṽac
Gv iL (s) = = Zac (4)
Although the PWM inverter does not have a constant oper- ĩac
ating point at its output, and therefore has a varying duty cycle which means that whenever the inverter is subject to heavy
control signal, the inverter has the same frequency response re- loads, the voltage loop gain at 60 Hz is simply given by the
gardless of the operating point due to the linearity of the topology load impedance as shown in the Bode plots of Fig. 4. This
itself when the dc-link voltage is constant. In such case, the full- behavior also results in the varying steady-state error of the
bridge inverter can be modeled as a controlled ac voltage source voltage control loop.
as shown in Fig. 2. Since the controller design based on small- To accommodate for this varying loop gain at 60 Hz, PID
signal transfer functions is a popular engineering approach, the controllers are normally designed under light-load condition
inverter small-signal model and the corresponding control loops in order to ensure the fulfillment of stability requirements [6].
are presented in Fig. 3. The block Modulator in Fig. 2 represents This is necessary due to a lower phase margin observed in this
the PWM modulator gain, which is unity gain in this paper. The case as depicted in Fig. 4 (case 100 W, 144 Ω). This design
block Delay represents the sampling and computational delay guideline, although conservative and effective, translates into a
introduced by the DSP. The block LPF represents the low-pass larger steady-state error under heavy load due to a lower loop
filter in the voltage and current sensor loops. The parameters of gain observed at 60 Hz.
the inverter are given in Table I, and are used throughout the This load impedance effect also explains the steady-state error
analysis in the following sections. when feeding nonlinear loads. Specifically, a load is considered
DONG et al.: ON ZERO STEADY-STATE ERROR VOLTAGE CONTROL OF SINGLE-PHASE PWM INVERTERS WITH DIFFERENT LOAD TYPES 3287

TABLE I
PARAMETERS FOR INVERTER MODEL

Fig. 5. Normal PID control under no load condition: v a c [100 V/div], il

[20 A/div], and Ve rr [10 V/div].

Fig. 4. Inductor-current to output-voltage transfer function under different

loading conditions.

nonlinear if its impedance changes with the applied voltage. The

nonlinear load effect at 60 Hz can be regarded as a continuous
large-signal transient response manifested by load steps, such
as a rectifier load. This type of load can be simply visualized as Fig. 6. Normal PID control under 1 kW resistive load condition:
v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].
load steps between no load and full load as the rectifier diodes
conduct or are blocked by the dc capacitor. To deal with this
behavior naturally requires a high loop gain and high control
bandwidth. Fig. 5 shows the steady-state waveforms of an inverter de-
Another main load issue is the filter load or harmonic load, signed to achieve stability under light-load condition using a
which may introduce small-signal oscillations or specific har- PID controller under no load. Figs. 6 and 7 show the results
monics due to self-resonances. A high control loop gain is there- under 1 kW resistive load and nonlinear load conditions, re-
fore required to damp the resonant points if they are within the spectively. The crest factor of the nonlinear load is around 1.9.
control bandwidth. Also, the control loop gain should be small These waveforms show the load current il , and the output volt-
to damp the resonance if the resonant point is located beyond the age v ac regulated to be 120 V rms. The resultant voltage errors
control bandwidth. Alternatively, active damping control tech- Verr from D/A converter are also shown in figures on the upper
niques can be used as well, which however tend to reduce the side. As seen, this design approach yields a large steady-state
overall bandwidth of the converter. error under different loading conditions as mentioned earlier.
3288 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 10. P + R control.

Fig. 7. Normal PID control under nonlinear load condition: v a c [100 V/div],
il [20 A/div], Ve rr [10 V/div].

Fig. 8. Proportional gain plus load current feedback (P + LCF) voltage Fig. 11. P + R + LCF control.
control.

is, therefore, not capable of compensating the dynamic response

of the converter; thus, the steady-state error still remains.
In order to achieve a high loop gain at 60 Hz, a resonant (R)
regulator of the form in (6) is normally used, such as in [34],
[36]. Fig. 10 shows a block diagram of the scheme in question,
which effectively eliminates the steady-state error. The design
and implementation of such resonant controller can be found
Fig. 9. Block diagram of P + LCF voltage control.
in [29]
2s
III. STATIONARY FRAME CONTROL R(s) = k . (6)
s2 + ωo2
A. Analysis on LCF and P + R Control
Fig. 8 shows a block diagram of the proportional gain plus B. Proposed PID + R + LCF Control
load current feedback (P + LCF) voltage control scheme. In
order to handle large load variations, its main feature is the P + R control still suffers from the load-dependent transient
current feedback loop used to cancel out the load dynamics for response. This drawback can be counteracted by adding an LCF
the first-order plant model mentioned in [25]–[27]. However, as proposed in Fig. 11. In this way, the resonant controller
this approach is limited to the extent of the cancellation efficacy achieves an infinite gain at 60 Hz eliminating the voltage error,
as illustrated in Fig. 9. This is due to the effects and phase as well as the same dynamic performance regardless of the load
delays introduced by the sensors, digital sampling process, and type.
the nonideal nature of the current loop. The complete control- This new control structure can be further improved by re-
to-output voltage small-signal transfer function including the placing the proportional gain P in the voltage loop by a PID
aforementioned effect is shown in (5). In effect, (5) can be regulator Hv , which provides this loop with an additional phase
reduced to a first-order plant model only in the presence of an margin and a higher bandwidth. Such a control scheme is shown
ideal sensor (Hfilter (s) = 1) and current loop (Hi closed (s) = 1) in Fig. 12. Compensators Hi (current loop compensator) and Hv
are shown in (7) and (8), respectively; their design procedure
ṽc Hi closed (s) can be readily found in [6]. The zeros in (7) and (8) are used to
Gv c1 (s) = = 1 .
ṽac sCac + Za c [1 − Hfilter (s)Hi closed (s)] compensate the phase drop and to obtain the desired phase mar-
(5) gin around the open-loop crossover frequency, which reduces
In this case by using an additional LCF loop, a proportional the voltage spikes and oscillations during transient responses as
gain suffices to achieve a desired control bandwidth. However, a well as maintaining a good enough stability margin. The poles
proportional gain cannot achieve enough loop gain at 60 Hz, and in (7) and (8) on the other hand are placed beyond the crossover
DONG et al.: ON ZERO STEADY-STATE ERROR VOLTAGE CONTROL OF SINGLE-PHASE PWM INVERTERS WITH DIFFERENT LOAD TYPES 3289

Fig. 12. PID + R + LCF control.

Fig. 14. Loop gain of voltage control system using P + R and PID + R.

Fig. 13. Loop gain of voltage control system using PID + R with and without
LCF. Fig. 15. PID + R control under 1 kVar capacitive load condition:
v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].

frequency to attenuate the loop gain beyond the bandwidth,

thereby damping any possible high-frequency resonance due to
external loads
(s + ωz i1 ) (s + ωz i2 )
Hi (s) = kip (7)
s (s + ωpi1 ) (s + ωpi2 )
(s + ωz v 1 )
Hv (s) = kv p . (8)
s (s + ωpv 1 )
This control scheme can be extended to use more banks of res-
onant controllers to achieve high loop gain at different frequen-
cies [22]; in this way, it can damp several harmonics introduced
by nonlinear loads.
The resultant voltage loop gain, with and without LCF under Fig. 16. PID + R control under nonlinear load condition: v a c [100 V/div], il
[20 A/div], and Ve rr [10 V/div].
heavy load, can be analyzed by examining the frequency re-
sponse of the voltage loop gain in (9) and (10), respectively. The
corresponding closed current-loop transfer function is shown in loop gain of this controller translates into a quicker response to
(11) this step-like load transitions providing good regulation.
The voltage loop-gain difference between PID + R and P + R
Gv c2 (s) = [Hv (s) + R(s)] Gv c1 (s)Hfilter (s) (9)
under light-load condition can be examined similarly by using
G′v c2 (s) = [Hv (s) + R(s)] Gv iL (s)Hfilter (s) (10) (10) and (11). As shown in Fig. 14, the PID + R controller
achieves a 1.1 kHz control loop bandwidth with a 55◦ phase
GiL (s)Hdelay (s)Hi (s)
Hi closed (s) = . (11) margin, while the P + R controller achieves only an 800 Hz
1 + GiL (s)Hfilter (s)Hdelay (s)Hi (s) bandwidth with a 53◦ phase margin. Also, the overall loop gain
Fig. 13 shows how the addition of the LCF loop effectively of the P + R case within the control bandwidth is lower than
increases the voltage gain at low frequency without sacrificing that of the PID + R controller.
the infinite gain characteristic at 60 Hz. This is a most desirable Figs. 15 and 16 and Figs. 17 and 18 show, respectively, the
trait when feeding nonlinear loads. In this case, the overall higher experimental waveforms depicting the inverter operating with
3290 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 17. PID + R + LCF control under 1 kVar capacitive load condition:
v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].

Fig. 20. Transient response of a load step from no load to 1.5 kW resistor
load.

Fig. 21. Single-phase EMI filter and DM equivalent second-order load.

the desired phase margin and high bandwidth that the carefully
Fig. 18. PID + R + LCF control under nonlinear load condition: designed PID can. As seen in Fig. 20, the PID controller presents
v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div]. a relatively better dynamic response than the P + R; however, it
suffers from a larger steady-state error under the 1.5 kW loading
condition, evinced by the slight delay observed in this figure.

C. Stability of PID + R + LCF, PID + R + CCF,

and PID + R Controls
Another type of load considered is the second or higher order
passive load. This type of load is widely present in distributed
power systems given the elevated number of harmonic and elec-
tromagnetic interference (EMI) filters used as filtering devices in
switch-mode power converters [38], [39]. Fig. 21 shows specif-
ically the input EMI filter of a PFC converter as well as its
differential-mode (DM) equivalent circuit. Such load can easily
generate instabilities due to its interaction with the feeding con-
verter. As stated earlier, this resonance can be damped by a PID
Fig. 19. Transient response of a load step from no load to 1.5 kW resistor
load.
plus a resonant controller if it is located within the control band-
width. Also, if the resonant frequency is much higher than the
control bandwidth, the additional pole in the PID controller will
PID + R and PID + R + LCF control schemes feeding a 1 kVA help attenuate it. Critical frequencies are consequently those im-
capacitive nonlinear load. As observed, both cases present small mediately after the control crossover frequency, given the nega-
steady-state errors compared with the PID controller. Addition- tive phase margin and low damping effect that the control-loop
ally, it can be observed how the LCF helps to further reduce the displays in that range. In this case, any harmonic component
voltage error due to the low-frequency loop-gain improvement, could still be amplified leading to oscillations.
especially under heavy-load condition. Fig. 22 shows the oscillatory behavior obtained when the
Figs. 19 and 20 show the transient response to a load step from single-phase inverter in question feeds a second-order type of
no load to a 1.5 kW resistive load under the aforementioned load using a PID + R + LCF controller. This instability is due
controllers. The load step is executed by a DSP-controlled ac to the lack of damping in the system and a direct consequence of
switch. These oscillograms clearly show how the PID + R + the load current feedback used in this case. In effect, if this LCF
LCF controller presents the highest bandwidth and loop gain. loop is removed, the control scheme regresses to the regulation
The P + R + LCF controller accordingly has a higher voltage of the inductor current and a stable behavior for this type of load
spike and longer regulation time, as it simply cannot achieve is achieved as illustrated in Fig. 23.
DONG et al.: ON ZERO STEADY-STATE ERROR VOLTAGE CONTROL OF SINGLE-PHASE PWM INVERTERS WITH DIFFERENT LOAD TYPES 3291

Fig. 24. PID + R + CCF control.

Fig. 22. Instability with load current feedback under LC filter load.

Fig. 25. Inductor and capacitor current loop.

Fig. 23. Stable operation without load current feedback under LC filter load. CCF loop), reveals an undamped resonance at 11.2 kHz caused
by the second-order load. On the other hand, this resonance is
As seen in (5), the LCF may not perfectly decouple the load effectively damped in the inductor current control case as shown
effect, especially in the high-frequency range, due to digital de- by the black trace in this figure. The difference between these
lays and other nonideal system components. In such case, the two current loops can be further investigated by examining their
load resonance is fed back by the LCF and is still observable respective transfer functions, shown earlier as GiL and GiC in
from the voltage control loop creating a coupling between both (1) and (2). Specifically, GiL and GiC exhibit the same set of
current and voltage loops. This coupling veils the study of sta- double poles but a different set of zeros. The latter can be found
bility and interactions between these loops; therefore, the direct by replacing the following load impedance term Zac , as shown
analysis of the control-to-current transfer functions is preferred in (14), into (1) and (2)
in what follows. Specifically, so far an inductor current or in- 1
ductor current plus LCF have been considered. The latter can Zac = sL1 + (14)
sC1
also be thought of as an CCF loop, where the inner control loop
of the inverter regulates this current directly in order to regulate where L1 and C1 correspond to the load parameters and not to
the output (capacitor) voltage. This equivalent representation is the inverter inductor and capacitor (Lac −Cac ). The double zeros
shown in Fig. 24 [28], [31]. of the inductor current loop GiL and capacitor current loop GiC
The respective current loop gains are given by (12) and (13), are, respectively, given by
and their respective Bode plots in Fig. 25. The resonant peak is 
Cac + C1
due to the resonance of the LC filter (Lac , Cac ) ωz L 1,2 = (15)
Cac C1 L1
HO L 1 (s) = Hi (s) · GiL (s) · Hdelay (s) · Hfilter (s) (12) 
1
ωz C 1,2 = . (16)
HO L 2 (s) = Hi (s) · GiC (s) · Hdelay (s) · Hfilter (s). (13) C1 L1
The load used in this case is of an L–C filter type with L1 = The same load term can be used to determine the two double
10 µH and C1 = 20 µF (ESR = 10 mΩ). The gray trace in this poles of both transfer functions, which are given as (17) and
figure, corresponding to the inductor current plus LCF case (or (18) at the bottom of the next page.
3292 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 26. PID + R + LCF control under LC filter load: v a c [100 V/div] and Fig. 27. PID + R control under LC filter load: v a c [100 V/div] and
ia c [10 A/div]. ia c [10 A/div].

If the EMI DM inductor L1 is much smaller than Lac , which For higher order loads however, feeding back the load current
is normally the case (the corner frequency of the EMI filter may introduce high-frequency resonances into control loops,
is higher than that of the output filter), (17) and (18) can be making the simpler PID + R inductor current loop a better safer
approximated, respectively, by, (19) and (20) as shown at the choice. This is also the reason why this paper refers to the LCF
bottom of this page, which yields the following pole frequencies loop as a feedback loop rather than a feedforward term, as most
in previous work has mentioned [25]–[27], [29].

1 IV. SYNCHRONOUS FRAME CONTROL
ωp1,2 = (21)
Cac Lac
 A. OGMs for Synchronous Frame Control
Cac + C1
ωp3,4 = . (22) The digital implementation of the control system has a strong
Cac C1 L1 impact on the resonant R control performance, since the loss-
This shows that one double pole (21) is around the line filter less infinite Q filter cannot be physically realized [40]. Also, the
resonance, and the other (22) is caused by the filter load. More resonant controller characteristics are degraded by the quanti-
importantly, it shows that the double zeros ω z L 1,2 and the dou- zation error due to the limited long word length in fixed-point
ble pole ω p 3,4 cancel out in the inductor current loop, providing DSPs [40].
enough damping at this frequency that only a very small damp- Recently, a digital-based synchronous d–q frame controller
ing resistor is needed. Figs. 26 and 27 show the experimental has been proposed for single-phase converters using orthogonal
results depicting this oscillation issue introduced by the LCF components by different OGMs [40]–[45]. With this approach,
(or CCF) feedback loop. The resonant frequency in this case is just as in the three-phase counterpart, all state and control vari-
10 kHz. In consequence, the PID + R with LCF (or CCF) regu- ables become dc quantities with which zero steady-state error
lator presents a better fit for first-order linear or nonlinear loads. can be achieved by means of simple PID regulators. As such,

 

 (C + kC + C ) + C 2 + [(1 + k) C ]2 + 2 (1 − k) C C
 ac 1 1 ac 1 ac 1 L1
ωp1,2 = , k= (17)
2Cac C1 L1 Lac
 

 (C + kC + C ) − C 2 + [(1 + k) C ]2 + 2 (1 − k) C C
 ac 1 1 ac 1 ac 1 L1
ωp3,4 = , k= . (18)
2Cac C1 L1 Lac

 

 (C + kC + C ) + C 2 + [(1 − k) C ]2 + 2 (1 − k) C C
 ac 1 1 ac 1 ac 1 L1
ωp1,2 = , k= (19)
2Cac C1 L1 Lac
 

 (C + kC + C ) − C 2 + [(1 − k) C ]2 + 2 (1 − k) C C
 ac 1 1 ac 1 ac 1 L1
ωp3,4 = , k= (20)
2Cac C1 L1 Lac
DONG et al.: ON ZERO STEADY-STATE ERROR VOLTAGE CONTROL OF SINGLE-PHASE PWM INVERTERS WITH DIFFERENT LOAD TYPES 3293

TABLE II
OGMS

Fig. 28. D–q frame controller for current and voltage loops.

The effect of generating the β-axis component can be ob-

served by looking at the equivalent stationary frame controller.
The early work on the equivalency between the P + R in station-
ary frame and the PI in d–q frame has already been discussed
in [35] and then was applied in three-phase current-mode con-
trol systems [37], and also extended to single-phase systems by
assuming that v β and v α are independent variables [36], [37];
however, there is no general conclusion on the relationship be-
Fig. 29. D–q frame controller for a voltage loop. tween stationary and synchronous frame controls due to the
different dynamics introduced by the different OGMs. The re-
lationship between the synchronous frame controller Hdq and
a complete d–q frame controller [41] where both current and
the stationary frame controller Hα β by considering the OGM
voltage loops are transformed into the d–q frame can be im-
dynamics is as follows:
plemented as shown in Fig. 28. It might suffice however to
control only the voltage loop in the d–q frame and leaving a ĩα ref

Hdq (s + jωo )
stationary frame scalar control for the current loop in what is a = Hα β (s) = [1 − j · OGM(s)]
ṽα 2
mixed frame controller [6], [41]. This simplifies the final control 
system implementation as shown in Fig. 29. Hdq (s − jωo )
+ [1 + j · OGM(s)] . (23)
The advantage of single-phase d–q frame controls is straight- 2
forward; almost an infinite gain at dc in the PID compensator
that is not degraded in its digital implementation. The main Substituting the OGM(s) of differentiation method in Table II
drawback of this approach is the need to generate the orthogonal and the PI type d–q frame controller (24) into (23) yields
β-axis set of variables, inexistent in the single-phase case. Some 1
papers propose many OGMs to generate the β-axis component. Hdq (s) = kp + ki (24)
s
The earliest proposed method is to delay the α-axis components
2ki s
by one quarter cycle [40]. This method is easy to achieve, but Hα β (s) = kp + 2 . (25)
the transient response is naturally slow. Another approach is to s + ωo2
differentiate the α-axis component [41]. This gives the ideal in- So, mathematically, the single-phase d–q frame PI controller
stantaneous β-axis component, but it is hard to achieve because can be used instead of the stationary frame P + R controller in
of measurement noise. The second-order generalized integra- the voltage and current loops when applying the differentiation
tor method only generates and deals with the line-frequency method. This conclusion however cannot be extended to other
components [45], but attenuates higher order terms, thus filter- OGMs.
ing out any noise and harmonic signals from reaching the DQ
voltages/currents that a control system should observe and reg-
ulate. Kim et al. [45] proposed an all-pass-filter method, but the B. Unbalanced αβ/dq Transformation
performance is degraded with line-frequency harmonics. An- To tackle the OGM limitations, a so-called unbalanced
other paper proposed an estimator [42], such as a Kalman filter, d–q transformation is proposed and shown in Fig. 30. The
achieving good performance; however, this method is complex α-axis component Xα is decomposed as two mirror-symmetrical
to implement especially in what regards the actual tuning of the vectors (X and X′ ) with the opposite rotating directions. The pro-
estimator gain. jected β-axis component remains zero all the time.
Besides generating the β-axis component for the d–q trans- As such, each d- or q-channel is comprised of two projected
formation, these different methods introduce different additional components (X and X′ ), which can be written as shown later
small-signal dynamics into the control loops, some of which are by simply forcing the imaginary β-axis component to be zero
summarized in Table II. when transforming both reference and sensor ac voltage signals.
3294 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 33. Unbalanced single-phase d–q + LCF control under no load condition:
v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].

Fig. 30. Unbalanced d–q transformation.

Fig. 34. Unbalanced single-phase d–q + LCF control under 1 kW resistive

load condition: v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].
Fig. 31. Unbalanced d–q control.

Fig. 35. Unbalanced single-phase d–q + LCF control under 1 kVar capacitive
Fig. 32. Unbalanced d–q + LCF control. load condition: v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].

In (26) and (27), T represents the αβ/dq transformation

VD ref V cos (ωt + ϕ) cos(ϕ)

=T· = 0.5V
VQ ref 0 sin(ϕ)
cos (2ωt + ϕ)
+ 0.5V (26)
− sin (2ωt + ϕ)

VD ref V1 cos (ω1 t + ϕ1 )

=T ·
VQ ref 0
Fig. 36. Unbalanced single-phase d–q + LCF control under nonlinear load
cos (ω1 t − ωt + ϕ1 ) condition: v a c [100 V/div], il [20 A/div], and Ve rr [10 V/div].
= 0.5V1
sin (ω1 t − ωt + ϕ1 )
cos (ω1 t + ωt + ϕ1 ) between (26) and (27) yields
+ 0.5V1 . (27)
− sin (ω1 t + ωt + ϕ1 )
VD error 1 V cos(ϕ) − V1 cos(ω1 t − ωt + ϕ1 )
=
VQ error 2 V sin(ϕ) − V1 sin(ω1 t − ωt + ϕ1 )
where V, ω, and Φ are reference values, while V1 , ω 1 , and Φ1
are the actual variables. As seen, both expressions show the 1 V cos(2ωt + ϕ) − V1 cos(ω1 t + ωt + ϕ1 )
+ . (28)
presence of a dc term X and a 2ω term X′ . Then, taking the error 2 V1 sin(ω1 t + ωt + ϕ1 ) − V sin(2ωt + ϕ)
DONG et al.: ON ZERO STEADY-STATE ERROR VOLTAGE CONTROL OF SINGLE-PHASE PWM INVERTERS WITH DIFFERENT LOAD TYPES 3295

TABLE III
STEADY-STATE ERROR COMPARISON

Furthermore, it can be easily shown that the PI or PID regulator have the similar control performance as P + R and P + R +
in the d–q frame Hdq forces the dc error (first term in (28)) to LCF under filter/harmonic load.
zero, shown as follows Table III summarizes the peak-to-peak voltage errors under
different control schemes. As seen, high loads present overall
V1 cos (ω1 t − ωt + ϕ1 ) − V cos ϕ 0
= . (29) bigger errors than light loads. Also, the proposed PID + R +
V1 sin (ω1 t − ωt + ϕ1 ) − V sin ϕ 0
LCF and unbalanced d–q + LCF have better performances.
Solving (29) leads to ω 1 = ω, Φ1 = Φ, and V1 = V. Con- Due to the higher computational cost of the synchronous frame
sequently, the double-frequency components in (28) are also controller, the choice of controllers between stationary frame
cancelled by the action of this regulator. This shows that zero and synchronous frame depends on the specific system require-
steady-state error can be effectively achieved while forcing the ments, DSP performance, and the designer’s own preference.
orthogonal β-axis terms to be zero. The tradeoff is, however, It should be also noted that different methods can have a great
that the 2ω frequency error will appear during transient condi- impact on the steady-state voltage magnitude error, whereas not
tions, which is different from the standard d–q frame control, as much an effect on the total harmonic distortion if the corre-
where the 2ω component is cancelled under both steady-state sponding PID regulators are carefully designed achieving high
and transient conditions. bandwidth.
Now, by simply defining v β = 0, a simple PI compensator in
(24) can be used in (23), which yields V. CONCLUSION
s This paper has investigated the multiloop control system of
Hα β (s) = kp + ki 2 . (30)
s + ωo2 single-phase full-bridge PWM inverters. Several prevalent con-
trol schemes have been compared in terms of steady-state per-
As seen in (30), the unbalanced d–q frame controller forcing
formance and load immunity capability. It was shown that P +
v β = 0 is equivalent to a P + R regulator in the stationary
R control reduces the steady-state error, while LCF control and
frame, eliminating the drawbacks of the conventional d–q frame
its equivalent, CCF control, can improve the transient perfor-
approach by using other OGMs. It should be noted that the gain
mance under different loads. Nonetheless, both LCF and CCF
of the resonant term in (30) is half of that of the differenti-
were shown to introduce oscillations when feeding higher order
ation OGM method shown in (25). Equation (30) also shows
loads (like harmonic or EMI filters). Synchronous frame con-
an equivalence to the demodulating integral block in [46]. It
trols with different OGMs were also discussed, and an unbal-
means that the demodulating integral block is essentially forc-
anced d–q frame method was proposed by defining and forcing
ing OGM (s) = 0. Finally, the d–q frame control structure for
the β-axis or orthogonal component to be zero (v β = 0), thus
single-phase PWM inverters is shown in Figs. 31 and 32, where
achieving zero steady-state error while reducing the effort on
Fig. 31 shows the cascaded current voltage loop implementation
generating the orthogonal component. Experimental results un-
and Fig. 32 the same scheme with the addition of a load cur-
der four loading conditions with a 1.5 kW laboratory prototype
rent feedback loop used to improve the dynamic response under
were presented for verification.
different loading conditions. The modeling and design of the
controllers in the d–q frame can be found in [40]. This unbal-
APPENDIX
anced d–q implementation method can also be applied to other
single-phase applications, such as phase-locked loop, and ac The derivation of (24) is shown as follows. In Fig. 29, the
current P/Q regulation for grid-connected inverter applications. current reference from DQ voltage controller is only the α-axis
Figs. 33–36 show steady-state waveforms of the unbalanced component from dq/αβ transformation
d–q + LCF control under no load, 1 kW resistive load, 1 kVA ca-
ĩα ref (t) = ĩd (t) cos (ωo t) − ĩq (t) sin (ωo t) . (A.1)
pacitive load, and 1 kVA nonlinear load conditions, respectively.
Due to the equivalency, the steady–steady control performance The trigonometric functions can be expressed as Euler’s form
of the unbalanced d–q + LCF is similar if not identical to that
ej ω o t + e−j ω o t ej ω o t − e−j ω o t
presented by the P + R + LCF control scheme. In fact, the cos (ωo t) = , sin (ωo t) = .
unbalanced d–q + LCF controller features excellent regulation 2 2j
(A.2)
under all of the above, but a slightly degraded performance
The current references id and iq are from the PID controllers in
under the nonlinear load case. This is due to the fact that the
the d–q channel
unbalanced PI is equivalent to a P + R controller. As such, the
unbalanced d–q and unbalanced d–q + LCF also, respectively, ĩd (t) = ṽd (t) ∗ Hdq (t), ĩq (t) = ṽd (t) ∗ Hdq (t) (A.3)
3296 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

where v d (t) and v q (t) are the voltage error in the d–q channel. distortion,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 504–510, Feb.
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[37] D. N. Zmood, D. G. Holmes, and G. H. Bode, “Frequency-domain analysis Rolando Burgos (S’96–M’03) received the B.S. de-
of three-phase linear current regulators,” IEEE Trans. Ind. Appl., vol. 37, gree in electronics engineering, the electronics engi-
no. 2, pp. 601–610, Mar. 2001. neering professional degree, and the M.S. and Ph.D.
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vol. 11, no. 1, pp. 170–181, Jan. 1996. 1997, 1999, and 2002, respectively.
[39] J. C. Crebier and J. P. Ferrieux, “PFC full bridge rectifiers EMI modeling In 2002, he joined as a Postdoctoral Fellow at
and analysis-common mode disturbance reduction,” IEEE Trans. Power the Center for Power Electronics Systems, Virginia
Electronics, vol. 19, no. 2, pp. 378–387, Mar. 2004. Polytechnic Institute and State University, Blacks-
[40] R. Zhang, M. Cardinal, P. Szczesny, and M. Dame, “A Grid simulator burg, where he became a Research Scientist in 2003,
with control of single-phase power converters in D-Q rotating frame,” in and a Research Assistant Professor in 2005. In 2009,
Proc. IEEE Power Electron. Spec. Conf., 2002, pp. 1431–1436. he joined, as a Scientist in ABB Corporate Research, Raleigh, NC, where
[41] A. Roshan, R. Burgos, A. C. Baisden, F. Wang, and D. Boroyevich, “A since June 2010 he has been a Principal Scientist. Later that year, he became
D-Q frame controller for a full-bridge single-phase inverter used in small an Adjunct Associate Professor in the Electrical and Computer Engineering
distributed power generation systems,” in Proc. IEEE Appl. Power Elec- Department, North Carolina State University, Raleigh. His research interests
tron. Conf., 2007, pp. 641–647. include multiphase multilevel power conversion, stability of ac and dc power
[42] K. De Brabandere, T. Loix, K. Engelen, B. Bolsens, J. Van den Keybus, electronics systems, hierarchical modeling, control theory and applications, and
J. Driesen, and R. Belmans, “Design and operation of a phase-locked loop the synthesis of power electronics conversion systems.
with Kalman estimator-based filter for single-phase applications,” in Proc. Dr. Burgos is a member of the IEEE Power Electronics Society, where he
IEEE Ind. Electron. Soc. Conf., 2007, pp. 525–530. currently serves as a Secretary of the Committee on simulation, modeling and
[43] T. Thacker, R. Wang, D. Dong, R. Burgos, F. Wang, and D. Boroyevich, control, and as an Associate Editor for the IEEE POWER ELECTRONICS LETTERS
“Phase-locked loops using state variable feedback for single-phase con- and the IEEE TRANSACTIONS ON POWER ELECTRONICS.
verter systems,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2009,
pp. 864–870.
[44] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “A new single-phase PLL
structure based on second order generalized integrator,” in Proc. IEEE
Power Electron. Spec. Conf., 2006, pp. 1–6. Fei Wang (S’85–M’91–SM’99–F’10) received the
[45] R. Y. Kim, S. Y. Choi, and I. Y. Suh, “Instantaneous control of average B.S. degree from Xi’an Jiaotong University, Xi’an,
power for grid tie inverter using single phase D-Q rotating frame with all China, in 1982, and the M.S. and Ph.D. degrees from
pass filter,” in Proc. IEEE Annu. Conf. Ind. Electron., 2004, pp. 274–279. the University of Southern California, Los Ange-
[46] D. N. Zmood and D. G. Holmes, “Stationary frame current regulation of les, in 1985 and 1990, respectively, all in electrical
PWM inverters with zero steady-state error,” IEEE Trans. Power Electron., engineering.
vol. 18, no. 3, pp. 814–822, May 2003. From 1990 to 1992, he was a Research Scientist
[47] D. S. Bayard, “An LTI/LTV decomposition of adaptive feedforward sys- in the Electric Power Lab, University of Southern
tems with sinusoidal regressors,” in Proc. Amer. Control Conf., pp. 2542– California. In 1992, he was an Application Engineer
2546. at the GE Power Systems’ Engineering Department,
Schenectady, NY. From 1994 to 2000, he was a Se-
nior Product Development Engineer with GE Industrial Systems, Salem, VA.
From 2000 to 2001, he was the Manager of Electronic and Photonic Systems
Technology Lab, GE Global Research Center, Schenectady, NY and was respon-
sible for establishing the Electrical Systems Technology Program in Shanghai,
China. In 2001, he was a Research Associate Professor at the Center for Power
Dong Dong (S’09) received the B.S. degree in elec- Electronics Systems (CPES), Virginia Tech, Blacksburg, where he was an As-
trical engineering from Tsinghua University, Beijing, sociate Professor in 2004. From 2003, he also served as the CPES Technical
China, in 2007. He received the M.S. degree in elec- Director. Since 2009, he has been a Professor and Condra Chair of Excellence in
trical engineering from Virginia Polytechnic Institute Power Electronics with The University of Tennessee, Knoxville, and also with
and State University, Blacksburg, in 2009, where he the Oak Ridge National Laboratory, Oak Ridge, TN.. His research interests in-
is currently working toward the Ph.D. degree from clude power electronics, power systems, controls, electric machines, and motor
the Center for Power Electronics Systems. drives.
His research interests include modeling and real-
time control of single-phase-to-multiphase power
converters, utility-interactive power converter design,
passive filter design, and system integration for the
renewable energy systems and dc power distribution systems applications.
Dushan Boroyevich (S’81–M’86–SM’03–F’06) re-
ceived the Dipl.Ing. degree from the University of
Belgrade, Belgrade, Serbia, in 1976, and the M.S.
degree from the University of Novi Sad, Novi Sad,
Serbia, in 1982. He received the Ph.D. degree from
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, in 1986.
From 1986 to 1990, he was an Assistant Professor
Timothy Thacker (S’00–M’09) received the B.S.
and Director of the Power and Industrial Electronics
degree in electrical engineering from Virginia Poly-
Research Program in the Institute for Power and Elec-
technic Institute and State University (Virginia Tech), tronic Engineering, University of Novi Sad, and later
Blacksburg, in 2003, and the M.S. and Ph.D. de-
he was an Acting Head. He then joined the Bradley Department of Electrical
grees from the Center for Power Electronics Systems,
and Computer Engineering at Virginia Tech as an Associate Professor where he
Virginia Tech, in 2005 and 2009, respectively.
is currently the American Electric Power Professor. He is also the Codirector of
In 2009, he joined PowerHub Systems, Blacks- the Center for Power Electronics Systems, Virginia Tech. His research interests
burg, VA, where he is currently a Senior Engineer of
include multiphase power conversion, electronic power distribution systems,
research and product development. His research in-
power electronics systems modeling and control, and multidisciplinary design
terests include single and multiphase converter mod-
optimization.
eling and control, grid-interfaced converters, dis-
Dr. Boroyevich is the recipient of the IEEE William E. Newell Power Elec-
tributed and renewable energy systems, islanding detection algorithms, and
tronics Technical Field Award. He is currently the President of the IEEE Power
smart grid technologies.
Electronics Society.