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Operational amplifier notes
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25 viewsUnit - 2 - Operational Amplifiers
Operational amplifier notes
Uploaded by
prasannasrinivasan1595Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
/ 25
pn *
OPERATIONAL AMPLIFIER
1. Basic Operational Amplifier
a. Introduction:
The Operational Amplifier: is a direct coupled high: gain
differential input amplifier. Originally the operational amplifier had
only one input and the output voltage was always inverted with respect
to the input voltage. However common operational amplifier which
are recently available are of differential type and these amplifiers have
both inverting and non - inverting inputs.
An ideal operational amplifiers must. have the following
properties.
(i) ‘Input resistance R; must be infinite.
(i) Output resistance R, should: be as small as zero.
(iii) Voltage gain A, should be as high as infinite.
(iv) Band width should be as wide as infinite.
(v) Output voltage Vo = O when V, = V2 and
(vi) The characteristics do not change with temperature. N
Standard triangular symbol for an OP-AMP is shown in fig. 5-
1. It has two input points and .
one output point. One is marked
as plus and the other is marked
as minus. The plus point may be
compared as the emitter point of L
a transistor. So any signal .
applied at this point gets Fig. 5-1
amplified without any phase inversion at output. So it is similar to
common - base amplifier. Hence this input point is called the
non-inverting input point. 90
"A signal applied at the minus point is amplified with a phase
inversion of 180°. So this point may be compared to the base terminal
of a common emitter transistor amplifier. This input point is called
the inverting input point of the OP-AMP
If two input signals V, and V2 are applied the output voltage is
telated to the input by the equation.
Vo= AM -V,)
where A is.the voltage gain
With V, = 0, Vo = -AV, , and with V; = 0, Vo = AV, . The
sign (-) and (+) at the input terminal in the figure intended to serve
as indication of their inversion and non- inversion. If V, = V3 ic if
V, and V, make common voltage then Vj = 0. Thus these plus and
minus polarities indicate phase reversal only. It does not mean that
voltages V, and V, are negative and positive respectively. It also
does not mean that a positive input voltage has to. be. connected to
the plus marked non-inverting point and negative input voltage to the
negative-marked inverting point. All inputs and output voltages are
referred to a common reference usually the ground.
b. Inverting Operational Amplifier
____ The basic inverting amplifier is shown in fig 5-2. The non
inverting terminal has been grounded whereas R, connects the inpitt
signal V, to the inverting input. A feedback resistor Ry has been
connected from the output to the im
Verting input. 91
The input voltage is V, and the output voltage is Vo. The gain
of the operational amplifier is very large. So the voltage V at the
javerting input terminal is very small. In fact , it will be close to the
ground potential. It means that the point G is held virtually at ground
potential irrespective of the magnitude of the potential V; and Vo.
The current i flowing through R, is given by i= (V,- V)/Ry. The
input impedance of OP-AMP is infinite. So the current i will flow
through Ry and not into the OP-AMP. Applying Kirchhoff’s current
law at the point G, we can write,
V-Vo
ee tt eee (1)
Since the point G is at 4 virtual ground, ie V = 0, we get from
equation (1)
Vy/R, = -Vo/Re
SVo/V1 = ~BYR
». Gain Ay = ~Rp/Ry
given by the ratio of the feedback
nce Ry. The negative sign indicates
.d with respect to the input voltage.
Thus the voltage gain is
resistance Ry to the input resista!
that the output voltage is inverte
Let R/R = K&
V/V: = XK
“Vy = -KM ves)
oop gain of the inverting amplifier depends
Hence the closed -I ¢
0 external resistors Ry and R, and it is
on the ratio of the tw:
independent of amplifier parameters.
It is also seen that the OP-AMP works as a negative scaler. It
scales the input i.e it multiplies the input by a minus constant factor
K. It also works as a phase shifter and sign changer. 92
c. Non-inverting operational amplifier
The non - inverting amplifier is shown in fig. 5-3 . In this case,
the input voltage V, is applied to the non-inverting terminal. So this
circuit is called non-inverting amplifier.
Ke
VW
Fig 5-3
The gain of OP-AMP is infinite. So the potential of the point
G is also V2. The output voltage is Vp. The voltage across R, is
V2,and that across Ry is (Vo - V2)
. V2 .
wy = geamdig = al (a)
Applying Kirchhoff’s current law to the junction G, we get, .
Cite Oy (2)
- V, Vo-V2
iene +—— = 0
RR Yo _
Vy R,
a aw 1a et
eh voee(3)
In this case, the gain is 1 plus the ratio of the two resistances
R,and R;. Also the output voltage is in phase with the input voltage.
This circuit offers a high input impedance and a low output
impedance.
IfR, =O and R, =, the gain of the amplifier is unity. ‘Thus
this circuit is referred as voltage follower or a unit gain buffer. This
circuit can be used air an impedance matching device between a
high-impedance source and a low impedance load.
d. Differential operational amplifier
A circuit that amplifies the difference between two signals is
called a differential afaplifier. This type of amplifiers are very useful
‘a instrumentation circuit. A basic differential amplifier employing
operational amplifier is shown in fig. 5-4
Re
Fig. 5-4.
Here V, and V; are the input signal voltages and Vo is the output
voltage. Since the gain of the OP-AMP is infinite the potential of 94
the points 1 and 2 will be the same say V3. Application of Kirchhoff’s
current law at points 1 and 2 gives
Vi-V3 _ V3~Vo
. (1) and
» 2)
Subtraction of (1) from (2) we get
R,
Vo = R (V, - V2)
Vo R
“(Vy= V2)" Ry
or Ag= R/Ry siss(3)
‘Thus its gain of DIFF-AMP is R,/R;. *
Such a circuit is very useful in detecting very small difference
is signals, since the gain R,/R, can be chosen to be very large. For
example if R, = 100 R; , then a small difference (V,-V,) is
amplified 100 times.
e. Common - Mode Rejection Ratio (CMRR)
In an ideal DIFF-AMP, the output signal may.be given by the
equation, ,
Vo= Ay(V,- V2) (1)
‘Where Ay is the gain of the differential amplifier. If V, = V2»
then Vo=0. That is the signals comimon to both inputs gets cancelled
and produces no output voltage. This is true only for an ideal
OP-AMP. But a practical OP-AMP exhibits some small response to
the common mode component of the input Voltage too, For example
if one signal is +25 wV the second is -25uV, the output will not be
exactly the same as if Vg =
900 uV and V, = 850 b
e 2 wv . even thoug!
the difference Vy = 50 AV . is the same in the two cases, The output 95
depends not only upon the difference signal V4 of the two signals,
but also upon the average level called Common - mode signal V,
The common mode signal
Ve = $V, ee (2)
For differential amplifier, the gain at the.output with respect to
the positive terminal is slightly ‘different in magnitude to that of the
negative terminal. So even with the same voltage applied to both
inputs, the output is not zero. The output can be ‘expressed as.a linear
combination of the two input voltages.
SVo= AVA, 3)
where A, is the voltage amplification from input 1 to the output
under the condition that the input 2 is grounded and Ay is the voltage
amplification from input 2 to the output under the condition that the
input 1 is grounded. We know that
Ve = 3(1+¥,)
Va = (V,-V,)
LV, = Vy +V, ;
Vg oe Vpn Vy er sa OS (4)
From equation (4) :
My SVG 4 VgF2 Be (5)
Vz = V,-V4/2 Sererneae ©
Substituting equation (5) and (6) in (3) we get
Vo FAG V gt AGVG 8 oooh, iets LNs (2?
Whee Ay = 3(A-A) (8) and
A = AtA, 9)
The voltage gain for the difference signal is Ay and that for the
common - mode signal is Ay 96
The relative sensitivity of an OP-AMP to a difference signal as
compared to a common - mode signal is called Common - Mode
rejection ratio (CMRR). It gives the figure of merit p for the
differential amplifier.
Ag :
“. CMRR = s |} wee (10
p= la (10)
It is usually expressed in decibels (dB)
Problems
B An inverting amplifier has R, = 20 kilo-ohm and R,; = 100 kilo-
ohm. Find the output voltage, the input resistance and the input
current for an input voltage 1V.
Sol:
Ry
Output Voltage Vp = —-xV,
R
100
= - 59 * 1 =-5V
Input resistance R;, = Ry, = 20 kilo-ohm.
Input current = V,/R, = 1/20x 10%
0.005 mA.
v3) In an inverting OP-AMP, the resistance R, is 10 kilo - ohm and Me Te
2. Basic uses of Operational Amplifiers.
a. OP-AMP as sign and scale changer and Phase
Shifter
@ Sign Changer : In an inverting OP-AMP, we know that,
Rr Zz
Ay = “Rk =e,
If Z = Z’, then Ay = -1 and the sign of the input signal has been
changed. Hence such a circuits acts as a phase inverter. If two such
amplifiers are connected in cascade, the output from the second stage
equals the signal input without change of sign. Hence the output from
the two stages are equal in magnitude but opposite in phase such a
system is an excellent paraphase amplifier.
(ii) Scale changer: If the ratio Z'/Z = K, a real constant, then
Ay = -K and the scale has been multiplied by a factor -K Usually
in such a case of multiplication by a constant -1 or -K » Zand Z’ 98
are selected as resistances. If the inversion is not a a
second amplifier with unit gain may be used in casecade wil e
scale changer.
(iii) Phase Shifter: Assume that Z and Z’ are equal in magnitude ba
differ in angle. The operational amplifier shifts the phase of a
sinusoidal input voltage while at the same time preseeving, its,
amplitude. Any phase shift from 0 to 360° ( or + 180°) may be
obtained.
@ Integrating Amplifier
c
Fig, 5-5
An integrating amplifier is formed if a capacitor is connected
between input and out as shown in fig. 5-5 . This circuit produces
an output voltage that is proportional to the time integral of the input
voltage. Hence this circuit is called an integrator, ith the help of
an integrating amplifier, it is possible to solve ci plex equations.
Integrators are used in Sweep generators, in filters and in simulation
studies in analog computers. .
Tf no current flows throu;
igh the operational amplifier, we can
write
Vs A(Vg ~ Vo)
a rr snve(2)
Vg is very small so that dVo . ‘i
Ce TOR eel (3)
2dVg = =o
0 cet ne (4)
Taking integration on both sides
sve (S)
Vo = -qsva
Thus the output voltage Vo is equal to
the integral of the input voltage V,
a constant -1/CR times
(©)Differentiators
Fig. 5-6
of integration and may be obtained
The
Differentiation is the inverse
by interchanging R an C components of the integrator circuit.
differentiators is shown is Fig 5- 6.
If we neglect the current through the amplifier and Vg is taken
to be negligibly small, we get
L=l (Q)
4(V;-Vs) _ Ys-Yo
o a =k we (2)
Neglecting Vs we get
dV, Vo
Cy TTR 100
d
: ge itso (3)
we Vy = - CR @)
The output voltage Vo is equal to a constant ~CR times the time
derivative of the input voltage V,
(@) Adder or Summing Amplifier
Ry
Fig, 5-7
An adder or a summing amplifier using an OP-AMP is shown
in Fig. 5-7. Since the current flowing into the virtual ground is equal
to that flowing out of it, we can write
+ (1)
..Q)
e))
(4)
IfR; = R, then
Vo = = (Vy + V9 + eer wa (5)
i.e the output voltage Vo is numerically equal to the algebraic
sum of the input voltages. 101
Fig. 5-8
The schematic D / A converter is shown in fig. 5-8. The input
is an mbit binary word and is combined with a reference voltage
Vz to give an analog output signal. The output of a D/A convertor
can be either a voltage or current. For a voltage output the D/A
converter is mathematically described as .
Vo = KVps 2" #4 2 escent dy 2)
Where
Vo _ is the output voltage,
Vz, _ is the full scale output voltage,
K_ - is the scaling factor usually adjusted to unity, ,
dy, dy d, isn bit binary fractional word with the decimal point
located at the left
d, is the most significant bit (MSB) with a weight of
~ Vpg/2 and
d, is the least. significant bit (LSB) with a weight of Vpg/2"
There are various ways to implement the above equation. In this
we will discuss the following resistive methods.
(i) Binary weight method and
(ii) R -2R ladder method. 102
‘(DIA converter with Binary -weighted resistor:
Fig. 5-9
Fig. 5-9 shows a D / A converter using an OP-AMP and binary
weighted resistors. Here the OP-AMP is connected in the inverting
mode. But it can also be connected in non- converting mode. do ,
d,, d, and d3 are four electronic switches which are controlled by
binary input word. These switches are single pole double throw type.
If the binary input to a particular switch is 1, it connects the resistance
to the reference voltage. If the input bit is 0, the switch connects the
resistor to the ground. £
When the switch dg is closed, the voltage across R is 5V because
V, = V, = 0 V. Therefore the current through R is 5V / 10K2 =
0.5 mA. However, the input bias current is negligible. Hence the
current through feedback resistor Rp is also 0.5 mA. This in tum
produce an output voltage of is along closed, the current will be 1
mA. and the output voltage of {(1kQ) (0.5mA) = -0.5V. Thus the
OP-AMP work only as a current -to-voltage converter. When d1 is
along closed, the current will be 1 mA and the output voltage vo is
-1V. If both switches dy and d, are closed; the current through
Rg will be 1.5 m.A which will be converted to an output voltage of
-1.5V. | 103
Thus depending on whet
5, ther switches d,
bina: , 8 dp to
te ime weighed cron Wl best i pt eth
Tee cameeaeg ns i equal to the curents though Rp which in
switches are closed, the ak ae ee vohees, | yea al
A ut wil 3
voltage equation is given He will be maximum . The output
d,
Vo= Re (Pests =)
R*R/2*R/4* R/S
where each of the iny ? 3
iputs d3, dy, d, and d,
(45V) or low (OV). 13, d, dy and dy may either be high
-1V
-15V
Output
Fig 5-9(a)
Fig 5-9(a) shows analog outputs versus possible combination of
inputs. The output is a negative going staircase waveform with 15
steps of -0.5V each. In practice, the steps may not all be the same
size because of the variation in logic high voltage level. The size of
the steps depend on the value of Rp. Therefore a desired step can be
obtained by selecting 4 proper value of Rr.
The accuracy and stability depends upon the accuracy of the
resistors and the tracking of each other with temperature. There are,
however, a number of problems in this type. One of the disadvantages
of binary weighted type is the wide range of resistors values required.
For better resolution the input binary word length has to be increased. 104
Thus as the number of bit increases the range of resistance value
increases. The fabrication of such a large resistance in IC is not
Practical. Also the voltage drop across such a large resistor due to”
the bias current would also affect the accuracy. The difficulty of
achieving and maintaining accurate ratio restricts the use of weighted
Tesistor type to below 8-bits.
a
(id) R-2R Ladder Method :
‘The binary ladder is a resistive network whose output voltage is a
Properly weighted sum of the digital inputs. A ladder for 4 bits is shown
in Fig 5-10. This ladder consists of resistances having only two valves.
‘The left end of the ladder is terminated in a resistance of 2R.
Fig 5-10
Let us consider all the inputs are at ground. Beginning at node
A, the total resistance looking into the terminating resistor is 2R. The
total resistance looking out towards the 2° input is also 2R. These
two resistances can be combined to form an equivalent resistor of
value R as shown in Fig. 5-11. Moving to node B, we can show that
the total resistance looking into the branch towards node A is 2R, as
is the total resistance looking out toward the 2) input. In a similar
Way We move to the node C and D and the resistance looking into
the node is 2R. This is t d igital i
py ‘S Ime regardless of whether the digital inputs
=
Fig 5-11 7 BES ee
105
This resistance characteristic of ladder can
be used to determine the output voltage for the aN
various digital inputs.. Let the digital input be
4000. Since there is no voltage source to the
left of D, the equivalent circuit will be as 2g |
shown in Fig. 5-12. In this case the output Wa
voltage is = °
Fig. 5-12
2R v
Lave JR a
Va = *VoRy oR = 72 ”
Thus a 1 in the MSB position will provide an output voltage of
+V/2.
Now let the input be 0100.
In this case the equivalent circuit | yy)
will be as shown in Fig. 5-13. In
this case we can show that the
output will be
* < Ww v,
Ya = qe
Fig. 5-13. *
.. (2)
aie
Thus the second MSB provides an output voltage of +V/4. In
a similar way we can show that the third will produce +V/8 and the
fourth +V/16, Hence the total output voltage due to combination of
input levels will be
I<
Va =
. 3)
vi<
al<
wl<
a
This R-2R ladder can be used in the D/A converter. The D/A
converter with R and 2R resistors is shown in Fig 5-14. won| cart
TOA T vos
ne
2" 2
roxn zoxn# 204M
Fig. 5-14
The binary inputs are simulated by switches do through ds. The
output is proportional to the binary inputs. If the switches are closed
then the input is high. If the switches are open, then the input is low.
Assume that switch d; is closed. It is the most significant bit (MSB)
so the input through d, is high (+5V). Other switches are connected
to the ground. The resultant circuit will be as shown in Fig. 5-15.
The resistance to the left of switch d3 is 2R. In this figure, the (-)
input is at virtual ground (V> = 0). Therefore the current through the
equivalent resistance 2R in zero. However, the current through 2R
connected to +5V is 5V/20KQ. = 0.25mA. The same current flows
through Ry and in turn produces the output Voltage
Vo = -(20KQ\(0.25mA) = -SV 0 ase (4)
Ry, +R Vv, 20 a,
ie et
Osh “TTP Ph 2048
WKS
0 — .
TOT He
“5V
Vy--5V
Fig, 5.15
Using the same analysis, the output Voltage corresponding to
all possible combinations of binary inputs can be calculated. The
output Voltage equation can be written as eee ee
wr
4; d, d, dy
No = Re (Se aR aR TR
where each of the inputs d3, d, d, and do may be either high
(45V) or low (OV).
y A/D converters
A/D converters convert
an analog voltage to the
digital output. As in the case
of D/A converters analog
coaverters are also specified
as 8, 10, 12 or 16 bit. ThE ppoiog cual
block diagram of A/D input, "| ZZ foutput
converter is shown in Fig. chee
5-16. Fig. 5-16. Its function
js just opposite to that of D/A {
converters. It accepts an Vp (Reference!
analog input voltage Vq and :
as an output binary Fig. 5-16
word dy, d,..... d, of functional value D so that
Start £0
Le J usB
agp
D = dy 2) dy 2? + ne dz"
where dy is the most significant bit and d, is the least significant
bit, An A/D converters usually has two additional control’lines. The
START input to tell the A/D when to start the conversion and end
of conversion (EOC) output to announce when the conversion is
complete. A/D converters are classified into two groups according
to their conversion technique. They are
(i) Direct type A/D converter and.
(ii) Integrating type converter.
Direct type A/D converters compare a given ‘analog signal with
the internally generated equivalent signal. The integrating type of
A/D converters perform conversion in an indirect manner-by first
changing the znalog input signal to a linear function of time or
frequency and then to a digital code. We will discuss successive 108
approximation type converter and counter type converters. These two
belong to direct type A/D converters,
(®) Successive Approximation Converter
Start
Fig. 5-17
Fig. 5-17 shows a successive approximation type of A/D
converter. It uses a very efficient strategy to complete n-bit
conversion in just n-clock periods. The heart of the circuit is an 8-bit
successive-approximation register (SAR) Its output is applied to an
8-bit D/A converter. The analog output of the D/A converter is then
compared to an analog input signal by the comparator. The output
of the comparator is a serial data input to the SAR. The SAR then
adjusts its digital output until it is equivalent to analog input. The
8-bit latch at the end of conversion holds onto the resultant digital
data output. The circuit works as follows. .
With the arrival of the START command, the SAR sets the MSB
d; = 1, with other bits to Zero. So the trial code is 10000000. The
D/A converter then generates an analog equivalent. The output Va
is now compared with the analog input V,. If V, is greater than the
D/A converter output V4, then 10000000 is less than the correct digital
representation. The MSB is left at ‘1’ and the next lower significant
nit is made ‘1’ and further tested, Pe Rak eee | | eer) Wer ree eet eeere ere eeet [rt
109
However, if Va is less than DAC output, then 10000000 is
greater than the correct digital representation. So reset MSB to ‘0’
ged go on to the next lower significant bit. This procedure is
repeated for all subsequent bits, one at a time until all bit positions
have been tested. Whenever the DAC output crosses Va, the
comparator changes state and this can be taken as the end of
conversion (EOC) command. The advantage of the successive
approximation A/D converter is its high speed and excellent
resolution. For example, the 8-bit successive approximation A/D
converter requires only eight clock pulse.
(i Counter Type AID Converter :
‘A higher resolution A/D converter using only one comparator
could be constructed if a variable reference voltage were available.
This reference voltage could then be applied to the comparator and
when it became equal to the imput analog voltage the conversion
would be complete.
ANALOG INPUT
Fig. 5-18.
To construct such a converter, we begin with a simple binary
counter, The digital output signal will be taken from this counter. 110
The output of this counter is given to a binary ladder to form a simple
D/A converter. If a clock is applied to the input of the counter, the
output of the binary ladder is the familiar staircase waveform. This
waveform is exactly the reference voltage signal with a minimum
of gating and control circuitry, this simple D/A converter, can be
changed in the desired A/D converter.
Counter type A/D converter is shown in Fig. 5-18. The counter
is reset to zero count by the reset pulse. Upon the release of reset,
the clock pulses are counted by the binary counter. These pulses go
through the AND gate which is enabled by the voltage comparator
high output. The number of pulses counted increase with time. The
binary word representing this count is used as the input of a D/A
converter. The output of this is a staircase of the type shown in Fig.
5-18. The analog output Vj of DAC is compared to the analog input
V, by the comparator. IF V, >Vq, the output of the comparator
becomes high and the AND gate is enabled to allow the transmission
of the clock pulses to the counter. When V,
