2-7 plemented in the computer s fe & note on scalar data type, . Write « note on fixed point mumber representation Find I's complement of (10101109), e can selate addition and subtraction operations of numbers by the following jonship : =B) = (A) + (-B) and A)- (B) = @ A) + GB) efore, we can change subtraction operation to an addition operation by g the sign of the subtrahend. 0 Example : Add (6);9 to (7),o in binary. 1 aay Carry a LOLt/1 0} = Gq 1+1= 10 CREE TPAfOlt} =A» ¢ first three operations produce a sum whose length is one digit, but when the * operation is performed sum is two digits. The higher significant bit of this It is called a carry, and lower significant bit is called sum. e logic circuit which performs this operation is called a half-adder. The circuit ich performs addition of three bits (two significant bits and a previous carry) is l-adder. : an Biron ‘rants reprwentabion te povtyay the \ CF On gaitherokiC serokiows TECHNICAL PUBLICATIONS" An up thrust for knowledgeArithmetic Operations Computer Architecture Half Adders The half-adder operation needs two binary inputs : two binary outputs : sum and carry. augend and addend bits; and «The truth table shown in Table 22.1 gives the relation between input and outpul variables for half-adder operation. Inputs Outputs A Cary Inputs A Outputs s— Sum Table 2.2.1 Truth table for half-adder Fig. 2.2.1 Block schematic of half-adder K-map simplification for carry and sum a fa Logic diagram Fig, 2.2.2 Maps for half-adder Fig. 2.2.3 Logic diagram for half-adder Limitations of Half-Adder : * In multidigit addition we have to add two bits along with the carry of previous digit addition. * Effectively such addition requires addition of three bits. This is not possible with half-adder. Hence half-adders are not used in practice. ERXYY Full adder . A fulladder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. © Two of the input variables, to be added. The third inpi significant position. denoted by A and B, represent the two significant bits ut Cin, represents the carry from the previous lower TECHNICAL PUBLICATIONS”. An up thrust for knowledge c Looe” 2 anthmatio Operations ces + the truth table for full-adder is shown in Table 2.2.2. Full adder om Cout Fig. 2.2.4 Block schematic of full-adder Cout = AB+A C;, 4B Cin, Fig. 2.2.5 Maps for full-adder yi AR p> o £ g > a> o> o=Di Fig. 2.2.6 Sum of product implementation of full-adder A BCin +A B Ci, +A B Cig +A BCin Cin (AB+AB)+C,, (AB+AB) = C,,(A © B)+C,, (A@ B) Cin (A® B) + Cy, (A® B) = Cy, @(A@ B) " TECHNICAL PUBLICATIONS™- An up thrust for knowledgesinyplitied Boolean function circuit =<) eee Sominitee dlanantone 2-10 Arithmetic Opera With this for Rabadder can be implemented as shown in a the Big. 27, = : ho, A Coy SABHA CH FB Cin ~ Cy ABHA CH BABB Cig ATA C ABS ABC g FAB Cig FABCin +A BCin = BCyp tA Jementation of full-ad AB (L4.Cig + Cig) tA BC ig FA BCin Fig, 2.2.7 Impl ABH ABC, HABCig = AB+ Cin (AB +AB) = AB+Cin (A ® B) First hatfadder ‘Second half-adder . Cpe Aes) ‘sum Cig (AS 8) — Cour Gr AB it te Fig, 2.2.8 Implementation of a full-adder with two half-adders and an OR gate . 3 Oaheln FERRY Parallel Adder { Pte ple os an BAL By Ao + A bit, parallel adder can be constructed using ee L Ea mumber of full adder circuits connected ~~ in fs Sy Sy parallel. + Fig. 229 shows the block ‘Fig. 2.2.9 Block diagram of n-bit parallel adder Giagram of mbit parallel adder using n number of full-adder circuits connecte fe, ie. the carry output of each adder is connected to the carry input 0 next hig] her-order adder. Binary Subtraction * In a 2's complement subtraction, negative number is represented in th complement form and actual addition is performed to get the desired result example, operation A ~ B is performed using following steps : 1, Take 2's complement of B. 2. Result — A + 2's complement of B. 3. If cary is generated then the result is positive and in the true form. Ir case, carry is ignored. 4. If carry is not generated then the result is negative and in the 2's comple form.Computer Architecture Perform (28) 9 ~(15)19 using 6-bit 's complement representation. Solution : (28): = (011100), (15)i0 = (001111), (EECET wn Carry EOOGE 1's complement of (18)10 4) ada ia 1| 2's complement of 15, i.e., (-15)49 ala Carry (28)i0 ©} 4} 4] 4] 0] 0] Binary equivatent of (28)49 + 18 Sign Extension 1] 4[0[o[0]| 1] 2's comptement of 15, ie. (-15)49 ®h0 Ignore Carry ——-Seofola| alo 1| Result: Binary equivalent of (13)19 (13)49 GEREEEZE) Perform (15)19 -(28) 9 using 6-bit 2's complement representation. Solution : (15)i9 = (001111) (28)10 = (011100) Of 4] 1] 170] 0] Binary equivatent of (28),9 16,4 Carry [1[ofo[o] 4] 1] tscomplement of (28),9 + 1|-Add1 1[o]o|1jolo 2's complement of (28), i-e., (28); Can (15)49, (2101114) 4/4] Binary equivatent of (18)49 + t]o]o]1]0[0| 2scomptement of (28), (28)i9 111} 0] 011} 1} Result = Binary equivalent of (-13)49 (13)49 0}0|1|1{0]0| 1's complement of result 1| Add1 1| Result = Binary equivalent of (13)49Computer Architecture Arithmetic Of tic Opera [2X] Parallel Subtractor The subtraction A — B can be done by taking the 2’s complement of B and adg it to A. © The 2’s complement can be obtained by taking the 1’s complement and adg one to the least significant pair of bits. The 1’s complement can be implemen with inverters and a one can be added to the sum through the input carry to 2's complement, as shown in the Fig. 2.2.10. B; As B, Ay B, Ay By Ao Ce Sy S) Sy So Fig. 2.2.10 4-bit parallel subtractor Addition/Subtraction Logic Unit e Fig. 2.2.11 shows hardware to implement integer addition and subtraction consists of n-bit adder, 2’s complement circuit, overflow detector logic circuit | AVE (overflow flag). Number a and number b are the two inputs for n-bit adder. For subtraction, subtrahend (number from B register) is converted into its 2’s complement form making Add/Subtract control signal to the logic one. B Register Add / subtract control +-Complementer n-bit adder Parallel adderComputer Architecture ented + When Add/Subtract control signal is one, all bits of number b are complemen and carry zero (C.) is ab es result as R vl te one. Therefore n-bit adder gi where b+ 1 represents 2's complement of number b. Overfiow in Integer Arithmetic ¢ When = adding signed #1 i ee 4 es ace beyond the end of the yp word does not serve as the ae overflow indicator. LS + If we add the numbers + 7 Lf») and + 3 in a 4bit adder, BratBaat Rot the output is 1010, which is the code of ~ 6, a wrong 5 result. In this case, carry bit from the MSB position is 0. Similarly, if we add — 5 and — 6, we get output = + 5, another error. In this case carry bit from the MSB position is 1. Fig. 2.2.12 Overflow detector logic circuit * One thing we can surely say that, the addition of numbers with different signs cannot cause overflow, because the absolute value of the sum is always smaller than the absolute value of one of the two operands. * From above discussion we can conclude following points : 1. Overflow can occur only when adding two numbers that have the same sign. 2. The carry bit from the MSB position is not a sufficient indicator of overflow when adding signed numbers. 3. When both operands a and b have the same sign, an overflow occurs when the sign of result does not agree with the signs of a and b. The logical expression to detect overflow can be given as Overflow = ana bp-1 Raa tana Pa Raa where 4-1 = MSB of number a by-1 = MSB of number b MSB of the result TECHNICAL PUBLICATIONS”. &n up thst for knowledgeArithmetic Op, Computer Architecture 2-14 Solution : Case 1 : Both numbers positive 1/1] 1] Carry of4[4{4 on +fofo]1{4 (3) ijolijo Result : 2's complement of 6 . Fig. 2.2.13 Result is ~ 6 ; it is wrong due to overflow. Case 2 : Both numbers negative 1 Carry afo[1]4 2's complement of 5, i.e. (— 5) +[1[1[ 0} 0 2's complement of 4, (- 4) o}1j1f1 G7) Fig. 2.2.14 Result is + 7 ; it is wrong due to overflow. Design of Fast Adder (Look-ahead Carry Addition) * The n-bit adder ripple carry adder discussed in the last section is implemen using full-adder stages. In which the carry output of each full-adder stage connected to the carry input of the next higher-order stage. * The sum and carry outputs of any stage cannot be produced until the input c2 occurs; this leads to a time delay in the addition process. This delay is known carry propagation delay, which can be best explained by considering the follow addition. of the second position (stage), produces a carry into t Te When Added to the bits of the third positios last position. third position. The latte Produces a carry into the BS The key thi oa ae es poe in this example is that the sum bit generated in the ls Rous Seios tree on the carry that was generated by the addition in t eee ed ee that adder will not produce correct result uni . ‘ough the intermediate full-. s. Thi 2 time delay that depends on the Propagation delay Beaton ia nepreschaaot ‘Arithmetic Operations ee ge eae eh father i considered to have a propagation delay of 30 ns, Theref NAIL not reach its correct value until 90 ns after LSB carry is generated. fore, total time required to perform addition is 90+3 120 ns. This Situation becomes much worse if we extend the adder circuit to add a greater ‘ adder were handling 16-bit numbers, the carry propagation number of bits. If the delay could be 480 ns, ¢ Generally, carry prop: agation delay and sum propagation delay are measured in terms of gate delays, Looking at Fig. 22.6 we can notice that for full-adder requires two gate delays and sum requires only one gate delay. When we connect such full adder circuits in cascade to generate r-bit ripple adder as shown in the Fig. 22.9, C,; is available in 2(n-1) gate delays, and Sp-1 is correct one XOR gate delay later. The final carry-out, Cy is available after 2n gate delays. Thus for {bit ripple adder C, is available after 8(2x4) gate delays, C3 is available in 6[2(4-1)] gate delays and S; is available in 7 gate delays. * One method of speeding up this process by eliminating inter stage carry delay is celled lookahead-carry addition. This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated. It uses two functions : carry generate and carry propagate. * Consider the circuit of the full adder shown in Fig. 2.2.15. Here, we define two cto eee SEE eye P, = A,B, a “= D-D GAB t The output sum and cary ¢, can be expressed as 5S =PeG Ga = GtRG is called a carry generate and it produces on carry when both A; and B; are ardless of the input carry. Fig. 2.2.15 Full adder circuit a carry propagate because it is term associated with the propagation of from G; to C11. Now Ci1 can be expressed as a sum of products of the P and G outputs of all the preceding stages, le, the carriers in a four stage carry-lookahead adder are defined Go + Po Gin as TECHNICAL PUBLICATIONS”. An up ust or knowiodge aesComputer Architecture 2-16 ‘Avthmetc Opa Cy = Gy + Py C= Gy + PGy +P, Py te Cy = Gz + Py Cp = Gy + Pp Gy + Py PL Gy + P2 Pi Po cm Cy = Gy + P3 C3 oe = G3 + Ps Gy + Py Py Gy + Py Py Py Go + Ps P2 Pt vSn ahead adder circuit design * Fig. 2.2.16 shows the general form of a carry-looka this way. Carry - lookahead generator {eee z : a Fig. 2.2.16 General form of a carry-lookahead adder circuit Ant «We can cascade such 4-bit carry-lookahead adders to form a 16-bit or 32-bit ac We require four 4-bit carry-lookahead adders to form 16-bit carry-lookahead a and eight 4-bit carry-lookahead adders to form 32-bit carry-lookahead adde: 32-bit adder, the carry out Cy form the low-order 4-bit adder is available 3 delays after the input operands A, B and Cg are applied to the 32-bit adder. Ther s available at the outputof the second dder after a further 2 gate delays, C12 is available _aftera further 2 gate delays, and so on. Finally, Cog the carry-in to the high-order 4-bit adder, is available after a total of (6x2) + 3 = 15 gate delays, C3 is C.., pan after 2 more gate delays, ie. after 17 gate Gp vs and $3, is available after 3 gate delays, ie. 18 °° Gate delays, These gate delays are very less compared f0 total delays of 63 and 64 for S3) and C3 if ripple-carry adder is used, s Fia. 2247 esr eneConputer Arohitectun sete Arithmetic Operations errr Sy 8, 8, So ty lookahoad gonorator Ag By Ag Be A By Ao Bo Fig. 2.2.18 Multilevel Generate and Propagate Functions * In the 32-bit adder just discussed, the carriers Cy, Cg, C2, ... ripple through the 4-bit adder blocks with two gate delays per clock. This is analogous to the way that individual carries ripple through each bit stage in a ripple-carry adder. By using multi-level block generate and propagate functions, it is possible to use the lookahead approach to develop the carries Cy, Cg, Cy, ... in parallel, in a multi-level carry-lookahead circuit. The Fig. 2.2.19 shows a 16-bit adder implemented using four 4-bit adder blocks. Here, blocks provide new output ctions defined as Gj, and PL, where K = 0 for the first 4-bit block, K = 1 for second 4-bit block and so on. In the first block, Ph = P3P2P1Po " G] = G3+P3G2 +P3P,G1+P3P2PiGq TECHNICAL PUBLICATIONS". An up thst for knowoageArithmetic Operation, }Computer Architecture X12 Yis-12 Ya Yaa Sy On Xe Vive { 4 4-bit adder o12 4-bit adder 16. Fig. 2.2.19 16-bit carry-lookahead adder built from 4-bit adders Therefore, we can use first-level G; and P, functions to determine whether bit stage i generates or propagates a carry, and we can use the second level Gk and) PX. functions to determine whether block K generates or propagates a carry. With these new functions available, it is not necessary to wait for carries to ripple through the 4bit blocks. Looking at Fig. 2.2.15, we can determine Cyg as Cig = Gh +P5G) +PyPic! +Plplpig! +plplplpic, The above expression is identical in form to the expression for C4; only variable names are different. Therefore, the structure of the carry-lookahead circuit in the Fig. 2.2.19 is identical to the carry-lookahead circuit shown in the Fig. 2.2.18 However, it is important to note that the carries C4, Cg, Cy and Cig generated internally by the 4bit adder blocks are not needed in the Fig. 2.2.19 because they are generated by the multi-level carry-lookahead circuits. Let see the delay in producing outputs from the 16-bit carry-ahead adder. The delay in developing the carries produced by the carry-lookahead circuits is two gate delays more than the delay needed to develop the Gk and PX. functions. The Gx and PJ functions require two gate delays and one gate delay, after the generation of G; and P;, Therefore, all carries produced by the carry-lookahead circuits are available 5 gate delays after A, B and Co are applied as inputs. The carry Cys is generated inside the higher-order 4-bit block in the Fig. 2.2.19 in two gate delays after Cy) followed by Sis in one further gate delay. Therefore, S15 is available after 8 gate delays. These delays, 5 gate delays for Cys and 8 gate delays for Sj5 are less as compared to 9 and 10 gate delays for Cys and Sy5 in cascaded 4-bit carry-lookahead adder blocks, respectively. TECHNICAL PUBLICATIONS” - An up thrust for knowledge respectively,Ncomputer Architecture + We can cascade two 16-bit adders to implement 32-bit adder, Here, only two more gate delays are required to get Cay ond Sy and Cay and Spe reapectively Therefore, Cag is available after 7 gate delays and Sq) available after 10 gate delays. Fhese delays are less compared to 18 and 17 ate delays for the outputs if the 32-bit adder is built from a cascade of eight 4-bil adders. + If we go for third level then we can built 64-bit using four 16-bit adders. Delay through this adder will be 12 gate delays for Say and 7 pate delays for Cist- Anninotie Operations same feu ions