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Lectures wk5

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Abhay Kumar
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8 views

Lectures wk5

Uploaded by

Abhay Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Static noise margin (SNM) of the unstressed SRAM cell.

The window in the ``butterfly'' curve


illustrates the hardiness against noise.

Figure of merit for an SRAM cell is its static noise margin (SNM).
It can be extracted by nesting the largest possible square in the two voltage transfer curves (VTC) of the involved CMOS inverters
The SNM is defined as the diagonal length of the square, given in volts.
When an external DC noise is larger than the SNM, the state of the SRAM cell can change and data is lost.

1
Static Noise Margin

• SNM quantifies the amount of voltage noise required at the internal nodes of a bitcell to flip
the cell’s contents.
• Degraded SNM can limit voltage scaling for SRAM designs.

BL WL BLB

M3
VN
M6 SNM is length of diagonal
M2
M1 M4
M5 of the largest embedded
Q VN QB square on the butterfly
Inverter 1 Inverter 2 curve
[1]
2
Cont’d
The minimum supply voltage of SRAMs is determined by both Read SNM and Write SNM levels;
reducing Vth in the NMOS transistor improves Write SNM but worsens Read SNM.

Moves to the left

Moves upward

SNM Butterfly Curve

SNM is lower during read access because the VTC is


degraded by the voltage divider across the access
transistor (M2,M5) and drive transistor (M1,M4)[2]

3
SNM during HOLD and READ

BL BLB BL prech 1 BLB prech 1


WL=0 WL=1
M3 M6 M3 M6
M2 M2
M5 M5
M1 M4 M1 M4
1 0 [1] 1 0

Read SNM is worst-case


4
6T Cell Layout
B- B+ N Well
Connection

VDD

PMOS
Pull Up

Q/ Q

NMOS
Pull Down
GND

SEL

SEL MOSFET

Substrate
Connection
7
6T SRAM Array Layout

8
Another 6T Cell Layout Stick Diagram

bit bit’
VDD

T T

T T

T T word
Gnd
GND and contact shared
with cell to left These four contacts shared
with (mirrored) cell below

2 Metal Layer Process


9
6T Array Layout (2x2)
Stick Diagram Gnd
bit bit’ bit bit’ VDD
VDD
Gnd

word

word

VDD
10
6T Cell Full Layout
•Transistor sizing
M2
• M2 (pMOS) 4:3
• M1 (nMOS) 6:2
• M3 (nMOS) 4:2
•All boundaries shared
•38λ H x 28λ W
•Reduced cap on bit lines

M1

M3
11
6T Cell – Example Layout &
Abutment
Vdd
Vdd
T3 Vdd Vss Vdd
T4 T4 T3 T3 T4

T1 T1
T2 T2
Vss Vss
Vss
T1 T5 T6 Vdd
T6 T5
T2
Vss
T5 T6 T6 T5
Vss Vss
T2 T2
Vss T1 T1
Vss
T4 T4
Vdd
T3 T3
Vdd
Vdd
T5 T6 B B’ B’ B B
4 x 4 array
2 x 2 abutment 12
6T and 4T Cell Layouts
R1 GND Vdd VDD
T6 T5
BIT T4
R2 BIT!
T3

Q Q
T1
T4 T3T2
Word
Line GND
T1 T2 WL

BL BL
13

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