Icc2 Library Manager
Icc2 Library Manager
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Preface
This preface includes the following topics:
• About This Guide
• Customer Support
Audience
This user guide is for engineers who use the Library Manager tool to prepare NDM cell
libraries.
To use the Library Manager tool, you need to be familiar with the following:
• Logical and physical design principles
• The Linux operating system
• The tool command language (Tcl)
Related Publications
For additional information about the Library Manager tool, see the documentation on the
®
Synopsys SolvNet online support site at the following address:
https://solvnet.synopsys.com/DocsOnWeb
You might also want to see the documentation for the following related Synopsys products:
• Library Compiler™
Release Notes
Information about new features, enhancements, changes, known limitations, and resolved
Synopsys Technical Action Requests (STARs) is available in the IC Compiler II Release
Notes on the SolvNet site.
To see the IC Compiler II Release Notes,
1. Go to the SolvNet Download Center located at the following address:
https://solvnet.synopsys.com/DownloadCenter
2. Select IC Compiler II, and then select a release in the list that appears.
Conventions
The following conventions are used in Synopsys documentation.
Convention Description
Customer Support
Customer support is available through SolvNet online customer support and through
contacting the Synopsys Technical Support Center.
Accessing SolvNet
The SolvNet site includes a knowledge base of technical articles and answers to
frequently asked questions about Synopsys tools. The SolvNet site also gives you
access to a wide range of Synopsys online services including software downloads,
documentation, and technical support.
To access the SolvNet site, go to the following address:
https://solvnet.synopsys.com
If prompted, enter your user name and password. If you do not have a Synopsys user
name and password, follow the instructions to sign up for an account.
If you need help using the SolvNet site, click HELP in the top-right menu bar.
• Breakpoints
• Scaling Group
• Antenna Properties
Physical Library
A physical library is a library that contains only physical information (frame views, and
optionally design or layout views) for the library cells. Many vendors provide the physical
information about the library cells for a technology in a physical library. In other cases,
they provide GDSII, OASIS, or LEF files that contain the physical information for the library
cells, and you must use these files to generate the physical library. This type of library is
used as an input to generate a cell library.
See Also
• Cell Library
Logic Library
A logic library is a library that contains only logical information, such as timing, power,
noise, and functionality, for the library cells. This type of library is used as an input to
generate a cell library.
See Also
• Cell Library
Cell Library
A cell library is a unified library that contains the logical and physical information for a
specific technology and one or more of its library cells. Each library cell is represented as
a single object with multiple views that contain various types of information about the cell.
Figure 1 shows a conceptual view of a cell library. The views shown in green are the views
used by the implementation tools. Table 1 describes each of the view types.
Timing view Contains the timing, power, and functional information The implementation tools use the timing
for a cell. It should contain timing and power information view to perform static timing analysis,
for all necessary characterization points (voltage and power analysis, and optimization.
temperature) for a given process setting. The data for each
characterization point is stored in a pane.
Layout view Contains the physical shape information for a cell, not The library manager uses the layout view
including connectivity and pins. This view is created only to create the design view.
when you read GDSII or Open Artwork System Interchange The implementation tools use the layout
Standard (OASIS) source libraries. view for mask generation.
Design view Contains all of the physical shape information for a cell, The library manager uses the design view
including connectivity and pins. to create the frame view.
Frame view An abstraction of the physical layout of a cell that contains The implementation tools use the frame
only the information needed for placement and routing, view to perform placement and routing.
such as the block boundary, pins, via regions, and routing
blockages.
Figure 2 shows the difference between a design view and a frame view of a standard cell.
You create a cell library by loading information from the following sources:
• The technology file
The technology file contains information about the routing layers and routing rules for a
specific technology. For information about the technology file syntax, see the Synopsys
Technology File and Routing Rules Reference Manual.
• The logic libraries
The source files for the logic libraries are Liberty libraries in compiled (.db) format.
These files contain the timing, power, and functionality information for the library cells
(standard cells or macro cells). Each file represents a characterization point for a
specific process, voltage, and temperature.
Note:
This book assumes that the logic libraries use the power and ground (PG)
pin syntax. For information about using older logic libraries that use the
rail_connection attribute to define the PG pin connections or do not
define the PG pins, see Appendix C, Using Non-PG Logic Libraries.
See Also
• Preparing Cell Libraries
Technology Library
A technology library is a library that contains only the information from the technology file
and TLUPlus files. It does not contain any library cells.
See Also
• Cell Library
Aggregate Library
An aggregate library combines multiple cell libraries into a single cell library with a defined
search order for the included cell libraries. When you refer to a cell in an aggregate library,
the tool uses the defined search order to find the first occurrence of the cell. You can use
an aggregate library to group related cell libraries for easier maintenance and distribution.
See Also
• Creating an Aggregate Library
Library Workspace
A library workspace is the in-memory representation of a cell library while it is being built.
You use a library workspace to create a new cell library, modify an existing cell library,
or create an aggregate cell library. You load the source files into the library workspace,
validate the contents, and then commit the workspace to save it as a cell library.
There are two types of library workspaces:
• Root workspace
This is the main library workspace. Only a single root workspace can be open at one
time. If you are creating a single cell library, you work only with a root workspace.
• Subworkspaces
Subworkspaces are used in the exploration flow to partition source data into multiple
cell libraries. Each subworkspace generates a single cell library.
See Also
• Creating a Library Workspace
Pane
A pane is the representation of the timing and power data for a cell. In general, a pane
represents the data at a single characterization point (temperature and voltage) for a given
process setting. In some cases, the data for multiple characterization points at the same
process setting can be merged into a single pane, which is called a scaling group.
If you are not using scaling groups, the timing view of a cell contains a pane for each logic
library that contains that cell. Each pane is indexed by its voltage and temperature values.
See Also
• Scaling Group
Breakpoints
In a logic library, a timing arc is represented as a lookup table. The index values specified
in the lookup table are referred to as the breakpoints for the timing arc. During timing
analysis, the tool uses interpolation to determine the timing values for points between the
specified breakpoints.
See Also
• Timing Arc Checks
Scaling Group
For a given process, you might have multiple logic libraries that represent different
characterization points (voltage and temperature). By default, timing analysis is performed
only at these characterization points. If the characterization points for a set of logic
libraries form a complete grid, you can create a scaling group, which merges the
characterization points into a single pane. A pane that represents a single logic library
uses the indexes specified in the logic library for the timing arc, typically input slew and
output capacitance. A pane that represents a scaling group has indexes for voltage,
temperature, or both, in addition to the indexes specified in the logic library. These higher-
dimension delay tables enable very efficient delay calculations in the implementation tools.
In addition, they enable interpolation between the voltage and temperature values of the
characterization points, which enables efficient multivoltage analysis and optimization.
See Also
• Creating and Using Scaling Groups
Antenna Properties
MOS transistor gate oxides are easily damaged by electrostatic discharge, especially
during the manufacturing process. The static charge collected on lower-level wires during
multilevel metalization processing can destroy gate oxides and ruin the chip. This issue is
called the “antenna problem.”
To protect the MOS device from being damaged, the area of the metal connected to a gate
oxide during a given metal mask stage must be limited to a certain value. When the metal
area exceeds this value, a reverse-biased diode can be used to provide a discharge path
to protect the gate oxide at a cell input.
The diffusion areas of output pins provide protection for gate oxides at input pins.
However, at intermediate stages of the manufacturing process, unconnected metal wires
extending from the input pins can cause antenna problems to occur. For many process
technologies, antenna properties specify the maximum ratio of antenna area (the metal
area of dangling connections) to gate area (the gate area of input pins). This ratio can be a
constant value or a value derived by an antenna equation.
See Also
• Automatic Antenna Property Extraction Using the IC Validator Tool
• Defining Antenna Properties on Standard Cells
• Defining Antenna Properties on Hard Macro Cells
For detailed information about the library preparation flow, see Preparing Cell Libraries.
User Interfaces
The Library Manager tool operates in the X windows environment on Linux. It provides a
flexible working environment with both a shell command-line interface and a graphical user
interface (GUI).
• The shell command-line interface, lm_shell, is a text-only environment in which you
enter commands at the command-line prompt. It is typically used for scripts, batch
mode, and push-button operations and is always available during a library manager
session.
• The GUI provides a wizard to perform library preparation, as well as tools for viewing
and editing the cells in your library. The look and feel of the library manager GUI is
consistent with the look and feel of other Synopsys GUIs.
The library manager uses the tool command language (Tcl). Using Tcl, you can extend the
lm_shell command language by writing reusable procedures and scripts (see the Using Tcl
With Synopsys Tools manual).
You can start or exit a session in either lm_shell or the GUI, and you can open or close the
GUI at any time during a session. The following topics describe how to start and exit the
tool using the command-line interface:
• Starting the Command-Line Interface
• Exiting the Library Manager Tool
See Also
• Working With the Library Manager GUI
You can include other options when you start lm_shell. For example,
• -file script_file_name to execute a script
See Also
• Starting the Tool in the GUI
• Using the Command Log File
• Setup Files
• Using Tcl Scripts
See Also
• Exiting the Tool From the GUI
See Also
• Using Tcl Scripts
where category is the name of the tool feature affected by the application option. Some
application option categories have subcategories to further refine the area affected by the
application option.
You use the following commands to work with application options:
• set_app_options: Sets one or more application options.
For more information about working with application options, see Application Options.
Using Variables
In general, the library manager modifies default behavior by using application options
rather than application variables; however it does support user-defined Tcl variables, as
well as a minimal number of application variables, such as the search_path variable.
See Also
• Defining the Search Path
• Using Application Options
To display the man page for an lm_shell application option, enter the man command
followed by the option name. You can also view the following types of summary pages for
application options:
• Category summaries
To view a man page the summarizes all of the application options for a specific
category, enter the man command followed by category_options. For example, to
see the man page that summarizes all library manager application options, use the
following command:
lm_shell> man lm_options
• Subcategory summaries
To view a man page the summarizes all of the application options for a specific
subcategory, enter the man command followed by category.subcategory_options.
For example, to see the man page that summarizes all signoff antenna extraction
application options, use the following command:
lm_shell> man signoff.antenna_options
• Command summaries
To view a man page the summarizes all of the application options for a specific
command, enter the man command followed by command_options. For example, to
see the man page that summarizes all application options that affect the read_db
command, use the following command:
lm_shell> man read_db_options
If you enter the man command on the lm_shell command line, the man page is displayed in
the shell and in the console log view if the GUI is open. If you enter this command on the
console command line in the GUI, the man page is displayed in the GUI man page viewer.
A Tcl script is a text file that contains a sequence of any lm_shell commands. It can also
include comments, which are indicated by a pound sign (#) at the beginning of a line.
# This is a comment
See Also
• Starting the Command-Line Interface
Setup Files
A setup file is a special Tcl script that the tool automatically executes at startup. It can
contain commands that perform basic tasks, such as initializing application options.
The setup file for the library manager is named .synopsys_lm.setup. The tool looks for this
file both in your home directory and in the project directory (the current working directory in
which you start the tool). The file is read in the following order:
1. The .synopsys_lm.setup file in your home directory
Typically the settings in this file define your working environment.
2. The .synopsys_lm.setup file in the project directory
Typically the settings in this file affect the processing of a specific library.
See Also
• User Interfaces
• Using Application Options
• Using Variables
• Using Tcl Scripts
See Also
• Setup Files
• Physical-only flow
Use this flow to create a separate physical-only cell library for the cells that exist only in
a physical library source file and do not exist in any of the logic library files. A physical-
only library typically contains cells such as filler cells, tap cells, flip-chip pad cells,
endcap cells, and decoupling capacitor cells.
The group of files used for this flow includes all of the logic and physical library source
files; however, the generated cell library includes only those cells that exist only in the
physical library source files.
Note:
You must read at least one logic library when using the physical-only flow;
otherwise, workspace validation fails and you cannot save the cell library. To
build a library of cells using only physical library source files, use the frame
flow.
• Exploration flow
Use this flow to automatically analyze the library source files and generate a script that
you can use to create a cell library.
• Edit flow
Use this flow to modify the physical data for cells in an existing cell library.
• Aggregate flow
Use this flow to combine multiple separate cell libraries into a single cell library.
Figure 4 shows the results of using the normal and physical-only flows on a library
workspace that contains two .db files, each of which contains a different characterization
point for the same set of cells, and one LEF file.
See Also
• Cell Library
• Technology Library
See Also
• Cell Library
To build a technology library, you follow the same flow, but omit steps four through eight,
which involve the source files for the library cells.
After a cell library is built, it does not need to be rebuilt unless one of the library source
files changes or a new version of the implementation tool requires an updated library.
See Also
• Using the Exploration Flow
• Modifying a Cell Library
• Creating an Aggregate Library
For example, to use the normal flow to create a cell library named mylib, use the following
command to create the library workspace:
lm_shell> create_workspace mylib
See Also
• Library Workspace
• Analyzing the Library Source Files
• Using the Exploration Flow
• Modifying a Cell Library
• Creating an Aggregate Library
Normal normal
Technology-only normal
Frame-only frame
Physical-only physical_only
Exploration exploration
Verification verification
Edit edit
Aggregate aggregate
For example, to use the normal flow to create a cell library named mylib, use the following
command:
lm_shell> create_workspace mylib
To use the physical-only flow to create a cell library named mylib_po, use the following
command:
lm_shell> create_workspace -flow physical_only mylib_po
To create a workspace for the exploration flow, use the following command:
lm_shell> create_workspace -flow exploration mylib_explore
Note:
Unless you are using the exploration flow, you can have only one library
workspace open at a time. To remove the current library workspace
from memory without committing it to a saved cell library, use the
remove_workspace command.
See Also
• Library Workspace
• Analyzing the Library Source Files
• Using the Exploration Flow
• Verifying Libraries
• Modifying a Cell Library
• Creating an Aggregate Library
With a scale factor of 1000, the bounding box is stored as {500 500} {505 505}, instead
of {5000 5000} {5053 5053}. With a scale factor of 10000, the bounding box is stored as
{5000 5000} {5053 5053}.
The scale factor for a library workspace must be a multiple of both the length precision
of the technology file associated with the workspace and the scale factor of the physical
library source files loaded into the workspace.
The default scale factor is 10000, which means that each database unit represents 1
Angstrom. However, the recommended scale factor is the technology length precision as
specified by the lengthPrecision attribute in the technology file. To use the technology
length precision as the scale factor, set the lib.setting.use_tech_scale_factor
application option to true before running the create_workspace command.
lm_shell> set_app_options \
-name lib.setting.use_tech_scale_factor -value true
If neither the default scale factor nor the technology length precision is appropriate for your
library, you can explicitly specify the scale factor by using the -scale_factor option with
the create_workspace command.
To determine the scale factor for an existing cell library, query its scale_factor attribute.
• To load a technology file into an existing library workspace, use the read_tech_file
command.
For example, to load the my.tf technology file into the current library workspace, use
the following command:
lm_shell> read_tech_file my.tf
• To associate a technology library with a library workspace when you create the
workspace, use the -use_technology_lib option with the create_workspace
command.
For example, to use the normal flow to create a cell library named mylib that gets its
technology data from the mytech.ndm technology library, use the following command:
lm_shell> create_workspace -use_technology_lib mytech.ndm mylib
• To associate a technology library with an existing library workspace, use the read_ndm
command to read the technology library into the library workspace.
For example, to associate the mytech.ndm technology library with the current library
workspace, use the following command:
lm_shell> read_ndm mytech.ndm
When you read a technology file into a library workspace, the tool performs syntax and
semantic checks on the contents of the technology file. The technology file checker has
two modes:
• User mode (the default)
In this mode, the tool downgrades the message severity for suspected errors for the
general user.
• Developer mode
In this mode, the tool increases the message severity for suspected errors for
the technology file developer to correct or waive. To enable this mode, set the
file.tech.library_developer_mode application option to true.
See Also
• Technology Data Access
• Creating a Library Workspace
This attribute identifies the default site for floorplanning. It must be set only on the
default site.
For example, to set the site definition named unit as the default site for floorplanning,
use the following command:
lm_shell> set_attribute [get_site_defs unit] is_default true
This attribute defines the site symmetry requirement for cell placement. It must be set
on all sites defined in the technology file. The attribute value is a list that contains one
or more of the following values:
◦ X - the site can be flipped about the x-axis
For example, to specify that the site definition named unit can be flipped about the x-
axis, set its symmetry attribute as follows:
lm_shell> set_attribute [get_site_defs unit] symmetry {X}
To specify that it can be flipped about both the x- and y-axis and can be rotated 90
degrees, use the following command:
lm_shell> set_attribute [get_site_defs unit] symmetry {X Y R90}
In general, the LEF file defines these site attributes, and the library manager automatically
sets them when you read the LEF file. If you load the physical data by reading a GDSII
or OASIS file or if the LEF file does not define these attributes, use the set_attribute
command to set them manually.
To report the site definitions, use the report_site_defs command.
Note:
The cell library contains only single-height site definitions. The Fusion Compiler
and IC Compiler II tools use the single-height site definition for both single-
height cells and multiple-height cells.
This attribute identifies the preferred routing direction for the layer. Valid values for this
attribute are horizontal, vertical, diagonal_45, and diagonal_135. For example,
to set the preferred routing direction for the M2 layer as horizontal, use the following
command:
lm_shell> set_attribute [get_layers M2] \
routing_direction horizontal
Note:
You can also specify the routing_direction layer attribute in the physical
rules file. For information about the syntax of the physical rules file, see
Physical Rules File Syntax. For information about loading a physical rules
file, see Loading the Physical Rules File.
• track_offset layer attribute
This attribute defines the offset in microns used to create the routing grid for the layer.
The first routing track is located at the specified distance from the placement grid
origin. For example, to set the track offset for the M2 layer as 0.1 micron, use the
following command:
lm_shell> set_attribute [get_layers M2] track_offset 0.1
In general, the LEF file defines these layer attributes, and the library manager
automatically sets them when you read the LEF file. If you load the physical data by
reading a GDSII or OASIS file or if the LEF file does not define these attributes, use the
set_attribute command to set them manually.
via_layers
tf_via_layer_name1 ITF_via_layer_name1
...
tf_via_layer_namen ITF_via_layer_namen
To include comments in the layer mapping file, start the line with an asterisk (*) or pound
sign (#).
After you read in a TLUPlus or common technology file, it is identified by its parasitic
technology model name. By default, the parasitic technology model name is the base
name of the specified file; however, you can specify a different name by using the -name
option.
For example, to read in a TLUPlus file named my.tlup using a layer mapping file named
my.layermap and store it in the workspace with a parasitic technology model name of
para1, use the following command:
lm_shell> read_parasitic_tech -tlup my.tlup \
-layermap my.layermap -name para1
If the library workspace already contains signal electromigration constraints, they are
replaced by the constraints in the new file.
To load logic libraries into the library workspace, use the read_db command.
For example, to load the db1_pvt1.db file, use the following command:
lm_shell> read_db db1_pvt1.db
To load all the .db files in the current directory, use the following command:
lm_shell> read_db [glob *.db]
If you specify the files with a relative path or with no path, the tool uses the search path
defined with the search_path variable to locate the files.
When you load a logic library into a library workspace, the library manager performs the
following tasks:
• Creates timing views in the library workspace for each of the blocks in the library
source file
• Saves the logic library attribute settings for the library, library cells, and library cell pins
in the library workspace
If you load more than one logic library into a workspace, the first logic library that you read
is considered the base library. The tool uses the base library for many consistency checks
among the logic libraries loaded for a workspace. If an attribute is defined in more than
one logic library, the tool uses the value from the first logic library in which the attribute is
defined.
By default, the tool processes all of the cells defined in the library source file. To process a
subset of the cells, filter the cells as described in Specifying Which Blocks to Process.
By default, the generated cell library contains the timing views generated from all of the
logic libraries loaded into the library workspace. To filter the logic libraries based on your
design operating corners, use the set_pvt_configuration command, as described in
Filtering Logic Libraries Based on Operating Corners.
See Also
• Pane
• Defining the Search Path
• Identifying the Process Associated With a Logic Library
For example, to read the db1.db logic library and set a process label of PVT1 on the
generated pane, use the following command:
lm_shell> read_db -process_label PVT1 db1.db
To set a process label of PVT2 on the generated pane after reading the logic library, use
the following command:
lm_shell> set_process -libraries {db1} -label PVT2
Note that this command does not affect loading of the logic libraries. It affects only which
logic libraries are actually used by the cell library. If you change the PVT configuration, the
library manager adjusts the logic library usage appropriately.
To see the logic libraries loaded into the library workspace, use the get_libs command.
To see which logic libraries are actually used by the library workspace based on the PVT
configuration, use the report_workspace command.
You must use the -mode_label option with these commands to specify the mode
associated with the timing arcs and generated clocks defined in the model.
For example, to read the .db file for the model1 extracted timing model, use the following
command:
lm_shell> read_db -mode_label functional model1.db
If you specify the model files with a relative path or with no path, the tool uses the search
path defined with the search_path variable to locate the files.
If you specify the LEF file with a relative path or with no path, the library manager uses the
search path defined with the search_path variable to locate the file.
By default, the read_lef command
• Processes all of the cells defined in the library source file
To process a subset of the cells, filter the cells, as described in Specifying Which
Blocks to Process.
• Creates a design view for each processed block
By default, if a block already has a physical representation in the library workspace,
the tool creates a design view with a new name. To change this default behavior,
either use the -merge_action option to change the behavior for all blocks or use a
block mapping file to specify the behavior for specific blocks. For details, see Handling
Duplicate Physical Blocks.
By default, the read_lef command derives the block boundary from the OVERLAP
layer in the LEF file, if it exists. If it does not exist, the command derives the rectangular
block boundary from the SIZE statement in the LEF file. To derive the rectangular
cell boundary from the SIZE statement even if the OVERLAP layer exists, use the
-cell_boundary by_cell_size option.
If a block has PROPERTY definitions in the LEF file, the read_lef command saves the
properties as user-defined attributes of the block. By default, the command saves all
the block properties; to save only specific block properties, specify the property names
with the -properties option.
When the library manager reads a LEF file, it stores certain settings as attributes on
the blocks or block objects. To use the LEF file only to update the attribute settings on
the existing blocks in the library workspace, and not to create design views, use the
-merge_action attributes_only option.
If the height and width of a block does not match the size of any site definition, the tool
issues an error message.
• Fails if the LEF file contains layer information that conflicts with the technology file
See Also
• Defining the Search Path
• Validating the LEF File
• Determining the Block Types When Reading LEF Files
• Determining the Electrical Equivalence for PG Terminals When Reading LEF Files
Validating the LEF File
To analyze an input LEF file before loading it into the workspace, enable check-only mode
by using the -syntax_only option. The check-only mode provides diagnostic information
about the correctness and integrity of the LEF file. The check-only mode does not load any
information into the workspace.
lm_shell> read_lef -syntax_only myphys.lef
Determining the Electrical Equivalence for PG Terminals When Reading LEF Files
By default, the read_lef command does not calculate the electrical equivalence (EEQ)
setting for the PG terminals. To calculate the EEQ setting for the PG terminals, use the
-create_eeq_setting_for_block_and_pad option. By default, when the library manager
calculates the EEQ setting, it considers the direction of the PG port. To ignore the port
direction, use the -ignore_pg_direction_for_eeq option.
Resolving Site Definition Conflicts When Reading LEF Files
If the LEF file contains site information that differs from the site information in the
technology file loaded into the library workspace, the read_lef command fails to load the
LEF file. Use one of the following methods to resolve the conflicts so you can load the LEF
file:
• If the files contain sites with the same definitions, but different names, you can specify
the site name mapping by using the -convert_sites option with the read_lef
command. For example, to change the site name in the myphys.lef file from unit to
new_unit, use the following command:
lm_shell> read_lef -convert_sites {unit new_unit} myphys.lef
• If the files contain sites with the same names, but different definitions, you can
enable the tool to automatically rename conflicting site names by setting the
file.lef.auto_rename_conflict_sites application option to true before running
the read_lef command.
When you enable this option, the tool uses the following naming convention to rename
the conflicting site names:
lef_file_name.site_name[_n]
The numeric suffix is added only if required to make the site name unique.
When the tool reads a library source file in GDSII or OASIS format, it assumes that all of
the blocks are standard cells and all of the pins are signal pins. It generates a layout view
for each block in the file. If it finds a duplicate block, it creates a layout view with a new
name. The tool then performs connectivity analysis to determine the pins and connectivity
information and generates a design view for each block.
Caution:
GDSII and OASIS files do not provide all of the physical information required to
perform placement and routing. At a minimum, you must specify the block type
and site definition for the blocks in the GDSII or OASIS file.
The following topics describe how to modify the behavior of the read_gds and
read_oasis commands:
When you load a layer mapping file into the library workspace, it is used by both the
read_gds and read_oasis commands.
In this case, the command loads only those layers specified in the layer mapping file
and ignores all other layers defined in the library source file.
• -ignore_missing_layers
In this case, the command loads only those layers defined in the technology file and
ignores all other layers defined in the library source file.
You can also set these options in the layer mapping file, as described in Layer Mapping
File Syntax. If you specify these options both on the command line and in the layer
mapping file, the settings in the layer mapping file override the command-line settings.
Note:
Use the single-height site definition, which is often named unit, for both single-
height and multiple-height cells. The implementation tool automatically identifies
the polarity of the power and ground pins and places the single-height and the
multiple-height cells accordingly.
To report the site definitions in the technology data, use the report_site_defs command.
Defining the Standard Cell Boundaries
The height of a standard cell must be the same as the height of its site definition and the
width must be an integer multiple of the width of its site definition. When you read a GDSII
or OASIS file, the tool determines the boundary for each standard cell. If a boundary layer
is defined, the tool uses it to determine the standard cell boundary. Otherwise, the tool
generates a default boundary.
In some cases, the cell boundary determined by the tool is not correct and you must adjust
it.
• If the boundary for a cell is not specified in the library source file and the cell layout
assumes shared power and ground pins, the default boundary generated by the tool
is incorrect. You must adjust the cell boundary by reducing it to the center line of the
pin geometries. Figure 6 shows the default and adjusted boundaries for a standard cell
with shared power and ground pins.
Figure 6 Boundary for Standard Cell With Shared Power and Ground Pins
• If the boundary for a cell is defined incorrectly in the library source file, manually specify
the boundary by using the set_attribute command to modify the bbox attribute of
the library cell. For example, the script shown in Example 1 reduces the boundary for a
set of library cells by 0.115 units on the left side, 0.051 units on the bottom, 0.115 units
on the right side, and 0.109 units on the top.
• To specify the pin name mapping using an application option, use the following syntax:
lm_shell> set_app_options -name file.format.port_type_map \
-value { mapping_list }
In either method, each item in the mapping_list argument uses the following format:
"port_type pin_name"
where
• port_type is one of power, gound, pwell, or nwell
In the physical rules file, items in the mapping_list argument are separated by a comma. In
the application option, they are separated by a space.
For example, to set all pins named VDD as power pins and all pins named VSS as ground
pins when reading GDSII files, either
• Include the following statements in the physical rules file:
stream_in_instructions () {
type : gds;
port_type_map("power VDD", "ground VSS");
}
See Also
• Physical Rules File Syntax
Completing the Information for I/O Cells
GDSII and OASIS files contain only cell geometry information; therefore, if you load the
physical data by reading a GDSII or OASIS file, you must specify additional physical
information that is required for placement and routing.
I/O cells must have the following attributes to identify their physical characteristics:
• design_type library cell attribute
This attribute specifies the I/O cell type. I/O cells must have one of the following
settings for the design_type attribute: corner, pad, pad_spacer, flip_chip_driver,
or flip_chip_pad.
Use one of the following methods to set this attribute:
◦ Use the cell_type statement in the cell group in the physical rules file
◦ Use the set_attribute command
This attribute specifies the orientation for proper placement of the I/O cell in the bottom
I/O guide. Modify this attribute to correct any I/O orientation issues.
• class terminal attribute
This attribute specifies the I/O pin type and is required for the flip-chip flow. Valid values
for the class attribute are bump, core, and none.
Editing Layout Views Before Performing Connectivity Analysis
In some cases, you might need to edit the layout views before performing connectivity
analysis. To do this,
1. Read the library source files without performing connectivity analysis by using the
-trace_option none option when you run the read_gds or read_oasis command.
Tracing method Cell types for which this is the de- -trace_option -layer Key-
fault tracing method Keyword word
Create terminal shapes only for Modules, macro cells, analog cells, pins_only pins_only
shapes that overlap pin text. and black box cells
Tracing method Cell types for which this is the de- -trace_option -layer Key-
fault tracing method Keyword word
Trace the connectivity only on the Library cells, pad cells, corner cells, same_layer same
same layer as the pin text. pad spacer cells, cover cells, flip-
chip pads, flip-chip drivers, physical-
only cells, well tap cells, end cap
cells, diode cells, filler cells, and
metal fill
• To specify the text layer mapping using application options, use the following syntax:
lm_shell> set_app_options \
-name file.format.text_layer_map -value { mapping_list }
lm_shell> set_app_options \
-name file.format.use_only_mapped_text -value true | false}
where
• metal_layer and text_layer are the layer names in the technology file
• data_type, which is optional, is the data type number in the technology file
2
1. To reduce runtime, limit the number of geometries traced by setting the -trace_connectivity_limit option
or enable all-layer tracing only for specific pins by using the -trace_all_layers_for option.
In the physical rules file, items in the mapping_list argument are separated by a comma. In
the application option, they are separated by a space.
For example, to map the M1PIN text layer to the M1 metal layer and the M2PIN text layer
to the M2 metal layer when reading GDSII files, either
• Include the following statements in the physical rules file:
stream_in_instructions () {
type : gds;
text_layer_map ("M1 M1PIN", "M2 M2PIN");
}
See Also
• Physical Rules File Syntax
Mapping Exclude Layers
If the GDSII or OASIS file contains layers that are used as exclude layers, which define
geometries to remove from metal layers during connectivity tracing, you must map the
exclude layers to the metal layers.
You can specify the exclude layer mapping either in the physical rules file or by setting an
application option.
• To specify the exclude layer mapping in the physical rules file, use the following syntax:
stream_in_instructions () {
type : gds | oasis | both;
exclude_layers("mapping_list");
}
• To specify the exclude layer mapping using application options, use the following
syntax:
lm_shell> set_app_options -name file.format.exclude_layers \
-value {mapping_list}
where
• metal_layer and exclude_layer are the layer names in the technology file
• exclude_purpose, which is optional, is the purpose number in the technology file
• mask_type is the mask constraint of the geometries
Valid values are mask_one, mask_two, and mask_three.
In the physical rules file, items in the mapping_list argument are separated by a comma. In
the application option, they are separated by a space.
For example, to subtract the mask_one geometries on the EM1 layer from the mask_one
geometries on the M1 layer and the geometries on the EM2 layer from the geometries of
the same mask type on the M2 layer when reading GDSII files, either
• Include the following statements in the physical rules file:
stream_in_instructions () {
type : gds;
exclude_layers ("M1 EM1:mask_one", "M2 EM2");
}
See Also
• Physical Rules File Syntax
Layer Mapping File Syntax
The syntax used to specify the layer mapping in the layer mapping file is
[object_type] tf_layer[:tf_purpose][:use_type]
[:mask_type] stream_layer[:stream_data_type]
where
• object_type specifies the types of objects to which the mapping applies
Valid values are data (all non-text objects), text, and all. The default is all.
• tf_layer is the layer number in the technology file, which is a required argument
• tf_purpose is the purpose number in the technology file
Valid values are either an integer value or the drawing keyword.
• use_type is the usage of the geometries in the design
Valid values are power, ground, signal, clock, boundary,
hard_placement_blockage, soft_placement_blockage, routing_blockage, and
area_fill.
• stream_layer is the layer number in the GDSII or OASIS file, which is a required
argument
• stream_data_type is the data type in the GDSII or OASIS file
To include comment lines in the layer mapping file, start the line with a semicolon (;).
The layer mapping file also supports the following optional statements to further control
how the read_gds or read_oasis command loads the library source files:
read_always true|false [-mapped_only] [-ignore_missing_layers]
blockage_as_zero_spacing true|false
cell_prop_attribute attribute_value
net_prop_attribute attribute_value
pin_prop_attribute attribute_value
Table 5 describes how these statements affect the behavior of the read_gds and
read_oasis commands. You can also specify most of these settings on the command line.
If you set an option both on the command line and in the layer mapping file, the setting in
the layer mapping file takes precedence.
read_always true -read_always true The command loads all layers defined
in the library source file. If the library
source file contains layers that are
not defined in the technology file, the
command creates new layers.
This is the default behavior.
read_always false -read_always false The command loads only those layers
-mapped_only -mapped_layers_only specified in the layer mapping file and
ignores all other layers defined in the
library source file.
read_always false -read_always false The command loads only those layers
-ignore_missing_layers -ignore_missing_layers defined in the technology file and
ignores all other layers defined in the
library source file.
The following example shows a layer mapping file. The comments describe how the
statements affect the behavior of the read_gds and read_oasis commands.
; Map GDSII or OASIS layer 10 with data type 2 to power net shapes
; on technology file layer 56 with a purpose of 4
data 56:4:power 10:2
When you load frame views into the library workspace, the library manager verifies that
they are consistent with any existing frame views in the library workspace and issues a
warning message if it finds inconsistencies.
Each time you run the command, you can specify only a single library; to load multiple
libraries, you must run the command multiple times. You cannot use this command to load
aggregate libraries.
You can specify the library path with an absolute path, a relative path, or no path. If you
use a relative path or no path, the library manager uses the search path to find the library.
For example, to load the physical data for blocks with the empty label from the myblock
design library into the current library workspace, use the following command:
lm_shell> read_ndm myblock
To load the physical data for blocks with a label of mylabel from the myblock design library
into the current library workspace, use the following command:
lm_shell> read_ndm -label mylabel myblock
Note:
The generated library does not contain labels, regardless of the options used
with the read_ndm command.
When you load frame views from a design library, the library manager verifies that the
frame views in the design library are consistent with any existing frame views in the library
workspace and issues a warning message if it finds inconsistencies.
Each time you run the command, you can specify only a single library; to load multiple
libraries, you must run the command multiple times.
You can specify the library with an absolute path, a relative path, or no path. If you use a
relative path or no path, the library manager uses the search path to find the library.
The IC Compiler tool writes out a set of files into a new directory named icc2_frame.
The generated files include the technology files and a tar file that contains the FRAM
views converted to LEF format.
2. In the Library Manager tool, create a library workspace by using the
create_workspace -flow frame command.
For example, to create a library workspace using the technology data exported from
the IC Compiler tool for the my_reflib reference library, use the following command:
3. Import the converted FRAM views generated by the IC Compiler tool into the library
workspace by using the import_icc_fram command.
For example, to import the converted FRAM views exported from the IC Compiler tool
for the my_reflib reference library, use the following command:
lm_shell> import_icc_fram \
/path/icc2_frame/data/LEF/my_reflib.tar.gz
Note:
You cannot mix imported Milkyway FRAM data with other physical data,
such as LEF, GDSII, or OASIS data. If you use imported Milkyway FRAM
data, all physical data in the library workspace must come from imported
Milkyway FRAM data.
4. Validate the workspace, as described in Validating the Workspace.
5. Commit the workspace, as described in Committing the Workspace.
See Also
• Building Cell Libraries
• Loading Physical Data from an Existing Library
• Add the block with a new name by using the -merge_action add option, which is the
default
• Specify the handling for specific blocks in a block mapping file by using the
-block_map file_name option
The settings in the block mapping file override the -merge_action setting. For
information about the block mapping file syntax, see Block Mapping File Syntax.
Note:
The read_lef command supports only the block_name and rw_type
arguments; it ignores all other arguments.
The arguments are defined as follows:
• block_name is the name of the block, which is required
You can use regular expressions to specify the block names; the read_lef, read_gds,
and read_oasis commands use glob-style pattern matching to identify the blocks.
When you use a block mapping file with the read_gds or read_oasis command, any
blocks that do not match a pattern in the block mapping file are loaded into the library
workspace as standard cells.
• rw_type specifies how to load the block into the library workspace
This argument overrides the default behavior specified by the -trace_option option
of the read_gds or read_oasis command for the specified blocks. Valid values for this
argument are
◦ add
Does not create a physical representation for the block. The read_gds and
read_oasis commands ignore this setting if the block is a subblock of a
hierarchical block.
◦ overwrite
Updates the existing physical representation for the block by merging the new data
with the existing data.
◦ retain
Keeps the instance but does not create the reference library cell.
◦ flatten (supported only by the read_gds and read_oasis commands)
If you do not specify this argument, the read_gds and read_oasis commands use a
type of lib_cell.
Note:
You can also specify the block type for a library cell by using the cell_type
statement in the cell group in the physical rules file or by using the
set_attribute command to set its design_type attribute
For more information about setting block types, see Specifying the Block Types When
Reading GDSII or OASIS Files.
• -fixed_mask sets the is_mask_shiftable attribute for the block to false
Each standard cell in a library source file must be associated with a site definition. Use
this option to override the default site definition for a specific cell.
Note:
You can also specify the site definition for a library cell by using the site
statement in the cell group in the physical rules file or by using the
set_attribute command to set its site_name attribute
For more information about setting site definitions, see Specifying the Site Definitions
When Reading GDSII or OASIS Files.
• -centerline_boundary shrinks the default boundary to the center line of the pin
geometries for the block
This argument overrides the -centerline_boundary option of the read_gds or
read_oasis command for the specified blocks.
For more information about adjusting the block boundary, see Defining the Standard
Cell Boundaries.
To include comment lines in the block mapping file, start the line with a semicolon (;).
The following example shows a block mapping file. The comments describe how the
statements affect the behavior of the read_gds and read_oasis commands.
; Flatten all blocks with MEM in their name two levels deep
*MEM*:flatten:2
; Ignore the rest of the blocks, they will be loaded only when they
; happen to be in a *CORE* block’s hierarchy
*:ignore
library (library_name) {
distance_unit : 1um | 1mm;
length_precision : 1 | 10 | 100 | 1000 | 10000;
unit_site_width : float;
stream_in_instructions () {
type : gds | oasis | both;
exclude_layers("mapping_list");
port_type_map("mapping_list");
text_layer_map("mapping_list");
trace_copy_overlap_shape_from_sub_cell : true | false;
trace_terminal_length : float;
trace_terminal_type : pg | signal | all;
trace_unmapped_text : true | false;
use_only_mapped_text : true | false;
}
site (site_name) {
width : float;
height : float;
type : core | pad;
symmetry ("list_of_symmetries");
is_default: true | false;
}
layer(layer_name) {
routing_direction: unknown | horizontal | vertical |
diagonal_45 | diagonal_135)
number_of_masks: 0 | 1 | 2 | 3 | 4;
}
placement_rules (group_name) {
forbidden_horizontal_site_spacing(label1, label2, min, max);
forbidden_vertical_abutment_pairs(label1, "label1_1,
label1_2, ...");
cell (cell_name) {
allowable_orientation : ("list_of_orientations");
cell_type : type;
is_mask_shiftable : true | false;
site : site_name;
horizontal_spacing_labels ("left_label, right_label", ...);
vertical_abutment_labels_top ("label_t1, label_t2, ...");
vertical_abutment_labels_bottom ("label_b1, label_b2, ...");
shape ( ) {
shape_use : detail_route;
layer_name : layer_name;
rectangle("llx, lly", "urx, ury");
polygon ("x1, y1", "x2, y2", …, "xn, yn");
}
pin (pin_name) {
direction : inout | input | internal | output;
port_type : signal | tie_high | tie_low | clock | reset |
analog_signal | scan | power | ground | analog_power |
analog_ground | nwell | pwell | deep_nwell | deep_pwell;
pg_type : primary | backup | internal;
is_secondary_pg : true | false;
connect_within_pin : none | via | via_wire;
is_diode : true | false;
is_em_via_ladder_required : true | false;
must_join_group("layer_name1, layer_name2...", group_name);
must_join_pin : pin_name;
pattern_must_join : true | false;
terminal ( ) {
layer_name : layer_name;
rectangle("llx, lly", "urx, ury");
polygon ("x1, y1", "x2, y2", ..., "xn, yn");
}
distance_unit
The distance_unit statement defines the linear distance unit. Valid values
are 1um or 1mm. The value must correlate with the value specified for the
unitLengthName attribute in the technology file.
length_precision
The length_precision statement specifies the number of database units
per distance unit, thereby defining the precision of distance measurements
stored in the database. Valid values are 1, 10, 100, 1000, and 10000. For
example, if you set distance_unit to 1um and length_precision to 1000, the
database unit is 0.001 micron. Thus, all distance measurements are rounded
to the nearest 0.001 micron. The value must match the value specified for the
lengthPrecision attribute in the technology file.
unit_site_width
The unit_site_width statement specifies the placement site width. This value
is used by the horizontal cell spacing rule. If you specify horizontal cell spacing
rules but do not specify this attribute, the legalizer determines the placement site
width.
stream_in_instructions
The stream_in_instructions group specifies how to process the
information when loading GDSII or OASIS files. You can have at most two
stream_in_instructions groups, one for GDSII (type : gds) and one for
OASIS (type : oasis). The following table describes the statements available
in the stream_in_instructions group.
Statement Description
exclude_layers Specifies the rules for mapping between metal layers and the
layers that are used to exclude geometries from the specified
layers.
For more information about this statement, see Mapping
Exclude Layers.
port_type_map Identifies the power and ground pins by mapping the pin name
to its type. The mapping applies to all cells in the library source
file.
For more information about this statement, see Identifying
Power and Ground Pins.
Statement Description
text_layer_map Maps the text layers to the metal layers so that the tool can
associate metal shapes with a net or pin when the text is not on
the same layer as the metal shapes.
For more information about this statement, see Mapping Text
Layers.
trace_terminal_length Controls whether the commands split long pins on the block
boundary into a terminal and a net shape.
By default (0), the commands do not split long pins.
When set to a positive integer, the commands split pins that are
longer than the specified value. After splitting, the new terminal
is the specified length; the rest of the pin is converted to a net
shape.
trace_terminal_type Specifies the types of long pins that are considered for splitting.
By default, both PG and signal pins are considered.
trace_unmapped_text Controls whether the commands trace all routing layers for text
that is not mapped to any routing layer.
use_only_mapped_text Controls whether the commands use only the text specified by
the text_layer_map statement when tracing ports.
site
The site group defines a new site definition or modifies an existing site
definition. A physical rules file can contain multiple site groups. Each group
must have a unique name. If the site group name matches an existing site
definition in the library, the tool updates the existing definition. Otherwise, it
creates a new definition. To create a new definition, you must specify at least the
height and width statements.
The following table describes the statements available in the site group.
Name of the site group name Specifies the name of the site definition.
layer
The layer group specifies layer-specific information. The following table
describes the layer attributes you can specify in the physical rules file. The
group’s name must match an existing layer name in the technology data of the
library.
placement_rules
The placement_rules group specifies a placement rule for the library. A
physical rules file can contain multiple placement_rules groups. Each group
must have a unique name.
You can specify the following types of placement rules in the physical rules file:
• Horizontal cell spacing rule
The forbidden_horizontal_site_spacing statement defines a horizontal
spacing rule. You can specify multiple horizontal spacing rules. Each rule is
identified by a unique label. The rules are assigned to specific cells by setting
the horizontal_spacing_labels attribute in the cell group. For detailed
information, see Horizontal Cell Spacing Rule.
• Vertical pin abutment rule
The forbidden_vertical_abutment_pairs statement defines a vertical
abutment rule. You can specify multiple vertical abutment rules. Each rule is
identified by a unique label. The rules are assigned to specific cells by setting
the vertical_abutment_labels attribute in the cell group. For detailed
information, see Vertical Abutment Rule.
cell
The cell group specifies cell-specific information, including library cell
attributes, cell-specific settings for placement rules, and library pin attributes.
The following topics describe specific attributes and geometries in the physical
rules file syntax:
• Library Cell Attributes
• Routing Shape Geometries
• Library Pin Attributes
• Pin Terminal Geometries
You must specify the labels as left-right pairs. If you specify only one pair, the labels
apply to all rows. Otherwise, you must specify the label pairs for all rows, starting with
the bottom row in R0 orientation.
If there is no horizontal spacing requirement on a side, specify NONE as the label. You
can assign multiple labels to a library cell.
For example, to assign a label named X to the right side of the cellA library cell and the
left side of the cellB and cellC library cells and a label named Y to the right side of the
cellC library cell, use the following statements:
cell (cellA) {
horizontal_spacing_labels (NONE, X);
}
cell (cellB) {
horizontal_spacing_labels (X, NONE);
}
cell (cellC) {
horizontal_spacing_labels (X, Y);
}
The following statement specifies that there must be at least one placement site
between X labels and any boundary:
placement_rules (group1) {
forbidden_horizontal_site_spacing(X, SNPS_BOUNDARY, 0, 0);
}
The following statement specifies that two X labels cannot have a spacing of two
placement sites:
placement_rules (group1) {
forbidden_horizontal_site_spacing(X, X, 2, 2);
}
The following statement specifies that labels X and Z must have a spacing of less than
two placement sites or more than four placement sites:
placement_rules (group1) {
forbidden_horizontal_site_spacing(X, Z, 2, 4);
}
See Also
• Defining Cell Spacing Constraints for Legalization
For example, the following statement specifies that sites with label 1 cannot abut sites
with label 1 or 2:
placement_rules (rule2) {
forbidden_vertical_abutment_pairs (1, "1, 2");
}
The following statement specifies that sites with label 2 cannot abut sites with label 2:
placement_rules (rule2) {
forbidden_vertical_abutment_pairs (2, "2");
}
2. Add label patterns to the library cells that have abutment constraints by using the
vertical_abutment_labels_top and vertical_abutment_labels_bottom
statements in the affected cell groups. These statements have the following syntax:
vertical_abutment_labels_top ("label_t1, label_t2, ...");
vertical_abutment_labels_bottom ("label_b1, label_b2, ...");
The number of labels in the pattern depends on the cell width in placement sites. For
example, if a cell is three placement sites wide, the pattern includes three labels. You
can specify multiple patterns for a cell by specifying the statements multiple times.
For example, to assign a pattern of 2 2 0 to the top and bottom of the cellA library cell,
a pattern of 0 0 0 to the top of the cellB library cell, and a pattern of 0 1 1 to the bottom
of the cellB library cell, use the following statements:
placement_rules (rule2) {
forbidden_vertical_abutment_pairs (1, "1, 2");
forbidden_vertical_abutment_pairs (2, "2");
}
...
cell (cellA) {
Figure 7 shows some illegal and legal abutments between the cellA and cellB library cells
based on this definition.
0 0 0 0 0 0 0 0 0
0 1 1 0 1 1 0 1 1
2 2 0 2 2 0 2 2 0
2 2 0 2 2 0 2 2 0
Illegal abutment Illegal abutment Legal abutment
By default, the read_physical_rules command reads the library-level rules and the
cell- and pin-level rules and attributes. You should load this information after loading the
physical data. To control the content loaded by the read_physical_rules command, use
the -include option, which takes one or more of the following values:
• all
Loads only the cell- and pin-level rules and attributes from the physical rules file.
• instructions
Loads only the stream-in instructions from the physical rules file. You must load this
information before reading GDSII or OASIS files.
• layer
Loads only the layer attributes from the physical rules file.
• library
Loads only the library-level rules from the physical rules file.
• pin_attr
Loads only the placement rules from the physical rules file.
• site
Loads only the site definitions from the physical rules file.
To write the library information from the library workspace into a physical rules file, use the
write_physical_rules command. See Writing the Physical Rules File.
• all
Writes only the cell- and pin-level rules and attributes into the physical rules file.
• instructions
Writes only the stream-in instructions into the physical rules file.
• layer
Writes only the layer attributes into the physical rules file.
• library
Writes only the library-level rules into the physical rules file.
• pin_attr
Writes the direction, port_type, pg_type, and is_secondary_pg pin attributes into
the physical rules file.
• placement_rule
Writes only the placement rules into the physical rules file.
• routing_blockage
Writes only the routing blockage rules into the physical rules file.
• shape
Writes only the routing shapes into the physical rules file.
• site
Writes only the site definitions into the physical rules file.
• terminal
Make sure that the version of the IC Validator executable that you specify is compatible
with the Library Manager version that you are using.
For more information about the IC Validator tool, see the IC Validator documentation,
which is available on SolvNet.
• Set the signoff.antenna.enabled application option to true.
• Set signoff.antenna application options to control the extraction behavior.
For a summary of these options, see Antenna Extraction Application Options.
...Checked? No
...DB/Liberty files:
1. /usr/LIBRARIES/DB/my_ff0p95v125c.db
2. /usr/LIBRARIES/DB/my_ff0p95vn40c.db
3. /usr/LIBRARIES/DB/my_ff1p16v125c.db
4. /usr/LIBRARIES/DB/my_ff1p16vn40c.db
Note:
This step is not required when creating a technology-only library. No checks are
performed when you run this command for a library workspace that contains
only technology data.
In addition to validating the workspace, the check_workspace command performs the
following tasks:
• Generates frame views for the physical cells in the workspace
For information about generating frame views, see Generating Frame Views.
• Sets the is_secondary_pg attribute for PG pins
For information about the secondary PG settings, see Identifying Secondary PG Pins.
• (Optional) Extracts the antenna properties
For information about extracting antenna properties, see Automatic Antenna Property
Extraction Using the IC Validator Tool.
When you run the check_workspace command, the tool performs the checks described in
the following topics:
• Library Checks (includes checks for unique characterization points)
• Cell Checks (includes checks for missing cells, differences in logic function, and
differences in the cell attributes)
• Pin Checks (includes checks for missing pins, and differences in the pin direction, type,
and order)
• PG Rail Checks (includes checks for differences in the number, names, and order)
• Timing Arc Checks (includes checks for missing arcs, incorrect arcs, and differences in
breakpoints)
• Leakage-Power Checks (includes checks for missing leakage-power information and
differences in power conditions)
In many cases, the library manager can automatically fix the issues detected by these
checks.
Note:
The checks performed by the check_workspace command validate the
consistency of the library source files loaded into the workspace; however,
the workspace might not contain all of the information required to perform
placement and routing.
To generate a cell library from a library workspace, the workspace must pass these
checks. However, in some cases you can generate a cell library using incomplete or
inconsistent source libraries by defining a mismatch configuration, as described in
Allowing Incomplete or Inconsistent Library Data. Cell libraries created with a nondefault
mismatch configuration are not valid for implementation and can be used only for preroute
feasibility analysis; these types of libraries are referred to as prototype libraries.
You can view the messages issued by the check_workspace command in the message
browser, as described in Using the Message Browser Window.
To generate more detailed messages during the validation, use the -details option
with the check_workspace command to specify one or more of the following categories:
arcs_progress, breakpoint_comparisons, combine_physical, leakage_progress,
physical_only_cells, or all.
Note:
Using the -details option can result in a very large log file. In general, you
should run the check_workspace command with the -details option only to
debug a specific issue.
Library Checks
The check_workspace command performs the following library checks:
• At least one physical library source file is loaded into the library workspace
• Each library logic loaded into the workspace has a unique characterization point
(process, voltage, and temperature).
The workspace must pass these checks before it can be committed.
PG Rail Checks
This topic describes the PG rail checks for logic libraries that use the PG-pin syntax. For
information about PG rail checks for older logic libraries that do not use the PG-pin syntax,
see Using Non-PG Logic Libraries.
Note:
You cannot mix logic libraries with and without PG-pin syntax in a library
workspace.
Logic libraries that use the PG-pin syntax define the PG pin connections by using library-
level voltage_map attributes and cell-level pg_pin groups. The voltage_map attributes
define the power rail names. The pg_pin groups define the PG pin connections for a cell;
they use the voltage_name attribute to assign one of the defined power rails to each
PG pin. The signal pins of a cell are associated with the PG rails by using the pin-level
related_power_pin and related_ground_pin attributes. Example 4 shows the use of
these attributes to define the power connections in a .lib logic library file.
The check_workspace command verifies that each logic library has the same number of
rails and that the rails have the same names and types. However, the tool ignores rails
that are defined in a voltage_map attribute but not used.
If the rail order differs, the tool automatically updates the order using the information from
the base library.
By default, if a rail name differs between the logic libraries, the tool issues an LM-043
error. If the mismatch is caused only by rail names and positions, and not rail type
differences, you can use the rename_rail command to make the rail names match. For
example, assume logic library A has a voltage_map setting of (VDD1.0, 1.0) and logic
library B has a voltage_map setting of (VDD1.1, 1.1). You could use the rename_rail
command to align these rails, as shown in the following example:
lm_shell> rename_rail -library A -from VDD1.0 -to VDD
lm_shell> rename_rail -library B -from VDD1.1 -to VDD
Cell Checks
To learn about the cell checks performed by the check_workspace commands, see the
following topics:
• Missing Cell Checks
• Logic Function Check
• Cell Attribute Checks
Missing Cell Checks
The check_workspace command checks for the following types of missing cells:
• A cell that exists in some, but not all logic libraries, and you are using the normal flow
The tool issues an error message if it finds missing or extra cells in a logic library, as
compared to the set of cells in the base library.
Note:
The cell name checks are case-sensitive. You can create a prototype library
using case-insensitive checks by defining a mismatch configuration, as
described in Allowing Incomplete or Inconsistent Library Data.
To create a cell library, you must do one of the following:
◦ Manually fix the source libraries and then rerun the check_workspace command
◦ Rerun the check_workspace command with the -allow_missing option to enable
the tool to add the missing cells to the generated cell library
The generated cell library will contain all cells that exist in at least one logic
library; if a cell does not exist in a logic library, it will have missing data in the pane
associated with that logic library.
• A cell that exists in the logic libraries, but does not have physical data
If a cell exists in the logic libraries, but does not have any physical data, the tool issues
an error message and you cannot commit the workspace.
To create a cell library, you must either
◦ Set the lib.logic_model.auto_remove_timing_only_designs application option
to true to automatically remove the cells from the workspace
◦ Manually remove the cells from the workspace by using the remove_lib_cell
command
◦ Update the library source files
To create a prototype library that includes placeholder cells for the missing physical
cells, define a mismatch configuration, as described in Allowing Incomplete or
Inconsistent Library Data.
• A physical cell that is not in the logic libraries
If a physical cell is not in any logic library, the tool behavior depends on the flow you
selected.
◦ For the normal flow, the cell is not included in the generated cell library.
◦ For the physical-only flow, the cell is included in the generated cell library.
For detailed information about physical-only cells detected during workspace validation,
specify the physical_only_cells keyword with the -details option.
By default, if a cell with the same name in different logic libraries has different values
for any of these attributes, the tool issues a warning message and stores the attribute
value from the base library in the cell library. You can resolve conflicts by using the
set_attribute command to change the attribute values.
To require a cell to have the same value for these attributes in all logic libraries, set the
lib.logic_model.require_same_opt_attrs application option to true.
Pin Checks
To learn about the pin checks performed by the check_workspace commands, see the
following topics:
• Missing Pin Checks
• Pin Definition Checks
Missing Pin Checks
The check_workspace command compares the pins defined for a cell in each logic and
physical library source file against the pins defined for the cell in the base library. If a cell in
the workspace is missing one or more pins as compared to the base library, the tool issues
an error message.
Note:
The pin name checks are case-sensitive. You can create a prototype library
using case-insensitive checks by defining a mismatch configuration, as
described in Allowing Incomplete or Inconsistent Library Data.
To generate a cell library, you must manually fix the following issues:
◦ A pin is defined as a signal pin in all logic libraries, but the bit_width, is_pad,
is_diode, or is_scan attribute setting differs
To fix this issue, you can use the set_attribute command to change the attribute
values.
◦ A pin is defined as a signal pin in one logic library, but is defined as a PG pin in
another logic library
If a pin is incorrectly defined as a signal pin and is not used in the logic function
definition, you can fix this issue by using the set_attribute command to change
the port_type attribute of the pin.
Note:
Changing a pin from a signal pin to a PG pin might cause the tool to
remove timing arcs for that pin.
You can use the set_attribute command only to change a signal pin to
a PG pin; you cannot change a PG pin to a signal pin.
◦ A pin is defined as a PG pin in all logic libraries, but the pg_type attribute differs
To fix this issue, you can use the set_attribute command to change the pg_type
attribute of the pin.
To create a prototype library that uses the pin type from the base library in the case of
mismatches, define a mismatch configuration, as described in Allowing Incomplete or
Inconsistent Library Data.
Note:
The mismatch configuration can only change a signal pin to a PG pin; it
cannot change a PG pin to a signal pin.
• PG pin connection
If the rail name specified for the voltage_name attribute in a pg_pin group is not
defined in a library-level voltage_map attribute or the voltage_name attribute for a PG
pin differs between libraries, the tool issues an error message. To fix this error, you can
use the set_attribute command to change the rail_name attribute. To see the rail
names defined for a library workspace, use the report_workspace -panes command.
• Related PG pin
Signal pins have a related power pin and a related ground pin; power pins can have a
related bias pin. Typically, these relationships are defined in the logic libraries.
If the logic libraries do not define these relationships, either because they do not define
the PG pins (and the PG pins are inherited from the physical library source file) or they
define the PG pins, but not the relationships, the check_workspace command tries to
derive these relationships as follows:
◦ If a cell has a single power pin and a single ground pin, the tool automatically
derives the related PG pin information.
◦ If a cell has multiple power pins, you must guide the tool to derive the related PG
pin information.
To guide the tool, use the set_attribute command to set the
related_power_pin_hint and related_ground_pin_hint attributes on the pins
with the missing information.
lm_shell> set_attribute [get_lib_pins lib/cell/pin] \
related_power_pin_hint PGpin_name
If the related PG pin information for a pin exists but is incorrect, you can correct
it by using the set_attribute command to set the related_power_pin_name,
related_ground_pin_name, or related_bias_pin_name attribute. For example,
lm_shell> set_attribute [get_lib_pins lib/cell/pin] \
related_power_pin_name PGpin_name
Note:
By default, the check_workspace command ignores missing power
and ground relationships during the workspace validation, which
might affect analysis performed by the implementation tool. To require
signal pins to have at least one related power or ground pin, set the
lib.workspace.allow_missing_related_pg_pins application option to
false before running the check_workspace command.
• Pin order
For each cell, the tool determines the pin order in each logic and physical library source
file that contains the cell, and verifies that it is the same in each library.
In a logic library, the tool determines the pin order from the logic function, followed by
other non-signal pins, such as internal pins, power pins, ground pins, p-well pins, and
n-well pins. In a physical library source file, the pin order is determined by the order in
which they are specified.
Note:
Although the tool can resolve many pin ordering issues, these issues might
be caused by out-of-date libraries. If the tool reports pin ordering issues, you
should verify that you are using the correct set of libraries before continuing.
If the pin order differs between a logic library and the base library, the result depends
on whether the mismatched pins contribute to the logic function.
◦ If so, the tool issues an error message and does not load the affected cell. You must
manually correct this problem to continue with library preparation.
◦ If not, the tool reorders the pins to match the order in the base library.
If the pin order differs between a physical library source file and the base library, the
tool automatically updates the pin order using the information from the base library.
The breakpoints for complimentary attributes must be functions of the same variables,
such as input_net_transition (Tinp) and total_output_net_capacitance (Cout).
However, if one of the attributes is defined as a function of both variables, but the other
is defined as a function of only one variable, the tool can resolve this difference.
The tool can also resolve differences in the complementary attributes for setup or hold
when one attribute is defined as a function of constrained_pin_transition (Tdat)
and the other is defined as a function of related_pin_transition (Tclk).
In the messages, the tool represents a timing arc using the following format:
cell from_pin to_pin [related_pin] sense [object_name] [{w:when_cond}]
[MIN] [{m:modes}] [DUPn]
The cell, from pin, to pin, and arc sense are always specified. The other fields are reported
only when relevant. The related pin is reported only when the delay table is dependent
on a related capacitance. If the library specifies a name for the timing group, that name
is reported in the object_name field. The when_cond field is reported for state-dependent
timing arcs and conditional timing checks. The MIN keyword indicates a minimum delay arc
and the DUP keyword indicates a duplicate arc.
For example, a negative-unate timing arc from pin A to pin Z on the NAND3 cell is
represented as “NAND3 A Z negative_unate”.
To pass workspace validation, you must either fix the errors, provide guidance to the tool
about how to handle them, or remove the cell with mismatched timing arcs from all logic
libraries.
If the tool finds missing or extra timing arcs for a cell in a logic library, as compared to
those in the base library, it issues a warning.
To add arcs that are not defined in the base library, but are defined in another logic library,
rerun the check_workspace command with the -allow_missing option. The arcs are
added only if the nodes in the timing graph are the same as in the base library.
Note:
If you choose to override these errors with the -allow_missing option, the cell
library will have missing data for the cell in some panes.
To remove cells with mismatched timing arcs from the logic libraries, use the
remove_lib_cell command. You must remove the cell from all logic libraries; otherwise,
this results in a missing cell error, which is described in Missing Cell Checks.
For detailed messages during the timing arc checks, specify the arcs_progress keyword
with the -details option. For detailed messages during the breakpoint comparisons,
specify the breakpoint_comparisons keyword with the -details option.
Note:
Using the -details option can result in a very large log file. In general, you
should run the check_workspace command with the -details option only to
debug a specific issue.
Leakage-Power Checks
For each cell with the same name in different logic libraries, the check_workspace
command verifies that it has the same leakage-power information, as defined in the
cell_leakage_power attribute and the leakage_power group.
If the tool finds missing or extra leakage-power information for a cell in a logic library, as
compared to those in the base library, it issues a warning. To get detailed information
about the missing leakage-power information, use the -details leakage_progress
option when you run the check_workspace command. In the messages, the tool
represents leakage-power information using the following format:
cell [related_power_pin] [{w:when_condition}]
To add leakage-power information that is not defined in the base library, but is defined in
another logic library, rerun the check_workspace command with the -allow_missing
option.
Note:
If you choose to override this error with the -allow_missing option, the cell
library will have missing data for the cell in some panes.
If the when statement in the leakage_power group is not identical between logic libraries,
the tool checks the logic equivalence of the conditions.
If the conditions are logically equivalent, the tool uses the condition from the base library.
If the conditions are not logically equivalent, the tool issues an error message and you
cannot commit the workspace.
Logic library PG pin attribute Cell library cell attribute Cell library pin at-
tribute
This option saves the cell library in the specified directory. For example, to save the cell
library in a directory named mylib.ndm, use the following command:
lm_shell> commit_workspace -output mylib.ndm
The -output option specifies the name of both the library and its root directory.
If you use this option, both the library and its root directory are named dir_name,
including any specified extension. If you do not use this option, the library name
is workspace_name, while its root directory is named workspace_name.ndm. The
following table shows the library and root directory names for the cell library generated
from the mylib workspace with and without the -output option:
• -version version_string
This option saves the cell library using the schema revision for an older tool version. To
see the available version strings, use the report_versions command.
By default, the command fails if the specified cell library already exists. To overwrite an
existing cell library, use the -force option. For example,
lm_shell> commit_workspace -output mylib.ndm
Error: File 'mylib.ndm' already exists (FILE-009)
lm_shell> commit_workspace -force -output mylib.ndm
The views saved in the generated cell library depend on the library preparation flow you
enabled and the settings of the related application options.
• For the normal and ETM library preparation flows, the timing and frame views are
saved
• For the frame-only and physical-only library preparation flows, only the frame views are
saved
• To save the design views, set the lib.workspace.save_design_views application
option to true.
• To save the layout views, set the lib.workspace.save_layout_views application
option to true.
You can have only a single workspace in memory at one time. After you commit a
workspace, it is removed from memory so that you can prepare another cell library.
See Also
• Library Preparation Flows
See Also
• Building Cell Libraries
• Frame View Generation Application Options
Regular blockage is_zero_spacing=false The router treats a regular blockage as real metal
and applies all design rules to the blockage.
Design rule via is_design_rule_blockag- Design rule via blockages are similar to zero-spac-
blockage e=true ing via blockages, but they honor the rules defined
for the via blockage layer in the DesignRule sec-
tions of the technology file.
Figure 8 shows an example design view for a standard cell. This example is used to
illustrate the various controls over blockage generation.
By default, when the library manager generates a frame view for a standard cell, it
preserves the blockages that exist within the cell and does not generate additional
blockages. Figure 9 shows the resulting frame view for the design view shown in Figure 8,
which includes all metal shapes from the design view.
Note:
By default, when you create a frame view for a macro by using the
create_frame command in the implementation tool, the tool trims the metal
shapes and regular blockages that touch a pin, as shown inFigure 9 .
Figure 10 shows the frame view, where the purple region represents the zero-spacing
blockage that replaced the regular blockage. The arrows represent the increased size of
the blockage.
For via blockages, you can convert zero-spacing blockages to design rule blockages on
specific layers by setting the lib.physical_model.design_rule_via_blockage_layers
application option.
To trim the metal shapes and regular blockages for specific layers, set the
lib.physical_model.trim_metal_blockage_around_pin application option. When
you set this option, you can choose to trim only those metal shapes and regular blockages
that touch the pin (touch) or all metal shapes and regular blockages within the minimum
spacing of a pin (all). The syntax to set this application option is
set_app_options
-name lib.physical_model.trim_metal_blockage_around_pin
-value { {layer1 all|touch|none}
{layer2 all|touch|none} ...
{layern all|touch|none} }
Figure 12 shows the resulting zero-spacing blockages when all metal shapes and regular
blockages in the vicinity of the pin are trimmed.
The tool keeps all of the shapes within the halo distance of the cell boundary and does
not create a blockage for this region. The tool creates a zero-spacing routing blockage for
the region deeper than the DRC distance from the cell boundary. The tool keeps all of the
shapes between the halo distance and the DRC distance. It discards the shapes that are
deeper than the DRC distance and replaces them with a large RC metal shape.
If a pin is closer to the cell boundary than the channel distance, it is considered a shallow
pin; otherwise, it is considered a deep pin. If a shallow pin is within the zero-spacing
blockage, the tool cuts a channel to the pin to enable same-layer routing to the pin.
To enable creation of a core blockage, set the lib.physical_model.block_all
application option to one of the following values:
• true
The tool creates a core blockage on all metal layers, including routing layers and base
layers.
• used_layers
The tool creates a core blockage only on metal layers used by the cell.
• top_layer_name
The tool creates a core blockage on the specified metal layer and all metal layers
below it.
• auto
Note:
If you set the halo distance for a layer, the tool creates a core blockage for
that layer, regardless of the setting of the lib.physical_model.block_all
application option.
By default, the DRC distance is derived from the largest fat table spacing value
defined for the layer in the technology file. To specify the DRC distance, set the
lib.physical_model.drc_distances application option. The syntax to set this
application option is
set_app_options
-name lib.physical_model.drc_distances
-value { {layer1 drc_distance1}
{layer2 drc_distance2} ...
{layern drc_distancen} }
By default, the channel distance is the minSpacing value plus the minWidth value
specified for the layer in the technology file. To specify the channel distance, set the
lib.physical_model.pin_channel_distances application option. The syntax to set this
application option is
set_app_options
-name lib.physical_model.pin_channel_distances
-value { {layer1 channel_distance1}
{layer2 channel_distance2} ...
{layern channel_distancen} }
To further reduce the number of shapes kept in the frame view, the tool can
• Merge neighboring shapes if the space between them is less than twice the
minSpacing value plus the minWidth value in the technology file (the merging
threshold)
When you set the lib.physical_model.merge_metal_blockage application option
to true, the tool fills the space between neighboring shapes to create a single larger
shape if the space between them is less than the merging threshold.
For example, if the technology file specifies a minSpacing of 2 and a minWidth of 4 for
a layer, the merging threshold is 2*2 + 4 = 8. Therefore, in Figure 14, the tool merges
the geometries on the left to create the blockage area on the right.
shapes from the frame view. When you set it to core, the tool removes the non-pin
shapes that are completely within the core area.
Creating Zero-Spacing Blockages Around Pins
When you specify a positive halo distance for the core blockage, it can be difficult for the
router to access the pins between the cell boundary and the core blockage because they
can be accessed only from inside the cell. If these pins are not colored or placed off-track
from the top-level design, routing DRC violations can occur.
To improve the accessibility by enabling access from outside the cell, the tool can create
zero-spacing blockages around the pins. To create zero-spacing blockages around the
pins, set the lib.physical_model.create_zero_spacing_blockages_around_pins
application option. The syntax to set this application option is
set_app_options
-name lib.physical_model.create_zero_spacing_blockages_around_pins
-value { {layer1 blockage_width1}
{layer2 blockage_width2} ...
{layern blockage_widthn} }
If a pin is on the cell boundary or within the DRC distance of the cell boundary it is
considered a shallow pin, and the tool does not create a blockage on the boundary
side. Otherwise, the pin is considered a deep pin, and the tool creates a blockage of the
specified width on all sides of the pin, as shown in Figure 15.
The edge_threshold argument defines the threshold for the length of an edge. An edge is
a segment along the contour of a connected non-pin shape whose length is less than or
equal to the specified value, and is not part of a concave corner. All other segments of the
connected non-pin shape are sides. When generating the frame view, the tool trims sides
by pins, but does not trim edges.
The ext_spacing argument defines the width of the zero-spacing blockage on the top,
bottom, right, and left sides of the non-pin shapes. The corner_keepout_spacing argument
defines the width of the blockages at the corners of the non-pin shapes.
For example, the following command creates the zero-spacing blockage shown in
Figure 16.
lm_shell> set_app_options \
-name lib.physical_model.keepout_spacing_for_non_pin_shapes \
-value {M1 {0.55 0.7 0}}
Note:
To use this feature, you must ensure that core blockage creation is disabled for
the affected layers.
via region provides guidance to the router about where to drop a via to make a connection
to prevent DRC violations.
By default, the tool
• Generates via regions for cells with the following design types: library cells, diodes, end
caps, fill cells, filler cells, physical-only cells, and well taps
For all other design types, the tool generates pin access edges and directions, which
guide the router to connect to the pins properly on the same layer.
To generate via regions for all design types, set the
lib.physical_model.enable_via_regions_for_all_design_types application
option to true.
• Requires the router to place the via enclosure inside the pin shape when inserting vias
in the via region
This “within-pin” connection ensures that the router will not introduce any DRC
violations in the lower metal layer of the cell being connected.
In certain situations, such as when a pin is small and the minimum enclosure
around the via is large, the “within-pin” connection is too restrictive. To
allow the router to place the via enclosure outside the pin shape, set the
lib.physical_model.connect_within_pin application option to false. When this
option is false and the router cannot fit the lower-metal enclosure within the pin, it
makes the connection anyway, which causes the lower-metal enclosure to extend
beyond the pin shape. This type of connection is said to “change the pin shape.” In
that case, the router must spend time checking for and fixing lower-metal design rule
violations in the cell, which increases routing runtime.
For large pins, you might want to restrict the connection region to a portion of the pin,
which is referred to as the must-connect area. For information about creating must-
connect areas, see Creating Pin Must-Connect Areas.
• Considers only the default vias and their rotations for all ports
To consider nondefault vias when generating the via regions, specify the contact codes
by setting the lib.physical_model.include_nondefault_via application option.
To specify the contact codes to use for specific ports, set the
lib.physical_model.port_contact_selections application option.
• Does not generate via regions for power and ground ports
To generate via regions for specific power and ground ports, specify the ports by
setting the lib.physical_model.include_routing_pg_ports application option.
See Also
• Updating Via Regions
For example, to associate the spare CB layer with the M2 layer, use the following
command:
lm_shell> set_app_options \
-name lib.physical_model.pin_must_connect_area_layers \
-value { {M2 CB} }
Figure 17 shows the pin shapes on the M2 layer, as well as the must-connect area defined
on a spare layer (the CB layer). Figure 18 shows the resulting frame view, with the zero-
spacing blockages shown in purple.
For example, to specify a width threshold of 0.135 microns for the M2 layer, use the
following command:
lm_shell> set_app_options \
-name lib.physical_model.pin_must_connect_area_thresholds \
-value { {M2 0.135} }
Figure 19 shows the resulting frame view, with the zero-spacing blockages shown in
purple.
By default, frame view generation does not consider must-join pins. If you require
that pins with multiple terminals on a layer be routed as must-join pins, set the
lib.physical_model.derive_pattern_must_join application option to one of the
following values:
• true
Sets the pattern_must_join attribute to true on all pins with multiple terminals on the
layer that meet one of the following criteria:
◦ The port_type attribute of the pin is not set to one of the following power-related
values: power, ground, nwell, pwell, deep_nwell, or deep_pwell.
◦ The port_type attribute is set to one of the power-related values and the
is_secondary_pg attribute is set to true.
◦ The port_type attribute is set to one of the power-related values and the pin is
specified in the lib.physical_model.include_routing_pg_ports application
option.
• exclude_pg
Sets the pattern_must_join attribute to true on all pins with multiple terminals on the
layer whose port_type attribute is not set to one of the following power-related values:
power, ground, nwell, pwell, deep_nwell, or deep_pwell.
Use color-based frame view generation only when the technology file contains double-
patterning rules.
When color-based frame view generation is enabled, the tool represents the RC metal of
each metal layer as color one shapes that are trimmed by both the colored and uncolored
shapes with the maximum spacing specified in the technology file.
For example, Figure 20 shows the design view for a colored cell. Figure 21 shows the
frame view generated for the block without the color-based flow. Figure 22 shows the
frame view generated for the block with the color-based flow.
You can use either of the following methods to validate and commit the library
workspace when you use the exploration flow:
• Validate and commit the exploration flow library workspace by running the
process_workspaces command on it.
When you run this command, the tool validates each subworkspace in the root
workspace and, if the workspace passes validation, commits it to a cell library.
This command performs the same functions on each subworkspace as the
check_workspace and commit_workspace commands, but uses less peak memory
when processing multiple subworkspaces.
For more information about workspace validation, see Validating the Workspace.
To specify validation options for the process_workspaces command, use the
-check_options option.
• Generate a library preparation script and source it to create the cell library, as
described in Using a Library Preparation Script.
To reduce the runtime of the exploration flow, use the fast exploration flow, as described in
Using the Fast Exploration Flow.
This command partitions the library source files into subworkspaces based on the names
of the library cells. It analyzes the logic libraries to identify both single-cell and multiple-cell
logic libraries. The group_libs command checks only the library cell names; it does not
check the pins, function, or timing arcs of the library cells.
For each subworkspace, the group_libs command adds the physical library source files
that include at least the same set of cells. If the physical library source files contain cells
that are not in any of the logic libraries, the group_libs command also creates a physical-
only subworkspace.
By default, the group_libs command
• Checks for cell shadowing across subworkspaces, and fixes any detected issues
Cell shadowing occurs when a library cell with the same name exists in multiple cell
libraries. In this case, the tool uses the data from the first cell library in which it finds the
cell, and it ignores that cell’s data in all other cell libraries.
By default, the group_libs command adjusts the grouping such that each cell exists in
only one generated cell library, which includes all the PVT panes for the cell. To disable
these fixes, set the lib.workspace.group_libs_fix_cell_shadowing application
option to false.
• Tries to put as many macro cells as possible into a single subworkspace
When using this strategy, the command groups all macro cells with the same set of
characterization points into a single subworkspace. This strategy creates the smallest
number of subworkspaces.
To create subworkspaces that each contain a single
macro cell with all of its characterization points, set the
lib.workspace.group_libs_macro_grouping_strategy application option to
single_cell_per_lib before running the group_libs command. Using this strategy
can generate a large number of subworkspaces.
• Assigns a name of <root_workspace>_physical_only to the physical-only
subworkspace, if there is one
To specify a name for the physical-only subworkspace, set the
lib.workspace.group_libs_physical_only_name application option.
The default behavior of this command depends on the current workspace. If the current
workspace is the root workspace, it generates a script for each subworkspace. If the
current workspace is a subworkspace, it generates a script only for that workspace. To
generate a script for specific workspaces, specify the workspaces as an argument to
the command. For example, to generate a Tcl script only for the my_lib workspace, use
the following command:
lm_shell> write_workspace -file libgen.tcl my_lib
You should review the generated script files, and modify as necessary to ensure that it
meets your needs before using it to perform your library preparation.
2. Remove the existing root workspace, which also removes all of its subworkspaces, by
using the remove_workspace command.
lm_shell> remove_workspace
If the check_workspace command reports any issues, you must resolve the issues
and rerun the script. For information about resolving the issues, see Validating the
Workspace. In addition, you might need to modify the generated script to resolve some
issues.
See Also
• Performing Automated Library Analysis
• Using a Library Preparation Script
This is the default behavior of the workspace validation and must be used to generate
cell libraries that can be used throughout the implementation flow.
• auto_fix
lib_missing_logical_port Logic library cell is missing a signal port that exists in the
Supported repairs: base logic library or physical library cell.
• create_placeholder_logic_ Creates a placeholder port on the logic library cell.
lib_port
lib_missing_physical_port Physical library cell is missing a port that exists in the base
Supported repairs: logic library.
• create_placeholder_ physica- Creates a placeholder port on the physical library cell. The
l_lib_port placeholder port is added on the M1 layer with a location of
(0, 0). The terminal width and height are both equal to the
minimum width defined for the M1 layer.
lib_missing_physical_reference A cell exists in the logic libraries, but not in any physical
Supported repairs: library source file.
• create_placeholder_physical Creates a placeholder physical cell that has the same
_lib_cell dimensions as the LEF unit site and the same number of
ports as the cell in the logic libraries, but no real physical
information.
lib_missing_rail_pg Logic library cell is missing a signal port that exists in the
Supported repairs: base logic library or physical library cell.
• create_pg_for_rail Creates a placeholder port on the logic library cell.
lib_port_direction A library cell pin has a different direction than in the base
Supported repairs: library.
• change_lib_port_direction Uses the pin direction from the base library in the case
of signal pin mismatches. Uses the pin direction from the
physical library cell in the case of PG pin mismatches.
Note:
The library manager fixes many types of pin direction
mismatches by default. For details, see Pin Definition
Checks.
lib_port_type A library cell pin has a different type than in the base library.
Supported repairs: Uses the pin type from the base library in the case of signal
• change_lib_port_type pin mismatches. Uses the pin type from the physical library
cell in the case of PG pin mismatches.
Note:
The library manager fixes many types of pin type
mismatches by default. For details, see Pin Definition
Checks.
If these predefined configurations do not meet your needs, you can define your own
configuration, as described in Creating a Mismatch Configuration.
To set a mismatch configuration, use the set_current_mismatch_config command, as
described in Setting a Mismatch Configuration. To see the mismatches that were identified
and fixed during the check_workspace command, use the report_design_mismatch
command after validating the workspace.
See Also
• Setting a Mismatch Configuration
• Reporting Mismatch Configurations
See Also
• Creating a Mismatch Configuration
• Reporting Mismatch Configurations
Command Report
In the following example, the tool reports the details of the current mismatch configuration,
including the mismatch error types and repair strategies. The report includes mismatch
error types that apply to both the library manager and the implementation tool; only the
error types with a category of library apply to the library preparation process.
lm_shell> report_mismatch_configs
****************************************
Report : Reporting Mismatch Configs
****************************************
Config : default
-------------------------------------------------------------------------------------
Mismatch-Type Category Action Allowed Actions
Strategy Available Strategies
-------------------------------------------------------------------------------------
lib_missing_physical_reference
library error {repair error accept }
null {create_placeholder_physical_lib_cell }
lib_missing_logical_port
library error {repair error accept }
null {create_placeholder_logic_lib_port }
lib_missing_physical_port
library error {repair error accept }
null {create_placeholder_physical_lib_port }
lib_port_type library accept {accept }
change_lib_port_type
{change_lib_port_type }
lib_port_direction
library accept {accept }
change_lib_port_direction
{change_lib_port_direction }
lib_port_name_synonym
library ignore {repair accept ignore }
null {record_lib_port_name_synonym }
...
lib_cell_name_case
library ignore {repair accept ignore }
null {record_lib_cell_name_case_insensitivity }
lib_port_name_case
library ignore {repair accept ignore }
null {record_lib_port_name_case_insensitivity }
lib_missing_rail_pg
library ignore {repair accept ignore }
null {create_pg_for_rail }
...
1
See Also
• Creating a Mismatch Configuration
• Setting a Mismatch Configuration
Verifying Libraries
The Library Manager tool provides a verification flow to validate the logical information or
frame views of a library. You can use this flow to
• Compare the logical information in a logic library source file and an existing cell library,
as described in Verifying Logical Information in a Cell Library.
• Compare the frame views in two libraries. The libraries can be cell libraries or physical
libraries, as described in Verifying the Frame Views Between Libraries.
The cell library opened in the verification workspace is referred to as the base library.
2. Compare the logical information in a logic library source file to the cell library in the
library workspace by using the compare_db command.
lm_shell> compare_db -process_label myprocess mylib.db
The library opened in the verification workspace is referred to as the base library.
2. Compare the frame views in another library to the base library by using the
compare_ndm command.
lm_shell> compare_ndm mylib2.ndm
3. Modify the cell library by performing one or more of the following tasks:
• Load new technology data, as described in Loading the Technology Data.
To determine the consequences of loading new technology data into an existing cell
library, use the report_tech_diff command.
• Modify the technology data, as described in Completing the Technology Data.
• Load physical library source files into the library workspace, as described in
Loading the Physical Data.
• Load a physical library or cell library into the library workspace by using the
read_ndm command, as described in Loading Physical Data from an Existing
Library.
Note:
When you load a cell library into an edit workspace, only the physical
information is loaded; the timing information is not used.
• Modify the physical attributes for one or more cells.
In general, you can modify physical cell attributes by using the set_attribute
command. You can also set certain attributes by loading a physical rules file, as
described in Loading the Physical Rules File.
• Update the frame views for one or more cells by using the update_clib_frame
command.
Note:
You can update frame views directly in the on-disk library, without
creating an edit-flow library workspace. For details, see the man page.
• Rename one or more cells by using the rename_clib_cell command.
Note:
You can rename cells directly in the on-disk library, without creating an
edit-flow library workspace. For details, see the man page.
• Remove one or more library cell by using the remove_clib_cell command.
Note:
You can remove cells directly from the on-disk library, without creating an
edit-flow library workspace. For details, see the man page.
• Update the via regions, as described in Updating Via Regions.
• Define antenna properties, as described in Defining Antenna Properties on
Standard Cells and Defining Antenna Properties on Hard Macro Cells.
• Edit the layout for one or more cells, as described in Editing the Physical Layout.
4. Validate the contents of the library workspace by using the check_workspace
command, as described in Validating the Workspace.
When you validate the library workspace, the tool checks only the modified physical
data. By default, the tool generates updated frame views only for cells with modified
design views. To generate a frame view for a cell whose design view is unchanged, set
the frame_update attribute on the cell to true before running the check_workspace
command.
If you want to use the same frame generation options that were used when the cell
library was created, use the write_frame_options command to generate a Tcl
script with the application option settings, and source this script before running the
check_workspace command.
source frame_options.tcl
check_workspace
commit_workspace -force -output existing.ndm
For details about via region creation and the application options used to modify the
default behavior, see Creating Via Regions.
• Create new via regions by using the create_via_region command
• Remove existing via regions by using the remove_via_regions command
To update the via regions in the existing frame views, you must use the edit flow, as shown
in the following example:
lm_shell> create_workspace -flow edit mylib.ndm
lm_shell> read_tech_file new.tf
lm_shell> derive_via_regions
lm_shell> check_workspace
lm_shell> commit_workspace
Attribute Description
antenna_area These attributes define the antenna area of an input pin. The anten-
antenna_side_area na_area attribute defines the antenna polygon area. The antenna_sid-
e_area attribute defines the antenna sidewall area.
The attribute values use the following syntax:
{layer_name area_value}
Note:
If these attributes are not specified for a pin, the implementation tool
uses the pin shapes to compute the antenna area.
Attribute Description
diff_area This attribute defines the diode protection value of an output pin.
The attribute value uses the following syntax:
{layer_name area_value}
Note:
If this attribute is not specified for a pin, the implementation tool
uses the setting of the route.detail.default_diode_protectio-
n application option.
is_diode This attribute specifies whether a pin is a diode that can be used by the
implementation tool to fix antenna violations.
For example,
lm_shell> set_attribute mylib/hm1/z diff_area \
{M1 0 M2 0 M3 0 M4 0.0595}
2. Use the set_port_antenna_property command to set the gate area, antenna area,
and antenna ratio properties on the hard macro input ports. This command has the
following syntax:
set_port_antenna_property -port port -data property_settings_list
In the property_settings_list argument, specify the properties for one or more layers
using the following syntax:
{ {metalLayer layer_name gate_size area_value mode1_area mode1_data
mode2_ratio mode2_data mode3_area mode3_data mode4_area mode4_data
mode5_ratio mode5_data mode6_area mode6_data} ... }
where
• layer_name is the name of the metal layer in the technology file
• mode1_data is the area of the specified metal layer when the connectivity is traced
up to that metal layer
• mode2_data is the maximum internal ratio of the area of the metal layer below the
specified metal layer when the connectivity is traced up to the specified metal layer
• mode3_data is the total metal area
• mode4_data is the sidewall area of the specified metal layer when the connectivity
is traced up to the specified metal layer
• mode5_data is the maximum internal ratio of the sidewall area of the metal layer
below the specified metal layer when the connectivity is traced up to the specified
metal layer
• mode6_data is the total metal sidewall area
The library manager also supports a simplified syntax that excludes the property
names:
{ {layer_name area_value mode1_data mode2_data mode3_data
mode4_data mode5_data mode6_data} ... }
For example, you can use either of the following commands to set the antenna
properties on the a pin of the hm1 hard macro cell:
lm_shell> set_port_antenna_property -port mylib/hm1/a -data \
{ {metalLayer M1 gate_size 0.3436 mode1_area 6.664
mode2_ratio 2.05346 mode3_area 12.708 mode4_area 17.5392
mode5_ratio 7.04044 mode6_area 12.682}
{metalLayer V1 gate_size 0.3436 mode1_area 6.664
mode2_ratio 2.05346 mode3_area 12.708 mode4_area 17.5392
mode5_ratio 7.04044 mode6_area 12.682} }
or
lm_shell> set_port_antenna_property -port mylib/hm1/a -data \
{ {M1 0.3436 6.664 2.05346 12.708 17.5392 7.04044 12.682}
{V1 0.3436 6.664 2.05346 12.708 17.5392 7.04044 12.682} }
Note:
For the layer below the pin layer, set the hierarchical antenna properties
to 0. Also, if the gate_size value for a metal layer is zero, such as for an
output pin, the mode2_ratio and mode5_ratio values for that layer must be
0.
3. Load the cell libraries into the library workspace, as described in Opening a Cell
Library.
All of the cell libraries in the library workspace become part of the aggregate library. To
remove libraries from the workspace, use the remove_lib command.
4. Validate the contents of the library workspace, as described in Validating the
Workspace.
5. Set the search order, as described in Setting the Search Order.
6. Commit the library workspace to disk, as described in Committing the Workspace.
See Also
• Aggregate Library
• Modifying an Aggregate Library
See Also
• Creating an Aggregate Library
Note:
The open_lib command takes the path to the cell library rather than the library
name. For libraries created with version N-2017.09 and later versions, this is
the path to the library’s root directory. For libraries created with earlier versions,
this is the path to the library file.
Each time you run the command, you can specify only a single cell library to open; to open
multiple cell libraries, you must run the command multiple times.
You can specify the cell library with an absolute path, a relative path, or no path. If you use
a relative path or no path, the tool uses the search path to find the library.
See Also
• Defining the Search Path
Querying Libraries
To list the libraries loaded into memory, use the get_libs command.
lm_shell> get_libs
{mylib mylib_lvt mylib_hvt}
If you have opened an aggregate library, the get_libs command returns the cell libraries
within the aggregate library. The cell library names are prefixed with the aggregate library
name.
lm_shell> get_libs
{AGG1|reflib1 AGG1|reflib2 }
You can specify a pattern to restrict the set of libraries. For example, to include only the
low threshold voltage libraries, enter the following command:
lm_shell> get_libs *lvt
{mylib_lvt}
Reporting Libraries
To report information about a cell library, use the report_lib command. You must specify
the name of an open cell library as an argument. You can run this command both before
and after committing the library workspace.
By default, this command provides information about the library, such as the number of
cells, the power rails, the characterization points (panes), and the operating condition
definitions. Use the following options to report additional information about the cell library:
• -antenna
Reports the library cells that are missing antenna properties and the affected pins.
• -parasitic_tech
obstructions, shorted pins, routing ports without geometry information, ports whose
is_secondary_pg or is_diode attribute differs between the timing view and the frame
view, and fully blocked terminals.
To report details about the cell objects, such as the number of terminals, shapes, and
routing blockages, and to report both fully and partially blocked terminals, use the
-verbose option.
• -timing_arcs
By default, the library manager determines the wire tracks from the library being
reported. If the wire track information is stored in a technology library, use the
-technology_lib option to specify the library.
• -wire_track_colors
Power rails:
Pane count: 2
Pane 0:
Process label: (none)
Process number: 1
Voltage rail count: 3
Voltage for rail 0 (<default>): 1.08
Voltage for rail 1 (V): 1.08
Voltage for rail 2 (VL): 1.08
Temperature: 125
Thresholds:
r/f InputDelay: 0.5/0.5 r/f OutputDelay: 0.5/0.5
l/h RiseTrans: 0.1/0.9 h/l FallTrans: 0.9/0.1
TransDerate: 1
Operating Conditions:
To report the frame view properties for one or more library cells, use the
report_frame_properties command. You can run this command only after committing
the library workspace. You must use the -library option to specify the name of an open
cell library and the -output option to specify the name of the output file.
lm_shell> open_lib mylib
lm_shell> report_frame_properties -library [current_lib] \
-output frame.txt
By default, the command reports the frame view properties for all cells in the cell library.
To report the frame view properties for a specific cell, use the -block option to specify the
cell name. Note that when you use this option, you must explicitly specify the frame view
of the cell.
Example 6 shows an example frame properties report, which was generated by the
following command:
lm_shell> report_frame_properties -library [current_lib] \
-output frame.txt -block mylib/AND2/frame
****************************************
**********************
Design : AND2
**********************
Total number of row: 1.
See Also
• Frame View Generation Application Options
Note:
To reduce runtime when you load physical library source files in the physical-
only flow, the tool loads only the cell names, and not detailed information for
the cells. The tool loads the detailed information during workspace validation.
This means that after loading the physical library source files, you can query
the library cell names, but you cannot query other information such as pins,
attributes, and shapes until after workspace validation.
If you need to examine the cells in detail before workspace validation, load the
physical library source files in the normal flow.
See Also
• Validating the Workspace
You can customize the report by using the -columns option to specify the information
to report. The following column names are valid for this report: area, design_type,
dont_touch, full_name, is_combinational, is_isolation, is_level_shifter,
is_memory_cell, is_sequential, is_three_state, name, pad_cell, pin_count,
valid_purposes, and view_name. To display all of the available information, specify
-columns all.
• To report information about one or more library cell pins, use the report_lib_pins
command. You must use the -objects option to specify the library cell pins.
Use the following format to specify the library cell pins:
library_name/cell_name/pin_name. You must specify the library name, the cell name,
and the pin name. You can specify a pattern, including wildcards for the library name,
cell name, and pin name.
By default, the report includes the full name and direction for the specified pins.
For example, to report on all the pins of the AND2 cell in the mylib cell library, use the
following command:
lm_shell> report_lib_pins -objects mylib/AND2/*
****************************************
Report : lib_pin
****************************************
full_name direction
------------------------- --------
mylib/AND2/IN1 in
mylib/AND2/IN2 in
mylib/AND2/OUT out
1
You can customize the report by using the -columns option to specify the
information to report. The following column names are valid for this report:
direction, disable_timing, full_name, function, is_async_pin,
is_clock_pin, is_data_pin, is_pad, is_preset_pin, is_three_state,
is_three_state_enable_pin, is_three_state_output_pin, name, pin_number,
port_type, rail_name, signal_type, and three_state_function. To display all of
the available information, specify -columns all.
• To report information about one or more timing arcs, use the
report_lib_timing_arcs command. You must use the -objects option to specify
the library timing arcs.
The easiest way to specify the timing arcs is to use the get_lib_timing_arcs
command and use the -of_objects option to specify the library cell for which you
want to report the timing arcs.
By default, the report includes the from pin, to pin, sense, when condition, and SDF
condition for the specified timing arcs.
For example, to report on all the timing arcs of the AND4 cell in the mylib cell library,
use the following command:
lm_shell> report_lib_timing_arcs \
-objects [get_lib_timing_arcs -of_objects mylib/AND2]
****************************************
Report : lib_timing_arc
****************************************
You can customize the report by using the -columns option to specify the information
to report. The following column names are valid for this report: from, from_lib_pin,
is_disabled, is_user_disabled, sdf_cond, sense, to, to_lib_pin, and when. To
display all of the available information, specify -columns all.
Format Command
LEF write_lef
GDSII write_gds
OASIS write_oasis
lm_shell> close_lib
lib.workspace.group_libs_naming_ str- list (default = ””) Controls the naming strategy used for
ategies the subworkspaces created by the g-
roup_libs command.
By default, the tool creates the
subworkspace names by using a
unique combination of logic library
prefix and suffix characters.
For more information, see Performing
Automated Library Analysis.
file.format.port_type_map list (default = “”) Identifies the power and ground pins
by mapping the pin name to its type.
The mapping applies to all cells in the
library source file.
For more information about this
application option, see Identifying
Power and Ground Pins.
file.format.text_layer_map list (default = “”) Maps the text layers to the metal
layers so that the tool can associate
metal shapes with a net or pin when
the text is not on the same layer as
the metal shapes.
For more information about this
application option, see Mapping Text
Layers.
lib.physical_model.block_core_ m- list of layer-float pairs Specifies the margin between the core
argin (default = “”) blockage and the macro cell boundary
for each layer in the frame view.
If you specify this option for a layer,
the tool creates a core blockage with
the specified margin regardless of the
setting of the lib.physical_mod-
el.block_all application option.
lib.physical_model.derive_ patte- false | true | ex- Controls whether frame view genera-
rn_must_join clude_pg tion sets the pattern_must_join at-
tribute on ports that have more than
one terminal on a metal layer.
lib.physical_model.include_ nonde- list (default = “”) Specifies the nondefault vias to in-
fault_via clude for via region extraction.
lib.physical_model.include_ routi- list (default = “”) Specifies the PG ports that require
ng_pg_ports via regions and access edges in the
frame view.
lib.physical_model.pin_must_ con- list of layer-spare layer Specifies the spare layer associated
nect_area_layers pairs (default = “”) with each pin layer. The spare layer
defines the must-area within the pin
geometry.
Use this option to restrict the via
landing area on complex-shaped pins.
lib.physical_model.preserve_ met- auto | true | false Controls whether metal blockages are
al_blockage trimmed when creating the frame view.
By default, metal blockages are
preserved (not trimmed) for the
following types of cells: library cells,
diode cells, end cap cells, fill cells,
filler cells, physical-only cells, and
well-tap cells.
For all other types of cells, the tool
trims metal blockages that touch a pin.
lib.physical_model.source_drain_ string (default = “”) Specifies the name of the input file
annotation containing the source-drain annotation
information for the cells in the library
workspace.
signoff.antenna.contact_layers_ bet- list (default = “”) Specifies the contact layers (contact
ween_m0_diffusion layers are the layers that connect
metal0 to diffusion). Specify the lay-
ers by using the layer names from the
technology file.
signoff.antenna.custom_runset_file string (default = “”) Specifies the custom runset file for
advanced gate layers.
signoff.antenna.gate_class1_layers list (default = “”) Specifies the marking layers for gate
thickness class 1. Specify the layers
by using the layer names from the
technology file.
signoff.antenna.gate_class2_layers list (default = “”) Specifies the marking layers for gate
thickness class 2. Specify the layers
by using the layer names from the
technology file.
signoff.antenna.gate_class3_layers list (default = “”) Specifies the marking layers for gate
thickness class 3. Specify the layers
by using the layer names from the
technology file.
signoff.antenna.hierarchical_gate_ c- string (default = “”) Specifies the gate class include file
lass_include_file for advanced gate class marker lay-
ers.
signoff.antenna.m0_layers_for_ diffu- string (default = “”) Specifies the m0 layers for diffusion
sion_connection connection. Specify the layers by us-
ing the layer names from the technol-
ogy file.
signoff.antenna.m0_layers_for_ poly_- string (default = “”) Specifies the m0 layers for poly con-
connection nection. Specify the layers by using
the layer names from the technology
file.
signoff.antenna.treat_source_ drain_- false | true Controls whether the tool treats the
as_diodes MOS source and drain as protec-
tion diodes and considers any MOS
source and drain regions that are
connected to a net to be a part of the
diode protection area available to that
net.
signoff.antenna.user_defined_ options list (default = “”) Specifies additional options for the
IC Validator command line.
The string that you specify in this
option is added to the command line
used to invoke antenna extraction
in the IC Validator tool. The library
manager does not perform any
checking on the specified string.
signoff.antenna.v0_layers_ between_- list (default = “”) Specifies the v0 layers (v0 layers are
m1_m0 the layers that connect metal1 to met-
al0). Specify the layers by using the
layer names from the technology file.
shell.common.single_line_messages false | true When set to true, error, warning, and infor-
mation messages that contain newlines are
output without newlines.
shell.common.tmp_dir_path string (default = / Specifies the directory that the tool uses for
tmp) temporary storage.
gui.command_form_use_object_ n- false | true Controls the value format for Tcl procedure
ames_for_proc_options options declared as design objects.
gui.custom_setup_files string (default = “”) Specifies the files to source when invoking
the GUI. These files are sourced in addition
to the standard setup files.
gui.enable_custom_setup_files false | true Controls whether the tool sources the cus-
tom setup files specified in the gui.custo-
m_setup_files application option.
gui.file_editor_command string (default = “”) Controls the command used to edit a file.
You can include other options when you start the GUI. For example,
• -f script_file_name to execute a script
See Also
• Starting the Command-Line Interface
If you want to execute a script before opening the GUI, use the -file option. For
example,
lm_shell> gui_start -file my_gui_setup.tcl
Note:
The GUI uses the DISPLAY environment variable to determine the display
location. Before opening the GUI, ensure that this variable is set to the name of
your Linux system display.
When you open the library manager GUI, it
1. Runs the commands in the .synopsys_lm_gui/setup.tcl setup files
The tool first runs the setup files in your home directory followed by the files in the
project directory (the current working directory in which you start the tool).
2. Runs the script specified by the -file option.
See Also
• Exiting the Library Manager Tool
The following topics describe how to use the wizard to perform these tasks:
• Creating a Cell Library
• Modifying a Cell Library
• Viewing a Cell Library
9. Validate the workspace by selecting Process Workspace and then clicking OK in the
Process Workspace dialog box.
The workspace must pass validation before you can create a cell library. For details
about workspace validation, see Validating the Workspace.
10. Create the cell library by selecting Commit Workspace and then clicking OK in the
Commit Workspace dialog box.
You can either enter the file path or click to browse for it.
3. If you want to update the technology data for the cell library, specify the technology
data source in the Technology text box.
You can specify either a technology file, which must have a file extension of .tf, or a
technology library, which must have a file extension of .ndm. You can either enter the
file path or click to browse for it.
You can either enter the path to the cell library or click to browse for it.
3. If you want to edit the cell library, select “Open reference library for edit.”
4. Click OK.
The library browser opens with the selected cell library.
See Also
• Using the Library Browser
Menus
Library
browser
Console
Command line
(part of console)
Status bar
To sort the blocks displayed in the library browser, click the caret (^) in the browser header.
To filter the blocks, enter a string in the search box. As you type, the library browser
updates to show only blocks that contain the text you entered. Click the X to the right side
of the text box to clear the filter.
To open a block in a block window to view or modify its layout, select a physical view
(frame, design, or layout) of the block, right-click, and choose Open Layout View. For
information about using the block window, see Working in the Block Window.
To see detailed information about the library cells, display the library browser cell
information.
• To display information for a specific cell, select one of its views and choose Cell
Information from the context-sensitive menu.
• To display information for all cells in the library, click the “Cell info” button, which is
located at the bottom right of the library browser.
Figure 31 shows these features in the library browser. Figure 32 shows an example cell
information report.
See Also
• Using the Error Browser
PG Rail Checks
For logic libraries that do not use the PG-pin syntax, the power rails and pins are derived
from the library-level power_supply group and cell-level rail_connection attributes.
The power_rail attributes in the power_supply group define the power rail names. The
rail_connection attributes on a cell associate these power rails with the cell’s power
pins. The signal pins of a cell are associated with the PG rails by using the pin-level
input_signal_level and output_signal_level attributes. Example 7 shows the use of
these attributes to define the power connections in a .lib logic library file.
output_signal_level : VDDH;
...
}
...
} /* end cell group*/
...
} /* end library group*/
The tool verifies that each logic library has the same number of rails and they have the
same names; however, if a rail is defined in a power_supply group but is not used, the
tool ignores mismatches involving that rail and does not include the rail definition in the
generated cell library.
If the rail order differs, the tool automatically updates the order using the information from
the base library.
By default, if a rail name differs between the logic libraries, the tool issues an LM-043
error. If the mismatch is caused only by rail names and positions, and not rail type
differences, you can use the rename_rail command to make the rail names match. For
example, assume logic library A has a power_rail setting of (VDD1.0, 1.0) and logic
library B has a power_rail setting of (VDD1.1, 1.1). You could use the rename_rail
command to align these rails, as shown in the following example:
lm_shell> rename_rail -library A -from VDD1.0 -to VDD
lm_shell> rename_rail -library B -from VDD1.1 -to VDD
You can also use the rename_rail command to correct the situation where the
rail_connection attribute for a cell uses the same PG pin name across libraries, but the
rail name differs.
PG Pin Connections
If the rail name specified for a rail_connection attribute is not defined in the library-
level power_supply group, the tool issues an error message. To fix this error, use the
set_attribute command to change the rail_connection attribute to a valid rail name.
To see the rail names defined for a library workspace, use the report_workspace -panes
command.