CE 223: Digital Logic and Design

Lecture23: Programmable Logic Devices

Dr. Md. Al-Amin Bhuiyan

Dept. of Computer Engineering
King Faisal University
Al Ahsa 31982, Saudi Arabia.

February 28, 2021

March 7, 2021 Dr. Al-Amin Bhuiyan [email protected]
 Overview
• A Programmable Logic Device is an IC that can be
programmed by the designer to implement digital
logic. During manufacturing, it has an undefined
function. However, it must be programmed before
use. Software development tools are available from
several manufacturers for programming PLDs.
• A PLD has an AND array and an OR array. Either or
both arrays can be programmed to implement
minterm (sum-of-product) Boolean expressions. The
three major types of PLDs are:
• Programmable Read Only Memory (PROM)
• Programmable Array Logic (PAL) and
• Programmable Logic Array (PLA)
 PLD
Fixed AND array Programmable
Inputs OR array Outputs

A B C D (Inputs)

Programmable OR array Programmable

minterms connection
(Fusible links)
ABC D
ABCD
ABC D
16×4 PROM
ABCD
ABC D
ABCD
ABCD
ABCD
ABC D
ABCD
ABC D
ABCD
ABC D
ABCD
ABCD
ABCD

Fixed
connection
Fixed AND array

Y3 Y2 Y1 Y0 (Outputs)
 B3 B2 B1 B0 (Binary inputs)
Truth table of a 4-bit
Binary-to-Gray conversion No connection
Binary Input Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

G3 is 1 (HIGH) when:

B3 B2 B1 B0 , B3 B2 B1 B0 , B3 B2 B1 B0 , B3 B2 B1 B0 , B3 B2 B1 B0 ,
B3 B2 B1 B0 , B3 B2 B1 B0 , and B3 B2 B1 B0
G3 G2 G1 G0
 Use a PROM to implement the following functions
A(x, y, z) = ∑m (1, 2, 4, 6)
B(x, y, z) = ∑m (0, 1, 6, 7)
C(x, y, z) = ∑m (2, 6)
D(x, y, z) = ∑m (1, 2, 3, 5, 7)

x y z

Minterms
x yz
x yz
xy z
x yz
x yz
x yz
xy z
xyz

A B C D

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Design a logic circuit using a PROM that accepts a 3-bit number
and generates an output equal to the square of the input number.
Dec
3-bit input
number Square output Equ

I2 I1 I0 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1
0 1 0 0 0 0 1 0 0 4
0 1 1 0 0 1 0 0 1 9
1 0 0 0 1 0 0 0 0 16
1 0 1 0 1 1 0 0 1 25
I2 I1 I0 0 1 0
(3-bit input) 1 1 0 1 0 0 36
input) 1 1 1 1 1 0 0 0 1 49

Minterms/Products
I2I1I0
I2I1I0
I2I1I0
I2I1I0
I2I1I0
I 2 I 1I 0
I 2 I 1I 0
I2I1I0

D5 D4 D3 D2 D1 D0
5 4 (Square
3 output)
2 1 0

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 Programmable Array Logic
Programmable Fixed
Inputs AND array OR array Outputs

A B C D E (5 inputs)
inputs)
Fixed OR array
(8 Programmable
AND gates)

Programmable AND array

(4 fixed
Y3 Y2 Y1 Y0 OR gates)
A 5×8×4 PAL 3 2 1 0 gates)
PAL
 Use a PAL to implement the following functions
F1 ( A, B, C , D, E , F )  A  D  BCF
F2 ( A, B, C , D, E , F )  BD F  DE  CE  CDE F
F3 ( A, B, C , D, E , F )  CD  AE  DE
A B C D E F (6 inputs)
inputs) F4 ( A, B, C , D, E , F )  CD  B DF
(16 Programmable Fixed OR array
AND gates)
1
2
3

4
5
6

7
8
9
10
11
12
13
14
15
16

Programmable AND array

F1 F2 F3 F4
1(4 output
2 functions)
3 4
A 6×16×4 PAL architecture
architecture

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 Programmable Logic Array (PLA)
Programmabl Programmabl
Inputs Outputs
e AND array e
OR array

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 Use a PLA to implement the following functions
F1 ( A, B, C , D, E , F )  A  D  BCF
F2 ( A, B, C , D, E , F )  BD F  DE  CE  CDE F
F3 ( A, B, C , D, E , F )  CD  AE  DE
F4 ( A, B, C , D, E , F )  CD  B DFA B C D E F

A
1
D
2
BCF
3
BDF
4
DE
5
CE
6
CDEF
7
CD
8
AE
9
BDF
10
11
12

F1 F2 F3 F4
Implementation of the functions using a 6×12×4 PLA
1 2 3 4

January 17, 2021 Dr. Al-Amin Bhuiyan [email protected] 11

 Programmable Logic Array (PLA)
Programmabl Programmabl
Inputs Outputs
e AND array e
OR array

January 17, 2021 Dr. Al-Amin Bhuiyan [email protected] 12

 Use a PLA to implement the following functions
F1 ( A, B, C , D, E , F )  A  D  BCF
F2 ( A, B, C , D, E , F )  BD F  DE  CE  CDE F
F3 ( A, B, C , D, E , F )  CD  AE  DE
F4 ( A, B, C , D, E , F )  CD  B DF
A B C D E F

A
1
D
2
BCF
3
BDF
4
DE
5
CE
6
CDEF
7
CD
8
AE
9
BDF
10
11
12

F1 F2 F3 F4
Implementation of the functions using a 6×12×4 PLA
1 2 3 4

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 Difference between PAL and PLA

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END