Faculty of Information and Communication Technology (FICT) Serial and Parallel data transfer

Parallel transfer
 whole byte of data transferred simultaneously using separate data lines
 a dedicated ground line required for each data line to reduce noise
 lower voltage for transmission
UCCE2043 Basic Microprocessor  example: printer ports

Serial Communication
Serial transfer

 a single line used: transfer one data bit after another
 higher voltage can be used

Interface  good for slower data transfer or over long distance, e.g. mouse, modem
 RS232: the most popular standard

H Y Lee
[email protected]

1 2

Serial Communication Transmission Types

Asynchronous: transfer single character at a
time without a clock or timing signal.

Synchronous: transfer a block of data at a time

UART: (eg: 8250/16450 and 16550)
 Universal Asynchronous Receiver

USART: (eg: 8251)
 UniversalSynchronous Asynchronous Receiver –
Transmitter

Eg: RS-232

From the book The 80x86 IBM PC by Muhammad Ali

3 4
Mazidi and Janice Gilispie pg. 510
 RS-232 Frame Format & Data Transfer Rate
Logic 1 = Mark
Logic 0 = Space
+3 to +25V
E.g.
-3 to -25V

Example
1=mark 0=space, transmission begins with start bit follow by the LSB and end with
1 or 2 stop bit
Start bit
0 b0 b1 … bn p s1 s 2
Asynchronous. Need of framing… Start Bit
Optional parity bit. 1-2 stop bits. ASCII
Parity Stop bit
2 stop bits is used in older systems due to slowness of the system to give it
sufficient time to organize itself before transmitting next byte.
total number of bits to be transferred is: 2 stop + 1 start +8 ASCII = 11 bits

Baud is the number of signal level changes per second in a line, regardless of the
111101000001111
information content of those signals. More in Appendix A
Idle
A
Bits per second (bps) is the rate of transfer of information bits
From the book The 80x86 IBM PC by Muhammad Ali
5 6
Mazidi and Janice Gilispie pg. 511

EIA-232-E OR RS-232 standard RS232 Connections

The PC/AT serial port is a programmable full-duplex asynchronous
communications communication channel, based upon the EIA, RS-
232-C communication's standard

The RS-232-C standard defines a 25-way D-type physical connector

IBM implemented a sub-set of this standard and defined a 9-pin D-
type connector

IBM 9-pin interface is now the 'de-facto' standard for
implementation of a limited serial, asynchronous communications
port

Even used in applications where there is no DCE
 e.g. connecting computer to printer, magnetic card reader, robot, … etc.
More in Appendix B

Stand for Recommended Standard.

RS-232 is still in used nowadays even with the existence of USB.

DTE
 data terminal equipment
 e.g. computer, terminal

DCE
 data communication equipment
 connects DTE to communication lines
 e.g. modem
7 8
 1.............5
RS232 pin out Function of Signals (I)

TxD: Transmit Data
6........9

RxD: Receive Data
9 Pin Conn 25 Pin Conn Signal Name
1 8 DCD (data carrier detect)
DSR: Data Set Ready
2 3 RxD Data (receive data)  Indicate whether DCE is powered on
3 2 TxD Data (transmit data)
4 20 DTR (data terminal ready)

DTR: Data Terminal Ready
5 7 GND (signal ground)  Indicate whether DTE is powered on
6 6 DSR (data set ready)  Turning off DTR causes modem to hang up
7 4 RTS (request to send) the line
8 5 CTS (clear to send)
9 22 RI (ring indicator)
RI: Ring Indicator
Shell 1, Shell FG (frame ground)  ON when modem detects phone call
9 10

Function of Signals (II)

DCD: Data Carrier Detect Handshaking in RS-232
 ON when two modems have negotiated
Are you ready
successfully and the carrier signal is RTS
to receive?
established on the phone line CTS

transmitter
RTS
RTS: Request To Send

receiver

CTS No

 ON when DTE wants to send data

RTS
CTS Yes

TD

CTS: Clear To Send Send RD
character
 ON when DCE is ready to receive data

SG: Signal Ground

11 12
 Electrical Characteristics UART to RS232 Connections

Single-ended
 one wire per signal, voltage levels are with respect to
system common (i.e. signal ground)

Mark: 1 is represented by: -3 to -25 Converting voltage from TTL
level to RS232 level

Space: 0 is represented by: +3 to +25

-3V to +3V is undefined

Line driver (1488)
 Converting voltage from TTL level To RS232 level

Line receiver (1489)
 Converting voltage from RS232 level To TTL level

High speed data transfer unreliable because of the
capacitance. Converting voltage from

Recommended maximum cable length is 15m, at RS232 level to TTL level
20kbps
From the book The 80x86 IBM PC by Muhammad Ali
13 14
Mazidi and Janice Gilispie pg. 512

COM1Serial
PC/AT PortPort – 8250/16450/16550 UART
The Serial Port

16550 is a 40-pin IC with an 8-bit data bus.
UART 8250
1488, RS -232
 It receives a single character from the CPU,
or 16450 or 16550

Reset
MR
Intrp
SOUT
Level Shift, Out

3, TX
9 - Pin
D - Type
frames it (insert start and stop bit), then
RTS 7, RTS
Connector
transmits it serially.
DTR 4, DTR

SD0..SD7  It can receive serial data, strip away the start

SI 2, RX

CTS 8, CTS and stop bits, make a character out of it, and
DSR 6, DSR
IOR
IOW
A0
DISTR
DOSTR
A0
RI 9, RI present it to the CPU.
RLSD 1, DCD
A1 A1
A2 A2
1489, RS -232 5, GND
 It also generates all the necessary modem
I/O decoded
CS

XTAL1
Level Shift, In
handshake signals.
1.8432 MHz. Osc.

FG

DISTR, DOSTR = Data Input and Data Output Strobes.

Data Sheet 8250/16450/16550
15 16
 8250 – 16450 - 16550 8250/16450 UART (replaced by 16550)
Sin = RxD Sout = TxD

A major limitation of the 8250/16450 - keeps interrupting the CPU for every
single byte of data receives or is to be transmitted.

In early PCs that was not a problem since everything in the PC was slow,
but in today's world of high-performance PCs and workstations, such a
limitation can be a source of severe bottleneck, especially in multitasked
systems.

16550 has an internal buffer of 16 bytes (instead of only 1 byte in 16450) to
store data for transmission and reception. The 16550 is fully 8250/16450
compatible.

In many IBM PC, this chip or an ASIC version of it is used to relieve the
CPU from constant interruption.

In the 16550 the CPU can write a 16-byte block of data into its transmission
buffer and let it transfer. When the buffer becomes empty it notifies the
CPU for another block of data.

In the same way, the 16-byte receive hold buffer keeps all the data
received, and when the buffer becomes full, it interrupts the CPU to pick
them up. This is much more efficient than interrupting the CPU for every
byte of data.

Although in such cases the CPU provides a block of data to the 16550 chip,
the data is transmitted or received serially one byte at a time with proper
framing.
Data Sheet 8250/16450/16550
17 18

UART Pins (I) UART Pins (II)

DO-D7
 Bidirectional data bus connected to the data bus of the CPU.

ADS’: Address strobe
 Note: For the IBM PC COM port the 74LS245 data bus  Used to latch address and chip select. Not needed on Intel
transceiver is activated only for the I/O address range of 3F8H - systems -- connected to ground.
3FFH.
CS0, CS1, CS2’: Chip selects

Sin and Sout
DDIS: Disable driver output
 These are the serial data pins, which become RxD and TxD of the
RS232 after conversion from TTL to RS232 voltage levels.  Set to 0 to indicate that the microprocessor is reading data from
the UART. Used to change direction of data flow through a

RTS’, CTS’, DTR’, DSR’, DCD’, and Rl’ buffer.
 These are the modem signals discussed in previous slides.

INTR: Interrupt Request

Xin and Xout (External Crystal Input/Output)
 Output to the microprocessor -- used to request an interrupt.
 Used for connection to the crystal oscillator.
 When the frequency is generated off-chip, it is connected to Xin,
MR: Master Reset
and Xout is ignored. In the IBM PC, Xin is connected to a  Connect to system RESET
frequency of 1.8432

OUT1, OUT2
 User defined output pins for modem or other device.
19 20
 UART Pins (III) Accessing 8250/16450/16550 UART Registers

RCLK: Receiver Clock
 Clock input to the receiver section of the UART. Always 16X the desired
receiver Baud rate.

BAUDOUT’
 Clock signal from Baud rate generator in transmitter.
 This is an output pin with clock frequency of sixteen times the baud rate of the
transmitter part of the chip.
 Normally this is connected to the RCLK input pin making the transmitter and
receiver of the chip work on the same baud rate.
 In such cases, the transmit and receive baud rate is always equal to the clock
frequency divided by the Divisor Word Register value times sixteen.

RD’, RD: Read inputs (either can be used)
 Cause data to be read from the register given by the address inputs.

RXRDY: Receiver Ready
 Used to transfer received data via DMA techniques.

TXRDY: Transmitter Ready
 Used to transfer transmitter data via DMA.

WR’, WR: Write (either can be used)
 Connects to microprocessor write signal to transfer commands and data to
A0,A1,A2: pins to access the internal registers of the 8250
16550.

DLAB: A bit in Line Control Register
21 22

UART in IBM PC (MORE COMPLETE) UART Addresses in IBM PC

Add Function

identification register (read only)

From the book The 80x86 IBM PC by Muhammad Ali Note: Please refer to Slide 22 and make comparison
23 24
Mazidi and Janice Gilispie pg. 523
 UART Registers Interrupt Enable Register

Transmitter Holding Register - (A2 A1 A0 =000, and DLAB =0)
 To transfer a byte serially, the byte must first be written to this register by the
CPU.
 After a byte is written into this register, the 8250 frames it with proper start
and stop bits and transfers it serially through the Sout pin.

Receiver Buffer Register - (A2 A1 A0 =000, and DLAB =0)
 When the 8250 receives the data through the Sin pin, it strips away the
framing bits, makes it a byte, and holds it in this register for the CPU to read.

Interrupt Enable Register - (A2 A1 A0 =001, and DLAB =0)
 Bits D7 - D4 of this register are always 0, and the rest are used for the
hardware-based interrupt to notify the CPU of certain conditions.
 While there is only one INTR pin on the 8250, there are four sources that can
activate it.
 The Interrupt Enable Register is used to mask or unmask any of these
sources.

25 26

Interrupt Enable Registers Interrupt Identification Register

D0 (received data available)
 If D0 =1, when a byte of data is received through the Sin pin, the INTR
pin is activated to notify the CPU that a byte has been received.
A2 A1 A0 - 010

D1 (transmit holding register empty)
 The 8250 moves the byte from the transmitter holding register into an
internal parallel-in-serial-out register in order to transmit it; then it has
room for a new byte. As soon as this happens, if Dl =1, INTR is activated
to notify the CPU that it has room for another byte.

D2 (receiver line status)
 Whenever an error is detected in the course of receiving data, the INTR
pin is activated if D2 = 1.
 The error could be due to a framing error or parity error or overrun error
or break condition. To see which one is the source of error, the Line
Status Register is tested, assuming that D2 = 1.

D3 (MODEM status)
 When D3 = 1, INTR is activated if any of the RS232 status lines changes
during the reception or the transmission

27 28
 Interrupt Identification Register Priority
Interrupt Identification Register Priority

One might wonder how the CPU can know which is the source
of INTR activation if all these conditions can activate the single
INTR pin.

This is exactly the function of the Interrupt Identification Register.
This is a read-only register used to poll to determine the source
of activation of the INTR pin.

While D0 indicates if an interrupt is pending, D1 and D2 provide
the source of the interrupt with the highest priority. They are
prioritized as shown in Table (Slide 28 or 29).

Another major use of this register is its ability to implement the
polling method in monitoring INTR. The polling method first
checks D0 to see if there is an interrupt pending and if there is
one, D 1 and D2 are tested to see which one.

D3 to D7 of this register are always 0.

29 30

Line Status Register(A2 A1 A0 =101) Line Status Register (A2 A1 A0 =101)

When D2 of the Interrupt Enable Register is set to high, one can monitor the Line
Status Register to see which of the errors (parity error, framing error, and so on)
has occurred.

D0: When the 8250 receives the serial data and strips away the framing bits, it
creates a byte to be given to the CPU. D0 indicates that a byte has been send to the
receiver buffer to be picked up by the CPU.

D1. If the 8250 cannot keep up with the stream of incoming serial bits, the old byte
is overwritten by the new data. This can happen if the CPU is slow and does not
pick up the data previously received.
 D1 = 1 indicates that the previous byte has been overrun by the new data.

D2 is set to 1 if the parity bit of the data received does not match the data format
register setup.

D3 indicates (when it equals 1) if the stop bit of the incoming data does not match
the data format register.

D4 is set to 1 if the Sin pin is low (space) for a period of one byte transfer (start bit +
data bits + parity + stop bit). This is referred to as break.

D5: If D5 =1, it indicates that the 8250 has room for a new byte to be transmitted. In
other words when the byte is transferred from the Transmit Hold Register into the
serial shift register, D5 is set to 1.
 When the CPU writes a byte to Transmit Hold Register, it becomes 0.

D6 =1 when both the Transmit Hold Register and Serial Shift Register are both
empty.

D7 always equals 0.
Note: You may refer to Slide 27 31 32
 Line Control Register (A2 A1 A0 =011) E.g.
Use the I/O port addresses in Slide 23 to program the data format
register for the following data format: 7 bits character, 1 stop bit, odd
parity, and break control set to off.

Solution:
We have 0000 1010 =0AH for the Line Control Register, and the program
is as follows:
MOV DX,3FBH ;the data format reg. port address
MOV AL,0AH ;DLAB =0, no brk cont, odd, 1 stop, 7 bits
OUT DX,AL ;issue it

Notice in the above example that DLAB can be 0 or 1 for the data
format register, but to access the buffer/hold register it must be 0, and
for the divisor latch it must be 1, as we will see the coming slide
Note: You may refer to Slide 22

33 34

Divisor Latch LSB (A2 A1 AO =000 and DLAB =1) and

Divisor Latch MSB (A2 A1 AO =001 and DLAB =1)
Divisor Register

The baud rate of the 8250 is programmed through these two
registers. The input frequency of Xin is the master clock.
 This clock is divided by the 16-bit integer contents of the divisor
latches and again by the number 16 to get the desired baud rate as
shown in the equation:
Divisor value = Xin clock freq / (baud rate x 16)

The table in next slide shows some of the divisor latch values in
both decimal and hex for the 1.8432-MHz crystal frequency.

To program the divisor latches we set the DLAB bit of the Line
Control (data format) Register to 1 before issuing the divisor values,
as shown in Examples. (Slides 37 & 38).

There are cases where the divisor is byte size instead of word size,
but both upper and lower bytes must still be issued.

35 36
 E.g. E.g.
Program the divisor latch for 300 baud, assuming that Xin=1.8432 Program the divisor latch for 2400 baud, assuming that Xin=1.8432
MHz. Use the I/O port addresses of Slide 23. MHz. Use the I/O port address of Slide 23.

Solution: Solution:
MOV AL,80H ;10000000 (binary) to access DLAB MOV AL,80H ; 10000000 to access DLAB
MOV DX,3FBH ;the address of line control reg MOV DX,3FBH ;the address of line control reg
OUT DX,AL ;make D7 =1 for DLAB; now send the divisor value OUT DX,AL ;make D7=1 for the DLAB; now send the divisor value
MOV AX,384 ;For 300 baud rate, Divisor Value=384 (Slide 35) MOV AX,48 ;For 2400 baud rate, Divisor Value=48 (Slide 35)
MOV DX,3F8H ;divisor latch address (LSB) MOV DX,3F8H ;divisor latch address (LSB)
OUT DX,AL ;issue the low byte OUT DX,AL ;issue the low byte
MOV AL,AH ; MOV AL,AH
INC DX ;the divisor latch address (MSB) INC DX ;the divisor latch address (MSB)
OUT DX,AL ;ISSUE THE HIGH BYTE OUT DX,AL ;issue the high byte

37 38

Transmitting A String via UART

DATA DB “I AM CT SMART STUDENT”,”$”

MOV SI,OFFSET DATA

BI: MOV DX,3FDH ; Line Status Register
Test Line Status Register for THR,
IN AL,DX keep on polling until THR & TSR empty
AND AL,01000000B
JZ BI
MOV AL,[SI]
CMP AL,”$”
JE B2 ; End of string
MOV DX,3F8H ; Transmit Holding Register
MOV DX,3FBH ;the data format reg port address
MOV AL,0AH ;DLAB =0, no brk cont, odd, 1 stop, 7 bits OUT DX,AL
OUT DX,AL ;issue it
MOV AL,80H ; 10000000 to access DLAB INC SI 1001 1000 = 98H data reg=R/W
MOV DX,3FBH ;the address of line control reg
OUT DX,AL ;make D7=1 for the DLAB ;now send the divisor value
JMP BI 1001 1001 = 99H status /control reg
0101 1110 = 5Eh
MOV AX,48 ;2400 baud rate
MOV DX,3F8H ;divisor latch address (LSB)
B2: RET
OUT DX,AL ;issue the low byte
MOV AL,AH
INC DX ;the divisor latch address (MSB)
OUT DX,AL ;issue the high byte 39 40
 Synchronous Serial Data Communication 8251A USART Block Diagram
Bus Interface Section Transmit Section

More efficient than asynchronous, more costly

Serial data over greater distances

Individual data words are transmitted in continuous blocks without
any START or STOP bits

The receiver can, MUST be synchronised to the transmitter
through the use of special sync characters sent before each block
of data and whenever the communications channel is idle

The sync character is a special pre-determined character code,
(e.g. in ASCII the code 16h (mnemonic SYN) is used), which Receive Section
enables the receiver to continually synchronise its internal clock
to that of the transmitter.

MODEM Control Section

41 42

8251A USART 8251A USART External Clock Connection

The receiver section is responsible for reading the serial bit stream of
data at RxD (receive data) input and converting it to parallel form.
 RxRDY (receive ready) output switched to logic 1 level to tell the
microprocessor that a character is available and is sitting inside the USART
and should be read from the Receive–Data Register.

Transmitter section receives parallel data from the microprocessor over
the data bus.
 The character is then automatically framed with the start bit, parity bit,
correct number of stop bits, and put into the Transmit Data Buffer Register.
 Finally, it is shifted out of this register to produce a bit serial output on the
TxD line.
 TxRDY is switched to logic 1 when the transmit buffer register is empty.

Does not have an internal baud rate generator but RxC and TxC should
be connected to an external clock generator. (see next slide)

From the book “The 8088 and 8086 Microprocessors” by

43 44
Walter A. Triebel and Avtar Singh. Pg. 546
USART 8251A Read/Write Operations 8251A USART Registers

8251A can be configured for various modes of
operation by setting the bits in three internal
control registers.
 Mode Control Register

The contents of Mode Control Register determine the way in
which 8251A’s Transmitter and Receiver works.
 Command Register

The microprocessor controls the operation of the serial interface
by issuing commands to Command Register.
 Status Register

Contains information related to its current state.

45 46

Mode Instruction (Asynchronous Mode)

Mode Control Register

Asynchronous
Mode

8251A Initialization
Flowchart

47 48
Mode Instruction (Synchronous Mode) 8251A USART Command Register

Read “The 8088 and 8086 Microprocessors” by Walter A.

UPDATE 2009 49 50
Triebel and Avtar Singh. Pg. 548

Status Register E.g.

Find the baud rate if each of the following options
is selected. Assume RxC= TxC=19,200Hz.
i) x16
ii) x64

Answer
i) 19200/16 = 1200
ii) 19200/64=300

UPDATE 2009 51 52
 E.g. E.g.

Find the I/O port address assigned to the
What value must be written into the mode control
8251 if CS is activated by A7-A1= register with baud rate divided by 16, character
“1001100” and A0 is connected to C/D size 16 bits, odd parity, one stop bit. Write an
assembly program.
Answer
Answer
1001 1000 = 98H Data Register
0101 1110 = 5Eh
1001 1001 = 99H Status Register MOV AL, 0100 0000 ;RESET THE 8251 D6 OF COMMAND REG
OUT 99H,AL
MOV AL,5EH
OUT 99H,AL

53 54

Mode
instruction-
Asynchronous
E.G.

Write a program that transfer the message
“I AM CT SMART STUDENT”,”$” into the
command
Status
8251. The “$” indicate the end of the
message: Use the data format and the
baud rate of the previous example.

55 56
 ANS. Appendix A: Baud Rate vs Bps
DATA DB “I AM CT SMART STUDENT”,”$”
Bps is simply the number of bits transmitted per second.
MOV AL,00 The Baud Rate is a measure of how many times per
OUT 99H,AL
OUT 99H,AL
second a signal changes (or could change).
OUT 99H,AL
MOV AL, 0100 0000
 For a typical serial port a 1-bit is -12 volts and a 0-bit is +12 v (volts).
OUT 99H,AL If the bps is 38,400 a sequence of 010101... would also be 38,400
MOV AL,5EH baud since the voltage shifts back and forth from positive to
OUT 99H,AL negative to positive, etc. and there are 38,400 shifts per second.
MOV SI,OFFSET DATA
BI: IN AL,99H  Suppose that a "change" may have more than the two possible
AND AL,00000001B
JZ BI
outcomes of the previous example (of +- 12 v). Suppose it has 4
MOV AL,[SI] possible outcomes, each represented by a unique voltage level.
CMP AL,”$” Each level may represent a pair of bits (such as 01). For example, -
JE B2 12v could be 00, -6v 01, +6v 10 and +12v 11. Here the bit rate is
OUT 98H,AL
INC SI double the baud rate. For example, 3000 changes per second will
JMP BI generate 2 bits for each change resulting in 6000 bits per second
B2: RET (bps). In other words 3000 baud results in 6000 bps.

Check out http://tldp.org/HOWTO/Modem-HOWTO-23.html for clearer explanation

58

Appendix B: A DTE-DTE Serial Communication

From the book “The 8088 and 8086 Microprocessors” by

59
Walter A. Triebel and Avtar Singh. Pg. 542