EE5311- Digital IC Design

Module 6 - Adders and Multipliers

Janakiraman V
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai

November 23, 2018

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 1/58
Learning Objectives
◮ Design a full adder with least PMOS stack size using self
duality principle
◮ Construct
√ adder architectures to reduce delay from O(N)
to O( N) - O(log2 (N))
◮ Draw timing diagrams to show the signal propagation of
various adders
◮ Design an array multiplier for both signed and unsigned
multiplication
◮ Optimize the arrary multiplier using the inverting property
of a Full Adder
◮ Derive the Modified Booth Encoding to reduce the
number of partial products
◮ Design and implement a multipler based on the Modified
Booth Encoding algorithm
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 2/58
Outline
◮ Adders
◮ Basic terminology
◮ Full adder circuit design
◮ Inverting Adder
◮ Carry Save Adder
◮ Carry Select Adder
◮ Carry Look Ahead Adder
◮ Multipliers
◮ Basic Terminology
◮ Booth and Modified Booth Encoding
◮ 2s Complement Airthmetic
◮ Array Multiplier
◮ Carry Save Multipler
◮ Signed multiplication and carry save implementation
◮ Final Addition
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 3/58
Basic Adder Terminology
A B Ci S Co Carry Status
0 0 0 0 0 Delete
0 0 1 1 0 Delete
0 1 0 1 0 Propagate
0 1 1 0 1 Propagate
1 0 0 1 0 Propagate
1 0 1 0 1 Propagate
1 1 0 0 1 Generate
1 1 1 1 1 Generate
Table: Truth Table of a Full Adder

S = A ⊕ B ⊕ Ci
Co = AB + BCi + Ci A
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 4/58
Basic Adder Terminology

◮ G = AB - Generate Carry
◮ D = A.B - Delete Carry
◮ P = A ⊕ B - Propagate Carry
G , D, P are independent of Ci

S = P ⊕ Ci
Co = G + PCi

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 5/58
Ripple Adder
A0 B0 A1 B1 A2 B2 A3 B3

Co0 Co1 Co2 Co3

Ci FA FA FA FA

S0 S1 S2 S3

tripple−adder = (N − 1)tcarry + tsum

◮ Worst case delay is linear in N i.e. tripple−adder ∝ N

◮ Carry optimization is more important than Sum

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 6/58
Properties of a Full Adder

Logic functions are written in SoP form (Sum of minterms)

X
S= m(1, 2, 4, 7)
X
S= m(0, 3, 5, 6)
X
Co = m(3, 5, 6, 7)
X
Co = m(0, 1, 2, 4)

Inverting Property

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 7/58
Full Adder - Inverting Property
A B A B

Ci FA Co Ci FA Co

S
S

Figure: Inverting Property

S = S(A, B, C )
Co = Co (A, B, C )

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 8/58
Full Adder
A B

A
Ci
B
Co
Ci A

A B B

Figure: Full Adder Carry Circuit

Co = AB + BCi + Ci A
S = ABCi + Co (A + B + Ci )

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 9/58
Full Adder - Problems
A B

A
Ci
B
Co
Ci A

A B B

Figure: Full Adder Carry Circuit

◮ Tall PMOS stacks in both Sum and Carry

◮ Load capacitance of Co is very large - 6CG + 2CDiff
◮ Carry goes through extra inverter - Critical path
◮ Sum optimization is not as important
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 10/58
Full Adder - Observations
A B

A
Ci
B
Co
Ci A

A B B

Figure: Full Adder Carry Circuit

◮ Ci is connected to smaller PMOS stack - Lower logical

effort
◮ Ci is connected to the transistor closest to the output.
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 11/58
Full Adder - Optimization

EVEN ODD EVEN ODD

A0 B0 A1 B1 A2 B2 A3 B3

Co0 Co1 Co2 Co3

Ci FA’ FA’ FA’ FA’

S0 S1 S2 S3

Figure: FA’ is a Full Adder w/o inverter in the carry path

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 12/58
Full Adder - Optimization

EVEN ODD EVEN ODD

A0 B0 A1 B1 A2 B2 A3 B3

Co0 Co1 Co2 Co3

Ci FA’ FA’ FA’ FA’

S0 S1 S2 S3

Figure: FA’ is a Full Adder w/o inverter in the carry path

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 13/58
Mirror Adder

6 A

A 12 B 4 B A 4 B 4C 4 6 B
i

12 4 A 4 6 Ci
Co S
Ci
6 2 A 2 3 Ci

A 6 6 2 B A 2 2 C 2 3 B
B B i

3 A

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 14/58
Mirror Adder - Features

◮ Requires 24 transistors as opposed to 28 transistors

◮ PUN and PDN as identical - Self duality
◮ Ci is connected to the transistors closest to the output
◮ Transistors in the carry stage need to be optimized
(Upsized) for speed
◮ Invereter not available to size for delay optimization
◮ Upsize carry stage to 3-4X

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 15/58
Transmission Gate Based Adder
A

P
Ci

P S
A
B B
Ci

P P

P Co
A
Ci
A A
P

Ci Ci

S = P ⊕ Ci
Co = G + PCi
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 16/58
Manchester Carry Gate - Static Implementation
P
VDD
A P
G
Co Ci Co
Ci D
P
P

S = P ⊕ Ci
Co = G + PCi
P =A⊕B
G = AB
D = A.B
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 17/58
Manchester Carry Gate - Dynamic Implementation
VDD VDD
P P
G φ

Ci Co Ci Co

D G
P
φ

S = P ⊕ Ci
Co = G + PCi
P =A⊕B
G = AB
D = A.B
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 18/58
Manchester Carry Chain Adder

VDD VDD VDD VDD

P0 P1 P2 P3
φ φ φ φ
Ci,0
G0 G1 G2 G3

φ φ φ φ

Co,0 Co,1 Co,2 Co,3

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 19/58
Manchester Carry Chain - Delay

R1 R2 R3 RN
Ci,0 Co,N

C1 C2 C3 CN

N(N + 1)
τ= RC
2

◮ Worst case delay - Carry propagates from input to output

◮ Delays scales as N 2 - Need to buffer between wires

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 20/58
Adder Optimization

◮ Ripple adder delay O(N)

◮ Practical only for few bits
◮ Desktops use 32 bits
◮ Servers use 64 Bits
◮ GPUs require 128 Bits
◮ Adders are citial to their performance
◮ Goal : Propagation delay should be < O(N)

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 21/58
Carry Skip Adder

P0 G0 P1 G1 P2 G2 P3 G3

Co0 Co1 Co2

Ci FA FA FA FA 0

Co3
S0 S1 S2 S3

BP = P0 P1 P2 P3

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 22/58
Carry Skip Chain

Bits 0−3 Bits 4−7 Bits 8−11 Bits 12−15

tGP Compute (G, P) Compute (G, P) Compute (G, P) Compute (G, P)

Carry Carry Carry Carry

Propagation Propagation Propagation Propagation

Sum Sum tbypass Sum tsum Sum

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 23/58
Carry Skip Chain
Bits 0−3 Bits 4−7 Bits 8−11 Bits 12−15

tGP Compute (G, P) Compute (G, P) Compute (G, P) Compute (G, P)

Carry Carry Carry Carry

Propagation Propagation Propagation Propagation

Sum Sum tbypass Sum tsum Sum

N
tcarry −skip = tGP + Mtcarry + ( − 1)tbypass + (M − 1)tcarry + tsum
M

◮ Still proportional to N, however linear with N/M

◮ Still better than ripple adder.
◮ Carry skip starts showing lesser delay for N > 4 − 8

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 24/58
Carry Skip vs Ripple Adder

20 Carry Skip Adder

Ripple Adder

15
tp

10

0
2 4 6 8 10 12 14 16
N

◮ The Carry-Skip adder is beneficial for N > 4 . . . 8

◮ The bypass overhead is high for small N

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 25/58
Linear Carry Select Adder

P0 G0 P1 G1 P2 G2 P3 G3

Co0 Co1 Co2

0 FA FA FA FA 0

P0 G0 P1 G1 P2 G2 P3 G3
Co3

Co0 Co1 Co2

1 FA FA FA FA 1
SUM
Ci,0

S0−3

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 26/58
Linear Carry Select Chain

Bit 0−3 Bit 4−7 Bit 8−11 Bit 12−15

Compute (G,P) Compute (G,P) Compute (G,P) Compute (G,P)

0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1

Ci,0 MUX MUX MUX MUX

SUM SUM SUM SUM

S0−3 S4−7 S8−11 S12−15

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 27/58
Linear Carry Select Chain

Bit 0−3 Bit 4−7 Bit 8−11 Bit 12−15

Compute (G,P) Compute (G,P) Compute (G,P) Compute (G,P)

0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1

Ci,0 MUX MUX MUX MUX

SUM SUM SUM SUM

S0−3 S4−7 S8−11 S12−15

N
tcarry −select = tGP + Mtcarry + tmux + tsum
M

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 28/58
Linear Carry Select Chain A15−0 , B15−0

t=1

t=2

t=3

t=4

t=5
C3 C0
t=6
C7
t=7
C11
t=8

CARRY-GEN-0 GEN PROP

CARRY-GEN-1 MUX

N
tmux + tsum
tcarry −select = tGP + Mtcarry +
M
Reference: Prof. Vinita’s Lecture notes [3]
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 29/58
Linear Carry Select Chain

Bit 0−3 Bit 4−7 Bit 8−11 Bit 12−15

Compute (G,P) Compute (G,P) Compute (G,P) Compute (G,P)

(1) (1) (1) (1) (1) (1) (1) (1)

0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1

(5) (5) (5) (5) (5) (5) (5) (5)

(6) (7) (8)
Ci,0 MUX MUX MUX MUX

(9)

SUM SUM SUM SUM

(10)
S0−3 S4−7 S8−11 S12−15

Increasing mismatch in arrival times at the mux

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 30/58
Square Root Carry Select Chain
Bit 0−1 Bit 2−4 Bit 5−8 Bit 9−13 Bit 14−19

Compute (G,P) Compute (G,P) Compute (G,P) Compute (G,P)

(1) (1) (1) (1) (1) (1) (1) (1)

0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1 0 Carry(0) Carry(1) 1

(3) (3) (4) (4) (5) (5) (6) (6) (7) (7)
(4) (5) (6) (7)
Ci,0 MUX MUX MUX MUX MUX

(7) (8)

SUM SUM SUM SUM SUM

(8) (9)
S0−1 S2−4 S5−8 S9−13 S14−19

◮ Equalize the arrival times at the multiplexer

◮ Let the first stage add M bits
◮ Subsequent stages progressively add one bit more
◮ There are P such stages

N = M + (M + 1) + (M + 2) + (M + 3) + . . . + (M + P − 1)
P(P − 1) P2 1
N = MP + = + P(M − )
2 2 2
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 31/58
Square Root Carry Select Chain
A13−0 , B13−0

t=1

t=2

t=3
C1 C0
t=4
C4 C2
t=5
C8 C5
t=6
C13 C9

CARRY-GEN-0 GEN PROP

CARRY-GEN-1 MUX

Reference: Prof. Vinita’s Lecture notes [3]

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 32/58
Square Root Carry Select Chain

Propagatation delay, for large N and small M

tadd = tGP + Mtcarry + Ptmux + tsum

P2
N≈
√ 2
tadd = tGP + Mtcarry + ( 2N)tmux + tsum
√
tadd = O( N)

Still limited by carry ripple

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 33/58
Carry Look Ahead Adder
Can we do away with the carry ripple?

Co,k = f (Ak , Bk , Co,k−1 )

Co,k = Gk + Pk Co,k−1
Co,k = Gk + Pk (Gk−1 + Pk−1 Co,k−2 )
Co,k = Gk + Pk (Gk−1 + Pk−1 (Gk−2 + Pk−2 (. . . P1 (P0 + G0 Ci,0 ))))

◮ Each bit now is independent of the carry ripple

◮ Extra hardware required
◮ Delay is indepenent of number of bits?

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 34/58
Carry Look Ahead Adder VDD

G3

G2

G1

G0

Ci,0
Co,3

P0

P1

P2

P3

◮ Not scalable for large N

◮ G0 , P0 drives all carry out cicuits. Needs strong driver
◮ N bits has N + 1 parallel branches - Large area required
◮ N bit implementaion has up to N + 1 transistor stacks -
Slow performance
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 35/58
Block Propagate and Generate
Define a sub-block from bits i − j and define the block
propagate and generate as follows
◮ Gi:j - Block Generates a carry out independent of carry in
- G3:2 = G3 + P3 G2
◮ Pi:j - Block Propagates a carry - P3:2 = P3 P2

Define a pair (Gi:j , Pi:j ) and a new DOT operator as

(G , P).(G ′ , P ′ ) = (G + PG ′ , PP ′ )
(G3:2 , P3:2 ) = (G3 , P3 ).(G2 , P2 )

DOT operator is associative but not commutative

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 36/58
 Carry Look Ahead Log Adder
Janakiraman, IITM

S15 (A15 , B15 )

S14 (A14 , B14 )

− Compute Propagate and Generate

− Compute Sum

− DOT operator

S13 (A13 , B13 )

S12 (A12 , B12 )

S11 (A11 , B11 )

S10 (A10 , B10 )

EE5311- Digital IC Design, Module 6 - Adders and Multipliers

S9 (A9 , B9 )

S8 (A8 , B8 )

S7 (A7 , B7 )

S6 (A6 , B6 )

S5 (A5 , B5 )

S4 (A4 , B4 )

S3 (A3 , B3 )

S2 (A2 , B2 )

S1 (A1 , B1 )

S0 (A0 , B0 )
37/58
Multipliers - Definitions

N−1
X
X = Xi 2i
i=0
M−1
X
Y = Yj 2j
j=0
Z =X ×Y
M+N−1 N−1 M−1
!
X X X
Z= Z k 2k = Xi Yj 2i+j
k=0 i=0 j=0

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 38/58
Multipliers - Definitions

1 0 1 1 Multiplicand
× 1 1 0 Multiplier
0 0 0 0 PP0
1 0 1 1 PP1
1 0 1 1 PP2
1 0 0 0 0 1 0 Result

Multipliers need to perform three main tasks:

◮ Partial Product (PP) Generation
◮ Partial Product Accumulation
◮ Final addition

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 39/58
Partial Product Generation
X0

X1

X2

X3

X4

X5

X6

X7
Yk
P P0

P P1

P P2

P P3

P P4

P P5

P P6

P P7
◮ AND of the multiplicand (X − N bits) with each bit of
the multiplier (Y − M bits)
◮ Generates M partial products which are N bits each
◮ Each PP is either ZERO or the Multiplicand itself
◮ Large number of additions
◮ How do you reduce the number of PP?
Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 40/58
Booth Encoding
◮ If multiplier = 0111-1110, No. of non-zero PP = 6
◮ Can be encoded as follows : 0111 − 1110 = 1000 − 0010
◮ 1 = −1
◮ Equivalent to treating the multiplier as a radix 4 number

(M−1)/2
X
Y = Yj 4j . . . (Yj ∈ {−1, 0, 1, 2})
j=0

◮ Number of partial products reduced to at most half

◮ Multiplying by {0, 1} is a simple AND operation
◮ Multiplying by {−1, 0, 1, 2} requires inversion and shiting

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 41/58
Modified Booth Encoding

Z = X × (YM−1 2M−1 + . . . Y4 24 + Y3 23 + Y2 22 + Y1 21 + Y0 )20

Z = X × (. . . Y4 24 + Y3 (24 − 23 ) + Y2 22 + Y1 (22 − 21 ) + Y0 ))
Z = X × (. . . + [−2Y3 + Y2 + Y1 ]22 + [−2Y1 + Y0 ]20 ))

Partition the miltiplier into sets of 3 with 1 overlapping

◮
bit (b2i+1 , b2i , b2i−1 )
◮ Multiplicand is operated on based on
−2b2i+1 + b2i + b2i−1
Reference: Prof. Vinita’s Lecture notes [3]

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 42/58
Modified Booth Encoding

b2i+1 b2i b2i−1 Recoded Bits

0 0 0 0
0 0 1 +Multiplicand
0 1 0 +Multiplicand
0 1 1 +2×Multiplicand
1 0 0 −2×Multiplicand
1 0 1 -Multiplicand
1 1 0 -Multiplicand
1 1 1 0

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 43/58
Example

1 1 0 1 -3
1 0 1 1 -5
0 0 0 0 0 0 1 1 3 Y1 Y0 Y−1 = 110[−X ]
0 0 0 0 1 1 12 Y3 Y2 Y1 = 101[(−X ) << 2]
0 0 0 0 1 1 1 1 15
◮ Sign extension is critical.

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 44/58
Partial Product Accumulation

◮ Generated PP have to be summed

◮ Requires a large nmumber of adders
◮ Simplest is an array of adders - Array Multiplier
◮ PP Shifting to the left is achieved through routing

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 45/58
2s Complement Numbers
Needed to represent negative numbers. MSB used to represent
the sign
N−1
X
X = Xi 2i
i=0
N−2
X
X = −2N−1 XN−1 + Xi 2i
i=0
N−2
X
X = −([2N−1 XN−1 − 1] − Xi 2i + 1)
i=0

◮ If XN−1 = 1, invert the least N − 1 bits and add 1

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 46/58
2s Complement Numbers - Sign Extension
Extend the sign bit (MSB) to additonal K bits to form a
N + K bit number

N−1
X
X = Xi 2i
i=0
N−2
X
X = −2N−1 XN−1 + Xi 2i
i=0
N−2
X
X = −2N−1 XN−1 (2K − 2K −1 − 2K −2 . . . − 2 − 1) + Xi 2i
i=0
K K −1 K −2 K K
(2 − 2 −2 . . . − 2 − 1) = 2 − (2 − 1) = 1

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 47/58
2s Complement Multiplication

M−2
X
M−1
Z = X × (−2 YM−1 + Yi 2i )
i=0
M−2
X
Z = X × (−2M−1 YM−1 ) + X × Yi 2i
i=0

◮ If bM−1 = 1, the final partial product should be Twos

Complement of X
◮ All intermedaite partial products should be signed
extensions of X

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 48/58
Example

1 1 0 1 -3
1 0 1 1 -5
1 1 1 1 1 1 0 1 -3 −3
1 1 1 1 1 0 1 -6 −3 << 1
0 0 0 0 0 0 0 0 << 2
0 0 0 1 1 24 2s complement of −3 << 3
0 0 0 0 1 1 1 1 15

◮ Sign extension is critical.

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 49/58
Array Multiplier
X3 X2 X1 X0 Y0

X3 X2 X1 X0 Y1
Z0

HA FA FA HA

X3 X2 X1 X0 Y2

Z1

FA FA FA HA

X3 X2 X1 X0 Y3

Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 50/58
Array Multiplier Critical Path Y0
X3 X2 X1 X0

X3 X2 X1 X0 Y1
Z0

HA FA FA HA

X3 X2 X1 X0 Y2

Z1

CP1
FA FA FA HA
CP2
X3 X2 X1 X0 Y3

Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3

◮ All path delays are almost equal

◮ Cannot optimize for one critical path

tmult = [(N − 1) + (M − 2)]tcarry + (M − 1)tsum + tand

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 51/58
Carry Save Multiplier Critical Path
X3 X2 X1 X0 Y0

X3 X2 X1 X0 Y1
Z0

HA HA HA HA

X3 X2 X1 X0 Y2

Z1

HA FA FA FA

X3 X2 X1 X0 Y3

Z2

HA FA FA FA

Z3

HA FA FA HA Vector Merge

Z7 Z6 Z5 Z4

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 52/58
Carry Save Multiplier Critical Path Y0
X3 X2 X1 X0

X3 X2 X1 X0 Y1
Z0

HA HA HA HA

X3 X2 X1 X0 Y2

Z1

HA FA FA FA

X3 X2 X1 X0 Y3

Z2

HA FA FA FA

Z3

HA FA FA HA Vector Merge

Z7 Z6 Z5 Z4

tmult−cs = tand + (M − 1)tcarry + tmerge

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 53/58
Optimized 2s Complement Multiplication

N−1
X
N−2
i M−1
X
M−2
j
Z = (−2 XN−1 + Xi 2 ) × (−2 YM−1 + Yj 2 )
i=0 j=0

M+N−2 N−1
X
M−2
j M−1
X
N−2
i
N−2 X
X M−2 i+j
Z =2 XN−1 YM−1 − 2 XN−1 Yj 2 ) − 2 YM−1 Xi 2 + Xi Yj 2
j=0 i=0 i=0 j=0

P
X3 X2 X1 X0 X = −2N−1 XN−1 + N−2 Xi 2i
Pi=0M−2
Y3 Y2 Y1 Y0 Y = −2M−1 YM−1 + j=0 Yj 2j
PN−1 i
Y0 X2 Y0 X1 Y0 X0 i=0
Y0 Xi 2
PN−1
Y1 X2 Y1 X1 Y1 X0 Y1 Xi 2i+1
Pi=0
N−1
Y2 X2 Y2 X1 Y2 X0 i=0
Y2 Xi 2i+2
Y3 X3 XN−1 YM−1 2N+M−2
PN−2
1 1 Y3 X2 Y3 X1 Y3 X0 1 1 1 i=0
YM−1 Xi 2i+M−1
1
PM−2
1 1 X3 Y2 X3 Y1 X3 Y0 1 1 1 j=0
XN−1 Yj 2j+N−1
1
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 54/58
Optimized 2s Complement Multiplication

X3 X2 X1 X0
Y3 Y2 Y1 Y0
1 X3 Y0 Y0 X2 Y0 X1 Y0 X0
X3 Y1 Y1 X2 Y1 X1 Y1 X0
X3 Y2 Y2 X2 Y2 X1 Y2 X0
1 Y3 X3 Y3 X2 Y3 X1 Y3 X0
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 55/58
Signed Carry Save Multiplier

X3 Y 1

X2 Y 1

X3 Y 0

X1 Y 1

X2 Y 0

X0 Y 1

X1 Y 0
1

X0 Y 0
HA HA HA HA
Z0

X3 Y 2

X2 Y 2

X1 Y 2

X0 Y 2
Z1

HA FA FA FA

X0 Y 3
X3 Y 3

X2 Y 3

X1 Y 3 Z2

HA FA FA FA
1

Z3

FA FA FA HA Vector Merge

Z7 Z6 Z5 Z4

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 56/58
Final Additon

◮ Vector merginig (tmerge ) is in the critical path

◮ Use a suitable fast adder to reduce the delay
◮ Carry save adder
◮ Carry select adder
◮ Carry Look Ahead Adder
◮ Make sure it fits well with the array multiplier layout

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 57/58
References

The material presented here is based on the following books/

lecture notes
1. Digital Integrated Circuits Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice
Hall India
2. CMOS VLSI Design, Neil H.E. Weste, David Harris and
Ayan Banerjee, 3rd Edition, Pearson Education
3. Prof. Vinita Vasudevan’s lecture notes on adders and
multipliers [http://www.ee.iitm.ac.in/vinita/digic.html]

Janakiraman, IITM EE5311- Digital IC Design, Module 6 - Adders and Multipliers 58/58