Received 20 February 2023, accepted 27 March 2023, date of publication 3 April 2023, date of current version 7 April 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3264016

Arbiter PUF—A Review of Design, Composition,

and Security Aspects
S. HEMAVATHY , (Graduate Student Member, IEEE),
AND V. S. KANCHANA BHAASKARAN , (Senior Member, IEEE)
Vellore Institute of Technology, Chennai 600127, India
Corresponding author: V. S. Kanchana Bhaaskaran ([email protected])

ABSTRACT Hardware security modules play a crucial role in protecting and preserving technologically
integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against
adversaries. Generally, cryptographic algorithms and security keys are quintessential for maintaining the
security of a system. Cryptography uses a secret key to encipher and decipher the data. These secret keys are
stored in a non-volatile memory that attackers can easily access. The hardware security primitive, Physical
Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices.
A PUF produces an output in response to an input based on the physical structure and intrinsic manufacturing
variations of an integrated circuit (IC). The generated random response being unpredictable, act as a robust
secret key in cryptographic protocols. The first silicon PUF is the Arbiter PUF, which can instantly produce
significantly more secret keys based on the input with a lightweight design. Due to its advantage, it is best
suited for device authentication in resource-constrained applications employing the Internet of Things (IoT).
The PUF is also suitable for applications such as the Internet of Vehicles, the Internet of Medical Things,
RFID (radio frequency identification) tags, and smart cards. In this paper, the basic Arbiter PUF design is
implemented in ZedBoard to analyze the PUF performance characteristics for 16, 32, and 64-bit responses.
A review of Arbiter PUF design, different compositions of Arbiter PUF, their individual characteristics, and
vulnerabilities against machine-learning attacks have been presented at their broader best in this paper.

INDEX TERMS Arbiter PUF, cryptography, hardware security, machine learning attacks, physical unclon-
able function, ZedBoard.

I. INTRODUCTION employed efficiently for efficient endorsement and enrol-

Industry 4.0 is a platform of boundless digitized technolog- ment to encipher and decipher the data by saving the
ical innovations. It relates, to the development of industrial secret keys in battery-backed Static Random Access Mem-
automation, privacy, and secret data exchange between con- ory (SRAM), Non-Volatile Memory (NVM) such as flash
sumer and security devices interconnected through the Inter- memory, and Electrically Erasable Programmable Read-only
net of Things and cloud computing, among other things. With Memory (EEPROM) [4]. If a cryptanalyst succeeds in infer-
Cyber-Physical Systems (CPS) set to evolve as the imminent ring the key by invasive attacks, the effect is catastrophic.
target for adversaries to be attacked through the core com- A contemporary technology that requires minimum resources
ponent of the system, it has become a challenging task for while possessing the propensity to resist attacks is essential
security professionals to safeguard the devices connected to to avoid these security problems. Efforts in that direction
CPS. have lead the research community to develop PUFs. Gassend
The authentication, authorization, and privacy of inter- et al. introduced the concept of Physical Random Function,
connected devices play a crucial role in IoT-based appli- later known as Physical Unclonable Function for reliable
cation platforms [1], [2], [3]. Cryptographic algorithms are authentication, in 2002 [5].
Integrated circuits are essentially manufactured to have
The associate editor coordinating the review of this manuscript and identical digital logic functionality so that their digital
approving it for publication was Jiafeng Xie. response to input remains unaffected. However, in the
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/
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semiconductor industry, the ICs housed in the same die incur attacks. However, the weak PUF size linearly increases to
inadvertent manufacturing variations, inter and intra-die vari- enable the extraction of more responses in tune with the
ations, doping level variations, and even a few logic pro- bit length. Each type of PUF has its own set of advantages
cess modules exhibiting different outputs for the same logic and disadvantages, and the specific type that is most suitable
functionality [6]. This unique behavior, which is even more for a given application depends on the requirements and
dominant for contemporary lower technology nodes, and usu- constraints of that application.
ally considered detrimental in the semiconductor industry, Arbiter PUF is the most extensively studied work in litera-
is being exploited in developing PUFs.This feature of PUF ture since it depends upon delay and timing information pro-
is exploited for generating its fingerprint, which is specific to vided by the ICs. In addition, they can be implemented using
the chip. IoT applications that necessitate lightweight security standard manufacturing processes, which makes them rela-
measures can integrate PUF for impenetrable security solu- tively easy to integrate into existing electronic systems. As a
tions at a lower cost factor. The paper offers a deeper insight result, they have gained significant attention from researchers
into the design, reproducibility, and security of PUFs, with a in fields such as computer security, license management, and
focus on the Arbiter PUF, its variants, and their resilience to secured communication. Rigorous researches have emerged
vulnerability. in the mathematical modeling of the APUF and its composi-
tions using Machine Learning, Side-Channel Analysis, and
Deep Learning. They motivate more research on APUF to
A. RELATED WORK make it increasingly resistant to modeling attacks.
PUFs can be classified as strong PUFs and weak PUFs based The significant contributions of the paper are as follows:
on the number of Challenge and Response Pairs (CRPs) • Understanding of the concept of PUF and its perfor-
employed [7]. Strong PUFs have a larger number of CRPs, mance characteristics with illustrative examples.
and the size of each CRP increases significantly with the • Design of a basic Arbiter PUF with emphasis on the
number of PUF circuits, and they ensure a secure environ- placement and routing of the switch block and the
ment without additional cryptographic hardware. A weak arbiter. The design is implemented in the ZedBoard
PUF, also termed ‘‘physically obfuscated key’’ [8], on the platform to evaluate its PUF metrics for the 16, 32, and
other hand, generally possesses one challenge that is used for 64-bit responses.
secured key storage. Several strong PUFs such as Arbiter PUF • Application of Arbiter PUF in security protocols during
(APUF) [6], Loop PUF [9], Configurable Ring Oscillator the enrollment and authentication phases.
PUF (CRO PUF) [10], Bistable Ring PUF (BR PUF) [11], • Elucidation of the characteristics and vulnerabilities of
Dual Mode PUF [12], and Configurable Tristate PUF (CT different compositions of Arbiter PUF.
PUF) [13] have been proposed in the literature with sig- • The mathematical modeling of the variants of APUF and
nificantly enhanced performance features. Loop PUF suf- its resilience against adversary attacks.
fers from replicating the delay chains when implemented The paper is structured as follows. Section II provides
in a Field Programmable Gate Array (FPGA) and needs a brief introduction to PUF and its metrics. Section III
more investigation for its robustness against machine learning elaborates the Arbiter PUF with a focus on design, timing
attacks. CRO PUF includes a specific inverter to the delay delay modeling, placement and routing, and typical applica-
chain based on the configuration of the challenge to the tions. Section IV presents the compositions of Arbiter PUF.
multiplexer. This delay information is easily traceable by the Section V describes the machine learning attacks achieved in
adversary to model the PUF. Comparing CT PUF to APUF, different types of Arbiter PUFs for various variants published
CRO PUF, BR PUF, and Dual Mode PUF, the modeling in the literature. Section VI concludes by highlighting the
accuracy of CT PUF utilizing an artificial neural network opportunities and future scope of research.
equals 50% [13]. Almost all the promising designs have
been successfully modeled with and without a mathematical II. PHYSICAL UNCLONABLE FUNCTIONS
model. Yet, the hardware complexity of APUF is significantly PUF can be precisely defined as a simulated physical system
lower than the other strong PUFs. using an input or challenge to generate a response or out-
Additionally, various other weak PUFs have also been put [20], [21]. Mathematically, a PUF can be defined as,
developed and studied in addition to strong PUFs. They
employ adiabatic logic [14], [15], delay-based design [16], f : Ch → R. (1)
memory-based logic [17], [18], and the metastability fea- f (ch) : r(ch ∈ Ch, r ∈ R). (2)
ture [19] to generate a secret key. These include the Ring
Oscillator PUFs (RO PUFs) [16] that use the phase delay where Ch is an external stimulus or an applied challenge, and
between the oscillation of two or more connected inverters R describes the output or response produced by the PUF.
to generate a unique response. The SRAM PUFs [17] use A PUF design is made such that replicating two identical
the inherent variations in the threshold voltages of transistors PUFs, even with extensive computational resources, becomes
in an SRAM cell to generate a unique response. The weak virtually impossible [5], [6]. The responses for the same PUF
PUFs being harder to model, are resilient to machine learning received from different ICs are unique, which acts as the

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TABLE 1. Basic symbols and notations.

FIGURE 1. Properties of PUF.

FIGURE 2. Illustrative example for Uniformity metric.

fingerprint for individual ICs. Thus, the PUF circuits are

unclonable, robust, easy to evaluate, and unique.
In silicon-based PUFs, the individual responses depend on Hori et al. [25], [26]. The evaluation parameters specified had
the hidden delay/timing feature [6], manufacturing variations one inter-device performance indicator: Uniqueness, and four
of ICs incurred even while using the same mask, uneven intra-device performance indicators: Randomness, Steadi-
wiring length, and non-stochastic doping processes [22]. ness, Correctness, and Diffuseness. Maiti et al. [27] defined
These random deviations have been modeled using Gaussian additional PUF parameters to compare different PUF models
and probabilistic distributions [23], [24]. It is impossible for of strong and weak PUFs. Inter-chip and Intra-chip varia-
an adversary to physically clone a PUF even if one acquires tions are fundamental concepts that explain variations among
all the necessary data. This is because the CRPs generated by devices or within a single device. These variations have been
the PUF cannot be described even by the manufacturer if the explained in three-axes, namely, device, space, and time [27].
process variations are high enough. If an attacker tries for an • Inter-chip variation: Inter-chip variation (HDinter ) [28]
invasive attack to study the nature of a device, it is apparent between any two different devices for the same dig-
that it invariably results in a change in the delay of the ital design PUF with a challenge vector Ch=Ch1 ,
devices or wires. Fig. 1 presents the properties of PUF, which Ch2 , . . . , Chm embedded in it can be expressed as,
determine the capabilities and limitations of the PUF and can
HDinter = P(Ri (Ch) ̸= Rj (Ch)). (3)
influence the suitability of the PUF for a given application.
Being tamper-evident and one-way mapped enables the use where Ri (Ch) and Rj (Ch) represents responses of ith and
of PUFs for security better than their counterpart security jth device, for a given challenge vector.
measures. The realizable, evaluable, and reproducible nature • Intra-chip variation: Intra-chip variation (HDintra ) [28]
of the device-level security of PUF enhances the use of the is a measure to identify the number of biased bits in R of
inherent feature of IC technology to the specific instance of length L for a given challenge in the same device.
the physical device. Physically and mathematically unclon- • Randomness Vs Uniformity: Randomness (Hn ) [26] can
able, unpredictable ensures a unique response from PUF. be well-defined as the balance of 0 and 1 in the response
Table 1 presents the basic symbols and notations used in this of PUF and can be expressed as,
paper.
Hn = − log2 max(pn , 1 − pn ). (4)
A. PUF METRICS The randomness of a bit-sequence can be described
A quantitative evaluation to explore the performance using Hn for a single device. Hn can take the maximum
of Arbiter PUF was first defined and evaluated by value 1 when pn = 0.5 and the most negligible value 0 for

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FIGURE 3. Illustrative example for Reliability metric.

pn = 0 or pn = 1. The relative frequency of appearance

of pn as 1 can be expressed as,
K T L
1 XXX
pn = bn,k,t,l . (5)
K .T .L
k=1 t=1 l=1
Uniformity (Unif ) [27] for a chip n can be evaluated
by determining the average hamming weight of the
response and represented as,
L
1X
(Unif )n = bn,l × 100%. (6)
L FIGURE 4. Illustrative example for Bit-aliasing metric.
l=1
For K different IDs,
K L
1 XX reliable response R for a given set of challenges irre-
(Unif )K = bn,k,l × 100%. (7) spective of the changes in environmental conditions such
K .L
k=1 l=1 as temperature and supply voltage [27]. A PUF can
The primary difference in the definition of Random- be reliable only if it can reproduce the same response
ness defined by Hori et al. [26] and Uniformity by (100%) despite hostile environmental conditions. The
Maiti et al. [27] is the total number of samples measured intra-chip hamming distance (HDintra ) is used to esti-
for each ID, T . Considering an example illustrated in mate the reliability metrics within a chip n by comparing
Fig. 2.a, the uniformity for an ideal PUF is expected the responses obtained at ambient temperature and nom-
to be 50%. If it is equal to either 100% or 0%, all the inal supply voltage Rn (l) with that of varying voltage and
bits in an L-bit response are either at logic-1 or logic-0. temperature R′n (l) for m samples.
As in Fig. 2.b, the hamming weight for an 8-bit response m
(11011100) counts to 5. The uniformity for the given 1 X HD(Rn (l), (R′n (l))
HDintra = × 100%. (8)
challenge (11000101) is 62.5% representing the number m n
i=1
of 1 is more than the number of 0.
• Reliability: The delay difference between the upper and The reliability of a PUF in terms of HDintra can be
lower paths ought to be significant enough to generate expressed as,
a reliable bit, albeit the delay increases with tempera- Reliability = 100% − HDintra . (9)
ture at different rates [29]. However, the delay between
two paths can intersect over the working temperature Consider an example of a comparison of PUF for the
when the path delay difference is negligibly small and ideal condition with an APUF, as depicted in Fig. 3.
increases the chance of bit flip. Reliability is a measure An ideal PUF shown in Fig.3.a generates a similar
to quantify the capability of the PUF to reproduce a output (01001100) for a given input of 11000101 for

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and is expressed as,

K L L
4 XX X
Un = (bn,k,l ⊕ bj,k,l ). (11)
K .L.N
k=1 l=1 j=1,j̸ =n

The sample mean Ū is the average of Un of all the

devices used for evaluation [25]. It is to be close to 1 to
predict that the CRPs are indistinguishable.
K X
L N −1 X
N
4 X X
Ū = (bn,k,l ⊕ bj,k,l ). (12)
K .L.N 2
k=1 l=1 i=1 j=i+1

Uniqueness can also be evaluated using Inter-chip Ham-

ming Distance (HDINTER ) between two chips, i and
j(i ̸= j), having n-bit responses Ri (n) and Rj (n). A chip
is deemed unique when the HDINTER is close to an ideal
value of 50%. The average inter-chip HD (Uniqueness)
can be expressed as in [27], U (HDINTER ) =
k−1 X
k
2 X HD(Ri (n), (Rj (n))
× 100%. (13)
k(k − 1) n
FIGURE 5. Illustrative example for Uniqueness metric. i=1 j=i+1

Fig. 5 illustrates the uniqueness with an example. Let

the responses from PUF1 and PUF2 be 01001001 and
two different temperatures, thus achieving reliability of 01100100, respectively, for a challenge of 11000101,
100%. However, in APUF, a bias exists in the output for as shown in Fig.5.a. The HD between the two responses
varying temperature conditions, as illustrated in Fig.3.b. for an ideal PUF is four, and the uniqueness equals
For the same challenge of 11000101, the HD for the 50%, illustrating the fact that the responses are unique
two responses is two, and the reliability reduces to 75% for PUF1 and PUF2. On the other hand, for the APUF
compared to the ideal PUF, indicating the PUF design is shown in Fig.5.b, for the same challenge, the HD is two,
unreliable at varying temperatures. and the uniqueness is 25%, elucidating the number of
• Bit-aliasing: Bit-aliasing for different chips is said to unique responses that are determined from an APUF is
happen when they produce similar response bits. Bit- comparatively less. The reason is that the responses are
aliasing within the chip is said to happen when homol- biased to 0 or 1 because the average delay variation is
ogous bits are biased due to static variations [27]. Both lesser than the average delay difference.
these are undesirable and is expressed as, With the background of the importance of PUF properties and
PUF metrics, Section III presents the Arbiter PUF.
N
1 X III. ARBITER PHYSICAL UNCLONABLE FUNCTION
(Bit − aliasing)k,l = bn,k,l . (10) Following the above discussions on PUF metrics as a back-
N
n=1
ground, this section presents a holistic review of the conven-
tional Arbiter PUF found in the literature. The performance
Fig. 4 elucidates the bit-aliasing for ideal APUF for characteristics of the conventional APUF have been studied
four different ICs given the challenge as 11000101. For using the programmable SoC (system-on-chip) ZedBoard
example, in Fig.4.b, consider the second bit of the 8-bit Zynq-7000 board from Xilinx® , and various PUF metrics
response; the bit-aliasing corresponds to 25%, indicating have been evaluated. This process step is followed by compar-
that the bit is more biased towards 0. One possible reason isons against other variants of APUF found in the literature,
can be inferred as an unsymmetrical physical layout of as explained in the subsequent sections. Hence, an actual
APUF resulting in delay variations and orienting the comparison of various PUF metrics pertaining to each contri-
output to generate 0, as shown in Fig.4.a. Thus, it is chal- bution by the researchers and interpretation of their designs
lenging to use PUFs as a means of securely identifying and their impact on the metrics have been made. This is the
a device, since it is possible for multiple devices to have first comprehensive study and analysis of the literature from
the same ‘‘fingerprint.’’ 2002 to the present, as perceived by the authors.
• Uniqueness: Uniqueness (Un ) [26] is a measure used Arbiter PUF [6] utilizes the property of intrinsic delay vari-
to indicate how unique are the generated IDs between ations of each device to generate a unique identity or token.
different devices. Uniqueness ought to be close to 50% It is devised to be the first silicon PUF structure and found to

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FIGURE 6. Arbiter PUF [6].

be best suited as lightweight hardware security fundamental

component. The APUF is built based on a linear additive
delay model consisting of a path-swapping switch/switch
block (SB) and an arbiter circuit. The SB, made of two
parallel 2-to-1 multiplexers (MUX), introduces the delay in
the design and has n-stages depending on the challenge length
(Fig. 6). The switch block delays are increased by adding
buffers and cross-coupling the path between the upper and
lower MUXes. The first switch block (Fig. 6) is initially
excited by a step input, and the parallel MUXes share the
rising edge. As depicted in Fig. 7, when the Ch=0, input
signals (i0 and i1 ) flow parallelly. If Ch=1, the signal path
is cross-coupled between the upper and lower MUXes, influ-
encing the wanton signal delay while traveling through each FIGURE 7. Switch block for Ch=0 and Ch=1 [6].
switch block. Finally, whichever signal reaches the arbiter
first wins the race and decides the random number value to
be a 0 or 1. The response will be 0 if the lower path signal
(o1 ) is faster than the upper path signal (o0 ) and vice-versa. more significant than the setup time of the D-FF, or else, the
output will remain at 0. A logical 1 or 0 is achieved when
the delay difference is prominent. If the delay difference is
A. ARBITER DESIGN considerably less, the arbiter enters a metastable condition,
An AND gate was initially used as an arbiter to capture the resulting in an unstable response. Since the path from D to
signal from the last SB and ascertain the response based Q and Clock to Q are asymmetrical, the output bits in a
on the edges of the two signals, and later, it was replaced D-FF are more biased. As shown in Fig. 9, RS-latch features
by a D Flip-Flop (D-FF) [6], and a Reset/Set latch (RS a symmetric propagation delay between the input and the
latch) [8]. As shown in Fig.6, when the input is applied to output that is used to reduce the bias [32]. A race condition
the APUF, the upper and lower paths pass the input signal is experienced when both the inputs S and R change from
with a specific delay based on the challenge. Let the delay high to low. To mitigate the impacts of metastability, an RS-
created by the upper and lower paths be T1 and T2 . As shown latch can be used in place of the D-FF. While implementing
in Fig.8, the delay difference, 1T = T1 − T2 will be the in FPGA, the D-FF utilizes only one Look-Up table (LUT),
input to the arbiter. Fig. 8 illustrates that the D-FF samples resulting in biased output due to uneven symmetrical routing
the response to be 1 when the positive edge of input D in either the upper or lower path. On the other hand, the use
arrives before the positive edge of input clk by a time value of a cross-coupled NAND gate for an RS-latch engages one

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in the design, along with additional interconnects. The delay

between the top and the bottom paths stands extended in the
upper path by 2 µm. An optimal sub-threshold voltage of
0.43 V has been applied based on the minimum power-delay
product value. The design model has also been verified with
a super-threshold voltage of 1.1 V. Even though the mean HD
and reliability are close to the ideal value in the proposal, the
number of CRPs considered is found to be significantly less.

C. TIMING DELAY MODEL, PLACEMENT AND ROUTING IN

FPGA
The prerequisite for modeling is the delay difference
introduced between the top and bottom path signals while
transitioning from one stage to another. Let us consider that
for stage i, the delay difference corresponding to challenge
FIGURE 8. Response based on the signal transition in D- FF [6].
bit 0 and 1 be represented as δ0,i and δ1,i , respectively [46].
The final delay difference can be easily computed if the delay
difference for every stage is calculated individually, consider-
ing crossed paths in the computation when the challenge bit
is 1. The delay difference 1Di after ith stage can be evaluated
recursively as
1Di = 1Di−1 .(−1)ci + δci ,i . (14)
where ci represents the ith challenge bit. The final output R
is calculated from the delay difference 1Dn after computing
the last delay stage n.
(
FIGURE 9. RS latch. 1 if 1Dn > 0
R= (15)
0 if 1Dn < 0

LUT for each NAND gate, thus achieving a symmetrical path The recursive delay vector w = (w1 , .., w(n+1) ) needs to be
with reduced bias in response. computed to design an efficient model for an APUF.
w1 = δ0,1 − δ1,1 , (16)
B. IMPLEMENTATION OF SWITCH BLOCK
wi = δ0,i−1 + δ1,i−1 + δ0,i − δ1,i , (17)
Considerable research contributions are found in achieving
symmetrical routing between the switching blocks. The var- and
ious configurations of SB design include employing MUX
wn+1 = δ0,n − δ1,n . (18)
primitives [33], [34], [35], Programmable Delay Line (PDL)
logic [32], [36], a 6-2 input LUT combining two parallel The total delay time of an n-stage APUF with a scalar multi-
MUX in one LUT [37], PDL and MUX without cross- plication 8 = (81 , . . . 8n+1 )ϵ {−1, 1}n+1 is given by,
coupling [38], tri-state buffers [39], and Path Changing
1Dn = wT φ. (19)
Switch (PCS) [40] focusing on response bias and enhanced
uniqueness. A Schmitt trigger has been used as a buffer APUFs require identical logic and routing for their com-
between the switch blocks instead of a CMOS (Complemen- binational paths so that the difference in delay across a
tary Metal-Oxide Semiconductor) buffer as it is susceptible defined path occurs only due to process variations. In order
to process variations in [41]. Recently, a 4 × 4 switch block to validate this fact, initially, the APUF was implemented by
has been presented instead of a 2 × 2 switch block, which the authors in a Spartan 2 FPGA device with the average
can generate a maximum of 6 responses [42]. However, it is inter-chip and intra-chip values being 1.05% and 0.10%,
claimed that the improved performance is only for random respectively. It ensures that, on average, only one response
placement. The path delay of a classical APUF has been remains unique, and the reliability of obtaining the same
transformed based on the acquired response of 0 or 1 using response is also significantly less, as also claimed in [6]. The
an adjustable module in an Adjustable APUF (A-APUF) [43]. response bits are biased depending on the relative delays of
A sub-threshold APUF [44], [45] has been designed based on the different paths through the circuit, addressing the neces-
the premise that these are more prone to process variations sity of symmetrical placement and routing of the delay paths
in 45 nm deep sub-micron technologies. The switch blocks in the FPGA. In comparison, the symmetrical placement
made of multiplexers have been replaced with NAND gates improved the inter-chip to 23% when implemented in an

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Application-Specific Integrated Circuit (ASIC) environment, TABLE 2. Uniqueness of APUF in various FPGA boards.
though it remained far from the desired value of 50% [6],
[47]. To accurately implement delay paths, FPGA requires
hard macros to integrate fixed placement and routing, and the
designer has to follow a lower level of abstraction instead of
RTL.
The responses are biased either due to the unsymmetrical
routing of instances or the architecture of the APUF model
and they can be termed implementation and architectural
biases [48], [49]. The technology node, implementation plat-
form, and external environmental factors will not affect the
architectural bias. As a result, the bias in the CRPs will
be only due to the architectural flaws of the PUF design. illustrates that the symmetrical placement of APUF in the
The implementation bias would be much influenced by the SoC board has resulted in a significantly high uniqueness of
evaluated FPGA platform that impacts the output based on 42.20% (16-bit) for 50,000 CRPs compared to other FPGA
CRPs. Different authors have handled broad categories of platforms. The uniqueness for 64-bit is 37.75% which is
placement of the SB for an APUF. While designing the MUX comparatively higher than other technology boards. The chal-
logic of the SB, one MUX primitive [33], [34], [35] from lenges were incremented by 1-bit to have a one-bit flip in the
each slice can be chosen for the upper and lower paths placed challenge, and the corresponding responses were recorded.
adjacently, thus setting the APUF instance horizontally or This customized IP design for a SOC board confirms that
vertically. Generally, in FPGA, each slice consists of four it is the most preferable one for lightweight and low-cost
LUTs in it. Tcl commands (BEL) will help fix the LUT in IoT applications, and it necessitates no additional overhead
positions A, B, C, and D in each slice. The input pins in the resources for error correction codes and fuzzy extractors.
LUTs can be locked by using the lock-pin attribute in the
Hardware Description Language (HDL) code [32]. The MUX E. APPLICATION, SECURITY PROTOCOLS, AND NIST
primitive can be replaced either by a 3-1 LUT for each MUX STANDARDS
logic or a 6-2 LUT for one switch block [37]. Each MUX/SB Physical Unclonable Functions can be used in various appli-
LUTs can be placed in one slice to have a unique token. cations due to their unique property and unclonability, rang-
If more than one LUTs are occupied in a slice while routing, ing from secure cryptographic key storage [51], [52], entity
it can result in a random placement of the switch block in an authentication [52], [53], authentication framework [54],
APUF. A random sequence of LUT for one APUF instance keyed-hash message authentication code [4], RFID tags [55],
will result in reduced uniformity [50]. Thus, it is preferable [56], [57], smart cards [5], [58], Certified execution
to place the arbiter in a separate slice. and software licensing [59], Digital rights management,
set-top boxes, and distributed computation [6], and IP
protection [60].
D. IMPLEMENTATION IN ZedBoard The demand for an increased number of heterogeneous
To validate the APUF, we have implemented it as a cus- devices in the IoT has also raised concerns for its secu-
tomized IP formed in the ZedBoard using a 3-1 LUT for rity. Hence, the IC vendors exploit resource-constrained
a MUX configuration, as shown in Fig.10. The upper and hardware-based technology solutions to secure IoT devices.
lower paths are symmetrically placed in the adjacent slices The usage of PUF in security protocols has also gained more
to enhance the manufacturing variations. Fig. 10 illustrates importance due to its lightweight structure and more CRP
the design of APUF as a customized IP (Intellectual Prop- space. The PUF models integrate additional techniques to
erty) to communicate between Programmable Logic (PL) obfuscate the challenge and hide the responses from mali-
and Processing System (PS). Using Xilinx SDK (Software cious attacks. Different authentication protocols [6], [59]
Development Kit), the challenges were given to the APUF, have been proposed to secure the secret key generated by
and responses were received. Pre-processing of responses the PUF employing fuzzy extractors and error correction
to evaluate the PUF parameters was realized using MAT- code [52] in providing reliable CRPs.
LAB. The APUF was designed for 16-bit, 32-bit, and 64- The security offered by the protocol increases as the prover
bit challenges, and responses of similar size were achieved. and the verifier can opt for more CRPs while using APUF.
The PUF metrics, namely, uniqueness, uniformity, and reli- Furthermore, the used CRPs are discarded after successful
ability, have also been evaluated. The uniformity of APUF authentication and updated with a new set of CRPs, which
is evaluated to be 63.65%, 63.78%, and 53.76% for 16-bit, is a tremendous advantage of using APUF. Table 3 shows the
32-bit, and 64-bit challenges. Thus, the responses of the various protocols that use APUF and its variants for secured
basic APUF are more biased towards 1. The reliability for authentication. It presents a glimpse of a few protocols. The
16-bit, 32-bit, and 64-bit challenges are 98.86%, 99.52%, Two-Stage Multiple-Choice Arbiter-based PUF (TSMCA
and 97.96%, validating a reliable random output. Table 2 PUF) proposed in [2] uses bi-directional authentication to

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FIGURE 10. Customized IP design of APUF connected with ZYNQ processing system.

TABLE 3. Security protocols used in authentication using APUF. model to produce a response to the unexpected challenge. The
steps are as follows,
• Exchange of PUF IDs and initialization messages
• Verifier sends a pseudo-challenge C1 to the prover
• Prover transforms C1 to dynamically generate pseudo-
challenges C2 and C3 based on the transformed response
(RV )
• Creation of unique secret patterns (g)
• Verifier searches for the matches of the secret pattern
received with any secret patterns specific to the particu-
lar device
The communication protocol in [62] has three phases,
viz., enrollment, authentication, and update, to authorize the
prover device as shown in Fig. 12. It is illustrated as follows:
• Enrollment:Trusted party delivers an initial message to
the server and the authenticating device
• FSM in the authentication server model responds to the
message
• Quadruple challenge is issued to the APUF and the
majority voter to generate a reliable 8-bit response
• APUF model is built using a tripartite classification
algorithm
• Authentication:Device and the server communicate with
each other to confirm authorization
improve the resilience between the server and tag and vice • Server acknowledges the device request by providing a
versa while authenticating RFID devices. The PUF has been random number (RN )
embedded in the RFID tag and provides the seed as a pass- • Random number produces a quadruple response in the
word to the random number generator to generate challenges. device using the PUF model (RF )
During authentication, the responses get verified by a string- • The server generates the response (RM ) for the same RN
matching method. using a software PUF model
In [61], a lightweight PUF-based authentication protocol • Device is authorized only if both responses are equal
utilizes APUF for authentication between the prover and • Update:After a fixed number of successful authentica-
verifier as shown in Fig. 11. The authentication protocol con- tion attempts, the relevant parameters are periodically
siders that the prover and the verifier possess the PUF circuit updated from memory during the update phase.

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FIGURE 12. Authentication protocol [62].

number is the most challenging part of the cryptographic

process. The random numbers used as private keys, public
keys, nonce, and block padding are generated using a True
Random Number Generator (TRNG) and a Pseudo-Random
Number Generator (PRNG). The malicious adversaries can
impersonate the random number generated through various
invasive and non-invasive attacks. The quality of random
numbers is tested using the statistical test, National Institute
of Standards and Technology (NIST) test-suite [73]. NIST
has 15 tests to evaluate the randomness of the bit string. Any
RNG must pass the NIST 800-22 test for commercial accep-
tance, though the NIST does not provide any suggestions for
designing the RNG.
FIGURE 11. Authentication protocol [61].
Random number generation using PUF has also gained
more importance due to its unpredictability and its robustness
Lockdown protocol of [68] deploys XOR-APUF to secure against malicious attacks in producing random numbers [74],
authentication for lightweight applications on the server side. [75], [76], [77], [78], [79]. As discussed in the previous
BST-PUF (Bit-Self-Test PUF) uses the reliability flag value section, the basic APUF produces random outputs, which
as helper data during the registration and recovery phase depend on timing and delay information. The responses thus
without additional logic [69]. It embeds a delay module to achieved are easily predicted using machine learning (ML)
set the threshold value based on the delay difference and algorithms due to their increased noise level content. Hence,
raises a reliability flag to determine a reliable response. PUF- the basic APUF successfully passes only a part of the NIST
FSM (Finite State Machine) [70], [71] proposes a method test. Various techniques are adopted to generate a random
that realizes CPUF without helper data and error correction number to pass the NIST test. The APUF-based TRNG [74]
code. The responses from the APUF have been combined uses a single incoming request to generate a random output.
with FSM and a random number generator. This approach is The PUF output is produced after several iterative processes
claimed robust by the author against reliability-based attacks to identify a meta-stable challenge that gives unpredictable
and the most suitable for authentication. The other strategy results. The PUF output corresponding to the meta-stable
for authentication is by using the remote configuration of challenge goes through a post-processing procedure using a
APUF on FPGA [72], which means that the PUF is not Von Neumann corrector to extract randomness.
physically available before authentication. In [75], the author presents a TRNG by introducing
The cryptographic applications and the protocols rely on non-linearity using APUF in the non-linear feedback shift
the random numbers generated by the Random Number register. The stability of the responses are improved by
Generator (RNG). Securing the unpredictable random comparing the signals from the last switch block using two

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cross-coupled arbiters. The output from TRNG is considered

valid only if the two arbiters acknowledge the output. RNG
undergoes extensive tests when designed, after production,
and in-field for validation. Statistical tests, online health tests,
and known answer tests (KATs) are general tests performed
to verify the stability of RNGs. In [76], KAT is used to test
the TRNG designed using APUF. KAT is performed in-field
during power-ups. For a known input, the output from the
TRNG is validated only if the output for the given input is
the same, or KAT will not be detected.

IV. VARIANTS OF ARBITER PUF

In this section, different variants of APUF are discussed in
terms of their performance, the robustness of the design, and
their resilient nature against adversary attacks.

A. NON-LINEARITY AND RECONFIGURABILITY IN AN

APUF MODEL
1) FEED-FORWARD APUF (FF-APUF)
The linear delay model of APUF has been used to design a
software-cloned APUF. The adversaries were able to build the
FIGURE 13. Feed-Forward MUX PUF (a) overlap (b) cascade and
delay models to determine the CRPs by reverse engineering. (c) separate structure [82].
In the Feed-Forward APUF (FF-APUF) [80], the challenges
to the intermediate stages of the switch blocks originate from
the feed-forward arbiter itself instead of the user issuing register) [57], hash functions [59], and obfuscating the
them. Note that it is essential for the challenges to reach responses [82]. Authors in [82] propose reconfigurable PUFs
the corresponding switch component before the delay signals to increase the reliability and security of the PUF perfor-
reach. Non-compliance can lead to bias in the final output. mance during authentication without altering its properties
The addition of the feed-forward arbiter for obfuscating the by 1) reconfiguring CRPs without configuring PUF and
challenges reduces the reliability and makes it resilient to 2) reconfiguring the PUF, thereby making CRPs reconfig-
modeling attacks. urable. Reference [83] secures against the ML attack on
Introducing non-linearity in FF-APUF does not result APUF by applying partial reconfiguration and the tribes
in achieving a unique identity. With heterogeneous types function.
of FF-APUF and XOR in [81], significant improvements Reconfiguring the FF-APUF overcomes the problem of
in uniqueness and enhanced resilient property to adversary degraded reliability. The Feed-Forward structure [80] does
attack have been proven. In the homogeneous approach, the not specify the feed-forward point in the design. Fig. 13
FF-arbiters are placed identically after a particular stage in depicts the three reconfigurable feed-forward MUX PUF
each APUF instance, while the arbiters are placed arbitrar- structures [82], viz., 1) Feed-Forward Overlap (FFO), where
ily in the heterogeneous approach. The authors claim that the feed-forward arbiter is added after every five to eight
placing the FF-arbiter close to the last switch block degrades stages so that the challenges from the feed-forward reach
its performance. For security analysis, FF-XOR PUF has before the delay signal traverses to it and with one stage over-
been simulated as a black box using ANN (Artificial Neural lap between every two feed-forward paths, 2) Feed-Forward
Network), and the results demonstrate that these models are Cascade (FFC) where the final stage of one feed-forward
proved resilient when the number of FF-APUF instances arbiter acts as the starting stage of another feed-forward path,
in the design is greater than 5, with a prediction accu- and 3) Feed-Forward Separate (FFS), with no overlap or
racy of 50%. Different security analyses have been carried cascade of feed-forward paths.
out using Logistic Regression (LR), ANN, and Covariance The Modified Feed-Forward MUX PUF (MFF MUX
Matrix Adaptation-Evolution Strategy (CMA-ES) for more PUF) [84] architecture has been proposed in continuation
than 100 x 103 to a 1 million training sets, and authors with his previous work [82] by Lao and Parhi In this PUF
conclude that the heterogeneous FF-XOR PUF is more secure design, the feed-forward arbiter output was given as a chal-
than the standard XOR PUFs. lenge to two successive MUX stages with feed-forward
arbiter connected in overlap, cascade, and separate structures
2) RECONFIGURABLE APUF (MFFO, MFFC, MFFS). With no improvement in security,
CRPs are reconfigured by different approaches, such the reliability has been enhanced in the modified design
as adding reconfigurable LFSR (linear feedback shift compared to the feed-forward MUX structure.

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FIGURE 14. Dynamically Configurable Hybrid PUF [85].

In Dynamically Configurable Hybrid (DCH) PUF [85],

LFSR has been used to configure the APUF to generate the
response. As a result, different response bits are obtained
depending on the configuration signals. The configurations
can be enhanced based on the LFSR bit length, which raises
the computational complexity of a modeling attack. The
author of [85] has also proposed configurable self-XOR (DC
SX-APUF) and configurable Feed-Forward (DC FF-APUF)
structures. In the former, the intermediate signals from vari-
ous switch blocks are fed to the feed-forward arbiter and then
FIGURE 15. Inter-chip and Intra-chip variation of APUF and variants of
to the MUX. Based on the configuration signal of the MUX, FFAPUF.
the output of the MUX is XOR-ed to generate the output. This
result is XOR-ed with the APUF output to determine the final
1-bit response. The resource utilized by this model is compar-
atively less compared to the n-XOR PUF. The DC FF-APUF
is similar to FF-APUF with an additional MUX added at the
output of the Feed-Forward with configuration signal. The
DCH PUF shown in Fig. 14, combines these two designs with
one branch of self-XOR and two Feed-Forward overlapped
structures. For an n-XOR model, only one LFSR has been
used to produce the configuration signal. Fig. 15 demon-
strates that introducing non-linearity and reconfigurability to
the basic APUF has improved the parameter, however, failing
to satisfy the primary goal of improved inter-chip and intra-
chip variations (ideal value 100%). The reason can be the lack FIGURE 16. PDL based switch [36].

of control over the placement and routing of parallel paths and

feed-forward arbiter. In comparison, the DCH PUF model has
shown a significant improvement with a uniqueness of 41% n-input LUT can be configured in which the LUT inputs
(ideal value = 50%), which can be studied further. However, other than the first one were used as don’t-care bits. The
it may be noted that experimental validation is realized only don’t-care inputs will regulate the propagation of signals
for a 7-bit response. inside LUT. The output of LUT is the inverted value of the
first LUT input. Instead of path-swapping structures, new
non-swapping switch structures are designed using two PDLs
B. UTILIZING THE FPGA ARCHITECTURE TO ENHANCE (SU and SL ) as shown in Fig. 16.a. Fig. 16.b shows the
SYMMETRICAL ROUTING equivalent circuit of the non-swapping switch structure with
1) PDL LOGIC the nominal delay values of ‘a’ and ‘d’ and the crosswise
To meet the symmetrical routing requirements, the MUX paths of ‘b’ and ‘c’ are identical.
logic in the FPGA was replaced by PDL with a single The structure of Programmable delay lines based APUF
LUT [36]. PDL was used to fine-tune the delay skews caused (PAPUF) [36] realized using PDL consists of N switch com-
by irregularity in signal routing. To implement PDL, any ponents and K tuning blocks. The PDL was fine-tuned using

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FIGURE 17. Flip-Flop APUF [86].

the delay characterization technique to obtain a maximum APUF. The cross-coupled NAND arbiter has been chosen
delay for different input patterns. The tuning blocks are free over the D-FF since it contributes a 10% skew to the routing
to be located at any place in the structure of PUF. Depend- path. Thus, Flip-Flop APUF shown in Fig. 17 uses only
ing on their selector inputs, these tuning blocks can insert 44 slices to generate a 1-bit response compared to 129 slices
additional delays in the top or bottom paths. The significant for a 64-bit challenge for an APUF design by saving 66% of
difference between the switches and the tuning blocks lies hardware resources.
in the connection of selector lines. The selector lines are The flip-flops are initially reset by CLEAR and then
standard for upper and lower paths, while in tuning blocks, enabled by the rising edge of the clock signal using START.
the upper and lower paths have different selector lines. The At the end of the three MUXes for every slice, the output
top and bottom paths and the arbiter have been symmetri- will select any of the four FFs to determine the delay path
cally routed. The tuning blocks also eliminate the bias in corresponding to the given challenge. The output from each
the delay. The design is evaluated for the same challenges, upper or lower path (TU or TL) of the PUF cell becomes an
and the responses have been obtained after majority voting input to the clock port of the next PUF cell. It continues till
to improve reliability. It enhances the response robustness the last stage, and its output is fed to the arbiter with the
and alleviates the meta-stability problem of the arbiter. The response bit generated based on the racing signal entering
author has also arrived at a new hypothesis that the responses the arbiter. The design [80] has also been evaluated for min-
were robust when the delay difference is found to be more entropy, conditional Shannon entropy, and conditional min-
significant at the arbiter input. entropy, as found to be 0.54, 0.90, and 0.61, respectively.
Additional delay incorporated into the Flip-Flop APUF
2) FLIP-FLOP BASED APUF DESIGN in FOXFF-APUF (Feedback Oriented XORed FF-APUF)
Flip-Flop APUF proposed by Gu et al. inserts additional slightly improves the uniqueness of an 8-bit challenge [88].
delay and symmetrical routing to increase the uniqueness This design introduces a delay before and after the third MUX
with four flip-flops and three MUXes in place of a single using a D-FF with feedback. Two configurations have been
MUX structure in APUF [86], [87]. The design reduces proposed, the first with three challenges as input and the
resource utilization significantly since the number of chal- second with only one challenge as input. The author verifies
lenges is increased three times compared to the conventional the uniqueness in Spartan-3 and Virtex-6 FPGA boards for

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FIGURE 19. DAPUF [33].

FIGURE 18. XOR APUF [52].

switch blocks and 6 arbiters, and the 6-bit output generated

an 8-bit challenge, concluding that it was better than the by the SR latch is XOR-ed to generate the final 1-bit response.
Flip-Flop APUF. The above results imply that the Flip-Flop The author has compared the DAPUF design with APUF,
APUF and FOXFF-APUF have shown better results than the which has the same set of responses being generated. The
conventional APUF design. This design requires fewer slices uniqueness results are thus improved for 2-1 DAPUF and
than APUF, which can reinforce the lightweight design focus. 3-1 DAPUF compared to 2-1 and 3-1 APUF by 41% and
Despite the trade-off for uniqueness and resource utilization, 50%, respectively. However, the performance of 2-2 DAPUF
the inclusion of tuning blocks and symmetrical routing in was found to be inferior to 2-2 APUF. At the same time,
PAPUF realized enhanced uniqueness for 90 nm compared Component-differentially-challenged XPUF (CDC-XPUF)
to 28 nm FPGA, though with increased resource utilization employs different challenges for each APUF instance [91].
than Flip-Flop APUF. Due to the improved uniqueness of the DAPUF model, var-
ious APUF variants have subsequently been designed on its
C. ROBUSTNESS TO MODELING ATTACKS premise. The Dual APUF discards the unreliable response to
The primary consideration while designing a new variant of improve the reliability by incorporating two additional paths
APUF would be the symmetric layout, augmenting the impact to determine the delay difference and filter out the incon-
of intrinsic variations to improve the uniqueness [89], thus sistent responses with lesser delay difference [92]. In Multi-
increasing the reliability against temperature sensitivity [90]. Block APUF (MB APUF), n-stage APUF has been divided
into two or four blocks with different voltages for each
1) REPLICATING APUF INSTANCES block to achieve enhanced entropy without increasing area
Cryptography exploits the XOR function to generate a ran- and power consumption, compared to DAPUF [22]. In Two-
dom number with an equal probability of 0 and 1. In that Stage Multiple-Choice Arbiter PUF (TSMCA PUF) shown
direction, to increase the randomness of APUF significantly, in Fig. 20, the reconfigurability has been achieved by con-
n-APUF instances are connected in parallel and their out- necting the switch block and the arbiter with a 5-1 MUX [2].
puts are XOR-ed to produce a 1-bit response (XOR APUF) The select lines of the MUX receive a part of the challenges.
as depicted in Fig. 18 [52]. The embedding of XOR logic The output from the MUX undergoes XORing and character
also obscures the outcome of each APUF instance. As n padding operations to produce the response. The MA-PUF
is increased, the computational time required to attack the (Mixed Arbiter-PUF) generates a response by integrating an
XOR APUF increases. The addition of XOR, however, intro- additional two 4-1 MUX with four switch blocks between the
duces non-linearity, at the cost of reduced reliability since it switch block and the arbiter to reduce the resilience against
involves n APUF instances. modeling attacks [93].
Double APUF (DAPUF) shown in Fig. 19 incurs less bias The drawback of Yilmaz et al. [64] proposal is that it
than the basic APUF, and hence the uniqueness is compara- cannot be utilized to authenticate a time-critical system, due
tively better than the conventional APUF [33], [34], [35]. The to the fact that along with the selected APUF configuration
SB for the n-bit challenge has been duplicated for DAPUF file, the challenges to FPGA also are needed to be sent.
and a hardcore MUX primitive has been used in the design. Furthermore, the CRPs have been generated from a single
The significant difference between the XOR APUF [52] and APUF, so that the adversary can quickly rebuild its tentative
the DAPUF is the cross-connections from the switch blocks model with known CRPs. Sahoo et al. have presented a
to the arbiter and the response generated. In DAPUF, the Multiplexer-based APUF (MPUF) of Fig. 21.a, in which the
input signal, and the output of the last switch block entering output of primitive APUFs is given as an input to MUX to
the arbiter are cross-coupled. The outputs from the arbiters achieve the final response [94]. Implementation of MPUF
are XOR-ed to produce the final response as depicted in increases area utilization. However, this also enhances the
Fig. 19. Similarly, the 3-1 DAPUF is designed using three computational complexity, necessitating each APUF instance

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FIGURE 22. MXPUF [97].

FIGURE 20. TSMCA PUF [2].

FIGURE 23. APUF with FDL [98].

It has two layers, identified as the upper and lower layers,

as shown in Fig. 22, and the PUF is intended to be more
resilient to measurement noise due to the feedback. The
upper and lower layers comprise an n-bit x-XOR APUF
and (n + 1)-bit y-XOR APUF, respectively. For a given n-bit
challenge Ch, the responses generated by the upper layer
have been interleaved in the middle of n-bit challenge Ch to
construct a new lower layer that generates the final response
bit. The reliability of (x, y)-MXPUF was found to be twice
that of the (x + y)-XOR APUF and less secured against
FIGURE 21. (a) (n, 2)-MPUF [94](b) (n, 2)-cMPUF [94]. Becker’s attack.
A Fault Detection Logic (FDL) proposed in [98] helps
detect the run-time alteration caused by fault injection in the
to be extensively studied by the adversary while modeling the PUF instances as depicted in Fig. 23. Fault injection can be
design. To make the MPUF robust against reliability-based stuck-at 0 faults in the arbiter (clock input of D-FF), which an
modeling attacks, a new variant, rMPUF has also been pre- attacker can add to the last switch block. FDL has three inputs,
sented [95]. In rMPUF, the selection inputs generated by viz., Enable (EN ), ytop , ybot , and output Y . If the value of Y
independent APUFs are given to 2:1 MUXes. The selection is 1, then the response obtained from that particular APUF
input for APUFs is modeled sequentially along the path from instance indicates the absence of fault, or else, the presence
the input to the response. The rMPUF has good reliability and of a fault. Adding FDL to the APUF instances makes it hard to
security properties with a trade-off in the cost of hardware introduce a fault in determining the CRPs by the adversaries.
overhead due to the large increase in the number of APUFs. The APUFs are combined parallelly to an XOR APUF to
Another variant of basic MPUF is the cMPUF depicted in increase the number of challenge bits, thereby increasing the
Fig. 21.b designed to be resistant to linear cryptanalysis [96]. uniqueness and the data complexity with reduced reliability.
To avoid the linear approximation between the response and The reliability of the design is reduced due to the addition of
data inputs connection pattern, half of the data inputs of MUX parallel instances of APUF.
have been complimented. It aims to introduce 50% noise in
training CRPs. Thus, it becomes hard to model the cMPUF by 2) PRE-PROCESSING THE CHALLENGES AND OBFUSCATING
the adversaries. Reference [94], has all the theoretical find- THE RESPONSES
ings validated using MATLAB, without any implementation • Obfuscating both challenge and response: The
in the FPGA board for the design verification. Lightweight Secure PUF (LSPUF) illustrated in Fig. 24
The divide and conquer approach used in reliability-based transforms the challenges and the responses obtained
modeling has successfully modeled the XOR APUF. The from the APUFs [58], [99]. The challenges to the APUF
challenges of the XOR APUF are obtained from the responses embedded in LSPUF are fed using XOR logic to satisfy
of another XOR APUF to protect against the above-said the Strict Avalanche Criterion (SAC). According to
attack in Multiple XOR PUF (MXPUF) [97] and iPUF [37]. SAC, even if one-bit flips in the challenge, each response

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trailing binary bit to convert to 130-bit challenges. These

challenges are non-linearly processed using a register
(C-REG) with N number of T Flip-Flops (T FF) thus
producing a robust challenge set. Randomized Arbiter
PUFs (R-APUFs) obfuscate the CRPs by exploiting the
randomizing property using ‘‘Shamir’s secret key’’ algo-
rithm to reconstruct the polynomials, thus resulting in
increased robustness [53].
The tripartite classification algorithm [62] has been
used to build an accurate APUF model to segregate the
CRPs. The CRPs segregate into five classes: unstable,
meta-stable zero, meta-stable one, stable zero, and sta-
ble one. The built-in logic observer (BILBO) module
breaks the linear dependency between the challenge
FIGURE 24. LSPUF [99]. and response mapping. The input challenge and the
quadruple response have been obfuscated in this way.
After ascertaining the response stability by repeating
bit ought to flip, with a 50% probability. The challenge each quadruple challenge, the data are fed into the
bits for multiple APUFs have been given in a circular Deep Neural Network (DNN) for training. Then, the
shift using an interconnect to satisfy SAC. The responses DNN is trained to model two different path lengths of
from several rows of APUF are combined using XOR APUF, N =24 for short APUF and N =128 for stan-
logic. These aim to improve the randomness of the dard APUF. The APUF model at the authentication
responses and fortify them against reverse engineering. server does not require helper data or raw CRPs to
However, the XOR logic for obfuscating necessitates be stored externally. Hence, it significantly increases
more resources to cater to the number of switch blocks its resistance against modeling attacks. In Obfuscated
and the responses. Challenge APUF (OC-APUF) [103], the server sends
PUF presented as Random Set-based Obfuscation the challenges to a challenge obfuscation module before
(RSO) utilizes the stable PUF responses obtained from authentication. The obfuscated challenges will be sent
the PUF and pre-stores them as a set for obfuscation to the OC-APUF, where the original challenges are
in [65]. Initially, a few stable CRPs of the PUFs are col- retrieved with the help of a recovery module, and
lected and stored in NVM using DMA (Direct Memory the corresponding responses get generated. Similarly,
Access) from the testing phase. In the second stage, the in the Challenge Pre-Processing APUF structure (CPP-
stable challenges stored are applied as input to the PUF APUF) [104], a CPP structure with a 4-input modified
circuit. The responses from the PUF get temporarily RS flip-flop is found embedded to mask the original
stored in registers that would later be utilized as a subset challenge.
for obfuscation, followed by a TRNG, which selects The Current-Starved Inverter APUF (CSI-APUF) [102]
two keys to obfuscate challenges and responses with has been proposed with NMOS-based CSI, biased
XOR operations. RSO-based APUF has been proven to at zero temperature coefficient points. As a result,
be resilient against machine learning attacks. Even if temperature-induced response bit flip will significantly
the adversary successfully collects 1 million CRPs, the decrease, thus improving reliability characteristics. The
threshold limit set in this method automatically updates current required to charge and discharge the CSI is con-
the CRPs. Finally, the obfuscated response is used for siderably smaller than the basic inverter. Therefore, the
authentication in the fourth stage. The prediction accu- manufacturing variations have been more pronounced
racy for 64 × 64 APUFs with a set size of 32 and 1 mil- in the CSI, increasing the delay difference between the
lion CRPs demonstrates that an adversary can manage upper and lower paths. The 64-bit Fibonacci LFSR pro-
with only a random guess. vides the necessary input challenges to the APUF. The
• Obfuscating the challenges: Non-linear masking of D latch has been replaced with a pair of RS-latch, with
original challenges has been proposed with two-party an AND gate connected to an active low enable input of
authentication using a C-REG in [100] and Multi- the second stage of RS-latch to act as an arbiter as shown
ple Input Signature Registers (MISR) in [101]. In the in Fig.25 to reduce the systematic bias. It also helps in
former, the challenges have been classified as weak reading a stable response bit from APUF.
and strong, based on their vulnerability to influence a The Dual LFSR PUF [57] combines a Randomness
response bit to flip without adding any additional hard- Adjustment Module to generate a masked challenge as
ware cost. 128-bit weak challenges are initially gener- an input. This module enhances the randomness and reli-
ated using a pseudorandom sequence generator in the ability by counting the number of zeros from the arbiter.
host machine, which is then padded with a leading and The counting is initialized using the RST key on FPGA.

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FIGURE 25. Arbiter in CSI-APUF [102].

If the number of zeros is not close to 50%, the delay

is included in the path to make it symmetric using the FIGURE 26. Performance parameters of the variants of APUF after
compensation circuit module. The reliability of APUF pre-processing the challenges and obfuscating the responses. The values
that are not defined are shown as NA.
gets strengthened by directing the output of the arbiter to
the voter and the XOR module, followed by extraction
of the response bit. Two Galois LFSRs are added to
obfuscate the challenge in a time-variant approach to
prediction accuracy of <65% due to the use of an obfuscation
make the PUF more robust during authentication against
technique rather than classical APUF, which had a prediction
man-in-the-middle attacks. Both the LFSRs depend on
accuracy of 100%.
the response from the APUF. The challenge to the APUF
is from the first LFSR when the response is 0, or else,
from the second LFSR. Moreover, the author does not D. COMBINING BASIC PUF MODULES AS SMALL
discuss the security analysis of the design. BUILDING BLOCKS
Multi-PUF [105] and MMPUF (MUX-based Multi- Yet another prototype in the design of PUFs is the Composite
PUF) [106] designs propose to obscure the challenge bits PUF [109], [110], which employs smaller PUFs as design
with a weak PUF design. Both use Pico PUF to obfuscate blocks. Composite PUFs have larger CRPs and reduced
the challenges of the strong APUF [108]. They differ in resource overhead with improved performance than the con-
the way Pico PUF gets connected to the APUF. In Multi- stituent PUF models generating the same CRPs. The authors
PUF, the original challenge and the output from weak in [16] provide a theoretical framework to choose the best
PUF are XOR-ed, and the masked challenges are pro- possible PUF composition of RO PUF, and APUF to improve
vided to APUF. On the other hand, in MMPUF, the MUX PUF parameters significantly. The delay lines of APUF are
receives a response from two Pico PUFs, and the original replaced with RO PUF in S-ArbRO PUF to enhance the
challenges are fed to the selected signals. The probabil- number of CRPs [111]. The Mem-APUF [112] is a digitized
ity of 0 and 1 is comparatively higher in MMPUF than in version of the APUF that resembles the behavior of the APUF
Multi-PUF. Even though the uniqueness has been signif- realized by integrating a weak PUF circuit with fixed-point
icantly improved in both designs compared to classical arithmetic. Splitting attack on iPUF [114] has motivated the
APUF, it does not fit precisely in the normal distribution design of an LP-PUF (composite PUF) [113], which com-
curve. While discussing the security, it is shown that as bines an FF-APUF and iPUF compatible with CMOS design.
the challenge bit length is increased, the prediction rate Table 4 summarizes Section IV based on the technol-
for Multi-PUF also increases, whereas, for MMPUF, it is ogy design environment employed, performance parameters
less than 59%. Similarly, MMPUF prediction accuracy and methods adopted to improve PUF characteristics, and
ranges from 52% to 74% when Support Vector Machine security analysis conducted in the respective literature. The
(SVM) and CMA-ES are used. However, the prediction conventional APUF designed with a linear additive delay
accuracy increases as the CRP size increases (64 and model suffers from poor uniqueness. The explanation is that
128-bit). the lack of symmetrical routing results in reduced latency
Fig. 26 illustrates that masking the challenges and between two paths. Adding many instances of APUF and
responses in RSO-PUF, MISR-APUF, and CPP-APUF has XOR functions to the basic APUF design model has reduced
significantly improved the uniqueness by almost near to the bit-biasing towards 1 or 0. Thereby, the unique ID of each
49%, while CSI-APUF, Multi-PUF, MMPUF, and CMPUF device is enhanced with increased uniqueness and reliability
have uniqueness greater than 40%. The obfuscation technique in DAPUF, XOR APUF, TSMCA PUF, and MPUF. Fur-
increases the complexity to the adversary since the input ther, obfuscation of the challenge and response of an APUF
or output dataset required for training the algorithm is lost. improves the uniqueness near the ideal value of 50% by mak-
Hence, LR analysis for the above-said design has a reduced ing it more difficult for an attacker to predict, or reproduce the

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outputs of the APUF based on knowledge of the challenges In the last few decades, adaptations of the XOR function in
and responses. the design of APUF compositions have become inevitable for
enhanced security due to the increased computational com-
V. MODELING ATTACK plexity. Reference [115] has experimentally verified that an
Software modeling builds a numerical model of PUF using exponential increase of XOR function enhances the rigidity
a computer algorithm with knowledge of datasets. In non- of XOR PUFs against attack, however, trading-off reliability
invasive attacks of APUF, presume that Bob, an adversary for the resource. Interestingly, Tobisch and Becker [46], [95]
has obtained a few sets of CRPs and the adversary can design invalidate this claim by performing a cloning attack on a com-
a numerical model with delay value and CRPs. In that case, mercially available RFID tag with a 4-way XOR PUF model
developing the PUF model is possible, which is subjective to using divide and conquer approach in the Reliability-based
ML attacks. CMA-ES and LR with R-prop algorithm. Reference [116]
Mathematical modeling of APUF, XOR APUF, and finds ML attacks still successful while using obfuscated
LSPUF [115] have been discussed in brief under this section. response bits by extracting the necessary information from
padded strings and helper data. CMA-ES has been used to
A. MATHEMATICAL MODELING OF APUF attack Slender PUF and reverse fuzzy extractor-based proto-
The linear delay additive model is used to design the APUF. cols that use PUF to create secret keys in [116]. It emphasizes
The final delay difference (1) between the top and bottom the need for protocols to be robust enough. Recent research
paths for an n-bit APUF can be expressed as, focuses on using Deep Learning (DL) [117], [118], genetic
programming [119], and ANN [120], [121] based techniques
1=w
⃗ T φ.
⃗ (20) to model the design with reduced error and improved predic-
The parameter vector w ⃗ and feature vector φ⃗ are of n + 1 tion accuracy of 64-bit and 128-bit CRPs.
dimensions. The vector w ⃗ includes the delays from all the
multiplexer components in the APUF stages. The feature D. MODELING ATTACK ON APUF
vector φ⃗ is a function of the input challenges. The response APUF remains the focus of most modeling attacks since
(R) of APUF is dependent on the sign of 1. The response it is the primary building block for analyzing attacks on
R = −1 when the APUF output is 0 or else, R = 1. APUF variants. Non-invasive, semi-invasive, and mathemati-
cal modeling attacks are used to extract the CRPs from APUF.
⃗ T φ).
R = sgn(1) = sgn(w ⃗ (21)
1) SIDE-CHANNEL ATTACK
B. MATHEMATICAL MODELING OF XOR APUF
Side-channel attack (SCA) is one of the most prominent
The XOR APUF is modeled with m APUFs in parallel, each
non-invasive attacks used to determine the secret key from
consisting of n stages. A set of similar challenges are applied
a PUF model [122], [123]. For every input and output in
to all the APUF instances, and their responses are XOR-ed to
the PUF design, FPGA implementation employs a register.
generate a final response. Mathematically, the response from
These registers serve as the data source for the power trace
each instance can be given as Ri ϵ {−1, 1}. Hence, Qfor an analysis. SCA depends on the architecture of PUF as well
m-XOR APUF, the final response becomes RXOR = m i=1 Ri . as the pseudo-random functions. In [123], using correlation
The mathematical model with the parameters and feature
power analysis, SCA is performed on LSPUF to collect the
vector of m-XOR APUF is written as,
CRPs. Two approaches were focused on the register that
m
Y stores the result of the XOR operation. The first method
RXOR = ⃗ Tl φ⃗l ).
sgn(w (22) recovers the hamming weight of the targeted register, and
i=1
the second obtains the difference of mean-based Differential
C. MATHEMATICAL MODELING OF LSPUF Power Analysis (DPA).
The LSPUF is also similar to m-XOR APUF, with the dif-
ference in introducing the challenges. As mentioned in Sec- 2) PHOTONIC EMISSION AND LASER-BASED TECHNIQUES
tion IV, the challenges to the LSPUF are delivered in a These techniques collect the CRPs from the FPGA using pho-
circular shift, and the output bits are XOR-ed to generate a tonic emission [124], and fault injection [125] from individ-
multi-bit output response denoted as out1 , out2 , .., outj . This ual APUF instances. An intrusive attack on the APUF [126]
approach can challenge the adversaries in extracting the exact successfully detects the CRPs with a high-resolution time
single-bit output. of 6 ps and assists in determining the internal timing delay
The design parameters for LSPUF are (i) the number of between each stage. This analysis also demonstrates that
output bits (r), (ii) the values that affect the single output bit APUF can be modeled even without a minimal number of
response (l), and (iii) the circular shift in choosing l values. CRPs. This technique measures the time delay between the
For n = 1, 2, . . . , j, enabled signal and photon emission at the output of the
final stage for each APUF occurrence. The authors of [126]
outn = ⊕i=1,2,...l resp(n+cs+i)mod m . (23) experimentally evaluated their findings by applying the

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TABLE 4. Compositions of Arbiter PUF.

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TABLE 4. (Continued.) Compositions of Arbiter PUF.

photonic emission on the rear side of the 180 nm Altera FPGA efficiently modeled the x-XOR PUF (x ≤ 9) [131], [132],
board. [133], [134], [135], and the LR approach is successful in
obtaining the entire CRPs [114], [115]. YU and Wen [136]
3) CRYPTANALYSIS ATTACK propose a novel hybrid ML attack model on XOR APUF
It is known that cryptanalysis and modeling attacks are using CNN and side-channel analysis. As CNN did not effec-
the two standard mathematical methodologies employed for tively extract the critical correlation between the N input
examining the security of PUFs. In the domain of PUF, challenge bits of the XOR APUF, SCA has been integrated
cryptanalysis refers to computational attacks that use CRPs to pre-process the challenge. Later, the correlated challenge
and PUF design attributes to determine the response and enters the CNN, which significantly raises the training accu-
they don’t require a mathematical model explicitly declared. racy to 98% [136]. Generally, XOR APUF employs the same
Although a strong key is determined utilizing fuzzy extractors challenges for all the APUF instances. The literature study
and error-correcting codes, [96] and [127] successfully model reveals that CDC-XPUF variants with different challenges for
the composite PUF using a cryptanalysis approach. different APUF instances have lower resilience against mod-
eling attacks [91]. CDC-XPUF [91], [137] employs different
challenges for each APUF instance in contrast to XOR APUF.
4) PREDICTABILITY TEST
The author has modeled the CDC-x-XPUF with x(3, 4, 5)
The unpredictable nature of CRPs is the quintessential feature
and demonstrated for x > 5. However, it fails to model the
expected from a PUF. Hamming Distance Test (HDT (t))
PUF with a training size of 100 million using four-layer, No-
and Propagation Criteria (PC(t)) are two of the few unpre-
Neuron, and LR with R-prop.
dictability tests used to validate the APUF variants, viz., XOR
APUF, LSPUF, and Composite PUF [128]. These tests esti-
mate the likelihood of output transition probability to evaluate F. MODELING ATTACK ON DAPUF
the t flipping bits due to the challenge pairs(Chi , Chj ) with The DAPUF (3-1 and 4-1) [34] has been proven significantly
HD(Chi , Chj ) = t and HD(Chi , Chj ) ≤ t. Reference [128] more resilient against modeling attacks by using SVMlight .
proves that the said testing schemes are insufficient to test the With 1000 CRPs given to the SVM for testing, the prediction
unpredictability and incorporate a new parameter (flipping bit rate was reduced to 57% compared with APUF. The CRPs
pattern vector e) to HDT . The adversary finds fewer chances are then increased to 17 million to model the DAPUF using
to rebuild the model if the value of HDT (e, t)=0.5. LR [118]. This technique has modeled the 2-1 DAPUF albeit
with increased complexity while applying it to 3-1 and 4-1
E. MODELING ATTACK ON XOR APUF DA-APUF. Though 3-1 DAPUF has been modeled with an
In [129] and [130], x-XOR PUF (x ≤ 6) is demonstrated to accuracy of 86%, modeling 4-1 DAPUF has not been suc-
be robust against attacks since it takes more computational cessful. On the other hand, the DL technique has effectively
time to achieve the final response. However, there exists managed to model the 3-1 and 4-1 DAPUF with 1 million
a significant correlation between the challenges assigned CRPs [118], posing a threat to PUF design. In [138], the
randomly to any one of the APUF components. CMA-ES authors have used Multilayer Perceptron (MLP) neural net-
algorithm [95], thus utilizes these correlated values along work with an Adaptive Moment Estimation optimizer [139]
with a divide and conquer attack to build each component and ReLU (activation function for hidden layers) to build
of APUF. The application of the neural network method has the XOR APUF and DAPUF. A comparatively reduced

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TABLE 5. Modeling attack of various compositions of APUF.

CRPs around 500 × 103 is used to model N XOR APUF and one at the output has been used to model the FF-APUF
(N = 2,3,4) and DAPUF (2-1, 3-1, and 4-1) and has achieved (64 and 128-bit) with varying lengths, l (1≤ l ≤ 6). The
an accuracy of around 80% for 4-1 DAPUF. For 1 mil- maximum training time to model was 374.7134 minutes and
lion CRPs, the accuracy was reported to be 81% for 4-1 324.0204 min with 200 × 103 CRPs for 64 and 128-bit
DAPUF. Hence, it is more claimed that among XOR APUF challenges (l-6), respectively. The training time was reduced
(N = 2,3,4) and DAPUF (2-1, 3-1, and 4-1), 4-1 DAPUF to 73 minutes for 1 million CRPs with ten loops by combining
has proved robust to modeling attacks with lower prediction additional bits (ghost bits) in [121] along with challenge bits
accuracy. to FF-APUF and XOR APUF using the above neural network
method.
G. MODELING ATTACK ON FEED-FORWARD APUF
Feed-Forward APUF is considered robust against modeling H. MODELING ATTACK ON LSPUF
attacks as the number of loops increases in N stage APUF The responses from the LSPUF have a significant degree of
with l-loops of feed-forward arbiter. FF-APUF [129] mod- entropy due to the obfuscated CRPs. For x > 6 [115], the
eled with the same number of loops achieved a prediction LSPUF is resilient to LR-based modeling. However, while
accuracy of about 95% for l ≥ 6 loops. The MLP neural adopting parallel implementation, it failed for x = 9 [46],
network [120] with three layers of the neuron at the input [95]. In [128], the modeling of y-XOR PUF helped to model

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the x-XOR PUF (y < x), thus reducing the time and data • Robustness:APUFs can be designed to be resistant to
complexity even without side-channel analysis. Furthermore, tampering and against attempts to reverse engineer the
obtaining CRPs is found indeed successful using SCA [124] response. This feature improves the security of the
and cryptanalysis [96]. PUF.
The factors that need to be considered while designing
I. MODELING ATTACK ON iPUF APUF include the delay difference, placement, and routing
Reference [117] uses the gradient-based numerical optimiza- of the switch blocks, size of the PUF model, cost, power
tion method to model the iPUF (4,4) with a training time of requirements, the execution time, and the compatibility of
5.23 minutes. This method uses the knowledge of parity vec- the APUF with the manufacturing process of the device in
tors obtained from the challenge. The challenges have been which it is being used. Factors that can influence the com-
collected using MATLAB simulation models and Rectified position of an APUF include the desired level of security,
Linear Unit (ReLU) as an activation function for learn- the size and complexity of the device, and the resources
ing mapping and patterns of the dataset. Probably Approx- available for implementing the PUF. Considering the above
imately Correct (PAC) [140], the sub-space pre-learning discussions, the APUF can be used securely for IP pro-
method [141] uses randomness and known CRPs to model tection, IoT device authentication, Internet of Vehicles, and
the iPUF. The uniformity metric is found helpful in splitting resource-constrained applications such as RFIDs and smart
the iPUF (4,4) [50], [117] applying LR. The latest technique cards.
employs the splitting attack [114] using the divide and con- As PUF technology evolves, there are several areas in
quer ML algorithm for 64-bit iPUF (8,8), and (1,9) with a which future research on APUFs could focus on improving
training size ranging between 300 million to 750 million their performance and capabilities. Typical directions can be
CRPs, and the prediction accuracy was near 95%. as follows:
Table 5 summarizes the modeling attack conducted by • Developing methods that will further strengthen the
respective authors on various APUF variants to understand confidentiality of APUFs against tampering and reverse
their resiliency against attacks for different machine-learning engineering.
techniques. One can easily model an attack on a conventional • Investigating measures to increase the number of possi-
APUF because of its linear additive model using LR, DL, ble CRPs and further improve the uniqueness of APUFs.
and fault injection with reduced time and prediction accuracy • Developing new fabrication techniques to lower the cost
of 99.9%. Adding APUF instances parallelly in the DAPUF of APUFs, to enable their integration into a broader
increases the computation time by reducing the prediction range of devices.
accuracy between 71% and 95% with increased CRPs. Simi- • Reduce the power consumption of APUFs, to make
larly, the XOR APUF and FFAPUF increase the training time them more suitable for low-power and battery-powered
to predict its random output as the parallel instances of APUF, devices.
the number of XOR and feed-forward loops are increased in • Integrate APUFs with other security features, such as
the design model. Thus, XOR APUF, FF-APUF, and iPUF secure communication protocols, to provide an addi-
are challenging to get modeled in machine learning because tional layer of protection.
they are designed to be unpredictable and exhibit high vari- • Investigate the robustness of PUFs against physical
ability in their outputs. This makes it difficult for a machine attacks such as differential power analysis, electromag-
learning model to accurately predict the response of an XOR netic analysis, and side-channel analysis.
APUF, FFAPUF, and iPUF, as the model needs to account for
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based security vulnerability study on XOR PUFs for resource-constraint in engineering from IE(I), the master’s degree
Internet of Things,’’ in Proc. IEEE Int. Congr. Internet Things (ICIOT), from BITS, and the Ph.D. degree from the Vel-
Jul. 2018, pp. 49–56, doi: 10.1109/ICIOT.2018.00014. lore Institute of Technology (VIT). With nearly
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learning approach to fast high-accuracy machine learning of large XOR and research experiences. After 11 years of teach-
PUFs with component-differential challenges,’’ in Proc. IEEE Int. Conf. ing at the SSN College of Engineering, she joined
Big Data (Big Data), Dec. 2018, pp. 1563–1568, doi: 10.1109/BIG- VIT Chennai and had been donning the role of
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of four books on linear integrated circuits and related subjects published by
‘‘A fast deep learning method for security vulnerability study of XOR
McGraw Hill Education and has contributed book chapters on low-power
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ics9101715.
VLSI circuit design. Her research interests include VLSI design for low-
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based modeling attacks on XOR arbiter PUFs revisited,’’ IACR Cryptol. fellow of the Institution of Electronics and Telecommunication Engineers
ePrint Arch., vol. 2021, p. 555, Sep. 2021. (IETE) and the Institution of Engineers (India) (IEI). She is a member of
[136] W. Yu and Y. Wen, ‘‘Efficient hybrid side-channel/machine learning the IET and a Life Member of the ISTE. She is a reviewer of international
attack on XOR PUFs,’’ Electron. Lett., vol. 55, no. 20, pp. 1080–1082, journals and conferences.
Oct. 2019, doi: 10.1049/el.2019.1363.

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