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24 views10 pages

10 DSD Presentation

Uploaded by

kolnadharish258
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Encoders and Decoders

EC2003-1: Digital System Design using Verilog

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Encoders and Decoders Decoders

Introduction to Decoders
Consider the logic circuit shown in Figure, having two inputs, w1
and w0 , and four outputs, y0 , y1 , y2 , and y3 .
As shown in the truth table, only one of the outputs is asserted at a
time, and each output corresponds to one valuation of the inputs.
This type of circuit is called a binary decoder.
A k-bit binary code in which exactly one of the bits is set to 1 at a
time is referred to as one-hot encoded. The outputs of a binary
decoder are one-hot encoded

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Encoders and Decoders Decoders

Decoders with Enable


An enable input, En, can be added in a decoder circuit. By setting
En = 1 decoder can be enabled. By making En = 0 none of the
outputs are asserted.

A binary decoder with n inputs has 2n outputs. A graphical symbol


for an n − to − 2n decoder is shown below

DSDV
Encoders and Decoders Decoders

3-to-8 Line Decoder


Decoders can be designed to have either active-high or active low
outputs.
Since the decoders outputs represent Minterms (Active High) or
Maxterms (Active Low) they can be used in Logic synthesis.
This decoder generates all of the minterms of the three input
variables. Exactly one of the output lines will be 1 for each
combination of the values of the input variables

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Encoders and Decoders Decoders

Active-low output BCD decoder

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Encoders and Decoders Decoders

Decoders

Larger decoders can be built using the sum-of-products structures or


by using smaller decoders.

DSDV
Encoders and Decoders Decoders

Decoders
Larger decoders can be built using the sum-of-products structures or
by using smaller decoders.

Decoder with Enable input can be considered as a demultiplexer.

DSDV
Encoders and Decoders Decoders

Logic Implementation using Decoders


Design a Verilog behavioural model to implement a 4-to-16 decoder.

1 Using the above decoder implement the function described by


the 4-input minterm list shown in Figure below.

2 Using the above decoder implement the function described by


the 4-input truth table below

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Encoders and Decoders Decoders

Logic Implementation using Decoders

DSDV
Encoders and Decoders Decoders

Logic Implementation using Decoders


Realize the following function using Active-low BCD decoder.

Rewriting f1 and f2, we have

DSDV

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