[EE1-02]

Question 1

1. a) i)
𝑓 = #𝐴 + 𝐵' + #𝐴 + 𝐵'

= 𝐴𝐵 + 𝐴𝐵 = 𝐴⨁𝐵
[4]
ii)
***************
******
****𝐶 (𝐵⨁𝐶) = ****
𝑔 = 𝐴𝐵 𝐴𝐵𝐶 + *******
𝐵⨁𝐶

= (𝐴̅ + 𝐵*)𝐶 + 𝐵𝐶 + 𝐵*𝐶̅ = (𝐴̅ + 𝐵* + 𝐵)𝐶 + 𝐵*𝐶̅

= 𝐶 + 𝐵*𝐶̅ = 𝐶 + 𝐵*
[4]

b) (i)
CD
AB 00 01 11 10

00 1 0 1 1

01 1 0 0 1

11 1 0 0 1

10 1 X 1
1

1 + 𝐴𝐵* + 𝐵*𝐶
𝑦=𝐷
[4]
(ii)

CD
AB 00 01 11 10

00 1 0 1 1

01 1 0 0 1

11 1 0 0 1

10 1 1 X 1

𝑦 = 3𝐴 + 𝐶 + 𝐷43𝐵 + 𝐷4
[4]

Here, 2 marks for each of the Karnaugh maps with correct grouping, and 2 for
each of the final expressions.

Page 1 of 6
 [EE1-02]

c)

AB + AC + BC
= AB + BC ( A + A) + AC
= AB + ABC + ABC + AC
= AB(C + 1) + AC ( B + 1)
= AB + AC

[4]
d)

Decimal Hexadecimal Binary BCD

7244 1C4C
0000 0000 1101 0111 (0010 0001 0101) BCD
(As decimal is (215)10)
14334 37FE
-2417 F68F

Give 2 marks per answer.

[8]

e)

C B A P Q
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

Give 2 marks for correct use of inputs A, B, and C in table, and 2 marks each for P, Q
outputs.
[6]

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 [EE1-02]

f) (i) Moore state diagram:

Give 1 mark for correct number of states and connections, and 2 for state and output labels.

[3]

(ii) State transition table:

Give 1 mark for basic table, 1 for the correct input/output state transitions, 1 for the correct
outputs
[3]

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 [EE1-02]

Question 2

a) (i)
Mealy diagram for the FSM:

0/0

1/0 01 10
0/0 00 1/0 0/0 11

0/0 1/0
State: S1S0
1/1 Input/output: X/Y

[8]
Give 2 marks for correct number of states, 3 for correct labelling, 3 for interconnections.

(ii)
State transition table for the FSM:

Current state Input Next state Output

S1 S0 X S1+ S0+ Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 0 1

[6]
Give 2 marks each for S1+, S0+ and Y.

iii)
The transition table for the D flip-flop is the following:

Transition D
0®0 0
0®1 1
1®0 0
1®1 1

Give 1 mark for seeing this.

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 [EE1-02]

For S1+:

K-map for S1+:

S1S0
X 00 01 11 10
0 0 0 1 0

1 1 1 0 0

𝑆17 = ***
𝑆1𝑋 + 𝑆0𝑆1𝑋*

Give 2 marks for k-map and 1 for expression.

For S0+:

K-map for S0+:

S1S0
X 00 01 11 10
0 0 1 0 0

1 1 0 0 0

𝑆17 = ***
𝑆0*** ***𝑋*
𝑆1𝑋 + 𝑆0𝑆1

Give 2 marks for k-map and 1 for expression.

For Y:

Y can be found directly from the state transition table:

Y = S1.S 0. X

Give 1 mark for this.

[8]

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 [EE1-02]

b) Boolean expressions for H, E and L are shown below:

( ) ( )( ) ( )( )( )
H = A3 B3 + A3 Å B3 A2 B2 + A3 Å B3 A2 Å B2 A1 B1 + A3 Å B3 A2 Å B2 A1 Å B1 A0 B0
( )( )( )(
E = A3 Å B3 A2 Å B2 A1 Å B1 A0 Å B0 )
( ) ( )( ) ( )( )( )
L = A3 B3 + A3 Å B3 A2 B2 + A3 Å B3 A2 Å B2 A1 B1 + A3 Å B3 A2 Å B2 A1 Å B1 A0 B0
Alternatively, given H and E as above, we have: L = H .E

Give 3 marks for H and L, and 2 for E

[8]

Page 6 of 6
3. Figures 3.1 and 3.2 show a non-pipelined CPU and its RAM. The CPU state machine
has 4 distinct states: F, E1, E2 and E3. The CPU instruction set is defined in Figure 3.3.
You may assume that all CPU registers are initially 0.
From its start the CPU executes, in sequence, LDI, LDA and LDN instructions as de-
termined by the program in Figure 3.4. Figure 3.5 shows how the CPU state changes
during the first 10 cycles of this program executing.

a) Draw the state transition diagram of the CPU state machine. Indicate condi-
tional state transitions as boolean expressions of IRMUX signals, assuming no
instructions other than as in Figure 3.3. [6]
' $
Calculated example.The state machine is similar to a smaller one used before in lab work, but
E3 is new, as is the calculation:

S
1 mark for each transition.

!B & !A

ER
!B & A

B | A !B & A
B = IRMUX(13)
A = IRMUX(12) F E1 E2 E3
SW
& %

b) State the number of cycles delay between Addr changing, and the correspond-
ing change in each of Dout, IR, IRMUX. Hence explain why the 4 DECODE
signals from IRMUX could not come from IR or Dout. [6]
 
New analysis related to an example seen before:
N

1 cycle delay from Addr to Dout and IRMUX (2 marks).

2 cycles delay from Addr to IR (1 mark).

IRMUX is needed to hold the instruction word for use in the DECODE block throughout exe-
cution from E1 - E3.
A

IR is not valid during E1.

Dout is not valid during E2,E3. (3 marks).

 

c) For each of the states E1, E2, E3 of the LDN (0x2100) instruction state the
contents of Dout, and describe how these relate to the LDN operation. [6]

Digital Electronics and Computer Architecture c Imperial College London 7/10

  
Analysis of new example. Similar hardware with LDI, LDA instructions has been used in lab
work:
1 mark for each value, 1 mark for each description.
E1: 0x2100. LDN instruction word.
E2: 0x0101. Contents of 0x100.
E3: 0x0246. Contents of 0x101 to be loaded into Acc.
 

d) Name the memory addressing modes implemented by LDA and LDN instructions
respectively, and state two advantages of immediate offset addressing, as used
in the ARM CPU, over LDA and LDN. [4]
 
Bookwork:

S
LDA implements direct addressing (1 mark).
LDN implements indirect addressing (1 mark).
(1) Immediate offset addressing in the ARM CPU performs indirection without needing an

ER
additional memory read (1 mark).
(2) It allows offset addressing to be used in an arbitrary sized memory space (1 mark).
 

e) Figure 3.6 shows a 16 bit binary adder Σ with carry in and out cin and cout
implementing single cycle two operand 16 bit arithmetic instructions. Two se-
quential cycles 0, 1 implement 32 bit subtraction: R0:R1 := R0:R1 - R2:R3.
i) State, with reasons, the values of N and cin in cycles 0 and 1. [6]
SW
ii) State, using X for don’t care, the values of A and B in each cycle. [2]
 
Application of bookwork:
cycle 0 cin=1 to implement 2’s complement negation (2 marks)
cycle 1 cin = CARRY to implement subtraction carry (2 mark)
Both cycles N = 1 to invert one operand for 2’s complement negation (2 marks)
Analysis of new example:
Cycle A (1 mark) B (1 mark)
N

0 X 1
1 1 0
 
A

Digital Electronics and Computer Architecture c Imperial College London 8/10

 Din(15:0)
1 Addr(11:0)

MUX3
12 12
16 Q 12
CNT_EN PC 0 SEL
Q D
DX EN ACC 12 Wren
D 12
4 DECODE
16 IRMUX(15:0) RAM
MUX1 MUX2
SEL DY SEL
0 1 0 1
16 16 16
IR(15:0) F E1 E2 E3
+/-

S
IR
Q
En
STATE
D MACHINE
16 16 16 16 16 Dout(15:0)

ER
Figure 3.1: CPU Block Diagram

WrenN AddrN DinN DoutN+1 Operation

0 a X Mem16 [a] Read
1 a d X Mem16 [a] := d

Figure 3.2: RAM operation: SN indicates signal S during cycle N

SW
Mnemonic IW(15:12) Operation
LDI 0b0000 Acc := IW(11:0)
LDA 0b0001 Acc := Mem16 [IW(11:0)]
LDN 0b0010 Acc := Mem16 [Mem16 [IW(11:0)]]

Figure 3.3: Instructions: IW(15:0) is the instruction word

N

Addr Mem16 [Addr] Assembler

0x000 0x0123 LDI 0x123
0x001 0x1100 LDA 0x100
A

0x002 0x2100 LDN 0x100

0x100 0x0101
0x101 0x0246

Figure 3.4: Initial RAM contents for program: all other locations are 0

Cycle 0 1 2 3 4 5 6 7 8 9
PC 0 1 1 2 2 2 3 3 3 3
State F E1 F E1 E2 F E1 E2 E3 F

Figure 3.5: States during first 10 cycles executing the program in Figure 3.4

Digital Electronics and Computer Architecture c Imperial College London 9/10

 S
cout
Q

to
register
file

16

cin
clk

CARRY

D
Q
A

ER B

0
INV block
X(i)

𝑥𝑖
Y(i)

𝑥𝑖
SW
A B
1 𝑥𝑖 𝑥ഥ𝑖
16 16
Y
INV N
from
X
register
file
Figure 3.6: CPU Adder and Invert block
N
A

Digital Electronics and Computer Architecture c Imperial College London 10/10