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Fully-differential opamp design

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 U NIVERSITY OF I DAHO

D EPARTMENT OF E LECTRICAL AND C OMPUTER E NGINEERING

ECE-515 A NALOG I NTEGRATED C IRCUIT D ESIGN

Fully-differential opamp design

Student Instructor
Elyes B ALTI Dr. Vishal S AXENA

December 16, 2017

Contents

1 Design specifications 4
1.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 First stage 8
2.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Common mode feedback loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Second Stage 10
3.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Common mode feedback loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Open-loop stability performance 13

4.1 Differential open-loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 First common mode open-loop gain . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Second common mode open-loop gain . . . . . . . . . . . . . . . . . . . . . . . 15

5 Closed-loop gain performance 17

5.1 Differential closed-loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 First common mode closed-loop gain . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Second common mode closed-loop gain . . . . . . . . . . . . . . . . . . . . . . 19

6 Transient responses 21
6.1 Differential step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Common mode step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Small and large step inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Metrics characterization 24
7.1 Slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 PVT characterization 25
8.1 Temperature variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.2 Supply voltage variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 Conclusion 27

1
List of Tables

1.1 Opamp design specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Short-channel 180nm process MOSFET parameters . . . . . . . . . . . . . . . . 5

4.1 Design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 DM open-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 First CM open-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Second CM open-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 DM closed-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 First CM closed-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Second CM closed-loop gain results . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Differential step input parameter . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 CM step input parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 DM input step voltage vs Settling times . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Slew-rates vs DM input step voltage . . . . . . . . . . . . . . . . . . . . . . . . 24

2
List of Figures

1.1 NMOS testing for 20 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 NMOS bias current ID = 20 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 PMOS testing for 20 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 PMOS bias current ID = 20 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 First stage schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 First stage symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 DDP schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 DDP symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Second stage schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Second stage symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Error amplifier schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Error amplifier symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Current injection schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Current injection symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Two-stage opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 DM open-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 First CM open-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Second CM open-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 DM closed-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 First CM closed-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Second CM closed-loop gain Bode plot . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 DM transient response for input step = 200 mV . . . . . . . . . . . . . . . . . . 21

6.2 CM transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Small input step = 50 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 Large input step = 300 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1 Temperature variations vs transient DM output voltage . . . . . . . . . . . . . 25

8.2 Supply voltage variations vs transient DM output voltage . . . . . . . . . . . 26

3
Chapter 1

Design specifications

Operational amplifier is considered as the core of the analog building blocks. High per-
formance opamp must exhibit high gain, wide bandwidth, low power consumption and
rail-to-rail output swings.

1.1 Requirements
In this project, the opamp design must satisfy the following specifications given by Table
1.1.
Table 1.1: Opamp design specifications

Parameter Specified value

Technology TSMC 180-nm
Supply voltage, VDD 1.8 V
Common-mode voltage, VCM 0.9 V
Typical load 100 kΩ, 1 pF
Unity gain frequency ( f un ) > 50 MHz
Open-loop gain (AOL ) > 60 dB
Closed-loop gain (ACL ) 6 dB
Closed-loop bandwidth ( f 3dB,CL ) > 20 MHz
V
Slew-rate (SR) > 100 µs
Phase margin (φM ) 60 deg
Output swing > 1.5·VDD
Power consumption Minimum possible

To meet these requirements, the opamp design must include the following specifica-
tions:
• Two-stages: the first stage provides a high gain, while the second stage provides a
high output swing (rail-to-rail) to drive a high load.

• The first stage does not necessarily provide high swing, but it has to provide high
gain with minimum power consumption. The folded cascode amplifier is not suitable
for the first stage since its gain is reduced 2 to 3 times compared to the telescopic and
also the power consumption is higher, although it provides not only a wider ICMR
and output swing, but also an excellent overlap of the ICMR and the output swing.
Finally, the best candidate amplifier for the first stage is the cascode since it provides
4
 a high gain. The cascode also provides a higher bandwidth compared to the folded
cascode since the last one has an additional pole due to the current summation at the
node linking the bias source and the upper side of the cascode.

• The second stage is class-AB so that the output has a rail-to-rail swings (from 0 to Vdd )

• Each stage has to be compensated separately, since this method is very robust com-
pared to the method of using one compensation feedback loop for the two stages.

• Dual Diff-Pair CM Detector can be used in the first stage because it drives only small
capacitive load and it does not affect the gain. However, it allows very limited output
swings which is not required for the first stage.

• Since the second stage is class-AB, the practical CMFB method is the current injection.

1.2 Bias circuit

In this project, a current of 20µA is biasing the first stage. To generate such current value,
A BMR circuit is designed and used as a bias circuit to feed the first stage. The process
of biasing should take place with a constant transconductance gm . To generate a current
of 20 µA for the process of 180 nm, I should determine first the corresponding size of the
MOSFET given that Vov is 90 mV. After the simulation and testing, I come up with the
following MOSFET parameters’ values so that to generate 20 µA.

Table 1.2: Short-channel 180nm process MOSFET parameters

Parameter NMOS PMOS

Vov 90 mV 90 mV
VTHN and VTHP 457 mV 463 mV
VGS and VSG 547 mV 553 mV
VDS,sat and VSD,sat 60 mV 60 mV
Bias Current ID 20 µA 20 µA
W/L 28/2 86/2
gmn and gmp 285 µA/V 260 µA/V
γon and γop 314 KΩ 437 KΩ

Figure 1.1: NMOS testing for 20 µA

5
Figure 1.2: NMOS bias current ID = 20 µA

Figure 1.3: PMOS testing for 20 µA

6
 Figure 1.4: PMOS bias current ID = 20 µA

Each branch of the first stage is fed by 20µ A, to satisfy this condition, the total bias
current of the first stage os 40µA. To achieve this value, the size of the NMOS must be
doubled to be 56/2 and for the PMOS is 172/2. Note that Vbias 2 and 3 feed PMOS and
NMOS, respectively.

7
Chapter 2

First stage

2.1 Specifications
In this design, the first stage should provide a sufficient high gain. To satisfy this require-
ment, I suggest the cascode amplifier given by Fig. 2.1.

Figure 2.1: First stage schematic

8
 Figure 2.2: First stage symbol

2.2 Common mode feedback loop

The first stage has to be compensated separately to be stable. The appropriate common
mode feedback (CMFB) loop is the dual diff-pair (DDP). The topology of the DDP should
include the Miller compensation cap Cc,CM1 . The schematic of the DDP CMFB is given by
Fig. 2.3.

Figure 2.3: DDP schematic

Figure 2.4: DDP symbol

9
Chapter 3

Second Stage

3.1 Specifications
In order to provide sufficient rail to rail output swing, the best candidate is the class-AB
stage. I also introduce the Miller cap Cc DM to compensate the differential path with the
zero nulling Rz to push the RHP zero out to infinity. The schematic is given by Fig. 3.1.

Figure 3.1: Second stage schematic

Figure 3.2: Second stage symbol

10
3.2 Common mode feedback loop
The second stage has to be compensated separately to be stable. The appropriate common
mode feedback (CMFB) loop is the current injection. The topology of the current injection
should include the Miller compensation cap Cc,CM2 and also the error amplifier to match
the output common mode voltage with the voltage reference (VCM2 = 0.9 V).
The bias current and widths are scaled down to save power (Ic0 =I0 /n). Also both stages
should have the same current density as follows:

I0 /2 Ic0 /2
= (3.1)
Wpmos Wcpmos

For the current injection CM detector, 1/4 of the current branch injects or removes the cur-
rent into or from the outputnodes to control theri CM-level. Also 3 by 1 of the DC current
split for the bias current of the second stage I2 used to avoid the potential instability. The
schematic of the error amplifier and the symbol are given by Fig. 3.3 and Fig. 3.4, respec-
tively.

Figure 3.3: Error amplifier schematic

Figure 3.4: Error amplifier symbol

11
 The current injection and the relative symbol are given by Fig. 3.5 and Fig. 3.6, respec-
tively.

Figure 3.5: Current injection schematic

Figure 3.6: Current injection symbol

12
Chapter 4

Open-loop stability performance

The following table presents the design parameters that I come up with to achieve the
opamp performance.

Table 4.1: Design parameters

Parameter Value
R1 100K
R2 200K
RCM 30K
CcCM1 0.94 pF
CcCM2 0.1 pF
CcDM 1.2 pF

The schematic of the two-stage opam with CMDM probes is given by the following
figure.

Figure 4.1: Two-stage opamp

4.1 Differential open-loop gain

To measure the differential mode (DM) open-loop gain, I performed an stb analysis and I
set the CMDM 3 to -1. The simulation results show an agreement with the requirement
13
detailed in the following table.

Table 4.2: DM open-loop gain results

Parameter Value
Av,DM 64.84 dB
φM 63.025 deg
f un 59.408 MHz

The Bode plot of the magnitude and phase of the open-loop gain is given by the follow-
ing figure.

Figure 4.2: DM open-loop gain Bode plot

4.2 First common mode open-loop gain

To evaluate the first CM open-loop gain, I performed an stb analysis and I set the CMDM
1 to 1. The following table summarizes the main results.

Table 4.3: First CM open-loop gain results

Parameter Value
Av,CM1 62.57 dB
φM 60.077 deg
f un 51.055 MHz

The Bode plot of the magnitude and phase of the open-loop gain is given by the follow-
ing figure.

14
 Figure 4.3: First CM open-loop gain Bode plot

4.3 Second common mode open-loop gain

To evaluate the first CM open-loop gain, I performed an stb analysis and I set the CMDM 2
to 1. The following table provides the main results of the open-loop gain of the second CM
stage.

Table 4.4: Second CM open-loop gain results

Parameter Value
Av,CM2 25.445 dB
φM 63.673 deg
f un 65.94 MHz

The Bode plot of the magnitude and phase of the open-loop gain is given by the follow-
ing figure.

15
Figure 4.4: Second CM open-loop gain Bode plot

16
Chapter 5

Closed-loop gain performance

To evaluate the closed-loop gain, the following steps must be achieved:

1. Remove all CMDM probes from the circuit.

2. For each loop (DM, CM1 and CM2), an AC voltage of 1V magnitude is introduced to
the input.

3. Measure the output voltage of each loop.

4. Perform an ac analysis of each loop.

5.1 Differential closed-loop gain

The main results are detailed in the following table.

Table 5.1: DM closed-loop gain results

Parameter Value
Av,DM 6.013 dB
f 3dB 21.379 MHz

The Bode plot of the magnitude and phase of the closed-loop gain is given by the fol-
lowing figure.

17
 Figure 5.1: DM closed-loop gain Bode plot

5.2 First common mode closed-loop gain

The main results are detailed in the following table.

Table 5.2: First CM closed-loop gain results

Parameter Value
Av,CM1 149.646 mdB
f 3dB 20.893 MHz

The Bode plot of the magnitude and phase of the closed-loop gain is given by the fol-
lowing figure.

18
 Figure 5.2: First CM closed-loop gain Bode plot

5.3 Second common mode closed-loop gain

The main results are detailed in the following table.

Table 5.3: Second CM closed-loop gain results

Parameter Value
Av,CM2 213.508 mdB
f 3dB 22.9087 MHz

The Bode plot of the magnitude and phase of the closed-loop gain is given by the fol-
lowing figure.

19
Figure 5.3: Second CM closed-loop gain Bode plot

20
Chapter 6

Transient responses

6.1 Differential step response

To evaluate the differential step response, I introduce a differential step of the following
characteristics:

Table 6.1: Differential step input parameter

Parameter Value
Amplitude 200 mV
rise 0.1 ns
fall 0.1 ns

The following figure shows the variations of the differential input and output voltages.

Figure 6.1: DM transient response for input step = 200 mV

6.2 Common mode step response

The following table provides the parameters of the CM step input.

21
 Table 6.2: CM step input parameter

Parameter Value
Amplitude 100 mV
rise 0.1 ns
fall 0.1 ns

The following figure shows the variations of the common mode input and output volt-
ages.

Figure 6.2: CM transient response

6.3 Small and large step inputs

Figure 6.3: Small input step = 50 mV

22
 Figure 6.4: Large input step = 300 mV

As the differential input step voltages increases, the slew-rate appears and varies. From
the figures, as the differential step increases, I noted that the low-to-high settling times
decrease while the high-to-low settling times increase. The table below summarizes the
values of settling times (high-to-low and low-to-high) with respect to the differential input
step voltage.

Table 6.3: DM input step voltage vs Settling times

DM input step Settling times

50 mV 29.933 ns
300 mV 30.64 ns

23
Chapter 7

Metrics characterization

7.1 Slew rates

The following table summarizes the dependence of the slew-rates on the differential step
input voltages

Table 7.1: Slew-rates vs DM input step voltage

DM input step SR+ V/µs SR− V/µs

50 mV 137.93 108.69
300 mV 301.51 265.01

7.2 CMRR
For fully-differential opamp, the CMRR metric is not defined. Thereby, CMRR is infinity.
However, the CMRR makes sense for the case of single-ended differential opamp.

7.3 PSRR
For fully-differential opamp, the PSRR metric is not defined. Thereby, PSRR is infinity.
However, the PSRR makes sense for the case of single-ended differential opamp.

24
Chapter 8

PVT characterization

8.1 Temperature variations

I run a temperature sweeping to control the transient response of the differential output
voltage. The following figure illustrate the thermal impact.

Figure 8.1: Temperature variations vs transient DM output voltage

I observe that the temperature variations affect the transient response of differential
output voltage. In fact, this impact is negligeable for positive slew-rate while charging the
capacitors. Nevertheless, as the temperature increases, the charging is longer, while the
capacitor gets charged faster for lower temperature value. However, the thermal impact
becomes pronounced for negative slew-rate (capacitors discharging). For higher values of
temperature, the capacitors take so long for discharging, whereas, the discharching is faster
for lower values of temperature.

25
8.2 Supply voltage variations

Figure 8.2: Supply voltage variations vs transient DM output voltage

The figure above illustrates the dependence of the transient response against the supply
voltage variations. For the case of no supply voltage (VDD = 0 V), the MOSFETS are in cut-
off region and the total opamp is in OFF-state, and the response is flat. For a supply voltage
of 0.45 V, the response is very low, since the gain is deteriorated because many MOSFETs
are still in cut-off or operating in triode region. As the supply voltage becomes higher than
900 mV, the two-stage opamp exhibits various response. The capacitors are charging and
discharging faster for higher supply voltages. For lower supply voltages, the capacitors
are slowly charging but they are discharging at a rate similar to the case of high supply
voltages.

26
Chapter 9

Conclusion

In this project, the design of the two-stage fully-differential opamp is achieved. The stability
analysis of the open-loop gain for the two-stage common modes and the differential mode
are studied. Based on the design parameters, the open-loops (CM1, 2 and DM) are stable
and achieve a phase margin greater than 60 deg. Also the first common and the differential
modes loop-gain achieve sufficient gains greater than 60 dB. In addition, the differential
closed-loop achieves a gain of 6 dB and cut-off frequencies higher than 20 MHz, while th
CMFB closed-loop achieve gains closer to zeros which confirm the system stability against
the common mode disturbance. Furthermore, the design shows slews-rates for various dif-
ferential input steps higher than 100 V/µs. Based on those results, the proposed design met
the requirements for an opamp of high performance. Furthermore, a framework analysis
of the transient responses (common and differential modes) are provided and the opamp
design is characterized based on various input steps, slew-rates and PVT variations.

27
 Bibliography

[1] The Designer’s Guide to SPICE and Spectre: http://www.designersguide.org/books/

dg-spice/

[2] Spectre User Simulation Guide, pages 160-165: http://www.designersguide.org/

Forum/YaBB.pl?num=1170321868

[3] https://secure.engr.oregonstate.edu/wiki/ams/index.php/Spectre/STB

[4] M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, Striving for Small-Signal Stability: Loop-
based and Device-based Algorithms for Stability Analysis of Linear Analog Circuits in the
Frequency Domain, Circuits and Devices, Jan 2001. http://www.kenkundert.com/docs/
cd2001-01.pdf

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