CHI - D Spec
CHI - D Spec
Architecture Specification
Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved.
ARM IHI 0050D (ID082919)
AMBA 5 CHI
Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved.
Release Information
Change history
Proprietary Notice
This document is NON-CONFIDENTIAL and any use by you is subject to the terms of this notice and the Arm AMBA
Specification Licence set about below.
This document is protected by copyright and other related rights and the practice or implementation of the information contained
in this document may be protected by one or more patents or pending patent applications. No part of this document may be
reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by
estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use
the information for the purposes of determining whether implementations infringe any third party patents.
THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES,
EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR
PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to,
and has undertaken no analysis to identify or understand the scope and content of, patents, copyrights, trade secrets, or other rights.
TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES,
INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR
CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING
OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure
of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof
is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers
is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document
at any time and without notice.
If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written
agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the
conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that
if there is any conflict between the English version of this document and any translation, the terms of the English version of the
Agreement shall prevail.
The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its
subsidiaries) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the
trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at
http://www.arm.com/company/policies/trademarks.
Copyright © 2014, 2017, 2018, 2019 Arm Limited (or its affiliates). All rights reserved.
ii Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
In this document, where the term Arm is used to refer to the company it means “Arm or any of its subsidiaries as appropriate”.
THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A
SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED (“ARM”) FOR THE USE OF THE RELEVANT
AMBA SPECIFICATION ACCOMPANYING THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE RELEVANT
AMBA SPECIFICATION TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY
CLICKING “I AGREE” OR OTHERWISE USING OR COPYING THE RELEVANT AMBA SPECIFICATION YOU
INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO
THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE RELEVANT AMBA SPECIFICATION TO YOU
AND YOU MAY NOT USE OR COPY THE RELEVANT AMBA SPECIFICATION AND YOU SHOULD PROMPTLY
RETURN THE RELEVANT AMBA SPECIFICATION TO ARM.
“Subsidiary” means, if You are a single entity, any company the majority of whose voting shares is now or hereafter owned or
controlled, directly or indirectly, by You. A company shall be a Subsidiary only for the period during which such control exists.
1. Subject to the provisions of Clauses 2, 3 and 4, Arm hereby grants to LICENSEE a perpetual, non-exclusive, non-transferable,
royalty free, worldwide licence to:
(i) use and copy the relevant AMBA Specification for the purpose of developing and having developed products that comply with
the relevant AMBA Specification;
(ii) manufacture and have manufactured products which either: (a) have been created by or for LICENSEE under the licence
granted in Clause 1(i); or (b) incorporate a product(s) which has been created by a third party(s) under a licence granted by Arm
in Clause 1(i) of such third party’s Arm AMBA Specification Licence; and
(iii) offer to sell, sell, supply or otherwise distribute products which have either been (a) created by or for LICENSEE under the
licence granted in Clause 1(i); or (b) manufactured by or for LICENSEE under the licence granted in Clause 1(ii).
2. LICENSEE hereby agrees that the licence granted in Clause 1 is subject to the following restrictions:
(i) where a product created under Clause 1(i) is an integrated circuit which includes a CPU then either: (a) such CPU shall only
be manufactured under licence from Arm; or (b) such CPU is neither substantially compliant with nor marketed as being compliant
with the Arm instruction sets licensed by Arm from time to time;
(ii) the licences granted in Clause 1(iii) shall not extend to any portion or function of a product that is not itself compliant with
part of the relevant AMBA Specification; and
(iii) no right is granted to LICENSEE to sublicense the rights granted to LICENSEE under this Agreement.
3. Except as specifically licensed in accordance with Clause 1, LICENSEE acquires no right, title or interest in any Arm
technology or any intellectual property embodied therein. In no event shall the licences granted in accordance with Clause 1 be
construed as granting LICENSEE, expressly or by implication, estoppel or otherwise, a licence to use any Arm technology except
the relevant AMBA Specification.
4. THE RELEVANT AMBA SPECIFICATION IS PROVIDED “AS IS” WITH NO REPRESENTATION OR WARRANTIES
EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY
QUALITY, MERCHANTABILITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE, OR THAT ANY
USE OR IMPLEMENTATION OF SUCH ARM TECHNOLOGY WILL NOT INFRINGE ANY THIRD PARTY PATENTS,
COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the Arm tradename,
or AMBA trademark in connection with the relevant AMBA Specification or any products based thereon. Nothing in Clause 1
shall be construed as authority for LICENSEE to make any representations on behalf of Arm in respect of the relevant AMBA
Specification.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. iii
ID082919 Non-Confidential
7. This Licence shall remain in force until terminated by you or by Arm. Without prejudice to any of its other rights if LICENSEE
is in breach of any of the terms and conditions of this Licence then Arm may terminate this Licence immediately upon giving
written notice to You. You may terminate this Licence at any time. Upon expiry or termination of this Licence by You or by Arm
LICENSEE shall stop using the relevant AMBA Specification and destroy all copies of the relevant AMBA Specification in your
possession together with all documentation and related materials. Upon expiry or termination of this Licence, the provisions of
clauses 6 and 7 shall survive.
8. The validity, construction and performance of this Agreement shall be governed by English Law.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
Product Status
Web Address
http://www.arm.com
iv Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Contents
AMBA 5 CHI Architecture Specification
Preface
About this specification ................................................................................................ x
Feedback ................................................................................................................... xv
Chapter 1 Introduction
1.1 Architecture overview ............................................................................................. 1-18
1.2 Topology ................................................................................................................ 1-20
1.3 Terminology ........................................................................................................... 1-21
1.4 Transaction classification ....................................................................................... 1-23
1.5 Coherence overview .............................................................................................. 1-25
1.6 Component naming ................................................................................................ 1-27
1.7 Read data source ................................................................................................... 1-29
Chapter 2 Transactions
2.1 Channels overview ................................................................................................. 2-32
2.2 Channel fields ........................................................................................................ 2-33
2.3 Transaction structure ............................................................................................. 2-39
2.4 Transaction identifier fields .................................................................................... 2-73
2.5 Details of transaction identifier fields ..................................................................... 2-74
2.6 Transaction identifier field flows ............................................................................. 2-77
2.7 Logical Processor Identifier .................................................................................... 2-98
2.8 Ordering ................................................................................................................. 2-99
2.9 Address, Control, and Data .................................................................................. 2-109
2.10 Data transfer ........................................................................................................ 2-118
2.11 Request Retry ...................................................................................................... 2-129
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. v
ID082919 Non-Confidential
Contents
vi Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Contents
Appendix C Revisions
Glossary
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. vii
ID082919 Non-Confidential
Contents
viii Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Preface
This preface introduces the AMBA 5 CHI Architecture Specification. It contains the following sections:
• About this specification on page x.
• Using this specification on page x.
• Conventions on page xii.
• Additional reading on page xiv.
• Feedback on page xv.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ix
ID082919 Non-Confidential
Preface
About this specification
Intended audience
This specification is written for hardware and software engineers who want to become familiar with the CHI
architecture and design systems and modules that are compatible with the CHI architecture.
Chapter 1 Introduction
Read this for an introduction to the CHI architecture, and the terminology used in this specification.
Chapter 2 Transactions
Read this for an overview of the communication channels between nodes, the associated packet
fields, transaction structures, transaction ID flows, and the supported transaction ordering.
x Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Preface
About this specification
Appendix C Revisions
Read this for a description of the technical changes between released issues of this specification.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. xi
ID082919 Non-Confidential
Preface
About this specification
Conventions
The following sections describe conventions that this specification can use:
• Typographical conventions.
• Timing diagrams.
• Signals on page xiv.
• Numbers on page xiv.
Typographical conventions
The typographical conventions are:
italic Highlights important notes, introduces special terminology, and denotes internal
cross-references and citations.
bold Denotes signal names, and is used for terms in descriptive lists, where appropriate.
monospace Used for assembler syntax descriptions, pseudocode, and source code examples.
Also used in the main text for instruction mnemonics and for references to other items
appearing in assembler syntax descriptions, pseudocode, and source code examples.
SMALL CAPITALS Used for a few terms that have specific technical meanings.
Timing diagrams
The Key to timing diagram conventions figure explains the components used in timing diagrams. Variations, when
they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that
time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus change
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar to
the bus change that the Key to timing diagram conventions figure shows. If a timing diagram shows a single-bit
signal in this way then its value does not affect the accompanying description.
xii Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Preface
About this specification
Time-Space diagrams
The Key to Time-Space diagram conventions figure explains the format used to illustrate protocol flow.
Protocol
nodes
RN-F HN-F
Allocation
I
Initial cache
state
REQ
Direction of
message flow
RESP
Lifetime of a
transaction
Forward progress
is unblocked Time
I->UC
Space
• The protocol nodes are positioned along the horizontal axis and time is indicated vertically, top to bottom.
• The lifetime of a transaction at a protocol node is shown by an elongated shaded rectangle along the time axis
from allocation to the deallocation time.
• The diamond shape on the timeline indicates arrival of a request and whether its processing is blocked
waiting for another event to complete.
• The cache state transition, upon the occurrence of an event, is indicated by I->UC.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. xiii
ID082919 Non-Confidential
Preface
About this specification
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Numbers
Numbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x.
Both are written in a monospace font.
Additional reading
This section lists relevant publications from Arm.
Arm publications
• AMBA® AXI and ACE Protocol Specification (ARM IHI 0022).
xiv Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Preface
Feedback
Feedback
Arm welcomes feedback on its documentation.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. xv
ID082919 Non-Confidential
Preface
Feedback
xvi Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 1
Introduction
This chapter introduces the CHI architecture and the terminology used throughout this specification. It contains the
following sections:
• Architecture overview on page 1-18.
• Topology on page 1-20.
• Terminology on page 1-21.
• Transaction classification on page 1-23.
• Coherence overview on page 1-25.
• Component naming on page 1-27.
• Read data source on page 1-29.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-17
ID082919 Non-Confidential
1 Introduction
1.1 Architecture overview
The components of CHI based systems can comprise of standalone processors, processor clusters, graphic
processors, memory controllers, I/O bridges, PCIe subsystems and the interconnect itself.
• Scalable architecture, enabling modular designs that scale from small to large systems.
• Independent layered approach, comprising of Protocol, Network, and Link layer, with distinct functionalities.
• Packet-based communication.
• All transactions handled by an interconnect-based Home Node that co-ordinates required snoops, cache, and
memory accesses.
• Optimized transaction flow for coherent writes with a producer-consumer ordering model.
• Error reporting and propagation across components and interconnect for system reliability and integrity.
• Handling sub cache line data errors using Data Poisoning and per byte error indication.
1-18 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.1 Architecture overview
Communication
Layer Primary function
granularity
Protocol Transaction The Protocol layer is the top-most layer in the CHI architecture. The function
of the Protocol layer is to:
• Generate and process requests and responses at the protocol nodes.
• Define the permitted cache state transitions at the protocol nodes that
include caches.
• Define the transaction flows for each request type.
• Manage the protocol level flow control.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-19
ID082919 Non-Confidential
1 Introduction
1.2 Topology
1.2 Topology
The CHI architecture is primarily topology-independent. However, certain topology-dependent optimizations are
included in this specification to make implementation more efficient. Figure 1-1 shows three examples of topologies
selected to show the range of interconnect bandwidth and scalability options that are available.
0 1 2 3 0 1 2 3
4 5 6 7 Ring
0
8 9 10 11
1
4×4
Crossbar
12 13 14 15 2
3
4×4 Mesh
4 5 6 7
Router
Crossbar This topology is simple to build, and naturally provides an ordered network with low latency. It is
suitable where the wire counts are still relatively small. This topology is suitable for an interconnect
with a small number of nodes.
Ring This topology provides a good trade-off between interconnect wiring efficiency and latency. The
latency increases linearly with the number of nodes on the ring. This topology is suitable for a
medium size interconnect.
Mesh This topology provides greater bandwidth at the cost of more wires. It is very modular and can be
easily scaled to larger systems by adding more rows and columns of switches. This topology is
suitable for a larger scale interconnect.
1-20 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.3 Terminology
1.3 Terminology
The following terms have a specific meaning in this specification:
Transaction A transaction carries out a single operation. Typically, a transaction either reads from
memory or writes to memory.
Message A Protocol layer term that defines the granule-of-exchange between two components.
Examples are:
• Request.
• Data response.
• Snoop request.
A single Data response message might be made up of a number of packets.
Packet The granule-of-transfer over the interconnect between endpoints. A message might be made
up of one or more packets. For example, a single Data response message can be made up of
1 to 4 packets. Each packet contains routing information, such as destination ID and source
ID that enables it to be routed independently over the interconnect.
Flit The smallest flow control unit. A packet can be made up of one or more flits. All the flits of
a given packet follow the same path through the interconnect.
Note
For CHI, all packets consist of a single flit.
Phit The physical layer transfer unit. A flit can be made up of one or more phits. A phit is defined
as one transfer between two adjacent network devices.
Note
For CHI, all flits consist of a single phit.
PoS Point of Serialization. A point within the interconnect where the ordering between Requests
from different agents is determined.
PoC Point of Coherence. A point at which all agents that can access memory are guaranteed to
see the same copy of a memory location. In a typical CHI based system it is the HN-F in the
interconnect.
PoP Point of Persistence. The point in a memory system, if it exists, at or beyond the Point of
Coherency, where a write to memory is maintained when system power is removed, and
reliably recovered when power is restored to the affected locations in memory.
Downstream cache A downstream cache is defined from the perspective of a Request Node. A downstream
cache for a Request, is a cache that the Request accesses using CHI Request transactions. A
Request Node can send a Request with data to allocate data into a downstream cache.
Requester A component that starts a transaction by issuing a Request message. The term Requester can
be used for a component that independently initiates transactions and such a component is
also referred to as a master. The term Requester can also be used for an interconnect
component that issues a downstream Request message independently or as a side-effect of
other transactions that are occurring in the system.
Completer Any component that responds to a transaction it receives from another component. A
Completer can either be an interconnect component, such as Home Node or a Misc Node,
or a component, such as a slave, that is outside of the interconnect.
Master An agent that independently issues transactions. Typically a master is the most upstream
agent in a system. A master can also be referred to as a Requester.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-21
ID082919 Non-Confidential
1 Introduction
1.3 Terminology
Slave An agent that receives transactions and completes them appropriately. Typically, a slave is
the most downstream agent in a system. A slave can also be referred to as a Completer or
Endpoint.
Endpoint Another name for a slave component. As the name implies, an endpoint is the final
destination for a transaction.
Protocol Credit A credit, or guarantee, from a Completer that it will accept a transaction.
Link layer Credit A credit, or guarantee, that a flit will be accepted on the other side of the link. A Link layer
Credit (L-Credit) is a credit for a single hop at the Link layer.
ICN A short form of interconnect, which is the CHI transport mechanism that is used for
communication between protocol nodes. An ICN might include a fabric of switches
connected in a ring, mesh, crossbar, or some other topology. The ICN might include
protocol nodes such as Home Node and Misc Node. The topology of the ICN is
IMPLEMENTATION DEFINED.
RN Request Node. Generates protocol transactions, including reads and writes, to the
interconnect.
HN Home Node. Node located within the interconnect that receives protocol transactions from
Request Nodes, completes the required Coherency action, and returns a Response.
SN Slave Node. Node that receives a Request from a Home Node, completes the required
action, and returns a Response.
MN Misc or Miscellaneous Node. Node located within the interconnect that receives DVM
messages from Request Nodes, completes the required action, and returns a Response.
IO Coherent node An RN that generates a subset of Snoopable requests in addition to Non-snoopable requests.
The Snoopable requests that an IO Coherent node generates do not result in the caching of
the received data in a coherent state. Therefore, an IO Coherent node does not receive any
Snoop requests.
Write-Invalidate protocol
A protocol in which an RN writing to a cache line that is shared in the system must
invalidate all the shared copies before proceeding with the write. The CHI protocol is a
Write-Invalidate protocol.
In a timely manner The protocol cannot define an absolute time within which something must occur. However,
in a sufficiently idle system, it will make progress and complete without requiring any
explicit action.
Don’t Care A field value that indicates that the field can be set to any value, including reserved or illegal
values. Any component receiving a packet with a field value set to Don't Care must ignore
the value set for that field.
Inapplicable A field value that indicates that the field is not used in the processing of the message.
1-22 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.4 Transaction classification
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-23
ID082919 Non-Confidential
1 Introduction
1.4 Transaction classification
Other
• DVMOp.
• PrefetchTgt.
• PCrdReturn.
Snoop
• SnpOnceFwd.
• SnpOnce.
• SnpStashUnique.
• SnpStashShared.
• SnpCleanFwd.
• SnpClean.
• SnpNotSharedDirtyFwd.
• SnpNotSharedDirty.
• SnpSharedFwd.
• SnpShared.
• SnpUniqueFwd.
• SnpUnique.
• SnpUniqueStash.
• SnpCleanShared.
• SnpCleanInvalid.
• SnpMakeInvalid.
• SnpMakeInvalidStash.
• SnpDVMOp.
1-24 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.5 Coherence overview
Regions of memory are coherent if writes to the same memory location by two components are observable in the
same order by all components.
Coherent interconnect
ICN (ICN) Cache
Main
SN-F
memory
Slave 1
The coherence protocol ensures that all masters observe the correct data value at any given address location by
enforcing that no more than one copy exists whenever a store occurs to the location. After each store to a location,
other masters can obtain a new copy of the data for their own local cache, to permit multiple cached copies to exist.
All coherency is maintained at cache line granularity. A cache line is defined as a 64-byte aligned memory region
that is 64-bytes in size.
The protocol does not require main memory to be up to date at all times. Main memory is only required to be updated
before a copy of the memory location is no longer held in any cache.
Note
Although not a requirement, it is acceptable to update main memory while cached copies still exist.
The protocol enables master components to determine whether a cache line is the only copy of a particular memory
location, or if there might be other copies of the same location, so that:
• If a cache line is the only copy, a master component can change the value of the cache line without notifying
any other master components in the system.
• If a cache line might also be present in another cache, a master component must notify the other caches using
an appropriate transaction.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-25
ID082919 Non-Confidential
1 Introduction
1.5 Coherence overview
Valid, Invalid When Valid, the cache line is present in the cache. When Invalid, the cache line is not
present in the cache.
Unique, Shared When Unique, the cache line exists only in this cache. When Shared, the cache line might
exist in more than one cache, but this is not guaranteed.
Clean, Dirty When Clean, the cache does not have responsibility for updating main memory. When Dirty,
the cache line has been modified with respect to main memory, and this cache must ensure
that main memory is eventually updated.
Full, Partial, Empty A Full cache line has all bytes valid. A Partial cache line might have some bytes valid, but
not all bytes valid. An Empty cache line has no bytes valid.
Figure 1-3 shows the seven state cache model. Cache line states on page 4-142 gives further information about each
cache state.
A valid cache state name that is not Partial or Empty is considered to be Full. In Figure 1-3 UC, UD, SC, and SD
are all Full cache line states.
Valid Invalid
Unique Shared
UC SC
Clean
UCE
I
UD SD
Dirty
UDP
1-26 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.6 Component naming
RN Request Node. Generates protocol transactions, including reads and writes to the interconnect.
An RN is further categorized as:
RN-F Fully coherent Request Node:
• Includes a hardware-coherent cache.
• Permitted to generate all transactions defined by the protocol.
• Supports all Snoop transactions.
RN-D IO coherent Request Node with DVM support:
• Does not include a hardware-coherent cache.
• Receives DVM transactions.
• Generates a subset of transactions defined by the protocol.
RN-I IO coherent Request Node:
• Does not include a hardware-coherent cache.
• Does not receive DVM transactions.
• Generates a subset of transactions defined by the protocol.
• Does not require snoop functionality.
HN Home Node. Node located within the interconnect that receives protocol transactions from RNs.
An HN is further categorized as:
HN-F Fully coherent Home Node:
• Is expected to receive all Request types except DVMOp.
• Includes a Point of Coherence (PoC) that manages coherency by snooping the
required RN-Fs, consolidating the snoop responses for a transaction, and sending
a single response to the requesting RN.
• Is expected to be the Point of Serialization (PoS) that manages order between
memory requests.
• Might include a directory or snoop filter to reduce redundant snoops.
Note
IMPLEMENTATION SPECIFIC, can include an integrated ICN cache.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-27
ID082919 Non-Confidential
1 Introduction
1.6 Component naming
SN Slave Node. An SN receives a request from an HN, completes the required action and returns a
response.
An SN is further categorized as:
SN-F A Slave Node type used for Normal memory. It can process Non-snoopable read write,
and atomic requests, including exclusive variants of them, and Cache Maintenance
Operation (CMO) requests.
SN-I A Slave Node type used for peripherals or Normal memory. It can process
Non-snoopable read, write and atomic requests, including exclusive variants of them,
and CMO requests.
Figure 1-4 shows various protocol node types connected through an interconnect.
Masters
(Fully coherent)
Master
(IO coherent)
Interconnect (ICN)
MN
RN-I
SN-I SN-F
Slave Slave
(Peripheral and/or Normal Memory) Slaves (Normal Memory)
1-28 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
1 Introduction
1.7 Read data source
Data
Req
Snoop
Data
Home ICN
Req
The Read latency saving techniques supported in this specification, which use the reduction of the number of hops,
can be categorized as:
The Data provider in the DCT Read transaction flows has to inform the Home that it has sent Data to the Requester
and, in some cases, it also has to send a copy of Data to the Home.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 1-29
ID082919 Non-Confidential
1 Introduction
1.7 Read data source
1-30 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 2
Transactions
This chapter gives an overview of the communication channels between nodes, the associated packet fields, and the
transaction structure. It contains the following sections:
• Channels overview on page 2-32.
• Channel fields on page 2-33.
• Transaction structure on page 2-39.
• Transaction identifier fields on page 2-73.
• Details of transaction identifier fields on page 2-74.
• Transaction identifier field flows on page 2-77.
• Logical Processor Identifier on page 2-98.
• Ordering on page 2-99.
• Address, Control, and Data on page 2-109.
• Data transfer on page 2-118.
• Request Retry on page 2-129.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-31
ID082919 Non-Confidential
2 Transactions
2.1 Channels overview
This section uses shorthand naming for the channels to describe the transaction structure. Table 2-1 shows the
shorthand name and the physical channel name that exists on the RN or SN component.
See Channel on page 12-315 for the mapping of physical channels on the RN and SN components.
2-32 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.2 Channel fields
The term transaction structure is used to describe the different packets that build a transaction and the transaction
structure can vary depending on a number of factors. Table 2-2 shows which Request fields can affect the
transaction structure. More information on the different transaction structures can be found in Transaction structure
on page 2-39 and Flit packet definitions on page 12-324.
Affects
Field Description
structure
QoS No Quality of Service priority. Specifies 1 of 16 possible priority levels for the
transaction with ascending values of QoS indicating higher priority levels. See
Chapter 10 Quality of Service.
TgtID No Target ID. The node ID of the port on the component to which the packet is
targeted. See Details of transaction identifier fields on page 2-74 and System
address map on page 3-134.
SrcID No Source ID. The node ID of the port on the component from which the packet
was sent. See Details of transaction identifier fields on page 2-74.
TxnID No Transaction ID. A transaction has a unique transaction ID per source node. See
Details of transaction identifier fields on page 2-74.
LPID No Logical Processor ID. Used in conjunction with the SrcID field to uniquely
identify the logical processor that generated the request. See Logical
Processor Identifier on page 2-98.
Deep No Deep persistence. Indicates that the Persist response must not be sent until all
earlier writes are written to the final destination. See Use of Deep attribute in
Persistent CMO on page 4-151.
ReturnNID No Return Node ID. The node ID that the response with Data is to be sent to. See
Details of transaction identifier fields on page 2-74.
ReturnTxnID No Return Transaction ID. The unique transaction ID that conveys the value of
TxnID in the data response from the Slave. See Details of transaction
identifier fields on page 2-74.
StashNID No Stash Node ID. The node ID of the Stash target. See StashNID on page 12-331.
StashNIDValid Yes Stash Node ID Valid. Indicates that the StashNID field has a valid Stash target
value. See StashNIDValid on page 12-331.
StashLPID No Stash Logical Processor ID. The ID of the logical processor at the Stash target.
See StashLPID on page 12-331.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-33
ID082919 Non-Confidential
2 Transactions
2.2 Channel fields
Affects
Field Description
structure
StashLPIDValid No Stash Logical Processor ID Valid. Indicates that the StashLPID field value
must be considered as the Stash target. See StashLPIDValid on page 12-331.
Opcode Yes Request opcode. Specifies the transaction type and is the primary field that
determines the transaction structure. See Request types on page 4-144 and
REQ channel opcodes on page 12-334.
Addr No Address. The address of the memory location being accessed for read and
write requests. See Address on page 2-109 and Addr on page 12-339.
Size Yes Data size. Specifies the size of the data associated with the transaction. This
determines the number of data packets within the transaction. See Data
transfer on page 2-118.
AllowRetry Yes Allow Retry. Determines if the target is permitted to give a Retry response. See
Request Retry on page 2-129.
PCrdType No Protocol Credit Type. Indicates the type of Protocol Credit being used by a
request that has the AllowRetry field deasserted. See Request Retry on
page 2-129.
ExpCompAck Yes Expect CompAck. Indicates that the transaction will include a Completion
Acknowledge message. See Transaction structure on page 2-39 and Ordering
on page 2-99.
MemAttr No Memory attribute. Determines the memory attributes associated with the
transaction. See Memory Attributes on page 2-110.
SnpAttr No Snoop attribute. Specifies the snoop attributes associated with the transaction.
See Likely Shared on page 2-115.
SnoopMe No Snoop Me. Indicates that Home must determine whether to send a snoop to the
Requester. See Atomics on page 2-62.
LikelyShared No Likely Shared. Provides an allocation hint for downstream caches. See Likely
Shared on page 2-115.
Order Yes Order requirement. Determines the ordering requirement for this request with
respect to other requests from the same agent. See Ordering on page 2-99.
Endian No Endianness. Indicates the endianness of Data in the Data packet for Atomic
transactions. See Endianness on page 2-122.
TraceTag No Trace Tag. Provides additional support for the debugging, tracing, and
performance measurement of systems. See Chapter 11 System Debug, Trace,
and Monitoring.
2-34 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.2 Channel fields
Affects
Field Description
structure
QoS No Quality of Service priority. As defined in Request channel fields on page 2-33. See
Chapter 10 Quality of Service.
TxnID No Transaction ID. As defined in Request channel fields on page 2-33. See Details of
transaction identifier fields on page 2-74.
FwdNID No Forward Node ID. Node ID of the original Requester. See Details of transaction
identifier fields on page 2-74.
FwdTxnID No Forward Transaction ID. The transaction ID used in the Request by the original
Requester. See Details of transaction identifier fields on page 2-74.
StashLPID No Stash Logical Processor ID. As defined in Request channel fields on page 2-33. See
Stash messages on page 7-256.
VMIDExt No Virtual Machine ID Extension. See DVM Operation types on page 8-268.
SrcID No Source ID. As defined in Request channel fields on page 2-33. See Details of
transaction identifier fields on page 2-74.
Opcode Yes Snoop opcode. See Snoop request fields and SNP channel opcodes on page 12-337.
Addr No Address. The address of the memory location being accessed for Snoop requests.
See Address on page 2-109 and Addr on page 12-339.
DoNotGoToSD No Do Not Go To SD state. Controls Snoopee use of SD state. See Do not transition to
SD on page 4-199.
DoNotDataPull Yes Do Not Data Pull. Instructs the Snoopee that it is not permitted to use the Data Pull
feature associated with Stash requests. See Snoop requests and Data Pull on
page 7-250.
RetToSrc Yes Return to Source. Instructs the receiver of the snoop to return Data with the Snoop
response. See Returning Data with Snoop response on page 4-198.
TraceTag No Trace Tag. As defined in Request channel fields on page 2-33. See Chapter 11
System Debug, Trace, and Monitoring.
Note
This specification does not define a TgtID field for the Snoop request. See Target ID determination for Snoop
Request messages on page 3-137.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-35
ID082919 Non-Confidential
2 Transactions
2.2 Channel fields
Field Description
TgtID Target ID. As defined in Request channel fields on page 2-33. See Details of
transaction identifier fields on page 2-74.
SrcID Source ID. As defined in Request channel fields on page 2-33. See Details
of transaction identifier fields on page 2-74.
TxnID Transaction ID. As defined in Request channel fields on page 2-33. See
Details of transaction identifier fields on page 2-74.
HomeNID Home Node ID. The Node ID of the target of the CompAck response to be
sent from the Requester. See Details of transaction identifier fields on
page 2-74.
CBusy Completer Busy. Indicates the current level of activity at the Completer. See
Completer Busy on page 11-307.
DBID Data Buffer ID. The ID provided to be used as the TxnID in the response to
this message. See Details of transaction identifier fields on page 2-74 and
Ordering on page 2-99.
Opcode Data opcode. Indicates, for example, if the data packet is related to a Read
transaction, a Write transaction, or a Snoop transaction. See DAT channel
opcodes on page 12-338.
RespErr Response Error status. Indicates the error status associated with a data
transfer. See Chapter 6 Exclusive Accesses and Error response fields on
page 9-281.
Resp Response status. Indicates the cache line state associated with a data transfer.
See Response types on page 4-166.
FwdState Forward State. Indicates the cache line state associated with a data transfer
to the Requester from the receiver of the snoop. See FwdState on
page 12-348.
DataPull Data Pull. Indicates the inclusion of an implied Read request in the Data
response. See Snoop requests and Data Pull on page 7-250.
DataSource Data Source. The value indicates the source of the data in a read Data
response. See Data Source indication on page 11-302.
CCID Critical Chunk Identifier. Replicates the address offset of the original
transaction request. See Data transfer on page 2-118.
DataID Data Identifier. Provides the address offset of the data provided in the packet.
See Data transfer on page 2-118.
2-36 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.2 Channel fields
Field Description
DataCheck Data Check. Detects data errors in the DAT packet. See Data Check on
page 9-291.
Poison Poison. Indicates that a set of data bytes has previously been corrupted. See
Poison on page 9-290.
TraceTag Trace Tag. As defined in Request channel fields on page 2-33. See
Chapter 11 System Debug, Trace, and Monitoring.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-37
ID082919 Non-Confidential
2 Transactions
2.2 Channel fields
Field Description
TgtID Target ID. As defined in Request channel fields on page 2-33. See Details of
transaction identifier fields on page 2-74.
SrcID Source ID. As defined in Request channel fields on page 2-33. See Details
of transaction identifier fields on page 2-74.
TxnID Transaction ID. As defined in Request channel fields on page 2-33. See
Details of transaction identifier fields on page 2-74.
CBusy Completer Busy. As defined in Data fields on page 2-36. See Completer
Busy on page 11-307.
DBID Data Buffer ID. As defined in Data packet fields on page 2-36. See Details
of transaction identifier fields on page 2-74 and Ordering on page 2-99.
PGroupID Persistence Group ID. As defined in Request channel fields on page 2-33.
See PGroupID on page 12-331.
Opcode Response opcode. Specifies the response type. See RSP channel opcodes on
page 12-336.
RespErr Response Error status. As defined in Data packet fields on page 2-36. See
Chapter 6 Exclusive Accesses and Error response fields on page 9-281.
Resp Response status. As defined in Data packet fields on page 2-36. See
Response types on page 4-166.
FwdState Forward State. As defined in Data packet fields on page 2-36. See FwdState
on page 12-348.
DataPull Data Pull. As defined in Data packet fields on page 2-36. See Snoop requests
and Data Pull on page 7-250.
TraceTag Trace Tag. As defined in Request channel fields on page 2-33. See
Chapter 11 System Debug, Trace, and Monitoring.
2-38 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
For a Request transaction to complete, a Snoop transaction might be required. However, such dependencies are not
visible at the Requester, so these two transaction types are generally presented separately. See Chapter 5
Interconnect Protocol Flows for examples of how Request and Snoop flows are related.
All transaction types, except PCrdReturn and PrefetchTgt can have a Retry sequence at the start of the transaction.
For ease of presentation, the Retry sequence is described separately. See Transaction Retry sequence on page 2-66.
The Snoopable Read transactions described in this section are used by a fully coherent Requester (RN-F) to carry
out a read when the snooping of other Snoopable Requesters (RN-Fs) is required.
The transaction structures for ReadOnce* transactions, which are also Snoopable transactions, are described along
with ReadNoSnp in subsequent sections of this chapter.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-39
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
A Snoopable Read transaction with DMT is used when the data can be sent directly from the Slave to the original
Requester. The progress of the Snoopable Read transaction with DMT is as follows:
3. The SN, as Completer, forwards the read data and any associated transaction response with the CompData
opcode directly to the Requester on the RDAT channel.
The read data can be sent using multiple transfers. See Data transfer on page 2-118.
4. Because the transaction request ExpCompAck bit is set, the Requester must return an acknowledgement,
using the CompAck opcode on the SRSP channel to indicate that the transaction has completed.
RN-F ICN SN
Snoopable
REQ
Read
ReadNoSnp REQ
RDAT RDAT
CompData
SRSP CompAck
• CompData must only be sent by the Completer after the associated request is received.
• The Requester must only send CompAck after at least one CompData packet is received.
Note
Prior to CHI Issue C, CompAck must not be sent until all Data packets of read data have been received.
The Snoopable Read transaction that Figure 2-1 shows can include a separate Comp and Data response instead of
the CompData response. The transaction structure for reads with separate Comp and Data response is described in
Reads with separate Non-data and Data-only responses on page 2-50.
Note
Prior to CHI issue C, a separate Comp and Data response is not permitted.
2-40 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
DMT restrictions
• A Requester can reuse the TxnID only after all the responses that could use the TxnID have been returned.
• Home must wait to send a DMT request to SN-F until it is guaranteed that all the following applicable
conditions are true:
— A Snoop request does not need to be sent.
— If a Snoop request is sent, then the Snoop response is received without a Dirty copy of the cache line
being returned.
— If the Snoop response returns a partial Dirty copy of the cache line, then the DMT can only be sent if
the partial data is written to SN-F and a completion for the write is received.
— If the snoop is a Forwarding type snoop, then it does not result in the cache line being forwarded to
the Requester.
Note
Home can enable DMT in combination with DCT but must wait for the DCT response to be received before sending
the DMT request to SN-F.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-41
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
A Snoopable Read transaction with DCT is used when the data is to be sent directly from the Snooped RN-F to the
original Requester. The progress of the Snoopable read transaction with DCT is as follows:
2. The ICN sends a Snp[*]Fwd request to the RN-F on the SNP channel.
3. The RN-F as the Completer forwards the read data and any associated transaction response to RN with the
CompData opcode on the DAT channel.
The data can be sent using multiple transfers. See Data transfer on page 2-118.
4. The RN-F also forwards a SnpRespFwded response to the ICN on the SRSP channel to indicate that read data
was forwarded to the Requester.
5. Because the transaction request ExpCompAck bit is set, the Requester must return an acknowledgement,
using the CompAck opcode on the SRSP channel to indicate that the transaction has completed.
RN ICN RN-F
Snoopable
REQ
Read
Snp[*]Fwd SNP
WDAT
RDAT CompData
SnpRespFwded SRSP
SRSP CompAck
2-42 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
This section shows the Read transaction structure without DMT or DCT.
The progress of a Snoopable Read transaction without Direct Data Transfer, from the Requester perspective, is
identical to a Snoopable Read transaction with Direct Data Transfer and is as follows:
2. The Completer returns the read data and any associated transaction response with the CompData opcode on
the RDAT channel.
The read data can be sent using multiple transfers. See Data transfer on page 2-118.
3. Because the ExpCompAck bit is set, the Requester must return an acknowledgement, using the CompAck
opcode on the SRSP channel to indicate that the transaction has completed.
CompAck can be sent as soon as the first Data packet of read data has been received.
Separate Comp and Data responses are possible. See Reads with separate Non-data and Data-only responses
on page 2-50.
Note
Prior to CHI issue C:
• CompAck must not be sent until all Data packets of read data have been received.
• Separate Comp and Data responses are not permitted.
RN ICN
Snoopable
REQ
Read
RDAT CompData
SRSP CompAck
• CompData must only be sent by the Completer after the associated request is received.
• If the data being sent is received from either a Slave or snooped Agent then the ICN is permitted to forward
the CompData packets as soon as it receives the first packet from the Slave or snooped Agent.
• CompAck can be sent as soon as the first Data packet of read data has been received.
Note
Prior to CHI Issue C, CompAck must not be sent until all Data packets of read data have been received.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-43
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Data obtained by ReadNoSnp either comes directly from the Slave Node or via the interconnect.
A ReadOnce, ReadOnceCleanInvalid, and ReadOnceMakeInvalid transaction is used to carry out a read when the
snooping of other masters is required but the Requester is not going to allocate the cache line in its own cache.
Note
ReadOnce, ReadOnceCleanInvalid, and ReadOnceMakeInvalid obtain a snapshot of the coherent data value. If a
Requester holds this value in a local buffer or cache, the data value will no longer be coherent.
In the remainder of this section ReadOnce* represents the three transaction types, ReadOnce,
ReadOnceCleanInvalid, and ReadOnceMakeInvalid.
Data obtained by ReadOnce* either comes directly from the Slave Node or a peer Request Node, or via the
interconnect.
ReadNoSnp and ReadOnce* transactions can optionally have an ordering requirement. For transactions that require
ordering, the Home must ensure that a transaction is observable before taking any action that could make a later
ordered transaction observable. Such a transaction can include a ReadReceipt response from the Home to the
Requester.
ReadNoSnp and ReadOnce* transactions can optionally set the ExpCompAck field, indicating that the transaction
will include a CompAck response. The use of a CompAck response is not functionally required for ReadNoSnp and
ReadOnce* transactions, as the RN issuing the transaction will not hold a copy of the cache line. However, use of
CompAck permits the use of DMT and separate Comp and Data responses in some cases.
2-44 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
1. Requester sends a request with the ReadNoSnp or ReadOnce* opcode on the REQ channel.
2. If the request Order field indicates that ordering is required, then a ReadReceipt response must be returned
on the CRSP channel when order has been established.
4. SN returns a ReadReceipt response to ICN on the CRSP channel if the ReadNoSnp request has Order[1:0]
set to 0b01.
5. SN, as Completer, returns the read data and any associated transaction response with the CompData opcode
directly to the Requester on the RDAT channel.
The read data can be sent using multiple transfers. See Data transfer on page 2-118.
6. If the transaction request ExpCompAck bit is set, the Requester must return an acknowledgement, using the
CompAck opcode on the SRSP channel to indicate that the transaction has completed.
CompAck can be sent as soon as the first Data packet of read data has been received.
Note
Prior to CHI Issue C, CompAck must not be sent until all Data packets of read data have been received.
RN ICN SN
ReadNoSnp
REQ
ReadOnce*
Optional
CRSP ReadReceipt
ReadNoSnp REQ
Optional
ReadReceipt CRSP
RDAT RDAT
CompData
Optional
SRSP CompAck
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-45
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
The life time at the Home of ReadNoSnp and ReadOnce* transactions that use DMT can be reduced by using the
ReadReceipt response from the Slave as a read received acknowledgment to deallocate the transaction at Home. The
ReadReceipt from SN, marked as optional in Figure 2-4, becomes required when used to early deallocate the request
at the Home when used instead of CompAck from the Requester, which typically comes later, to deallocate the
request. See ReadOnce* and ReadNoSnp with early Home deallocation on page 5-212 for an example of this type
of flow. See Table 2-6 on page 2-49 for the relationship between DMT and the use of Read Received Ack, in the
form of a ReadReceipt, and CompAck and Ordering requirements in ReadOnce* and ReadNoSnp transactions.
• Home must set Order[1:0] to the value 0b01 in the Read request to the Slave Node.
• For a Request with Order[1:0] set to the value 0b01 the Slave must send a ReadReceipt to acknowledge the
Read request when it can guarantee that the request is accepted and that it will not send a RetryAck response.
• Home is permitted to deallocate the request after receiving the ReadReceipt without waiting for a CompAck
if the requests from RN do not have an ordering requirement.
2-46 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
1. Requester sends a request with the ReadOnce* opcode on the REQ channel.
3. RN-F, as the Completer, forwards the read data and any associated transaction response to RN with the
CompData opcode on the DAT channel.
The read data can be sent using multiple transfers. See Data transfer on page 2-118.
4. RN-F also forwards a SnpRespFwded response to ICN on the SRSP channel to indicate that read data was
forwarded to the Requester. Alternatively, the response to the ICN can include data and will be a
SnpRespDataFwded response.
5. If the transaction request ExpCompAck bit is set, the Requester must return an acknowledgement, using the
CompAck opcode on the SRSP channel to indicate that the transaction has completed.
CompAck can be sent as soon as the first Data packet of read data has been received.
Note
Prior to CHI Issue C, CompAck must not be sent until all Data packets of read data have been received.
RN ICN RN-F
REQ ReadOnce*
Snp[*]Fwd SNP
WDAT
RDAT CompData
SRSP CompAck
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-47
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
The progress of a ReadNoSnp and a ReadOnce* transaction without Direct Data Transfer, from the Requester
perspective, is identical to a ReadNoSnp and ReadOnce* transaction with Direct Data Transfer and is as follows:
1. Requester sends a request with the ReadNoSnp or ReadOnce* opcode on the REQ channel.
2. If the request Order field indicates that ordering is required then a ReadReceipt response must be returned on
the CRSP channel when order has been established.
3. Completer returns the read data and any associated transaction response with the CompData opcode on the
RDAT channel.
The read data can be sent using multiple transfers. See Data transfer on page 2-118.
4. If the transaction request ExpCompAck bit is set, the Requester must return an acknowledgement, using the
CompAck opcode on the SRSP channel to indicate that the transaction has completed.
CompAck can be sent as soon as the first Data packet of read data has been received.
Note
Prior to CHI Issue C, CompAck must not be sent until all Data packets of read data have been received.
RN ICN
ReadNoSnp
REQ
ReadOnce*
CRSP ReadReceipt
ReadReceipt is sent if
RDAT CompData Order is set in the
transaction request.
SRSP CompAck
CompAck is sent if
ExpCompAck is set in
the transaction request.
Figure 2-6 ReadNoSnp and ReadOnce* structure without Direct Data Transfer
2-48 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
• CompData must only be sent by the Completer after the associated request is received.
• If the data being sent is received from either a Slave or snooped Agent then the ICN is permitted to forward
the CompData packets as soon as it receives the first packet from the Slave or snooped Agent.
Table 2-6 Permitted DMT and DCT for ReadNoSnp and ReadOnce* from an RN
01 - - - Not permitted.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-49
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Note
Separate Non-data and Data-only response is not supported prior to CHI Issue C.
The progress of a Read* with separate Comp and Data responses is as follows:
2-50 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
RN ICN SN
REQ Read*
ReadNoSnpSep REQ
CRSP RespSepData
ReadReceipt CRSP
SRSP CompAck
RDAT
RDAT DataSepResp
Required for:
ReadOnce and ReadNoSnp
if Order field is set.
Permitted, but not required,
for all other Reads
Comp and Data from Home
RN ICN
REQ
Read*
CRSP RespSepData
SRSP CompAck
RDAT
DataSepResp
Required for:
ReadOnce and ReadNoSnp
if Order field is set.
Permitted, but not required,
for all other Reads
Figure 2-7 Read* DMT structure with separate Non-data and Data-only responses
Note
As Figure 2-7 shows, the CompAck acknowledgement sent by the Requester to ICN is permitted, but not required,
to wait for DataSepResp except in the case of an ordered ReadOnce and ReadNoSnp request with CompAck,
whereas it is required to wait for RespSepData.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-51
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
• DataSepResp and RespSepData must only be sent by the Completer after the associated request is received.
RespSepData is permitted from the Home only. DataSepResp is permitted to be sent by the Slave or Home.
• CompAck acknowledgement must only be sent by the Requester after the RespSepData response is received:
— For Non-ordered requests, it is permitted, but not required, for a Requester to wait for any or all data
to be received before sending a CompAck acknowledgement.
— For ReadOnce and ReadNoSnp requests with an Order requirement, the Requester is required to wait
for at least one Data response to be received before sending a CompAck acknowledgement.
• It is required that the Completer must not wait for CompAck before sending all Data packets.
• ReadNoSnpSep must only be sent by the Home to the Slave after the associated request is received, and
Snoop responses are received for all snoops that are required to be sent.
• The Slave must send the ReadReceipt response to the Home only after receiving ReadNoSnpSep and
ensuring that it will not respond with RetryAck for that request.
• The ReadReceipt from the Slave is sufficient to indicate to the Home that the request to the Slave will be
completed.
A separate Comp response from the Slave to the Home is not required and must not be sent. For ReadOnce
and ReadNoSnp requests with an Order requirement, the Home determines that the request has been
completed by receiving a CompAck response.
• For ReadOnce and ReadNoSnp transactions, with an Order requirement, that include separate Comp and
Data responses, the Home must not send a ReadReceipt response. The RespSepData response from Home
includes an implied ReadReceipt.
In all cases, where a separate Data response and Home response can be used, it is also permitted to use a combined
CompData response.
Table 2-7 on page 2-53 shows the expected and permitted use of separate Non-data and Data-only responses, or the
combined CompData response, with different combinations of Order and ExpCompAck values for ReadNoSnp and
ReadOnce*.
2-52 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
Table 2-7 Use of separate Comp and Data responses with different combinations of Order and ExpCompAck for
ReadNoSnp and ReadOnce*
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-53
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Table 2-7 Use of separate Comp and Data responses with different combinations of Order and ExpCompAck for
ReadNoSnp and ReadOnce* (continued)
2-54 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
Dataless
The Dataless transactions can be divided into Non-Cache Maintenance (Non-CMO) and Cache Maintenance
(CMO) transactions.
The progress of a Non-CMO Dataless transaction from the Requester perspective is as follows:
3. If the transaction request ExpCompAck field is set, the Requester must return an acknowledgement that the
transaction has completed with the CompAck opcode on the SRSP channel:
• ExpCompAck must be asserted for:
— CleanUnique.
— MakeUnique.
• ExCompAck must not be asserted for:
— Evict.
— StashOnceUnique.
— StashOnceShared.
RN ICN
REQ Dataless
CRSP Comp
SRSP CompAck
CompAck is sent if
ExpCompAck is permitted and
set in the transaction request.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-55
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
These transactions are used to perform cache maintenance on different levels of caches in the system.
With the exception of CleanSharedPersistSep, only a single response is given for CMO transactions.
The progress of a CMO Dataless transaction from the Requester perspective is as follows:
3. For the CleanSharedPersistSep transaction the Completer also returns a Persist response to the Requester.
The Completer is permitted to combine the Comp and Persist responses into a single CompPersist response.
Figure 2-9 on page 2-57 shows the transaction structure and includes the transaction structure when the request is
propagated downstream of the ICN.
2-56 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
RN ICN
REQ CMO
CRSP Comp
CRSP Persist
RN HN SN
REQ CMO
CRSP Comp
Only if request is
CleanSharedPersistSep
• Comp must only be sent by the Completer after the associated request is received.
If there is an observer downstream of Home then the Home must wait for Comp from downstream before
sending the Comp response to the Requester.
• The Home, when sending CleanSharedPersistSep to the Slave Node, is permitted, but not expected, to set the
ReturnNID in the request to itself. If the Home sets the ReturnNID to itself, then it must send a Persist
response to the Requester in addition to a Comp. Home must wait for the Persist response from the Slave
before sending the Persist response to the Requester. In such a scenario Home is permitted, but not expected,
to wait for the Persist response from the Slave and then send a combined CompPersist response to the
Requester instead of sending an earlier separate Comp response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-57
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
2-58 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
Writes
Write transactions include the following:
• WriteNoSnp.
• WriteUnique.
• WriteBack.
• WriteCleanFull.
• WriteEvictFull.
A WriteNoSnp transaction is used to carry out a store where the snooping of other masters is not required.
WriteUnique transactions are used to perform a store to a location when the snooping of other Snoopable Requesters
(RN-Fs) might be required to obtain permission to store.
In the remainder of this section Non-CopyBack writes will refer to both WriteNoSnp and WriteUnique.
There is one optional behavior associated with Non-Copyback transactions. The behavior is determined by the
Order field in the transaction request. See Streaming Ordered Write transactions on page 2-106 for details on the
use of CompAck to force the order in which requests are observed.
1. The Requester sends a request with the Non-Copyback opcode on the REQ channel.
3. The Requester sends the write data and any associated byte enables with the NonCopyBackWrData opcode
on the WDAT channel. The write data can be sent using multiple transfers. See Data transfer on page 2-118.
4. If the ExpCompAck field is set in the transaction request, then the transaction completes with a CompAck
transaction acknowledge. Opportunistically, CompAck can be combined with the Data response and sent as
NCBWrDataCompAck.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-59
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
RN ICN RN ICN
DBIDResp
CRSP CRSP CompDBIDResp
Comp
RN ICN RN ICN
DBIDResp
CRSP CRSP CompDBIDResp
Comp
The separate DBIDResp and Comp, or the combined CompDBIDResp, must only be sent by the interconnect after
the associated request is received.
WriteData must only be sent by the Requester after either DBIDResp or CompDBIDResp is received.
2-60 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
Note
Prior to CHI Issue D, asserting ExpCompAck in WriteNoSnp was not permitted.
CopyBack
CopyBack transactions, except WriteEvictFull, are used to update main memory or a downstream cache for a
coherent location.
A WriteEvictFull transaction is used to update only a downstream cache for a coherent location.
2. The Completer returns a single combined CompDBIDResp response on the CRSP channel to indicate:
• It can accept the write data for the transaction.
• This request will complete before any snoop to the same address is received.
3. After the Requester has received the CompDBIDResp response it sends the write data, and any associated
byte enables, with the CopyBackWrData opcode on the WDAT channel. The write data can be sent using
multiple transfers. See Data transfer on page 2-118.
RN ICN
REQ CopyBack
CRSP CompDBIDResp
WDAT WriteData
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-61
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Atomics
Atomic transactions can be classified in two categories based on their transaction structure:
Figure 2-12 on page 2-63 shows the structure of Atomic transactions at the Requester interface.
1. The Requester sends a request with the Atomic transaction opcode on the REQ channel.
2. Depending on the type of Atomic transaction the Completer has different options:
a. If the request is an AtomicStore then the Completer has one of the following options:
• Return separate responses:
— Return a DBIDResp response that provides a data buffer identifier indicating that it can
accept the Write data for the transaction.
— Return a Comp response to indicate that the transaction is observable by other
Requesters.
Both responses are returned on the CRSP channel.
• Return a single combined CompDBIDResp response to indicate:
— It can accept the write data for the transaction.
— The transaction is observable by other Requesters.
The combined response is returned on the CRSP channel.
b. If the request is an Atomic Load, AtomicSwap, or AtomicCompare then the Completer does the
following:
• Returns a DBIDResp response on the CRSP channel. The DBIDResp response provides a data
buffer identifier indicating that it can accept the Write data for the transaction.
• Returns the Read data and any associated transaction response with the CompData opcode on
the RDAT channel.
3. The Requester sends the Write data and any associated byte enables with the NonCopyBackWrData opcode
on the WDAT channel. For AtomicCompare the Write data can be sent using multiple transfers. See Data
transfer on page 2-118.
2-62 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
RN ICN RN ICN
AtomicLoad
REQ AtomicStore REQ AtomicSwap
AtomicCompare
DBIDResp DBIDResp
CRSP CRSP
Comp CompData
The separate DBIDResp and Comp, or the combined CompDBIDResp must only be sent by the Completer after the
associated request is received.
The CompData must only be sent by the Completer after the associated request is received.
WriteData must only be sent by the Requester after either DBIDResp or CompDBIDResp is received.
• If the request is an AtomicStore and the DBIDResp and Comp responses are sent separately:
— Typically, the DBIDResp is sent by the Completer before Comp. However, it is permitted for
DBIDResp and Comp to arrive in any order.
— The Requester must send the Write data after it has received the DBIDResp response.
— The Requester must not wait to receive the Comp response before the Write data is sent.
— The Completer is permitted to wait for the WriteData before sending the Comp response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-63
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
This specification permits self-snooping of the Requester in Atomic transactions. The optional self-snoop is not
shown in the figure. Self-snooping is controlled by the SnoopMe bit value in the Atomic request. See SnoopMe on
page 12-343. The Request-Response rules for self-snooping in Atomic transactions are:
• An RN that does not invalidate its own cached copy of the cache line before sending an Atomic request must
rely on self-snooping to:
— Invalidate its own cached copy of the cache line.
— Obtain a copy of the cache line if Dirty.
Note
An RN is permitted:
• To send a CopyBack request while the Atomic request to the same address with SnoopMe asserted is in
progress.
• To issue an Atomic request with SnoopMe asserted while a CopyBack request to the same address is in
progress.
DVM
1. The Requester sends a request with the DVMOp opcode on the REQ channel.
2. The Completer returns a DBIDResp response that provides a data buffer identifier indicating that it can
accept the write data for the transaction.
3. The Requester sends the write data for the DVM transaction, with the NonCopyBackWrData opcode, on the
WDAT channel. Only a single data transfer occurs for a DVM transaction.
2-64 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
RN ICN
REQ DVMOp
CRSP DBIDResp
Optional for
WDAT WriteData Non-sync
DVMOp only
CRSP Comp
PrefetchTgt
A Request to a shareable memory address sent from a Request Node directly to a Slave Node. The request can be
used by the Slave Node to fetch and buffer data from main memory in anticipation of a subsequent Read request to
the same location.
• The Requester sends a PrefetchTgt request on the REQ channel. The PrefetchTgt transaction does not include
a response.
RN SN
REQ PrefetchTgt
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-65
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Retry sequence
Request transactions are first sent without a Protocol Credit (P-Credit). If the transaction cannot be accepted at its
Completer, then a RetryAck response must be given that indicates that the transaction has not been accepted and
can be sent again when an appropriate credit is provided. When a transaction is sent a second time, with a credit, it
is guaranteed to be accepted.
For further details on the Retry process and the use of credits see Request Retry on page 2-129.
3. The Completer provides a PCrdGrant response on the CRSP channel, when appropriate, to indicate that a
credit is available to re-send the transaction.
4. The Requester sends the transaction again, with a credit, on the REQ channel.
RN ICN
Transaction
REQ
no Credit
RetryAck
CRSP
PCrdGrant
Transaction
REQ
with Credit
• RetryAck must only be sent by the Completer after the associated request is received.
• PCrdGrant must only be sent by the Completer after the associated request is received.
• RetryAck is typically sent by the Completer before PCrdGrant. However, it is permitted to send RetryAck
after PCrdGrant.
• RetryAck is typically received by the Requester before PCrdGrant. However, it is permitted to receive
RetryAck after PCrdGrant.
• The transaction with credit must only be sent by the Requester after both the RetryAck response and an
appropriate PCrdGrant response are received.
2-66 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
The sequence and rules are identical to those for a Retry sequence.
RN ICN
Transaction
REQ
no Credit
RetryAck
RSP
PCrdGrant
REQ PCrdReturn
• An RN-F and RN-D must respond to received Snoop requests, except for DVMOp(Sync), in a timely manner,
without creating any dependency on completion of outstanding requests.
A snoop transaction can also be used to stash data at the Snoopee. The options for the transaction structure of a Stash
type snoop are:
• Stashing snoop with Data from Home.
• Stashing snoop with Data using DMT.
Note
Figures relating to Snoop transactions show the snooped Request Node (RN) on the right, and the interconnect
(ICN) on the left. This is consistent with the ordering of the Request/Snoop process.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-67
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
1. The interconnect provides a Snoop request on the SNP channel that can be any Snoop transaction supported
by the RN.
ICN RN-F
Snoop
SNP
Transaction
SRSP SnpResp
• SnpResp must only be sent by the RN after the associated Snoop request is received.
1. The interconnect provides a Snoop request on the SNP channel. This can be one of the following Snoop
transactions:
• SnpOnceFwd, SnpOnce.
• SnpCleanFwd, SnpClean.
• SnpNotSharedDirtyFwd, SnpNotSharedDirty.
• SnpSharedFwd, SnpShared.
• SnpUniqueFwd, SnpUnique.
• SnpCleanShared.
• SnpCleanInvalid.
2. The RN returns the data and associated response using the SnpRespData or SnpRespDataPtl opcode on the
DAT channel.
ICN RN-F
Snoop
SNP
transaction
WDAT SnpRespData
• SnpRespData or SnpRespDataPtl, as required, must only be sent by the RN-F after the associated Snoop
request is received.
2-68 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
1. The interconnect provides a Snoop request on the SNP channel. This can be one of the following Snoop
transactions:
• SnpOnceFwd.
• SnpCleanFwd.
• SnpNotSharedDirtyFwd.
• SnpSharedFwd.
• SnpUniqueFwd.
2. The snooped RN forwards the Data to the Requester using the CompData opcode on the WDAT channel and
either:
• Sends a response to Home using the SnpRespFwded opcode on the SRSP channel.
• Sends Data to Home using the SnpRespDataFwded opcode on the WDAT channel.
Figure 2-19 shows the transaction structure with response without Data to Home.
Request
REQ
transaction
Snoop
SNP
transaction
SnpRespFwded SRSP
WDAT
RDAT CompData
SRSP CompAck
Figure 2-19 Snoop with Data forwarded to Requester with response to Home
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-69
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Figure 2-20 shows the transaction structure with response with Data to Home.
Request
REQ
transaction
Snoop
SNP
transaction
SnpRespDataFwded WDAT
WDAT
RDAT CompData
SRSP CompAck
Figure 2-20 Snoop with Data forwarded to Requester with Data to Home
2-70 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.3 Transaction structure
Stash snoops
Figure 2-21 shows an example of a stash type snoop with Data Pull, Data response from Snoopee, and Data from
Home. The RN-F provides data in response to the snoop. The RN-F is then returned CompData in response to the
Read transaction initiated by the SnpRespData_Read response.
ICN RN-F
SnpUniqueStash SNP
SnpRespData_*_Read WDAT
RDAT
CompData
CompAck SRSP
Figure 2-21 Stash type snoop with Data Pull, Data response from Snoopee, and Data from Home
Figure 2-22 shows an example of a stash type snoop with Data Pull, no Data response from Snoopee, and DMT.
Data is provided by a DMT read from memory.
SnpStashShared SNP
SnpResp_*_Read SRSP
ReadNoSnp REQ
RDAT
RDAT CompData
CompAck SRSP
* in SnpResp_*_Read can be I or UC
Figure 2-22 Stash type snoop with Data Pull, no Data response from Snoopee, and DMT
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-71
ID082919 Non-Confidential
2 Transactions
2.3 Transaction structure
Snoop DVMOp
The progress of a SnpDVMOp transaction is as follows:
1. The interconnect provides two Snoop requests with the SnpDVMOp opcode on the SNP channel.
2. The RN returns a single SnpResp snoop response on the SRSP channel.
Figure 2-23 shows the transaction structure.
ICN RN
SNP SnpDVMOp
RN-F or RN-D
SRSP SnpResp
• The SnpResp response must only be sent by the RN after both Snoop requests are received.
2-72 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.4 Transaction identifier fields
Transaction Identifier (TxnID), Data Buffer Identifier (DBID), Return Transaction Identifier (ReturnTxnID),
Forward Transaction Identifier (FwdTxnID)
These fields relate all the packets associated with a single transaction. See Details of transaction
identifier fields on page 2-74.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-73
ID082919 Non-Confidential
2 Transactions
2.5 Details of transaction identifier fields
A transaction request includes a TxnID that is used to identify the transaction from a given Requester. It is required
that the TxnID, except for PrefetchTgt, must be unique for a given Requester. The Requester is identified by the
SrcID. This ensures that any returning read data or response information can be associated with the correct
transaction.
A 10-bit field is defined for the TxnID to accommodate up to 1024 outstanding transactions. A Requester is
permitted to reuse a TxnID value after it has received either:
• All responses associated with a previous transaction that have used the same value.
• A RetryAck response for a previous transaction that used the same value.
Transaction identifier field flows on page 2-77 gives more detailed rules for the different transaction types. The
TxnID field is not applicable in a PrefetchTgt request and can take any value.
Note
• In CHI Issue B, the TxnID is not applicable in the PrefetchTgt request and must be set to zero.
• Prior to CHI issue D, the TxnID field width was 8-bits accomodating up to 256 outstanding transactions.
A value used in the TxnID field of a Request from Home to Slave can be reused by Home once all responses that
are required to deallocate the request are received or a RetryAck response is received.
A transaction that is retried is not required to use the same TxnID. See Request Retry on page 2-129.
A transaction request from Home to Slave includes a ReturnNID that is used to determine the TgtID for the Data
response or Persist from the Slave. Its value must be either the Node ID of Home or the Node ID of the original
Requester.
ReturnNID is inapplicable and must be set to zero in all requests from Requester to Home and Requester to Slave.
A transaction request from Home to Slave also includes a ReturnTxnID field to convey the value of TxnID in the
data response from the Slave. Its value, when applicable, must be either:
• The TxnID generated by Home, when the ReturnNID is the Node ID of the Home.
• The TxnID of the original Requester, when the ReturnNID is the Node ID of the original Requester.
ReturnTxnID is only applicable in a ReadNoSnp, ReadNoSnpSep, and non-store Atomic requests from Home to
Slave. The field is inapplicable and must be set to zero in all other requests from Home to Slave.
ReturnTxnID is inapplicable and must be set to zero in all requests from Requester to Home and Requester to Slave.
CompData from Home, and from the Slave node, includes the HomeNID field that is used by the Requester to
identify the target of the CompAck that it might need to send in response to CompData. HomeNID is applicable in
CompData and DataSepResp and is inapplicable and must be set to zero for all other data messages.
A CleanSharedPersistSep request includes a PGroupID to identify the Persistence Group that the request belongs
to. This 5-bit field is only applicable in:
• CleanSharedPersistSep from Requester to Home.
• CleanSharedPersistSep from Home to Slave.
• Persist response from Home.
• Persist response from Slave.
• CompPersist response from Slave to Home.
It is inapplicable and must be set to zero in all other requests and responses.
2-74 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.5 Details of transaction identifier fields
Note
There is no functional requirement for the HomeNID and DBID fields in the DataSepResp response because the
values that are provided in the RespSepData response are identical and can always be used. However, this
specification requires that these values are included to assist in debugging and protocol checking.
A Snoop request from Home to RN-F includes a FwdNID that is used to determine the TgtID for the Data response
from the RN-F. Its value must be the NodeID of the original Requester.
A Snoop request from Home to RN-F also includes a FwdTxnID field to convey the value of TxnID in the Data
response from the RN-F. Its value must be the TxnID of the original Request.
The DBID field permits the Completer of a transaction to provide its own identifier for a transaction. The Completer
sends a response that includes a DBID. The DBID value is used as the TxnID field value in the:
• WriteData response of Write, Atomic, and DVMOp transactions.
• CompData response of Stash transactions for Data Pull purposes.
• CompAck response of Read, Dataless, and WriteUnique transactions that include a CompAck response.
The DBID value used by a Completer in responses of a given transaction must be unique for a given Requester in
the following cases:
• DBIDResp or CompDBIDResp for all Write transactions.
• DBIDResp or CompDBIDResp for Atomic transactions.
• DBIDResp for DVMOp transactions.
• CompData or RespSepData for Read transactions that include CompAck, except in the case when
ReadOnce* and ReadNoSnp do not use the resultant CompAck for deallocation of the request at Home.
• Comp for Dataless transactions that include CompAck.
The DBID value is applicable in the DataSepResp response to Read requests that include CompAck and it must be
the same as the DBID value in the associated RespSepData response.
A Comp response message sent separate from a DBIDResp message for a Write transaction must include the same
DBID field value in the Comp and DBIDResp message.
A Comp response message sent separate from a DBIDResp message for a Atomic transaction is permitted, but is
not required, to include the same DBID field value in Comp and DBIDResp message.
A Completer is permitted, but not required, to use the same DBID value for two transactions with different
Requesters. A Completer is permitted to reuse a DBID value after it has received all packets required to deallocate
a previous transaction that has used the same value. Transaction identifier field flows on page 2-77 gives more
detailed rules for the different transaction types.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-75
ID082919 Non-Confidential
2 Transactions
2.5 Details of transaction identifier fields
The DBID value used by a Snoop Completer in response to a Stash type snoop that includes a Data Pull must be
unique with respect to:
• The DBID values in other Snoop responses to Stash type snoops that use Data Pull.
• The TxnID of any outstanding Request from that Snoop Completer.
Note
The advantage of using the DBID assigned by the Completer, instead of the TxnID assigned by the Requester, is
that the Completer can use the DBID to index into its request structure instead of performing a lookup using TxnID
and SrcID to determine which transaction write data or completion acknowledge is associated with which request.
If a Completer is using the same DBID value for different Requesters, which it must do if its operation requires more
than 1024 DBID responses to be active at the same time, then it must use SrcID in combination with DBID to
determine which request should be associated with a write data or response message.
The DBIDResp response is also used to provide certain ordering guarantees relating to the transaction. See
Transaction ordering on page 2-102.
2-76 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
• All fields with the same color are the same value.
• The curved loop-back arrows show how the Requester and Completer use fields from earlier packets to
generate fields for subsequent packets.
• A box containing an asterix [*] indicates when a field is first generated, that is, it indicates the agent that
determines the original value of the field.
• A field enclosed in parentheses indicates that the value is effectively a fixed value. Typically this is the case
for the SrcID field when a packet is sent, and the TgtID field when a packet arrives at its destination.
• It is permitted for the TgtID of the original transaction to be re-mapped by the interconnect to a new value.
This is shown by a box containing the letter R. This is explained in more detail in Chapter 3 Network Layer.
Note
An identifier field, in every packet sent, belongs to one of the following categories:
• New value. An asterisk indicates that a new value is generated.
• Generated from an earlier packet. A loop back arrow indicates the source.
• Fixed value. The value is enclosed in brackets.
• Not valid. The field is crossed-out.
In the following examples, any transaction IDs that are not relevant for the example are sometimes omitted for
clarity.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-77
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
RN ICN SN
* TgtID (TgtID)
* TgtID R (TgtID) * (SrcID) SrcID
* (SrcID) SrcID * TxnID TxnID
Read ReadNoSnp
* TxnID TxnID ReturnNID ReturnNID
ReturnTxnID ReturnTxnID
TgtID
ReadReceipt (SrcID)
(Optional) TxnID
DBID
(TgtID) TgtID
SrcID (SrcID)
To RN
TxnID CompData CompData TxnID
HomeNID HomeNID
DBID DBID
TgtID
(SrcID)
CompAck
TxnID
DBID
The required steps in the flow that Figure 2-24 shows are:
2-78 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
2. The recipient Home Node in the ICN generates a Request to the Slave Node.
The identifier fields of the request are generated as follows:
• The TgtID is set to the value required for the Slave.
• The SrcID is a fixed value for the Home.
• The TxnID is a unique value generated by the Home.
• The ReturnNID is set to the same value as the SrcID of the original request.
• The ReturnTxnID is set to the same value as the TxnID of the original request.
3. If the request to the Slave requires a ReadReceipt, the Slave provides the read
receipt.
The identifier fields of the ReadReceipt response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Slave. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The DBID field is not valid.
5. The Requester receives the read data and sends a CompAck acknowledgment.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the HomeNID of the read data.
• The SrcID is a fixed value for the Requester. This also matches the TgtID that was received.
• The TxnID is set to the same value as the DBID of the read data.
• The DBID field is not valid.
The CompAck response from Requester to Home is not required for all Requests.
If the original request requires a ReadReceipt, the following additional step is included:
• The Home receives the Request packet and provides the read receipt.
The identifier fields of the ReadReceipt response are generated as follows:
— The TgtID is set to the same value as the SrcID of the request.
— The SrcID is a fixed value for the Completer. This also matches the TgtID received.
— The TxnID is set to the same value as the TxnID of the request.
— The DBID field is not valid.
Details of transaction identifier fields on page 2-74 details when the TxnID value and DBID value can be reused.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-79
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
RN ICN SN
* TgtID
* (SrcID)
(TgtID)
* TxnID
SrcID
ReturnNID
* TgtID R (TgtID) ReadNoSnpSep TxnID
ReturnTxnID
* (SrcID) Read SrcID ReturnNID
* TxnID TxnID ReturnTxnID
(TgtID) TgtID
SrcID (SrcID)
RespSepData
TxnID TxnID
TgtID
DBID * DBID
(SrcID)
ReadReceipt
TxnID
TgtID
DBID
(SrcID)
CompAck
TxnID
DBID
(TgtID) TgtID
SrcID (SrcID)
To RN
TxnID DataSepResp DataSepResp TxnID
HomeNID HomeNID
DBID DBID
Figure 2-25 ID value transfer in a DMT transaction with separate Comp and Data
The required steps in the flow that Figure 2-25 shows are:
2. The recipient Home Node in the ICN generates a request to the Slave Node.
The identifier fields of the request are generated as follows:
• The TgtID is set to the value required for the Slave.
• The SrcID is a fixed value for the Home.
• The TxnID is a unique value generated by the Home.
• The ReturnNID is set to the same value as the SrcID of the original request.
• The ReturnTxnID is set to the same value as the TxnID of the original request.
2-80 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
3. The recipient Home Node in the ICN provides the separate read response.
The identifier fields of the read response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Home.
• The TxnID is set to the same value as the TxnID of the original request.
• The DBID value is a unique value generated by the Home and is the same value as the TxnID in the
request to the Slave.
4. The Requester receives the read response and sends a CompAck acknowledgment.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the SrcID of the read response.
• The SrcID is a fixed value for the Requester.
• The TxID is set to the unique DBID value generated by the Home.
• The DBID value is not valid.
5. The request to the Slave requires a ReadReceipt, the Slave provides the read
receipt.
The identifier fields of the ReadReceipt response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Slave. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-81
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
RN ICN RN-F
(TgtID) TgtID
SrcID * (SrcID)
TxnID TxnID
To RN
HomeNID CompData CompData HomeNID
DBID DBID
TgtID TgtID
(SrcID) * (SrcID)
CompAck To HN-F To HN-F SnpRespFwded
TxnID or TxnID
DBID SnpRespDataFwded DBID
The required steps in the flow that Figure 2-26 shows are:
2. The recipient Home Node in the ICN generates a fowarding snoop to the RN-F node.
The identifier fields of the snoop are generated as follows:
• The SrcID is a fixed value for the Home.
• The TxnID is a unique value generated by the Home.
• The FwdNID is set to the same value as the SrcID of the original request.
• The FwdTxnID is set to the same value as the TxnID of the original request.
2-82 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
4. The RN-F also provides a response to Home, either with or without read data.
The identifier fields of the response are generated as follows:
• The TgtID is set to the same value as the SrcID of the snoop.
• The SrcID is a fixed value for the RN-F.
• The TxnID is set to the same value as the TxnID of the snoop.
• The DBID field is not valid.
5. The Requester receives the read data and sends a CompAck acknowledgment.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the HomeNID of the read data.
• The SrcID is a fixed value for the Requester. This also matches the TgtID that was received.
• The TxnID is set to the same value as the DBID of the read data.
• The DBID field is not valid.
Note
An optional ReadReceipt from ICN to Requester can also be included.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-83
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
The Requester and Completer in this example are an RN and an HN-F respectively.
The identifier field flow includes an optional ReadReceipt response from the Completer, and an optional CompAck
response from the Requester.
For Read transactions that include a CompAck response the DBID is used by the Completer to associate the
CompAck with the original transaction.
A Read transaction that does not include a CompAck response does not require a valid DBID field in the data
response.
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
ReadReq
* TxnID TxnID
Optional
(TgtID) TgtID
SrcID (SrcID)
ReadReceipt
TxnID TxnID
DBID DBID
(TgtID)
TgtID
SrcID
(SrcID)
TxnID
TxnID
HomeNID CompData
(HomeNID) *
DBID
DBID *
Optional
TgtID (TgtID)
(SrcID) SrcID
CompAck
TxnID TxnID
DBID DBID
Figure 2-27 ID value transfer in a Read request with ReadReceipt and CompAck
The required steps in the flow that Figure 2-27 shows are:
2-84 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
2. If the transaction includes a ReadReceipt, the Completer receives the Request packet and provides the read
receipt.
The identifier fields of the ReadReceipt response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The DBID field is not valid.
3. The Completer receives the Request packet and provides the read data.
The identifier fields of the read data response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The HomeNID is a fixed value for the Completer. This also matches the TgtID received.
• The Completer generates a unique DBID value if ExpCompAck in the request is asserted.
4. The Requester receives the read data and sends a CompAck acknowledgment.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the HomeNID of the read data.
• The SrcID is a fixed value for the Requester. This also matches the TgtID that was received.
• The TxnID is set to the same value as the DBID of the read data.
• The DBID field is not valid.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-85
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
RN ICN SN
* TgtID (TgtID)
* (SrcID) SrcID
* TgtID R (TgtID) * TxnID TxnID
PCMOSep
* (SrcID) SrcID ReturnNID ReturnNID
PCMOSep
* TxnID TxnID ReturnTxnID ReturnTxnID
* PGroupID PGroupID PGroupID PGroupID
TgtID TgtID
(SrcID) Comp (SrcID)
TxnID TxnID (TgtID) TgtID
SrcID Comp (SrcID)
TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
Persist To RN Persist
TxnID TxnID
PGroupID PGroupID
The required steps in the flow that Figure 2-28 shows are:
1. The Requester starts the transaction by sending a request packet. The identifier fields of the request are
generated as follows:
• The TgtID is determined by the destination of the Request.
Note
The TgtID field can be remapped to a different value by the interconnect.
2-86 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
2. The recipient Home Node in the ICN generates a request to the Slave.
The identifier fields of the request to the Slave Node are generated as follows:
• The TgtID is set to the value required for the Slave.
• The SrcID is a fixed value for the Home.
• The TxnID is a unique value generated by the Home.
The TxnID value can be re-used by the Home after receiving the Comp response.
• The ReturnNID is set to the same value as the SrcID of the original request.
• The ReturnTxnID is inapplicable and must be set to zero.
• The PGroupID is set to the same value as the PGroupID of the original request.
3. The recipient Home Node in the ICN sends a Comp response to the Requester.
The identifier fields of the Comp response to the Requester are generated as follows:
• The TgtID is set to the same value as the SrcID of the original request.
• The SrcID is a fixed value for the Home.
• The TxnID is set to the same value as the TxnID of the original request.
4. The recipient Home Node can optionally send a Persist response to the Requester.
The identifier fields of the optional Persist response from the Home Node to the Requester, not shown in
Figure 2-28 on page 2-86, are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Home Node.
• The TxnID is inapplicable and must be set to zero.
• The PGroupID is set to the same value as the PGroupID of the request.
The recipient Home Node can optionally send a combined CompPersist response to the Requester, instead of
separate Comp and Persist responses.
The identifier fields in the CompPersist response are generated as follows:
• The TgtID is set to the same value as the SrcID of the original request.
• The SrcID is a fixed value for the Home.
• The TxnID is set to the same value as the TxnID of the original request.
• The PGroupID is set to the same value as the PGroupID of the original request.
6. The Slave Node also generates a Persist response to either to the Requester or the Home.
The identifier fields of the Persist response from the Slave Node are generated as follows:
• The TgtID is set to the same value as the ReturnNID of the request.
• The SrcID is a fixed value for the Slave.
• The TxnID is inapplicable and must be set to zero.
• The PGroupID is set to the same value as the PGroupID of the request.
7. The Slave Node can optionally send a combined CompPersist response to the Home Node, instead of separate
Comp and Persist responses if the ReturnNID and SrcID of the request are the same value.
The identifier fields of the CompPersist response from the Slave are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Slave.
• The TxnID is set to the same value as the TxnID of the request.
• The PGroupID is set to the same value as the PGroupID of the request.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-87
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
CopyBack transaction
This section describes the use of the identifier fields for a CopyBack transaction.
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
CopyBack
* TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
CompDBIDResp
TxnID TxnID
DBID DBID *
(TgtID)
SrcID
TgtID
TxnID
(SrcID)
WriteData DBID
TxnID
DBID
The required steps in the flow that Figure 2-29 shows are:
1. The Requester starts the transaction by sending a Request packet. The identifier fields of the request are
generated as follows:
• The TgtID is determined by the destination of the Request.
Note
The TgtID field can be remapped to a different value by the interconnect.
2. The Completer receives the request packet and generates a CompDBIDResp response. The identifier fields
of the response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The Completer generates a unique DBID value.
2-88 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
3. The Requester receives the CompDBIDResp response and sends the write data. The identifier fields of the
write data are generated as follows:
• The TgtID is set to the same value as the SrcID of the CompDBIDResp response. This can be different
from the original TgtID of the request if the value was remapped by the interconnect.
• The SrcID is a fixed value for the Requester.
• The TxnID is set to the same value as the DBID value provided in the CompDBIDResp response.
• The DBID field in the write data is not used.
• The TgtID, SrcID, and TxnID fields must be the same for all write data packets.
After receiving the CompDBIDResp response, the Requester can reuse the same TxnID value used in the
request packet for another transaction.
4. The Completer receives the write data and uses the TxnID field, which now contains the DBID value that the
Completer generated, to determine which transaction the write data is associated with.
After receiving all write data packets, the Completer can reuse the same DBID value for another transaction.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-89
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
WriteNoSnp transaction
This section describes the use of the identifier fields for a WriteNoSnp transaction.
Figure 2-30 shows the ID value transfer for separate Comp and DBIDResp. The Completer can opportunistically
combine the Comp and DBIDResp into a single CompDBIDResp response. The Requester can opportunistically
combine NCBWrData with CompAck.
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
WriteNoSnp
* TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
DBIDResp
TxnID TxnID
DBID DBID *
(TgtID)
TgtID
SrcID
(SrcID)
TxnID
TxnID NCBWrData
DBID
DBID
(TgtID) TgtID
SrcID (SrcID)
Comp
TxnID TxnID
DBID DBID
Optional
TgtID (TgtID)
(SrcID) SrcID
CompAck
TxnID TxnID
DBID DBID
Optional
TgtID (TgtID)
(SrcID) SrcID
NCBWrDataCompAck
TxnID TxnID
DBID DBID
The use of the identifier fields are the same as for a transaction with a combined response with the additional
requirements that:
• The identifier fields used for the separate DBIDResp and Comp responses must be identical.
• The TxnID value must only be reused by a Requester when both the DBIDResp and Comp responses have
been received.
2-90 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
The required steps in the flow that Figure 2-30 on page 2-90 shows are:
1. The Requester starts the transaction by sending a Request packet. The identifier fields of the request are
generated as follows:
• The TgtID is determined by the destination of the Request.
Note
The TgtID field can be remapped to a different value by the interconnect.
2. The Completer receives the Request packet and generates a DBIDResp response. The identifier fields of the
response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The Completer generates a unique DBID value.
3. The Requester receives the DBIDResp response and sends the write data. The identifier fields of the write
data are generated as follows:
• The TgtID is set to the same value as the SrcID of the DBIDResp response. This can be different from
the original TgtID of the request if the value was remapped by the interconnect.
• The SrcID is a fixed value for the Requester.
• The TxnID is set to the same value as the DBID value provided in the DBIDResp response.
• The DBID field in the write data is not used.
• The TgtID, SrcID, and TxnID fields must be the same for all write data packets.
4. The Completer receives the write data and uses the TxnID field, which now contains the DBID value that the
Completer generated, to determine which transaction the write data is associated with.
5. The Completer generates a Comp response when it has completed the transaction.
The identifier fields of the Comp response must be the same as the DBIDResp response and are generated as
follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The Completer uses the same DBID value as is used in the DBIDResp response.
6. The Requester sends a CompAck message, if the transaction requires it, after receiving DBIDResp or Comp.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the SrcID of the DBIDResp or Comp response.
• The SrcID is a fixed value for the Requester. This also matches the TgtID that was received.
• The TxnID is set to the same value as the DBID of the DBIDResp or Comp response.
• The DBID field is not valid.
After receiving both the Comp and DBIDResp response, the Requester can reuse the same TxnID value for another
transaction.
After receiving all the write data packets, the Completer can reuse the same DBID value for another transaction.
Note
There is no ordering requirement between the separate DBIDResp and Comp responses. The specification
requirement is that the values used are identical.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-91
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
WriteUnique transaction
This section describes the use of the identifier fields for a WriteUnique transaction. The WriteUnique transaction
can, under certain circumstances, additionally include a CompAck response from the Requester to the Completer.
In this case, the additional rules for the use of the identifier fields are:
• The TgtID, SrcID, and TxnID identifier fields of the CompAck response from the Requester to the Completer
must be the same as the fields used for the write data, that is:
— The TgtID is set to the same value as the SrcID of the CompDBIDResp response. If separate Comp
and DBIDResp responses are given, the TgtID is set to the same value as the SrcID of either the Comp
or DBIDResp response because the SrcID value in both must be identical. However, this can be
different from the original TgtID of the request if the value has been remapped by the interconnect.
— The SrcID is a fixed value for the Requester.
— The TxnID is set to the same value as the DBID value provided in the CompDBIDResp response. If
separate Comp and DBIDResp responses are given, the TxnID is set to the same value as the DBID of
either the Comp or DBIDResp response because the DBID value in both must be identical.
— The DBID field in the WriteData and in the CompAck is not used.
— If a combined WriteData and CompAck response is sent, then the TgtID is set to the same value as the
SrcID in the Comp, DBIDResp, or CompDBIDResp, and the TxnID in the combined response is set
to the same value as the DBID in Comp, DBIDResp, or CompDBIDResp.
• The Completer must receive all items of write data and the CompAck response before reusing the same DBID
value for another transaction.
Figure 2-31 shows the ID value transfer with a combined CompDBIDResp response.
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
WriteUnique
* TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
CompDBIDResp
TxnID TxnID
DBID DBID *
(TgtID)
TgtID
SrcID
(SrcID)
TxnID
TxnID WriteData
DBID
DBID
TgtID (TgtID)
(SrcID) SrcID
CompAck
TxnID TxnID
DBID DBID
2-92 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
Figure 2-32 shows the ID value transfer with a combined WriteData and CompAck response.
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
WriteUnique
* TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
CompDBIDResp
TxnID TxnID
DBID DBID *
TgtID (TgtID)
(SrcID) SrcID
TxnID TxnID
NCBWrDataCompAck
DBID DBID
Figure 2-32 ID value transfer with a combined WriteData and CompAck response
Note
Prior to CHI.C combining NCBWrData and CompAck is not permitted.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-93
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
StashOnce transaction
This section describes the use of the identifier fields for a StashOnce transaction with DataPull.
RN ICN RN-F
* (SrcID) SrcID
* TgtID R (TgtID) * TxnID TxnID
Snp[*]Stash
* (SrcID) SrcID StashLPID StashLPID
* TxnID TxnID
Stash
* StashNID StashNID
* StashLPID StashLPID
RN-F NID
same as
StashNID
SrcID (SrcID)
TgtID (TgtID) TgtID
Comp SnpResp_I_Read
TxnID TxnID TxnID
DBID DBID *
(SrcID) SrcID
TgtID (TgtID)
TxnID TxnID
CompData
* DBID DBID
* (HomeNID) HomeNID
TgtID
CompAck (SrcID)
TxnID
DBID
The required steps in the flow that Figure 2-33 shows are:
2-94 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
2. The Home Node in the ICN receives the Stash request packet and generates a snoop with Stash to the
appropriate RN-F.
The identifier fields of the request are generated as follows:
• The SrcID is a fixed value for the Home.
• The TxnID is a unique value generated by the Home.
• The StashLPID is set to the same value as the StashLPID of the original request.
Note
A Snoop request does not include a TgtID field.
3. The snooped RN-F generates a Snoop response. In this example, it includes a Data Pull indication.
The identifier fields of the Snoop response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the RN-F.
• The TxnID is set to the same value as the TxnID of the request.
• The DBID field is a unique value generated by the RN-F.
• The TxnID is set to the same value as the DBID of the Snoop response.
• The DBID field is a unique value generated by Home.
• The HomeNID is a fixed value for the Home.
5. The RN-F receives the read data and sends a CompAck acknowledgment.
The identifier fields of the CompAck are generated as follows:
• The TgtID is set to the same value as the HomeNID of the read data.
• The SrcID is a fixed value for the RN-F. This also matches the TgtID received.
• The TxnID is set to the same value as the DBID of the read data.
• The DBID field is not valid.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-95
ID082919 Non-Confidential
2 Transactions
2.6 Transaction identifier field flows
Requester Completer
* TgtID R (TgtID)
* (SrcID) SrcID
Request
* TxnID TxnID
(TgtID) TgtID
SrcID (SrcID)
RetryAck
TxnID TxnID
DBID DBID
PCrdType PCrdType *
(TgtID) TgtID
SrcID (SrcID)
PCrdGrant
TxnID TxnID
DBID DBID
PCrdType PCrdType
TgtID R (TgtID)
(SrcID) Request SrcID
* TxnID with Credit TxnID
PCrdType PCrdType
The required steps in the flow that Figure 2-34 shows are:
1. The Requester starts the transaction by sending a Request packet. The identifier fields of the request are
generated as follows:
• The TgtID is determined by the destination of the Request.
Note
The TgtID field can be remapped to a different value by the interconnect.
2-96 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.6 Transaction identifier field flows
2. The Completer receives the Request packet and determines that it is going to send a RetryAck response. The
identifier fields of the RetryAck response are generated as follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID received.
• The TxnID is set to the same value as the TxnID of the request.
• The DBID field is not valid.
• The Completer uses a PCrdType value that indicates the type of credit required to retry the transaction.
3. When the Completer is able to accept the retried transaction of a given PCrdType it sends a credit to the
Requester, using the PCrdGrant response. The identifier fields of the PCrdGrant response are generated as
follows:
• The TgtID is set to the same value as the SrcID of the request.
• The SrcID is a fixed value for the Completer. This also matches the TgtID of the request.
• The TxnID field is not used and must be set to zero.
• The DBID field is not used and must be set to zero.
• The PCrdType value is set to the type required to issue the original transaction again.
4. The Requester receives the credit grant and reissues the original transaction by sending a Request packet. The
identifier fields of the request are generated as follows:
• The TgtID is set to either the same value as the SrcID of the RetryAck response, which is also the same
as the SrcID of the PCrdGrant response, or the value used in the original request.
• The SrcID is a fixed value for the Requester.
• The Requester generates a unique TxnID field. This is permitted to be different from the original
request that received a RetryAck response.
• The PCrdType value is set to the PCrdType value in the RetryAck response to the original request,
which is also the same as the PCrdType of the PCrdGrant response.
• The Requester sends the Protocol Credit Return transaction by sending a PCrdReturn Request packet. The
identifier fields of the request are generated as follows:
— The TgtID must match the SrcID of the credit that was obtained.
— The SrcID is a fixed value for the Requester.
— The TxnID field is not used and must be set to zero.
The PCrdType must match the value of the PCrdType in the original PCrdGrant that was required to issue the
original transaction again.
There is no response or use made of the DBID field associated with Protocol Credit Return transactions.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-97
ID082919 Non-Confidential
2 Transactions
2.7 Logical Processor Identifier
The LPID must be set to the correct value for the following transactions:
• For Exclusive accesses, that can be one of the following transaction types:
— ReadClean.
— ReadShared.
— ReadNotSharedDirty.
— CleanUnique.
— ReadNoSnp.
— WriteNoSnp.
See Chapter 6 Exclusive Accesses for further details.
Note
For other transactions, the LPID value can be used to indicate the original logical processor that caused a transaction
to be issued. However, this information is not required by this specification and is optional.
2-98 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.8 Ordering
2.8 Ordering
This section describes the mechanisms that the protocol includes to support system ordering requirements. It
contains the following subsections:
• Multi-copy atomicity.
• Completion Response and Ordering.
• Completion acknowledgement on page 2-100.
• Transaction ordering on page 2-102.
For the meaning of the terms EWA, Device, and Cacheable see Memory Attributes on page 2-110.
• All writes to the same location are serialized, that is, they are observed in the same order by all Requesters,
although some Requesters might not observe all of the writes.
• A read of a location does not return the value of a write until all Requesters observe that write.
In this specification, two addresses are considered to be the same with respect to coherence, observability, and
hazarding if their cache line addresses and NS attribute are the same.
• For a Read transaction to a Cacheable location, a CompData or DataSepResp response guarantees that the
transaction is observable to a later transaction from any agent to the same location.
• For a Read transaction to a Cacheable location, a RespSepData response guarantees that no earlier transaction
will send a snoop to this Requester, and all later transactions will send a snoop only if required after the Home
receives the CompAck response for this transaction.
• For a Dataless transaction, a Comp response guarantees that the transaction is observable to a later transaction
from any agent to the same memory location.
• In addition, for CleanSharedPersist transactions, a Comp response guarantees that any data written earlier to
the same memory location is made persistent.
• For CleanSharedPersistSep transactions, a Persist response guarantees that any data written earlier to the
same memory location is made persistent.
• For a Write or an Atomic transaction to Non-cacheable or Device nRnE or Device nRE, a Comp or
CompData response guarantees that the transaction is observable to a later transaction from any agent to the
same endpoint address range.
• For a Write or Atomic transaction to a Cacheable or Device RE location, a Comp or CompData response
guarantees that the transaction is observable to a later transaction, from any agent, to the same location.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-99
ID082919 Non-Confidential
2 Transactions
2.8 Ordering
Note
• The size of an endpoint address range is IMPLEMENTATION DEFINED. Typically, this is:
— The size of a peripheral device, for a region used for peripherals.
— The size of a cache line, for a region used for memory.
• A Cacheable location can be determined by the assertion of the MemAttr[2] Cacheable bit in the request. A
Non-cacheable or Device location can be determined by the deassertion of the MemAttr[2] Cacheable bit in
the request.
If the Comp response for a Write transaction, with EWA asserted, to a Non-cacheable or Device location does not
guarantee that the transaction is observable to a later transaction from any agent to the same endpoint address range,
then one of the following techniques can be used to ensure ordering to the same endpoint address range:
• If the Write transaction has an Endpoint Order requirement, then a later transaction from the same agent that
also has an Endpoint Order requirement and is to the same endpoint address range will be ordered. See
Transaction ordering on page 2-102.
• The CompData response of a later Read transaction to the same location ensures the ordering of the Write
transaction with respect to a later transaction from any agent to any location within the same endpoint address
range.
A component must only give a Comp or CompDBIDResp response when it is guaranteed that all observers will see
the result of the atomic operation.
The sequencing of the completion of a Read transaction and the sending of CompAck is as follows:
1. An RN-F sends a CompAck after receiving Comp, RespSepData or CompData, or both RespSepData and
DataSepResp.
2. An HN-F, except in the case of ReadOnce*, waits for CompAck before sending a subsequent snoop to the
same address. For CopyBack transactions, WriteData acts as an implicit CompAck and an HN-F must wait
for WriteData before sending a snoop to the same address.
This sequence guarantees that an RN-F receives completion for a transaction and a snoop to the same cache line in
the same order as they are sent from an HN-F. This ensures transactions to the same cache line are observed in the
correct order.
When an RN-F has a transaction in progress that uses CompAck, except for ReadNoSnp and ReadOnce*, then it is
guaranteed not to receive a Snoop request to the same address between the point that it receives Comp and the point
that it sends CompAck.
For WriteNoSnp and WriteUnique transactions that require a CompAck message, an RN sends the CompAck after
receiving the Comp, DBIDResp, or CompDBIDResp response.
The use of CompAck for a transaction is determined by the Requester setting the ExpCompAck field in the original
request. The rules for an RN setting the ExpCompAck field and generating a CompAck response are as follows:
• An RN-F must include a CompAck response in all Read transactions except ReadNoSnp and ReadOnce*.
• Although not required, an RN-F is permitted to include a CompAck response in ReadNoSnp and ReadOnce*
transactions.
• An RN-F must not include a CompAck response in StashOnce, CMO, Atomic or Evict transactions.
• An RN-I or RN-D is permitted, but not required, to include a CompAck response in Read transactions.
• An RN-I or RN-D must not include a CompAck response in Dataless or Atomic transactions.
2-100 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.8 Ordering
• An RN that wants to make use of DMT must include a CompAck response in ordered ReadNoSnp and
ReadOnce* transactions.
• For Write transactions, CompAck can only be used for WriteUnique and WriteNoSnp transactions when they
require Ordered Write Observation guarantees. See Streaming Ordered Write transactions on page 2-106.
For transactions between an RN and an HN, where the HN is the Completer, the HN must support the use of
CompAck for all transactions that are required or permitted to use CompAck.
A Requester, such as an HN-F or HN-I that communicates with an SN-F or SN-I respectively, must not send a
CompAck response.
Table 2-8 shows the Request types that require a CompAck response, and the corresponding Requester types that
are required to provide that response.
ReadClean Yes -
ReadNotSharedDirty Yes -
ReadShared Yes -
ReadUnique Yes -
CleanUnique Yes -
MakeUnique Yes -
CleanShared No No
CleanSharedPersist* No No
CleanInvalid No No
MakeInvalid No No
WriteBack No -
WriteClean No -
Evict No -
WriteEvictFull No -
Atomics No No
StashOnce No No
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-101
ID082919 Non-Confidential
2 Transactions
2.8 Ordering
A Home must ensure that all required Snoop transactions are completed before initiating a transaction, such as a
ReadNoSnpSep, which could result in the DataSepResp response being sent to the Requester.
When a Requester receives a RespSepData response from Home, the request that it applies to has been ordered at
Home and the Requester will not receive any snoops for transactions that are scheduled before it. The Home, before
sending RespSepData response to the Requester, must ensure that no Snoop transactions are outstanding to that
Requester to the same address. Receiving of RespSepData does not guarantee that Home has completed snooping
of other agents in the system.
When the Requester gives a CompAck acknowledgement, this Requester is indicating that it will accept
responsibility to hazard snoops for any transaction that is scheduled after it. The following rules apply:
• For all transactions, except as described immediately below, the CompAck acknowledgement must be sent
after the RespSepData response is received. It is permitted, but not required, to wait for the DataSepResp
response before the CompAck acknowledgement is given.
• For ReadOnce and ReadNoSnp transactions with an ordering requirement, that is, Order field is set to b10 or
b11 and ExpCompAck field is asserted, it is required that the CompAck acknowledgement is given only after
both DataSepResp and RespSepData responses are received.
• The Requester must wait to receive both RespSepData and DataSepResp before issuing another request to
the same address.
Note
This specification requires that CompAck must not be given when only DataSepResp is received.
Requester Order between an RN, HN pair and a HN-I, SN-I pair is supported by the Order field in a request. The
Order field indicates that the transaction requires one of the following forms of ordering:
Request Order This guarantees the order of multiple transactions, from the same agent, to the same address
location.
Endpoint Order This guarantees the order of multiple transactions, from the same agent, to the same
endpoint address range. This guarantee also includes the guarantee of Request Order.
Request Accepted
This guarantees that the Completer will send a positive acknowledgement only when it has
accepted the request.
2-102 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.8 Ordering
0b10 Request Order/Ordered Write Observation required Reserved in Read requests from RN to HN
HN-F to SN-F. HN-I to SN-I
0b11 Endpoint Order required, which includes Request Order
Ordering requirements
The Order field must only be set to a non-zero value for the following transactions:
• ReadNoSnp.
• ReadNoSnpSep.
• ReadOnce*.
• WriteNoSnp.
• WriteUnique.
• Atomic.
• The Requester requires a ReadReceipt to determine when it can send the next ordered request.
• At the Completer a ReadReceipt means the request has reached the next ordering point that will maintain
requests in the order they were received:
— For requests that require Request Order it will maintain order between requests to the same address
from the same source.
— For requests that require Endpoint Order it will maintain order between requests to the same endpoint
address range from the same source.
• A completer that is capable of sending separate Non-data and Data-only responses can send RespSepData
response instead of ReadReceipt and achieve the same functional behavior.
When a WriteNoSnp or a non-Snoopable Atomic transaction requires Request Order or Endpoint Order:
• The Requester requires a DBIDResp to determine when it can send the next ordered request.
• The Completer sending a DBIDResp response means that a data buffer is available, and that the write request
has reached a PoS that will maintain requests in the order they were received:
— For requests that require Request Order it will maintain order between requests to the same address
from the same source.
— For requests that require Endpoint Order it will maintain order between requests to the same endpoint
address range from the same source.
When a WriteUnique transaction without ExpCompAck asserted, or a Snoopable Atomic transaction require
Request Order:
• The Requester requires a DBIDResp to determine when it can send the next ordered request.
• The Completer sending a DBIDResp response means that it will maintain order between requests to the same
address from the same source.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-103
ID082919 Non-Confidential
2 Transactions
2.8 Ordering
All architectural mechanisms applicable to increasing streaming efficiency and corresponding constraints are
defined in Streaming Ordered Write transactions on page 2-106.
Table 2-10 shows the ordering guarantee that is obtained for different combinations of transactions that require
order.
The transactions that Table 2-10 shows as First Transaction and Second Transaction are from the same Requester.
When transactions from the same Requester specify a different ordering requirement, the ordering guarantee that is
provided is the least restrictive of the two.
When a ReadNoSnp or ReadNoSnpSep has the Order field set to 0b01, a ReadReceipt response from the Completer
guarantees that the Completer has accepted the request and will not send a RetryAck response.
2-104 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.8 Ordering
RN HN
ReadNoSnp-1
Request
accepted
ReadReceipt-1
ReadNoSnp-2 is sent
after ReadReceipt-1
is received
ReadNoSnp-2
ReadNoSnp-2 waits
for a CreditGrant Request gets
a Retry
response
RetryAck-2
PCrdGrant
ReadNoSnp-3
continues waiting for
ReadNoSnp-2 to
make progress
ReadNoSnp-2
ReadNoSnp-3 is sent
after Read Receipt-2
ReadReceipt-2
is received
ReadNoSnp-3
ReadReceipt-3
CompData_I-3
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-105
ID082919 Non-Confidential
2 Transactions
2.8 Ordering
3. After the ReadReceipt-1 response is received, RN sends the ReadNoSnp-2 request to HN.
4. HN cannot immediately accept the ReadNoSnp-2 request and returns the RetryAck-2 response to RN.
5. RN must now wait for a PCrdGrant to be sent from HN before resending the ReadNoSnp-2 request. RN does
not send ReadNoSnp-3 at this point, as it wants to order ReadNoSnp-3 behind ReadNoSnp-2. This ordering
requires that ReadNoSnp-2 must be accepted at HN before ReadNoSnp-3 is sent to HN.
8. After receipt of the ReadReceipt-2 response, RN sends the ReadNoSnp-3 request to HN.
10. HN completes the Request transactions by sending a combined Completion and Data response to the RN for
each request.
Note
Figure 2-35 on page 2-105 shows a single ordered stream of three reads from RN. However, an RN can have
multiple streams of reads, in which case requests must be ordered within a stream, but ordering dependency does
not exist between streams. One example of this is when the streams are from different threads within the RN, in
which case, the RN waits for the ReadReceipt of the previous request from the same thread only before sending out
the next ordered request from that stream.
If a Requester requires a sequence of Write transactions to be observed in the same order as they are issued, then
the Requester can wait for completion for a write before issuing the next write in the sequence. Such an observation
ordering is typically termed Ordered Write Observation. This specification provides a mechanism termed Streaming
Ordered Writes to more efficiently stream such ordered Write transactions.
The Streaming Ordered Write mechanism relies on the use of the Ordered Write Observation ordering requirement
and CompAck. Responsibilities of Requesters and HN-F when utilizing the Streaming Ordered Write solution are:
• The Requester must set the Order field to require Ordered Write Observation and set ExpCompAck on the
Write request.
• The Ordered Write Observation requirement in a Write request indicates to the HN-F that the completion of
coherence action on this write must not depend on completion of coherence action on a subsequent write.
• The Requester must wait for DBIDResp, CompDBIDResp, or Comp for a Write transaction before sending
the next Write request.
2-106 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.8 Ordering
• The Requester, after receiving DBIDResp, CompDBIDResp or Comp for the corresponding write, as well as
Comp responses for all earlier related ordered writes, must send a CompAck response. If write data is to be
sent, then the Requester is permitted to combine the CompAck with the WriteData response into a
NCBWrDataCompAck response. When the Requester combines CompAck with the WriteData response it
must send a combined response for all WriteData transfers. The method by which a Requester determines if
a group of ordered writes are related is IMPLEMENTATION DEFINED.
Note
Waiting to send CompAck until all prior ordered writes have received their Comp responses ensures that they
have completed their operations at their respective HN-Fs and any Requester observing the write for which
CompAck is sent will also observe all prior ordered writes.
• The Requester that receives DBIDResp and is ready to send CompAck must not wait for Comp to send
CompAck.
• HN-F must wait for a CompAck response from RN before deallocating a Write transaction and making the
write visible to other observers.
Note
Prior to CHI issue D:
• CompAck for a write was permitted to be sent only after the Comp response for the corresponding write was
received, as well as the Comp responses for all earlier related ordered writes.
The writes in this section refer to WriteUnique or WriteNoSnp only. The Streaming Ordered Writes mechanism can
be further optimized. If a previously sent write is to a different target, then the Requester does not need to wait for
the DBIDResp for the request before sending the next ordered write. However, if the interconnect can remap the
TgtID, then the Requester must presume that all Write transactions are targeting the same HN-F and must not use
the optimized version of the Streaming Ordered Writes flow.
An implementation using an optimized or non-optimized Streaming Ordered Writes solution must avoid deadlock
and livelock situations.
Note
• A technique for avoiding resource related deadlock or livelock issues is to limit Streaming Ordered Writes
optimization to one Requester in the system. All other Requesters in the system can use the Streaming
Ordered Writes solution without the optimization.
• In a typical system, the optimized Streaming Ordered Writes solution is most beneficial to an RN-I that is a
conduit for PCIe style, non-relaxed order, Snoopable writes. In most systems, one RN-I hosting this type of
PCIe traffic is adequate.
• Optimized Streaming Ordered Writes can be used by more than one Requester by making use of
WriteDataCancel messages to avoid Resource related deadlocks and livelocks.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-107
ID082919 Non-Confidential
2 Transactions
2.8 Ordering
Figure 2-36 shows a typical transaction flow in which an RN-I uses Streaming Ordered WriteUnique transactions.
This flow prevents a read acquiring the new value of Write-B before Write-A has completed.
Note
For clarity, in Figure 2-36 the Write-B DBIDResp and the NCBWrData flow is omitted.
I I I
WriteUnique-A
Request B is sent
after receiving
SnpCleanInvalid-A DBIDResp-A DBIDResp for
request A
SnpResp_I-A NCBWrData-A
WriteUnique-B
SnpCleanInvalid-A
SnpCleanInvalid-B
SnpCleanInvalid-B
SnpResp_I-B
SnpResp_I-A
SnpResp_I-B
Comp-B
CompAck-B
2-108 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.9 Address, Control, and Data
2.9.1 Address
This specification supports:
• Physical Address (PA) of 44 to 52 bits, in one bit increments.
• Virtual Address (VA) of 49 to 53 bits.
The REQ and SNP packet address fields are specified as follows:
• REQ channel: Addr[(MPA-1):0]
• SNP channel: Addr[(MPA-1):3]
Table 2-11 shows the relationship between the physical address field width and the supported virtual address.
PA VA
44 44 49
45 45 51
46 to 52 46 to 52 53
See DVMOp and SnpDVMOp packet on page 8-269 for DVM payload mapping in the REQ and SNP fields with
different ADDR field widths.
The Req_Addr_Width parameter is used to specify the maximum physical address in bits that is supported by a
component. Valid values for this parameter are 44 to 52, when not specified, the parameter takes the default value
of 44.
The REQ and SNP channel messages address field in the REQ channel is a 44-bit to 52-bit field labeled
Addr[(43-51):0] and in the SNP channel it is a 41-bit to 49-bit field labeled Addr[(43-51):3]. This field is used by
the different message types as follows:
• For Read, PrefetchTgt, Dataless, Write, and Atomic transactions the Addr field includes the address of the
memory location being accessed.
• For a Snoop request, except SnpDVMOp, the field includes the address of the location being snooped:
— Addr[(43-51):6] is the cache line address and is sufficient to uniquely identify the cache line to be
accessed by the snoop.
— Addr[5:4] identifies the critical chunk being accessed by the transaction. See Critical Chunk Identifier
on page 2-123. This specification recommends that the snooped cache returns the data in wrap order
with the critical chunk returned first.
Note
Addr[3] is supplied, but is not used.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-109
ID082919 Non-Confidential
2 Transactions
2.9 Address, Control, and Data
• For a DVMOp and SnpDVMOp request the Addr field is used to carry information related to a DVM
operation. See Chapter 8 DVM Operations.
• The Addr field value is not used for the PcrdReturn transaction and must be set to zero.
This bit is defined so that when it is asserted the transaction is identified as a Non-secure transaction.
For Snoopable transactions this field can be considered as an additional address bit that defines two address spaces,
a Secure address space, and a Non-secure address space. Any aliasing between the Secure and Non-secure address
spaces must be handled correctly.
Note
Hardware coherency does not manage coherency between Non-Secure and Secure address spaces.
EWA
EWA indicates whether the write completion response for a transaction:
• Is permitted to come from an intermediate point in the interconnect, such as a Home Node.
• Must come from the final endpoint that a transaction is destined for.
If EWA is asserted, the write completion response for the transaction can come from an intermediate point or from
the endpoint. A completion that comes from an intermediate point must provide the same guarantees required by a
Comp as described in Completion Response and Ordering on page 2-99.
If EWA is deasserted, the write completion response for the transaction must come from the endpoint.
Note
It is permitted for an implementation not to use the EWA attribute, in this case completion must be given from the
endpoint.
2-110 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.9 Address, Control, and Data
Device
Device attribute indicates if the memory type is either Device or Normal.
Device memory type must be used for locations that exhibit side-effects. Use of Device memory type for locations
that do not exhibit side-effects is permitted.
• A read must get its data from the endpoint. A read must not be forwarded data from a write to the same
address location that completed at an intermediate point.
• Combining requests to different locations into one request, or combining different requests to the same
location into one request, is not permitted.
• Writes to Device memory that obtain completion from an intermediate point must make the write data visible
to the endpoint in a timely manner.
Accesses to Device memory must use the following types, exclusive variants are permitted:
• Read accesses to a Device memory location must use ReadNoSnp.
• Write accesses to a Device memory location must use either WriteNoSnpFull or WriteNoSnpPtl.
• CMO transactions are permitted to Device memory locations.
• Atomic transactions are permitted to Device memory locations.
• The PrefetchTgt transaction is not permitted to Device memory locations. The bit value is inapplicable and
can take any value.
Normal memory type is appropriate for memory locations that do not exhibit side-effects.
Accesses to Normal memory do not have the same restrictions regarding prefetching or forwarding as Device type
memory:
• A Read transaction that has EWA asserted can obtain read data from a Write transaction that has sent its
completion from an intermediate point and is to the same address location.
• Writes can be merged.
Any Read, Dataless, Write, PrefetchTgt or Atomic transaction type can be used to access a Normal memory
location. The transaction type used is determined by the memory operation to be accomplished, and the Snoopable
attributes.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-111
ID082919 Non-Confidential
2 Transactions
2.9 Address, Control, and Data
Cacheable
Note
In a transaction that can take any Cacheable value, the value is typically determined from the page table attributes.
Allocate
The Allocate attribute is a an allocation hint. It indicates the recommended allocation policy for a transaction:
• If Allocate is asserted, it is recommended that the transaction is allocated into the cache for performance
reasons. However, it is permitted to not allocate the transaction.
• If Allocate is deasserted, it is recommended that the transaction is not allocated into the cache for
performance reasons. However, it is permitted to allocate the transaction.
Propagation of Attr
The MemAttr bits EWA, Device, Cacheable, and Allocate, must be preserved on a request from HN to SN that is
sent in response to a request to HN. The only exception to this rule is when the downstream memory is known to
be Normal, then the Device field value can be set to 0b0 to indicate Normal.
The SnpAttr attribute bit value in a request from HN to SN must always be set to 0b0.
For a ReadNoSnp or WriteNoSnp generated within the interconnect due to a Prefetch from Home, or an eviction
from the System cache:
• MemAttr bits EWA, Cacheable, and Allocate must all be set to 0b1.
• Device field value must be set to 0b0 to indicate Normal.
• SnpAttr field value must be set to 0b0 to indicate Non-snoopable.
2-112 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.9 Address, Control, and Data
Table 2-12 Legal combinations of MemAttr, SnpAttr, and Order field values
LikelyShared
Cacheable
Allocate
SnpAttr
Device
EWA
1 0 0 0 0 0 1 1 Device nRnE
0 0 1 0 0 1 1 Device nRE
0 0 1 0 0 0/1a 0 Device RE
a. Order = 0b10 is permitted in ReadOnce*, WriteUnique, ReadNoSnp, WriteNoSnp and Atomic transactions
only.
b. Order = 0b01 is not used for transactions’ ordering. See Order field encodings on page 2-103.
c. Non-cacheable Non-bufferable is an AXI memory type, not an ARM memory type.
d. LikelyShared = 1 is only permitted for ReadShared, ReadNotSharedDirty, ReadClean, WriteBackFull,
WriteCleanFull, WriteEvictFull, WriteUnique and StashOnce transactions.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-113
ID082919 Non-Confidential
2 Transactions
2.9 Address, Control, and Data
Memory type
This section specifies the required behavior for each of the memory types that Table 2-12 on page 2-113 shows.
Device nRnE
Device nRE
The required behavior for the Device nRE memory type is the same as for the Device nRnE memory type except
that:
• The write response can be obtained from an intermediate point.
Device RE
The required behavior for the Device RE memory type is same as for the Device nRE memory type except that:
• Read and Write transactions from the same source to the same endpoint need not remain ordered.
• Read and Write transactions from the same source to addresses that overlap must remain ordered.
The required behavior for the Normal Non-cacheable Non-bufferable memory type is:
• The write response must be obtained from the final destination.
• Read data must be obtained from the final destination.
• Writes can be merged.
• Read and Write transactions from the same source to addresses that overlap must remain ordered.
The required behavior for the Normal Non-cacheable Bufferable memory type is:
• The write response can be obtained from an intermediate point.
• Write transactions must be made visible at the final destination in a timely manner.
Note
There is no mechanism to determine when a Write transaction is visible at its final destination.
2-114 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.9 Address, Control, and Data
Note
For a Normal Non-cacheable Bufferable read, data can be obtained from a Write transaction that is still progressing
to its final destination. This is indistinguishable from the Read and Write transactions propagating to arrive at the
final destination at the same time. Read data returned in this manner does not indicate that the Write transaction is
visible at the final destination.
Write-back No-allocate
The required behavior for the Write-back No-allocate memory type is:
• Write transactions are not required to be made visible at the final destination.
• Read and Write transactions from the same source to addresses that overlap must remain ordered.
• The No-allocate attribute is an allocation hint, that is, it is a recommendation to the memory system that, for
performance reasons, the transaction is not allocated. However, the allocation of the transaction is not
prohibited.
Write-back Allocate
The required behavior for the WriteBack Allocate memory type is the same as for WriteBack No-allocate memory.
However, in this case, the allocation hint is a recommendation to the memory system that, for performance reasons,
the transaction is allocated.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-115
ID082919 Non-Confidential
2 Transactions
2.9 Address, Control, and Data
0 Non-snoopable
1 Snoopable
Table 2-14 shows the snoop attributes for the different transaction types.
ReadNoSnp, ReadNoSnpSep Y -
Evict - Y
WriteNoSnp Y -
WriteUnique - Y
Atomic transactions Y Y
The SnpAttr field value in a CMO, and in ReadNoSnp and ReadNoSnpSep from Home to Slave must be set to zero,
irrespective of the field value in the Request from the original Requester to Home.
Note
For transactions that can take more than one value of SnpAttr, the value is typically determined from page table
attributes.
2-116 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.9 Address, Control, and Data
Memory accesses from the different agents made with mismatched snoopability or cacheability attributes are
considered as software protocol errors. A software protocol error can cause loss of coherency and result in the
corruption of data values. It is required that the system does not deadlock on a software protocol error, and that
transactions always make forward progress.
A software protocol error for an access in one 4KB memory region must not cause data corruption in a different
4KB memory region.
For locations held in Normal memory, the use of appropriate software cache maintenance can be used to return
memory locations to a defined state.
The use of mismatched memory attributes can result in an RN-F observing a Snoop transaction to the same address
that it is performing a ReadNoSnp or WriteNoSnp transaction to. In this situation there is no defined relationship
between the Snoop transaction and the transaction that the RN-F has issued.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-117
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
Size[2:0] Bytes
0b000 1
0b001 2
0b010 4
0b011 8
0b100 16
0b101 32
0b110 64
0b111 Reserved
Normal memory
Transactions with a Normal memory type access the number of bytes defined by the Size field. Data
access is from the Aligned_Address, that is, the transaction address rounded down to the nearest Size
boundary, and ends at the byte before the next Size boundary.
This is calculated as:
Start_Address = Addr field value.
Number_Bytes = 2^Size field value.
INT(x) = Rounded down integer value of x.
Aligned_Address = (INT(Start_Address / Number_Bytes)) x Number_Bytes.
The bytes accessed are from (Aligned_Address) to (Aligned_Address + Number_Bytes) - 1.
Device Transactions with a Device memory type access the number of bytes from the transaction address
up to the byte before the next Size boundary.
The bytes accessed are from (Start_Address) to (Aligned_Address + Number_Bytes) - 1.
For write transactions to Device locations, byte enables must only be asserted for the bytes that are
accessed. See Byte Enables on page 2-119.
2-118 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.10 Data transfer
For Write transactions, an asserted byte enable indicates that the associated data byte is valid and must be updated
in memory or cache. A deasserted byte enable indicates that the associated data byte is not valid and must not be
updated in memory or cache.
In Write Data and Snoop response Data a byte enable value of zero must set the associated data byte value to zero.
If a snoop occurs between the sending of the Request and sending of the Data, and the Dirty copy of the Data from
the CopyBack is passed to the corresponding snoop response, then a CopyBackWrData_I packet is sent as the Data
response for the Copyback request indicating to the Home that the Copyback is canceled. A Requester must deassert
all BE values in a CopyBackWrData_I packet. The Requester must also deassert all BE values in a WriteDataCancel
packet that are a result of canceling of a WriteUniquePtl, WriteUniquePtlStash or WriteNoSnpPtl transaction.
The following Write transactions must have all byte enables asserted during the data transfers, except when the write
data is a CopyBackWrData_I packet:
• WriteNoSnpFull.
• WriteBackFull.
• WriteCleanFull.
• WriteEvictFull.
• WriteUniqueFull.
• WriteUniqueFullStash.
The following Write transactions are permitted to have any combination of byte enables asserted during the data
transfers. This includes asserting all and asserting none:
• WriteBackPtl.
• WriteUniquePtl.
• WriteUniquePtlStash.
• For a transaction to Normal memory, any combination of byte enables can be asserted during the data
transfers. This includes asserting all and asserting none.
• For a transaction to Device memory, byte enables must only be asserted for bytes at or above the address
specified in the transaction. Any combination of byte enables can be asserted that meets this requirement.
This includes asserting all and asserting none.
For all Write transactions, byte enables that are not within the data window, specified by Addr and Size, must be
deasserted.
For Atomic transactions, byte enables that are not within the data window, as specified below by Addr and Size,
must be deasserted:
• If Addr is aligned to Size, then the Data window is [Addr:(Addr+Size-1)].
• If Addr is not aligned to Size, then the Data window is [(Addr-Size/2):(Addr+Size/2-1)].
• For Atomic transactions all byte enables within the data window must be asserted.
For snoop responses with data that use the SnpRespData opcode, all byte enables must be asserted.
For snoop responses with data that use the SnpRespDataPtl opcode, any combination of byte enables can be asserted
alongside the data transfers. This includes asserting all and asserting none.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-119
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
The Data Identifier and Critical Chunk Identifier fields are used to identify data packets within a transaction.
A transaction size of up to 16-byte is always contained in a single packet. The DataID field value must be set to
Addr[5:4] because the DataID field represents Addr[5:4] of the lowest addressed byte within the packet.
Table 2-16 shows the relationship between the DataID field and the bytes that are contained within the packet, for
different data bus widths.
Table 2-16 DataID and the bytes within a packet for different data widths
Within a data packet, all bytes are located at their natural byte positions. This is true even if fewer data bytes are
transferred than the width of the data bus.
The number of data packets used for transactions to Device memory is independent of the address of the transaction.
The number of data packets required is determined only by the Size field and the data bus width.
Note
For some transactions to Device memory, it can be determined from the address at the start of the transaction that
some data packets will not contain valid data and are redundant. However, this specification requires that these data
packets are transferred.
2-120 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.10 Data transfer
Size
The Size field of the packet specifies the total data size of the Atomic transaction.
For the AtomicCompare transaction, the data size is the sum of the Compare and Swap data values.
Table 2-17 shows the permitted data sizes, and the relationship between inbound and outbound valid data size for
each Atomic transaction type. The size of the data value returned in response to an AtomicCompare transaction is
half the number of bytes specified in the Size field in the associated Request packet.
AtomicStore 1, 2, 4 or 8 byte -
• The position of data bytes in the Data packet matches the endianness of the operation, as specified in the
Endian field of the request.
The write data associated with an AtomicCompare transaction is provided as if it were for a transaction that is
aligned to the outbound data size.
• The byte address must be aligned in the Data packet to the inbound data size, which is equivalent to half the
outbound data size.
The two data values in an AtomicCompare transaction are placed in the data field in the following manner:
• The Compare and Swap data values are concatenated and the resulting data payload is aligned in the Data
packet to the outbound data size.
• The Compare data is always at the addressed byte location.
• The Swap data is always in the remaining half of the valid data.
For any given Compare data address, the Swap data address can be determined by inverting bit[n] in the Compare
data address where:
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-121
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
Alignment example
Figure 2-37 shows examples of data placement with different addresses and different Data size.
7 6 5 4 3 2 1 0
Example 3: Addr = 0x2 C C S S
2 Byte each
7 6 5 4 3 2 1 0
Example 4: Addr = 0x4 S S C C
In the first example that Figure 2-37 shows, the addressed byte location is 0x2 and the total size of data is two bytes.
In this case, the Compare and Swap data must be placed in an address location aligned to a two byte boundary that
includes the addressed location, that is, addresses 0x2 to 0x3. Compare data is placed in location 0x2 and Swap data
is placed in location 0x3.
Note
The address of the Swap data can be determined by inverting bit[0] of the Compare data address. Bit[0] is inverted
because the size of the Compare data and the size of the Swap data is one byte.
In the third example that Figure 2-37 shows, the addressed location is 0x2 and the total size of data is four bytes. In
this case, the Compare and Swap data must be placed in an address location aligned to a four byte boundary that
includes the addressed location, that is, addresses 0x0 to 0x3. Compare data is placed in location 0x2 and Swap data
is placed in location 0x0.
Note
The address of the Swap data can be determined by inverting bit[1] of the Compare data address. Bit[1] is inverted
because the size of the Compare data and the size of the Swap data is two bytes.
Endianness
The data on which an atomic operation executes can be in either little-endian or big-endian format. For arithmetic
operations, such as ADD, MAX, and MIN the component performing the operation needs to know the format of the
data.
The endian format of the data is defined by the Endian bit in the Atomic transaction Request packet. See Endian on
page 12-342.
2-122 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.10 Data transfer
The CCID field must match the value of Addr[5:4] of the original request. Transactions which contain multiple data
packets must use the same CCID value for all data packets.
When read data or write data is reordered by the interconnect, the CCID field permits quick identification of the
most critical bytes within a transaction by comparing the CCID value with the DataID value. When the two values
match, the data bytes being transferred are the critical bytes.
The interface property, CCF_Wrap_Order defines the capabilities of a Sender, and the guarantees provided by the
Receiver:
If some components in the system do not support sending Data packets in critical chunk first wrap order then the
receiver of Data must not rely on Data being received in critical chunk first wrap order.
Note
At design time, the CCF_Wrap_Order parameter can help a component to identify if Data packets need to be sent
in critical chunk first wrap order. For example, if the component knows that it is connected to an out-of-order
interconnect, then it might be able to simplify its Data packet path by not returning the Data packets in critical chunk
first wrap order.
If the interconnect has the CCF_Wrap_Order property set to True, then a component interfacing to that
interconnect, if capable, can send Data packets in critical chunk first wrap order, and the receiver can make use of
possible latency optimization due to receiving the critical chunk first.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-123
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
Note
Critical chunk first wrap order ensures that interfacing to protocols that do not support data reordering, such as AXI,
can be done in the most efficient manner when an ordered interconnect is used.
Start_Address = Addr
Number_Bytes = 2^Size
Lower_Wrap_Boundary = Aligned_Address
Note
Some of the steps to maintain wrap order might overlap and not be required if the required bytes are included in a
previous step.
2-124 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.10 Data transfer
In most of the examples, the size of the transaction is 64-byte and the data bus width is 128-bit. This requires 4 data
packets for each transaction.
In the following examples, the accompanying text highlights some interesting aspects. It is not intended to describe
all aspects of the example.
Example 2-1 Normal memory 64-byte Read transaction from an aligned address
Normal Memory
Read Transaction
Size = 0b110 (64B)
8F 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20
• The order of the data packets, as indicated by Packet 0, Packet 1, Packet 2, and Packet 3, is such that they
follow wrap order.
• The DataID changes for each packet, while the CCID field remains constant.
• The packet containing the data bytes specified by the address of the transaction has the same value for the
CCID and DataID fields.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-125
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
Example 2-2 Normal memory 64-byte Read transaction from an unaligned address
Normal Memory
Read Transaction
Size = 0b110 (64B)
8F 80 7F 70 6F 68 67 60 5F 50 4F 40 3F 30 2F 20
• The order of the data packets, as indicated by Packet 0, Packet 1, Packet 2, and Packet 3, is such that they
follow wrap order.
• The DataID changes for each packet, while the CCID field remains constant.
• The packet containing the data bytes specified by the address of the transaction has the same value for the
CCID and DataID fields.
Example 2-3 Normal memory 32-byte Read transaction from an unaligned address
Normal Memory
Read Transaction
Size = 0b101 (32B)
8F 80 7F 78 77 70 6F 60 5F 50 4F 40 3F 30 2F 20
Packet 0 Packet 1
• The size of the transaction is 32-byte and the data bus width is 128-bit, resulting in 2 data packets.
• The order of the data packets, as indicated by Packet 0 and Packet 1, is such that they follow wrap order.
2-126 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.10 Data transfer
Example 2-4 Normal memory 14-byte consecutive write transaction from an unaligned address
Normal Memory
Write Transaction
Size = 0b110 (64B)
8F 80 7F 70 6F 60 5F 58 57 50 4F 40 3F 30 2F 20
• The order of the data packets, as indicated by Packet 0, Packet 1, Packet 2, and Packet 3, is such that they
follow wrap order.
• The DataID changes for each packet, while the CCID field remains constant.
• The packet containing the data bytes specified by the address of the transaction has the same value for the
CCID and DataID fields.
• Fourteen consecutive bytes in memory are written, as indicated by the byte enables. However, other
combinations of byte enables are permitted. See Byte Enables on page 2-119.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-127
ID082919 Non-Confidential
2 Transactions
2.10 Data transfer
Device
Read Transaction
Size = 0b110 (64B)
8F 80 7F 70 6F 60 5F 58 57 50 4F 40 3F 30 2F 20
• The shaded area indicates the valid bytes in the transaction. The valid bytes extend from the transaction
address up to the next Size boundary.
• The transaction includes the transfer of a packet that contains no valid data.
Device
Write Transaction
Size = 0b110 (64B)
8F 80 7F 70 6F 68 67 60 5F 50 4F 40 3F 30 2F 20
• Byte enables are only permitted to be asserted for the bytes from the transaction address up to the next Size
boundary. It is not required that all byte enables meeting this criteria are asserted.
• Byte enables for bytes below the start address must not be asserted.
2-128 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.11 Request Retry
Request Retry is not applicable to the PrefetchTgt transaction. The PrefetchTgt transaction cannot be retried because
there is no response associated with this request.
A Requester is required to hold all the details of the request until it receives a response indicating that the request
has either been accepted, or must be sent again at a later point in time. To meet this requirement, with the exception
of PrefetchTgt, the AllowRetry field must be asserted the first time a transaction is sent.
A Completer that is receiving requests is able to give a RetryAck response to a request that it is not able to accept.
Typically, it will not be able to accept a request when it has limited resources and insufficient storage to hold the
current request until some earlier transactions have completed.
When a Completer gives a RetryAck response it is responsible for recording where the request came from, as
determined by the SrcID of the request. The Completer is also responsible for determining and recording the type
of Protocol Credit required to process the request. The PCrdType field in the RetryAck encodes the type of Protocol
Credit that will be granted by the Completer. When required resources become available, at a later point in time, the
Completer must then send a P-Credit to the Requester, using a PCrdGrant response. The PCrdGrant response
indicates to the Requester that the transaction can be retried.
Note
There is no explicit mechanism to request a credit. A transaction that is given a RetryAck response implicitly
requests a credit.
It is possible that a reordering interconnect can reorder the responses such that the PCrdGrant is received by the
Requester before the RetryAck response for the transaction is received. In this case, the Requester must record the
credit it has received, including the credit type, so that it can assign the credit appropriately when it does receive the
RetryAck response.
Note
It is expected to be rare that a PCrdGrant would be re-ordered with respect to a RetryAck response, as the delay
between a RetryAck and a PCrdGrant response will typically be much longer than any delay caused by interconnect
re-ordering.
When the Requester receives a credit, it can then resend the request with an indication that it has been allocated a
credit. This is done by deasserting the AllowRetry field. This second attempt to carry out the transaction is
guaranteed to be accepted.
The transaction that is resent must have the same field values as the original request, except for the following:
• TgtID. See Target ID determination for Request messages on page 3-136.
• QoS.
• TxnID.
• ReturnTxnID for ReadNoSnp and ReadNoSnpSep from HN to SN.
• RSVDC.
• AllowRetry, which must be deasserted.
• PCrdType, which must be set to the value in the Retry response for the original transaction.
• TraceTag.
There is no fixed relationship between credits and particular transactions. If a Requester has received multiple
RetryAck responses for different transactions and it then receives a credit, there is no fixed credit allocation, the
Requester is free to choose the most appropriate transaction from the list of transactions that received a RetryAck
response with that particular Protocol Credit Type.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-129
ID082919 Non-Confidential
2 Transactions
2.11 Request Retry
The retry mechanism supports up to sixteen different credit types. This lets the Completer use different credit types
for different resources. For example, a Completer might use one credit type for the resources associated with Read
transactions, and another credit type for Write transactions. Using different credit types gives the Completer the
ability to efficiently manage its resources by controlling which of the retried requests can be sent again.
The transaction must only be retried by the Requester when a PCrdGrant is received with the correct PCrdType.
Note
If a Completer is only using one credit type, this specification recommends that the PCrdType value of 0b0000 is
used. See PCrdType on page 2-131.
A Completer that is giving RetryAck responses must be able to record all the RetryAck responses that it has given
to ensure it can correctly distribute credits. If the Completer is using more than one credit type the RetryAck
responses that have been given for each credit type must be recorded.
A Requester must limit the transactions it issues so that the Completer is never required to track more than 1024
transactions that require a PCrdGrant response. This is achieved by limiting the maximum number of outstanding
transactions to 1024 for each Requester.
Note
Prior to Issue D the maximum number of outstanding transactions was limited to 256 for each Requester.
A transaction is outstanding from the cycle that the request is first issued until either:
• The transaction is fully completed, as determined by the return of all the following responses that are
expected for the transaction:
— ReadReceipt, CompData, RespSepData, DataSepResp, DBIDResp, Comp, and CompDBIDResp.
• As soon as it receives all the required responses for that request if the received responses are non-RetryAck
responses.
Each transaction request includes a QoS value which can be used by the Completer to influence the allocation of
credits as resources become available. See Chapter 10 Quality of Service for further details.
This specification does not define when this can occur, but two typical scenarios are:
• A transaction is canceled between the first attempt and the point at which it can be resent with P-Credit.
• A transaction is requested multiple times with increasing QoS values. However, only a single completion of
the transaction is required.
Note
If a Requester makes a second request before the first request has been given a RetryAck response then it must be
acceptable for both transactions to occur. However, as an example, this behavior would typically not be acceptable
for accesses to a peripheral device.
2-130 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
2 Transactions
2.11 Request Retry
A Requester returns a credit by the use of the PCrdReturn transaction. This is effectively a No Operation (NOP)
transaction that uses the credit that is not required. This transaction is used to inform the Completer that the allocated
resources are no longer required for the given PCrdType.
Any credits that are not required must be returned in a timely manner.
Note
Any unused pre-allocated credit must be returned to avoid components holding on to credits in expectation of using
them later. Such behavior is likely to result in an inefficient use of resources and to make analysis of the system
performance difficult.
AllowRetry
The AllowRetry field indicates if the Request transaction can be given a RetryAck response. See Table 12-27 on
page 12-342 for the AllowRetry value encodings. The AllowRetry field must be asserted the first time a transaction
is sent.
PCrdType
The PCrdType field indicates the credit type associated with the request and is determined as follows:
• A PCrdReturn transaction must have the credit type set to the value of the credit type that is being returned.
See PCrdType on page 12-345 for the PCrdType value encodings.
• For destinations that have a single credit class, or do not implement credit type classification, this
specification recommends that the PCrdType field is set to 0b0000.
Note
The value a Completer assigns to PCrdType is IMPLEMENTATION DEFINED.
The Completer must implement a starvation prevention mechanism to ensure that all transactions, irrespective of
QoS value or credit type required, will eventually make forward progress, even if over a significantly long time
period. This is done by ensuring that credits are eventually given to every transaction that has received a RetryAck
response. See Chapter 10 Quality of Service for more details on the distribution of credits for the purposes of QoS.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 2-131
ID082919 Non-Confidential
2 Transactions
2.11 Request Retry
RN-F HN-F
ReadOnce
(AllowRetry = 1) HN-F buffer entry
(PCrdType = 0b0000) not gained
RetryAck
(PCrdType = n)
PCrdGrant (P-Credit allocated)
(PCrdType = n)
Wait for
P-Credit
ReadOnce
(AllowRetry = 0)
(PCrdType = n)
n = 0x0 to 0xF
2. The Completer receives the request and sends a RetryAck response because it is not able to process the
transaction at this time.
• The request is logged and a PCrdType is determined at the Completer.
3. The Completer sends a P-Credit, using the PCrdGrant response, when it has allocated resource for the
transaction.
• The PCrdGrant includes the PCrdType allocated for the original request.
It is permitted, but not expected, for a Completer to send a PCrdGrant before it has sent the associated RetryAck
response.
Note
The Requester might receive PCrdGrant before RetryAck.
The second attempt at a transaction must not be sent until both a RetryAck response and an appropriate P-Credit is
received for the transaction.
2-132 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 3
Network Layer
This chapter describes the network layer that is responsible for determining the node ID of a destination node. It
contains the following sections:
• System address map on page 3-134.
• Node ID on page 3-135.
• Target ID determination on page 3-136.
• Network layer flow examples on page 3-138.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 3-133
ID082919 Non-Confidential
3 Network Layer
3.1 System address map
The exact format and structure of the SAM is IMPLEMENTATION DEFINED and is outside the scope of this
specification.
The SAM must provide a complete decode of the entire address space. This specification recommends that any
address that does not correspond to a physical component is sent to an agent that can provide an appropriate error
response.
3-134 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
3 Network Layer
3.2 Node ID
3.2 Node ID
Each component connected to a Port on the interconnect is assigned a node ID that is used to identify the source and
destination of packets communicated over the interconnect. A Port can be assigned multiple node IDs. A node ID
value can be assigned only to a single Port.
The width can be configured to any fixed value within this range for a given implementation and this value must be
consistent across all NodeID fields.
Defining and assigning a node ID for each node in a system is IMPLEMENTATION DEFINED and is outside the scope
of this specification.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 3-135
ID082919 Non-Confidential
3 Network Layer
3.3 Target ID determination
The target ID of a Request message is determined in the following manner using the system address map logic.
• If the request does not use a pre-allocated credit, then the target ID is determined by:
— Opcode for DVMOp.
— Address to node ID mapping for all other requests.
PrefetchTgt uses a different Address to Node ID mapper than other Requests. Two Requests from an
RN to the same Address, where one is a PrefetchTgt, target different nodes. PrefetchTgt always targets
an SN. All other Requests from an RN that use an Address to Node ID mapper target an HN.
• If the request uses pre-allocated credit, the target ID of the request must be obtained from either the source
ID of the RetryAck, provided as a response to the original Request message, or the target ID of the original
request.
For PCrdReturn:
• The target ID provided by the RN must match the source ID included in the prior PCrdGrant which provided
the credit being returned.
For transactions from an RN, with the exception of PrefetchTgt which is targeted to an SN-F, this specification
expects a Snoopable transaction to be targeted to HN-F and a Non-snoopable transaction to target HN-I or HN-F. It
is legal for a Snoopable transaction to be targeted at an HN-I. This might occur, for example, due to a software
programming error. In this case, the HN-I is required to respond to the transaction in a protocol compliant manner,
but coherency is not guaranteed.
An HN might also use address map logic to determine the target Slave Node ID for each Request.
3-136 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
3 Network Layer
3.3 Target ID determination
RespSepData Request.SrcID - -
SnpResp*b - - Snoop.SrcID
a. For Data Pull requests where Snoop response can be SnpResp or SnpRespData or SnpRespDataPtl.
b. SnpResp, SnpRespData, SnpRespDataPtl, SnpRespFwded, and SnpRespDataFwded.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 3-137
ID082919 Non-Confidential
3 Network Layer
3.4 Network layer flow examples
1. RN0 sends a request with Target ID of HN0 using the SAM internal to RN0.
• The interconnect does not remap the node ID.
5. RN0 sends, if required, a CompAck with TgtID of HN0 derived from the HomeNID in the Data Response
packet to complete the transaction.
TgtID=SN0
RN0 TgtID=HN0 HN0 SrcID=HN0 SN0
SrcID=RN0 ReturnNID=RN0
Dec Req Dec Req
Addr
TgtID=RN0
SrcID=SN0
HomeNID=HN0
RDATA
TgtID=HN0
SrcID=RN0
Resp
3-138 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
3 Network Layer
3.4 Network layer flow examples
Note
Only the target ID of the request from the RN is remapped. The TgtID in all other packets in the transaction flow is
determined in a similar manner to Simple flow on page 3-138.
TgtID=RN0
SrcID=SN0
HomeNID=HN1
RDATA
TgtID=HN1
SrcID=RN0
Resp
3. RN0 resends the request once both RetryAck and PCrdGrant responses are received.
• The TgtID in the retried request is the same as the SrcID in the received RetryAck or the TgtID in the
original request. The TgtID must pass through the remapping logic again.
4. The packets in the rest of the transaction flow get the TgtID in a similar manner to Flow with interconnect
based SAM.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 3-139
ID082919 Non-Confidential
3 Network Layer
3.4 Network layer flow examples
TgtID=RN0
SrcID=HN1
Retry
PCrdGrant
TgtID=SN0
TgtID=HN1 TgtID=HN1 SrcID=HN1
SrcID=RN0 SrcID=RN0 ReturnNID=RN0
Remap
Dec Req Req Dec Req
Dec
Addr
TgtID=RN0
SrcID=SN0
HomeNID=HN1
RDATA
TgtID=HN1
SrcID=RN0
Resp
3-140 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 4
Coherence Protocol
This chapter describes the coherence protocol and contains the following sections:
• Cache line states on page 4-142.
• Request types on page 4-144.
• Snoop request types on page 4-160.
• Request types and corresponding snoop requests on page 4-163.
• Response types on page 4-166.
• Silent cache state transitions on page 4-177.
• Cache state transitions at a Requester on page 4-178.
• Cache state transitions at a Snoopee on page 4-183.
• Returning Data with Snoop response on page 4-198.
• Do not transition to SD on page 4-199.
• Hazard conditions on page 4-200.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-141
ID082919 Non-Confidential
4 Coherence Protocol
4.1 Cache line states
I Invalid:
• The cache line is not present in the cache.
UC Unique Clean:
• The cache line is present only in this cache.
• The cache line has not been modified with respect to memory.
• The cache line can be modified without notifying other caches.
• In response to a snoop that requests data, the cache line is permitted, but not required to be:
— Returned to Home when requested.
— Forwarded directly to the Requester when instructed by the snoop.
UD Unique Dirty:
• The cache line is present only in this cache.
• The cache line has been modified with respect to memory.
• The cache line must be written back to next level cache or memory on eviction.
• The cache line can be modified without notifying other caches.
• In response to a snoop that requests data, the cache line must be:
— Returned to Home when requested.
— Forwarded directly to the Requester when instructed by the snoop.
4-142 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.1 Cache line states
SC Shared Clean:
• Other caches might have a shared copy of the cache line.
• The cache line might have been modified with respect to memory.
• It is not the responsibility of this cache to write the cache line back to memory on eviction.
• The cache line cannot be modified without invalidating any shared copies and obtaining
unique ownership of the cache line.
• In response to a snoop that requests data, the cache line:
— Is required to not return data if RetToSrc bit is not set.
— Can return data if RetToSrc bit is set.
— Is forwarded directly to the Requester when instructed by the snoop.
SD Shared Dirty:
• Other caches might have a shared copy of the cache line.
• The cache line has been modified with respect to memory.
• The cache line must be written back to next level cache or memory on eviction.
• The cache line cannot be modified without invalidating any shared copies and obtaining
unique ownership of the cache line.
• In response to a snoop that requests data, the cache line must be:
— Returned to Home when requested.
— Forwarded directly to the Requester when instructed by the snoop.
The following are examples of when empty cache line ownership can occur:
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-143
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
• Read requests:
— A data response is provided to the Requester.
— Can result in data movement among other agents in the system.
— Can result in a cache state change at the Requester.
— Can result in a cache state change at other Requesters in the system.
• Dataless requests:
— No data response is provided to the Requester.
— Can result in data movement among other agents in the system.
— Can result in a cache state change at the Requester.
— Can result in a cache state change at other Requesters in the system.
• Write requests:
— Move data from the Requester.
— Can result in data movement among other agents in the system.
— Can result in a cache state change at the Requester.
— Can result in a cache state change at other Requesters in the system.
• Atomic requests:
— Move data from the Requester.
— A data response is provided to the Requester in some Request types.
— Can result in data movement among other agents in the system.
— Can result in a cache state change at the Requester.
— Can result in a cache state change at other Requesters in the system.
• Other requests:
— Do not involve any data movement in the system.
— Can be used to assist with Distributed Virtual Memory (DVM) maintenance.
— Can be used to warm the memory controller for a following read request.
The following subsections enumerate the resulting transactions and their characteristics.
Note
In Read transactions on page 4-145, Dataless transactions on page 4-149 and Write transactions on page 4-152,
information is provided on the expected communicating node pairs. It is also legal for any transaction that is
expected to target an HN-F, but not an HN-I, to target an HN-I. This can occur in the case of an incorrect assignment
of memory type for a transaction. It is required that the HN-I responds to such a transaction in a protocol compliant
manner. See Appendix B Communicating Nodes for complete information on communication node pairs.
4-144 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
• Can have exclusive attribute asserted. See Chapter 6 Exclusive Accesses for details.
— Data cannot be obtained directly from the Slave Node using DMT if the
Exclusive bit is set.
• Permitted, but not required, to assert ExpCompAck in the Request.
• Permitted to assert Order field in the Request.
• Permitted to use DMT if ExpCompAck is asserted in the Request.
• Permitted to use DMT if both ExpCompAck and Order are deasserted in the
Request.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
ReadNoSnpSep A read request to tell the Completer to send only a Data response:
• Data only returned in the response.
• Data size is a cache line length.
• Must not assert ExpCompAck in the Request.
• The Order field of the request must be set to b01.
• Communicating node pairs:
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I
ReadOnce Read request to a Snoopable address region to obtain a snapshot of the coherent data.
• Data is included with the completion response.
• Data size is a cache line length.
• Data will not be cached at the Requester.
Note
It is permitted to retain a copy of the data obtained in a local cache, or buffer, but this
copy of the data will not remain coherent.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-145
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
ReadOnceCleanInvalid
Read request to a Snoopable address region to obtain a snapshot of the coherent data:
• Data is included with the completion response.
• Data size is a cache line length.
• Data will not be cached in a coherent state at the Requester.
• Permitted, but not required to assert ExpCompAck in the request.
• Permitted to assert Order field in the request.
• Permitted to use DMT if ExpCompAck is asserted in the Request.
• Permitted to use DMT if both ExpCompAck and Order field are deasserted in the
Request.
• It is recommended, but not required that a snooped cached copy is invalidated.
• If a Dirty copy is invalidated, it must be written back to memory.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
Note
ReadOnceCleanInvalid is used instead of ReadOnce or ReadOnceMakeInvalid where the
application determines that the data is still Valid, but will not be used in the near future.
Use of ReadOnceCleanInvalid by an application improves cache efficiency by reducing
cache pollution.
ReadOnceMakeInvalid
Read request to a Snoopable address region to obtain a snapshot of the coherent data:
• Data is included with the completion response.
• Data size is a cache line length.
• Data will not be cached in a coherent state at the Requester.
• Permitted, but not required, to assert ExpCompAck in the Request.
• Permitted to assert Order field in the Request.
• Permitted to use DMT if ExpCompAck is asserted in the Request.
• Permitted to use DMT if both ExpCompAck and Order field are deasserted in the
Request.
• It is recommended, but not required, that all snooped cached copies are invalidated.
• If a Dirty copy is invalidated, it does not need to be written back to memory.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
4-146 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
Note
ReadOnceMakeInvalid is used in preference to ReadOnce or ReadOnceCleanInvalid to
obtain a snapshot of a data value when the application determines that the cached data is not
going to be used again.
The application can free up the caches and also, by discarding Dirty data, avoid an
unnecessary WriteBack to memory.
ReadNotSharedDirty
Read request to a Snoopable address region.
• Data is included with the completion response.
• Data size is a cache line length.
• Requester will accept the data in any valid state except SD:
— UC, UD, SC.
• Can have exclusive attribute asserted. See Chapter 6 Exclusive Accesses for details.
— Data cannot be obtained directly from the Slave Node using DMT if the
Exclusive bit is set.
• Communicating node pairs:
— RN-F to ICN(HN-F).
• Request is included in this specification for use by caches that do not support the
SharedDirty state.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-147
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
ReadUnique Read request to a Snoopable address region to carry out a store to the cache line.
• All other cached copies must be invalidated.
• Data is included with the completion response.
• Data size is a cache line length.
• Data must be provided to the Requester in unique state only:
— UC, or UD.
• Communicating node pairs:
— RN-F to ICN(HN-F).
4-148 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
MakeUnique Request to Snoopable address region to obtain ownership of the cache line without a data
response. This request is used only when the Requester guarantees that it will carry out a
store to all bytes of the cache line.
• Data is not included with the completion response.
• Any dirty copy of the cache line at a snooped cache must be invalidated without
carrying out a data transfer.
• Communicating node pairs:
— RN-F to ICN(HN-F).
Evict Used to indicate that a Clean cache line is no longer cached by an RN.
• Data is not sent for this transaction.
• The cache line must not remain in the cache.
• Communicating node pairs:
— RN-F to ICN(HN-F).
StashOnceUnique
Request to a Snoopable address region. Request includes the Node ID of another RN and
the Request can optionally include the ID of a Logical Processor within that node. It is
recommended, but not required, that the other agent is snooped to indicate that it reads the
addressed cache line and ensures that it is in a cache state suitable for writing to the cache
line. The expected Read request is ReadUnique, or CleanUnique. When a valid target is not
specified, the addressed cache line can be fetched to be cached at the request Completer.
• Data is not included with the completion response.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
StashOnceShared
Request to a Snoopable address region. Request includes the Node ID of another RN and
the Request can optionally include the ID of a Logical Processor within that node. It is
recommended, but not required, that the other agent is snooped to indicate that it reads the
addressed cache line. The expected Read request is ReadShared or ReadNotSharedDirty.
When a valid target is not specified, then the addressed cache line can be fetched to be
cached at the request Completer.
• Data is not included with the completion response.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-149
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
CleanShared The completion response to a CleanShared request ensures that all cached copies are
changed to a Non-dirty state and any Dirty copy is written back to memory.
CleanSharedPersist The completion response to a CleanSharedPersist request ensures that all cached copies are
changed to a Non-dirty state and any Dirty cached copy is written back to the Point of
Persistence (PoP) or final destination.
CleanSharedPersistSep
The Persist or combined CompPersist completion response to a CleanSharedPersistSep
request ensures that all cached copies are changed to a Non-dirty state and any Dirty cached
copy is written back to the Point of Persistence (PoP), or final destination.
Functionality of CleanSharedPersistSep is similar to CleanSharedPersist but requires two
separate responses to the Requester:
• Comp response, indicating that the request has reached the Point of Coherency (PoC)
and hazards can be removed at the Requester.
• Persist response, indicating that the request has reached the PoP, or the final
destination.
It is expected, but not required, that a Requester, when sending a persistent CMO, uses a
CleanSharedPersistSep transaction instead of CleanSharedPersist.
Such a Requester must support receiving both separate Comp and Persist responses as well
as a combined CompPersist response.
CleanInvalid The completion response to a CleanInvalid request ensures that all cached copies are
invalidated. The request requires that any cached Dirty copies must be written to memory.
MakeInvalid The completion response to a MakeInvalid request ensures that all cached copies are
invalidated. The request permits that any cached Dirty copies are discarded.
• Data is not included with the completion response. The Resp field value in the Comp, indicating cache state,
must be ignored by both the Requester and the Home.
• Sending of a CMO transaction to the interconnect from an RN and from the interconnect to an SN is
controlled by the BROADCASTPERSIST (BP) and BROADCASTCACHEMAINTENANCE (BCM)
interface signals. See Optional interface broadcast signals on page 15-385.
Note
Permitting CMOs to be forwarded downstream of the Home Node incorporates system topologies where some
observers might directly access locations downstream of the Home Node and software cache maintenance is
required to make cached data visible to such observers.
4-150 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
1 0 0 0
0 0 1
0 0 0 0
0 0 1
0 1 1
1 1 1
— MemAttr values on a request received at Home must be preserved when the request is propagated to
the Slave, except when it is known that the Slave has only Normal memory, in which case the MemAttr
bit Device can be set to Normal.
• Snoopable attribute can take any value.
• Order field must not be asserted:
— A CMO intended for a particular address must not be sent to the interconnect before all previous
transactions sent to the same address that can allocate the received data in the Requester caches have
completed.
— A transaction, except Evict, WriteEvictFull, and PrefetchTgt, intended for a particular address, must
not be sent to the interconnect before a previous CMO sent to the same address has completed.
If a Requester has persistent CMO requests from different functional agents that it would like to identify for
performant persistent CMO handling, it can assign a different PGroupID value to each group of Persist requests.
Use of PGroupID is applicable only in CleanSharedPersistSep transactions. See PGroupID on page 12-331:
• The PGroupID value returned in the Persist response can be used by a Requester to separately track
completions of Persist responses from each group.
• It is expected that a Requester that does not support multiple persistence groups sets the PGroupID value to
zero.
• A Requester that is making use of PGroupID for passing a barrier typically will not reuse a PGroupID value
until all the earlier sent CleanSharedPersistSep requests from that group have received Persist responses.
• The Completer is required to reflect back PGroupID in the Persist and CompPersist responses.
• The PGroupID field in the Comp response from both the Home and Slave is inapplicable and must be set to
zero.
Systems with non-volatile memory to meet high availability expectations require guarantees that operation critical
data is preserved on back-up battery failure as well as on power failure. The guarantee can be provided by a system
by adding a mechanism to push previous writes to the Point of Deep Persistence. This specification supports this
feature using an attribute, called Deep, on Persistent CMO transactions.
Deep attribute is applicable in the CleanSharedPersist and CleanSharedPersistSep transactions. See Deep on
page 12-338.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-151
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
WriteNoSnpFull Write a full cache line of data from an RN to a Non-snoopable address region, or a write for
a full cache line of data from Home to Slave.
• Data size is a cache line length.
• All byte enables must be asserted.
• Can have the exclusive attribute asserted. See Chapter 6 Exclusive Accesses.
• Permitted to assert ExpCompAck only when Order field value is set to 0b10.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
WriteNoSnpPtl Write a partial cache line of data from an RN to Non-snoopable address region or a write for
a partial cache line of data from Home to Slave.
• Data size is up to a cache line length.
• Byte enables must be asserted for the appropriate byte lanes within the specified data
size and deasserted in the rest of the data transfer.
• Can have the exclusive attribute asserted. See Chapter 6 Exclusive Accesses.
• Permitted to assert ExpCompAck only when Order field value is set to 0b10.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
WriteUniqueFull Write to a Snoopable address region. Write a full cache line of data to the next-level cache
or memory when the cache line is Invalid at the Requester.
• Data size is a cache line length.
• All byte enables must be asserted.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
WriteUniquePtl Write to a Snoopable address region. Write up to a cache line of data to the next-level cache
or memory when the cache line is Invalid at the Requester.
• Data size is up to a cache line length.
• Byte enables must be asserted for the appropriate byte lanes within the specified data
size and deasserted in the rest of the data transfer.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
4-152 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
WriteUniqueFullStash
Write to a Snoopable address region. Write a full cache line of data to the next-level cache
or memory when the cache line is Invalid at the Requester. Also includes a request to the
Stash target node to read the addressed cache line. The expected Read request is
ReadUnique.
• Data size is a cache line length.
• All byte enables must be asserted.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
WriteUniquePtlStash
Write to a Snoopable address region. Write up to a cache line of data to the next-level cache
or memory when the cache line is Invalid at the Requester. Also includes a request to the
Stash target node to read the addressed cache line. The expected Read request type is
ReadUnique.
• Data size is up to a cache line length.
• Byte enables must be asserted for the appropriate byte lanes within the specified data
size and deasserted in the remainder of the data transfer.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F).
CopyBack transactions
CopyBack transactions are a subclass of Write transactions. CopyBack transactions move coherent data from a
cache to the next level cache or memory. Each CopyBack transaction must assert the appropriate byte enables with
the data. CopyBack transactions do not require the snooping of other agents in the system.
WriteBackFull Write-back a full cache line of Dirty data to the next level cache or memory.
• Data size is a cache line length.
• All byte enables must be asserted except when the write data is CopyBackWrData_I.
• The cache line must not remain in the cache.
• Communicating node pairs:
— RN-F to ICN(HN-F).
WriteBackPtl Write-back up to a cache line of Dirty data to the next level cache or memory.
• Data size is a cache line length.
• All appropriate byte enables, up to all 64, must be asserted.
• The cache line must not remain in the cache.
• Communicating node pairs:
— RN-F to ICN(HN-F).
WriteCleanFull Write-back a full cache line of Dirty data to the next level cache or memory and retain a
Clean copy in the cache.
• Data size is a cache line length.
• All byte enables must be asserted except when the write data is CopyBackWrData_I.
• The cache line is expected to be in Clean state at completion of the transaction.
• Communicating node pairs:
— RN-F to ICN(HN-F).
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-153
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
Without an Atomic transaction, an atomic operation has to be executed using a sequence of memory accesses. These
accesses might rely on Exclusive reads and writes.
• The blocking period of access to the memory location being modified is reduced, which then reduces the
impact on the forward progress of memory accesses by other agents.
• Providing fairness among different Requesters accessing a memory location becomes simpler, because
accessing of that memory location by an atomic operation is arbitrated at the PoS or PoC.
This specification defines the following terms relating to atomic operations and Atomic transactions:
Atomic operation The execution of a function involving multiple data values such that, the loading of the
original value, the execution of the function, and the storing of the updated value, occurs in
an atomic manner so that no other agent has access to the location during the entire
operation.
Atomic transaction A transaction that is used to pass an atomic operation, along with the data values required
for the execution of the atomic operation, from one agent in a system to another, so that the
atomic operation can be carried out by a different component in the system than the
component that requires the operation to be performed.
The following terminology is used to refer to the different data elements in the execution of an atomic operation:
InitialData The content of the addressed location before the atomic operation.
4-154 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
AtomicStore • Sends a single data value with an address and the atomic operation to be performed.
• The target, an HN or an SN, performs the required operation on the address location
specified with the data supplied in the Atomic transaction.
• The target returns a completion response without data.
• Outbound data size is 1, 2, 4, or 8 byte.
• Only appropriate byte enables must be asserted.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
• Number of operations supported is 8.
Table 4-1 shows the eight operations supported by the AtomicStore transaction.
STSMAX
• Update location with TxnData if:
— (((Signed INT) TxnData – (Signed INT) InitialData) > 0).
• InitialData is not returned to the Requester.
STUMAX
• Update location with TxnData if:
— (((Unsigned INT) TxnData – (Unsigned INT) InitialData) > 0).
• InitialData is not returned to the Requester.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-155
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
AtomicLoad • Sends a single data value with an address and the atomic operation to be performed.
• The target, an HN or an SN, performs the required operation on the address location
specified with the data value supplied in the Atomic transaction.
• The target returns the completion response with data. The data value is the original
value at the addressed location.
• Data will not be cached at the Requester.
• Outbound data size is 1, 2, 4, or 8 byte.
• Only appropriate byte enables must be asserted.
• Inbound data size is the same as the outbound data size.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
• Number of operations supported is 8.
Table 4-2 shows the eight operations supported by the AtomicLoad transaction.
LDSMAX
• Update location with TxnData if:
— (((Signed INT) TxnData – (Signed INT) InitialData) > 0).
• Return InitialData to the Requester.
LDUSMAX
• Update location with TxnData if:
— (((Unsigned INT) TxnData – (Unsigned INT) InitialData) > 0).
• Return InitialData to the Requester.
4-156 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
AtomicSwap • Sends a single data value, the swap value, together with the address of the location to
be operated on.
• The target, an HN or an SN, swaps the value at the address location with the data
value supplied in the transaction.
• The target returns the completion response with data. The data value is the original
value at the addressed location.
• Data will not be cached at the Requester.
• Outbound data size is 1, 2, 4, or 8 byte.
• Only appropriate byte enables must be asserted.
• Inbound data size is the same as the outbound data size.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
• Number of operations supported is 1.
AtomicCompare
• Sends two data values, the compare value and the swap value, with the address of the
location to be operated on.
• The target, an HN or an SN, compares the value at the addressed location with the
compare value:
— If the values match, the target writes the swap value to the addressed location.
— If the values do not match, the target does not write the swap value to the
addressed location.
• The target returns the completion response with data. The data value is the original
value at the addressed location.
• Data will not be cached at the Requester.
• Outbound data size is 2, 4, 8, 16, or 32 byte.
• Only appropriate byte enables must be asserted.
• Inbound data size is half of the outbound data size.
• Communicating node pairs:
— RN-F, RN-D, RN-I to ICN(HN-F, HN-I).
— ICN(HN-F) to SN-F.
— ICN(HN-I) to SN-I.
• Number of operations supported is 1.
• The Completer must wait for all snoop responses before sending the Comp or CompData response.
When the Slave Node supports the execution of atomic operations, the Home is permitted to forward Atomic
transactions to the Slave Node. Home cannot use DMT for Non-store atomics that are forwarded to SN. The rules
governing such forwarding are:
• The Atomic transaction must be sent to the Slave Node only after all the required Snoop transactions are
completed and any Dirty cached data is written back to the Slave Node.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-157
ID082919 Non-Confidential
4 Coherence Protocol
4.2 Request types
• The Slave Node can either send a separate Comp and DBIDResp or a combined CompDBIDResp as a
response to the Atomic Store transaction. For AtomicLoad, AtomicSwap, and AtomicCompare transactions
the Slave node must send DBIDResp and Comp with Data as CompData. CompData must use the value of
ReturnNID and ReturnTxnID from the request as the value of TgtID and TxnID respectively.
Note
By separating the Comp and DBIDResp responses, the Slave Node has an opportunity to signal an error in
the received data, or an error during execution of the atomic operation.
• Home must send Atomic transaction data after receiving DBIDResp without waiting for completion.
• Home is permitted to send the completion response to the Requester without waiting for the initiation or
completion of the Atomic transaction at the Slave Node.
A Requester with a cache can handle an Atomic transaction request to a Snoopable memory region as follows:
• If the cache line is Unique, then it can perform the atomic operation locally without generating an Atomic
transaction.
• Optionally, in all the above cases, the Requester is permitted to send the Atomic transaction with the
SnoopMe bit set to direct the interconnect to send a Snoop request to the Requester to invalidate, and if
required, extract the cached copy. See SnoopMe on page 12-343.
4-158 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.2 Request types
DVM transactions
DVM transactions are used for virtual memory system maintenance.
DVMOp DVM Operation. Actions include the passing of messages between components within a distributed
virtual memory system. See Chapter 8 DVM Operations for details.
• Communicating node pairs:
— RN-F, RN-D to ICN(MN).
Prefetch transaction
The prefetch target transaction is used to speculatively fetch data from main memory.
PrefetchTgt Prefetch Target. A Request to a Snoopable memory address, sent from a Request Node directly to a
Slave Node:
• The PrefetchTgt transaction does not include a response.
• The request can be used by the Slave Node to fetch the data from off-chip memory and buffer
it in anticipation of a subsequent Read request to the same location.
• The request does not include a response, therefore the Requester can deallocate the request
as soon as the request is sent.
• The following fields are inapplicable and can take any value:
— TxnID.
— Order.
— Endian.
— Size.
— MemAttr.
— SnpAttr.
— Excl.
— LikelyShared.
Note
Prior to CHI Issue C, the Transaction ID field is inapplicable and must be set to zero.
The receiver must accept the request without any dependency on receiving of a subsequent Read request to the same
address.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-159
ID082919 Non-Confidential
4 Coherence Protocol
4.3 Snoop request types
SnpOnceFwd, SnpOnce
Snoop request to obtain the latest copy of the cache line, preferably without changing the
state of the cache line at the Snoopee:
• SnpOnceFwd is permitted to be sent only to one RN-F.
• See Forward Snoop transactions on page 4-191 for the permitted responses to
SnpOnceFwd.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for the permitted
responses to SnpOnce.
• Expected not to change cache state.
SnpStashUnique
Snoop request recommending that the Snoopee obtains a copy of the cache line in a Unique
state:
• Permitted to be sent to only one RN-F.
• This specification recommends not sending the snoop for a StashOnceUnique request
if the cache line is cached in Unique state at the Stash target.
• Permitted to send the snoop to the Stash target for WriteUniqueFullStash and
WriteUniquePtlStash only if the Snoopee does not have a cached copy of the cache
line.
• The Snoopee must not return data with the Snoop response.
• Permits the Snoop response to include a Data Pull if the value of the DoNotDataPull
field is 0b0 in the Snoop request.
• Must not change the cache line state at the Snoopee.
SnpStashShared
Snoop request recommending that the Snoopee obtains a copy of the cache line in a Shared
state:
• Permitted to be sent to only one RN-F.
• This specification recommends not sending the snoop if the cache line is cached at
the target.
• The Snoopee must not return data with the Snoop response.
• Permits the Snoop response to include a Data Pull if the value of the DoNotDataPull
field is 0b0 in the Snoop request.
• Must not change the cache line state at the Snoopee.
SnpCleanFwd, SnpClean
Snoop request to obtain a copy of the cache line in Clean state while leaving any cache copy
in Shared state:
• SnpCleanFwd is permitted to be only sent to one RN-F.
• See Forward Snoop transactions on page 4-191 for permitted responses to
SnpCleanFwd.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
responses to SnpClean.
• Must not leave the cache line in Unique state.
4-160 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.3 Snoop request types
SnpNotSharedDirtyFwd, SnpNotSharedDirty
Snoop request to obtain a copy of the cache line in SharedClean state while leaving any
cached copy in a Shared state:
• SnpNotSharedDirtyFwd is permitted to be sent only to one RN-F.
• See Forward Snoop transactions on page 4-191 for permitted responses to
SnoopNotSharedDirtyFwd.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
responses to SnpNotSharedDirty.
SnpSharedFwd, SnpShared
Snoop request to obtain a copy of the cache line in Shared state while leaving any cached
copy in Shared state:
• SnpSharedFwd is permitted to be only sent to one RN-F.
• See Forward Snoop transactions on page 4-191 for permitted responses to
SnpSharedFwd.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
responses to SnpShared.
• Must not leave the cache line in Unique state.
SnpUniqueFwd, SnpUnique
Snoop request to obtain a copy of the cache line in Unique state while invalidating any
cached copies:
• SnpUniqueFwd is permitted to be sent to only one RN-F.
• See Forward Snoop transactions on page 4-191 for permitted responses to
SnpUniqueFwd.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
responses to SnpUnique.
• Must change the cache line to Invalid state.
SnpUniqueStash
Snoop request to invalidate the cached copy at the Snoopee and recommends that the
Snoopee obtains a copy of the cache line in Unique state:
• Permitted to be sent to only one RN-F.
• Snoop response can include data.
• See Stash snoop transactions on page 4-188 for responses to SnpUniqueStash.
• Permits the Snoop response to include a Data Pull if the value of the DoNotDataPull
field in the Snoop request is 0b0.
• If not using Data Pull, then this specification recommends, but it is not required, that
the Snoopee uses ReadUnique to prefetch the cache line.
SnpCleanShared Snoop request to remove any Dirty copy of the cache line at the Snoopee:
• Snoop response can include data.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
SnpCleanShared responses.
• Must not leave the cache line in a Dirty state.
SnpCleanInvalid Snoop request to Invalidate the cache line at the Snoopee and obtain any Dirty copy. Might
also be generated by the ICN without a corresponding request:
• Snoop response can include data.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
SnpCleanInvalid responses.
• Must change the cache line to Invalid state.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-161
ID082919 Non-Confidential
4 Coherence Protocol
4.3 Snoop request types
SnpMakeInvalid Snoop request to Invalidate the cache line at the Snoopee and discard any Dirty copy:
• Does not return data with the Snoop response, Dirty data is discarded.
• See Non-forward and Non-stash Snoop transactions on page 4-183 for permitted
SnpMakeInvalid responses.
• Must change the cache line to Invalid state.
SnpMakeInvalidStash
Snoop request to invalidate the copy of the cache line and recommends that the Snoopee
obtains a copy of the cache line in Unique state:
• Permitted to be sent to only one RN-F.
• Snoopee must not return data with the Snoop response, Dirty data must be discarded.
• See Stash snoop transactions on page 4-188 for the permitted SnpMakeInvalidStash
responses.
• Permits the Snoop response to include a Data Pull if the value of the DoNotDataPull
field in the Snoop request is 0b0.
4-162 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.4 Request types and corresponding snoop requests
Snoop to
Expected Alternative snoop
non-target
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-163
ID082919 Non-Confidential
4 Coherence Protocol
4.4 Request types and corresponding snoop requests
Table 4-3 Request types and the corresponding snoop requests (continued)
Snoop to
Expected Alternative snoop
non-target
The interconnect has the following behavior when generating a snoop request on receipt of a request from an RN:
• This specification supports a snoop filter or directory within the interconnect to track the state of cache lines
present in RN-F caches. The tracking can be as detailed as knowing each RN-F that has a copy of the cache
line, or as nonspecific as knowing that a cache line is present in one of the RN-F caches. Such tracking
permits the ICN to filter unnecessary snooping of an RN-F, for example:
— If the snoop filter indicates that the cache line is not present in any of the RN-F caches, then the
interconnect does not send a snoop request.
— If the cache line in the RN-F caches is already in the required state, for example the received request
is ReadShared and all cached copies of the cache line are in SharedClean (SC) state, then the
interconnect does not send a snoop request.
• It is permitted for the interconnect to generate a snoop request spontaneously without a corresponding request
from an RN. For example, the interconnect can send a SnpUnique or SnpCleanInvalid request as a result of
a backward invalidation from a snoop filter or interconnect cache.
• This specification permits the interconnect to select which snoop request to send. For example:
— For a WriteUniquePtl request, either a SnpCleanInvalid or SnpUnique snoop request can be sent. Both
of these snoop transactions invalidate the cache line and if the cache line is dirty then data is returned
with the response. The write data is written to memory once all Snoop responses are received and the
partial data has been merged with any dirty data received with the Snoop response.
The only difference in the behavior between the SnpCleanInvalid and SnpUnique snoop requests is
that SnpUnique can return data from the UniqueClean (UC) state but SnpCleanInvalid does not. Using
SnpUnique therefore might result in an unnecessary data transfer. This example shows the
disadvantage of using SnpUnique instead of SnpCleanInvalid in certain circumstances.
4-164 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.4 Request types and corresponding snoop requests
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-165
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
AtomicLoad, AtomicSwap, and AtomicCompare Completion is sent on the RDAT channel and uses the CompData
opcode.
The CompData and DataSepResp completion responses include the Resp field that indicates the following:
Cache state The final permitted state of the cache line at the Requester for all reads except ReadNoSnp and
ReadOnce*.
Pass Dirty Indicates if the responsibility for updating memory is passed to the Requester. The assertion of the
Pass Dirty bit is shown by _PD in the response name.
When using separate Comp and Data responses, RespSepData also includes the Resp field with Cache state and Pass
Dirty indications. The Resp field value in RespSepData must be either inapplicable and set to zero or the same as
in the corresponding DataSepResp.
Table 4-4 shows the permitted Read transaction completion, the encoding of the Resp field, and the meaning of the
response. An SN can send DataSepResp only in response to ReadNoSnpSep, it must send CompData in response to
ReadNoSnp.
Table 4-4 Permitted Read transaction completion and Resp field encodings
CompData_I 0b000 Indicates that a coherent copy of the cache line cannot be kept.
DataSepResp_I
RespSepData_I 0b000 Cache state in this response is not applicable. Cache state must
be determined from DataSepResp response.
CompData_UC 0b010 The final state of the cache line can be UC, UCE, SC or I, when
DataSepResp_UC the cache state in the response is applicable.
RespSepData_UC This response is also permitted for ReadNoSnp and ReadOnce*
transactions but the cache line will not be coherent.
Responsibility for a Dirty cache line is not being passed.
4-166 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.5 Response types
Table 4-4 Permitted Read transaction completion and Resp field encodings (continued)
CompData_UD_PD 0b110 The final state of the cache line can be UD or SD.
DataSepResp_UD_PD Responsibility for a Dirty cache line is being passed.
RespSepData_UD_PD
CompData_SD_PD 0b111 The final state of the cache line must be SD.
Responsibility for a Dirty cache line is being passed.
In a response with an error indication, the cache state is permitted to be any value, including reserved values. See
Errors and transaction structure on page 9-282.
The Comp response includes the Resp field that indicates the following:
Cache state The final state the cache line is permitted to be in at the Requester, except for CMO transactions.
For CMO transactions, the cache state field value is ignored and the cache state remains unchanged.
Note
Dataless transactions do not pass responsibility for a Dirty cache line.
Table 4-5 shows the permitted Dataless transaction completion, the encoding of the Resp field, and the meaning of
the response.
Table 4-5 Permitted Dataless transaction completion and Resp field encodings
Comp_UC 0b010 The final state of the cache line can be UC, UCE, SC or I
In a response with an error indication, the cache state is permitted to be any value, including reserved values. See
Errors and transaction structure on page 9-282.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-167
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
No cache state information, or responsibility for a Dirty cache line, is communicated using the Write transaction
completion. The Resp field of a Comp or CompDBIDResp response must be set to zero for a Write transaction
completion. All cache state information and responsibility for a Dirty cache line are communicated with the
WriteData, See WriteData response.
Comp Used when the Completion response is separate from the DBIDResp response.
CompDBIDResp Used when the Completion response is combined with the DBIDResp response.
All CopyBack requests must use the CompDBIDResp completion response.
Non-CopyBack writes and AtomicStore, can either send Comp and DBIDResp responses
separately or can opportunistically combine the Comp and DBIDResp responses and send
CompDBIDResp if both are ready to be sent to the Requester.
The WriteData response is sent on the WDAT channel and uses the following opcodes.
CopyBackWrData
• Used for WriteBack, WriteClean, and WriteEvictFull transactions.
• Transfers coherent data from the cache at the Requester to the interconnect.
• Includes an indication of the cache line state prior to sending the WriteData response.
NonCopyBackWrData
• Used for WriteUnique and WriteNoSnp transactions.
• Also used for a DVMOp transaction.
• The cache state in the response must be I.
NCBWrDataCompAck
• Used for WriteUnique and WriteNoSnp transactions.
• Combined NonCopyBackWrData and CompAck.
• The cache state in the response must be I.
The response includes the Resp field, which indicates the following:
Cache state Indicates the state of the cache line before sending the WriteData response. This state can differ from
the state of the cache line when the original transaction request was sent if a snoop request, to the
same address, is received by the Requester after sending the original transaction request, but before
sending the corresponding WriteData response.
Pass Dirty Indicates if the responsibility for updating memory is passed by the Requester. The assertion of the
Pass Dirty bit is shown by _PD in the response name.
4-168 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.5 Response types
Table 4-6 shows the permitted WriteData responses, the Opcode and Resp field encodings, and the meaning of the
response.
Table 4-6 Permitted WriteData responses and Opcode and Resp field encodings
Note
The cache line state at the Requester after the write transaction has completed is not determined from the cache state
information in the WriteData response. It can be determined if the cache line remains Valid or not after the
transaction by the opcode of the transaction:
• A WriteBack or WriteEvictFull transaction must be in I state.
• A WriteClean transaction can remain allocated and be in a Clean state.
The cache line state associated with a WriteData completion can be any value when the WriteData RespErr field
indicates there is a data error.
A Requester of any RN type can choose to cancel a WriteUniquePtl, WriteUniquePtlStash, or WriteNoSnpPtl after
sending the Write request and before sending the Write data. The DAT channel message WriteDataCancel is used
to inform the Home that the Write request is canceled.
• In WriteNoSnpPtl, WriteUniquePtl and WriteUniquePtlStash transactions, RN must wait for DBIDResp and
must not wait for Comp before sending either non-canceled or canceled Data.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-169
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
The Snoop response includes the Resp field, which indicates the following:
Cache state The final state of the cache line at the snooped node after sending the Snoop response.
Pass Dirty Indicates that the responsibility for updating memory is passed to the Requester or ICN.
Pass Dirty must only be asserted for a Snoop response with data. The assertion of the Pass Dirty bit
is shown by _PD in the response name.
The Snoop response also includes the FwdState field that is applicable in Snoop responses with DCT and indicates
the cache state and pass dirty value in the CompData response sent to the Requester.
These attributes convey sufficient information for the interconnect to determine the appropriate response to the
initial Requester, and to determine if data must be written back to memory. It is also sufficient to support snoop filter
or directory maintenance in the interconnect.
4-170 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.5 Response types
Note
The Snoop response cache state information provides the state of the cache line after the Snoop response is sent.
This is different from:
• A write data response, where the cache state information provides the state of the cache line at the point the
write data is sent.
• A read data response, where the cache state information indicates the permitted state of the cache line after
the transaction completes.
Table 4-7 shows the permitted Non-forward type snoop responses without data, the RSP Opcode and Resp field
encodings, and the meaning of the response.
Table 4-8 shows the permitted Forward type snoop responses without data, the RSP Opcode, Resp, and FwdState
field encodings, and the meaning of the response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-171
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
Table 4-8 Permitted Forward type snoop responses without data (continued)
4-172 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.5 Response types
Table 4-9 shows the permitted Non-forward type snoop responses with data, the DAT Opcode and Resp field
encodings, and the meaning of the response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-173
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
Table 4-10 shows the permitted Forward type snoop responses with data, the DAT Opcode, Resp, and FwdState
field encodings, and the meaning of the response.
4-174 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.5 Response types
Table 4-10 Permitted Forward type snoop responses with data (continued)
The cache line state associated with a Snoop response with data must be a legal value, even if the RespErr field
indicates there is a error.
The cache line state associated with a Snoop response without data is a don't care and can take any value if the
response has an error.
In responses to Stashing snoops, the Snoopee can send a Read request combined with the Snoop response
(SnpResp_X_Read), by setting the DataPull bit. The permitted Snoop responses with Data Pull are:
• For SnpUniqueStash:
— SnpResp_I_Read.
— SnpRespData_I_Read.
— SnpRespData_I_PD_Read.
— SnpRespDataPtl_I_PD_Read.
• For SnpMakeInvalidStash:
— SnpResp_I_Read.
• For SnpStashUnique:
— SnpResp_I_Read.
— SnpResp_UC_Read.
— Snp_Resp_SC_Read.
— SnpResp_SD_Read.
• For SnpStashShared:
— SnpResp_I_Read.
— SnpResp_UC_Read.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-175
ID082919 Non-Confidential
4 Coherence Protocol
4.5 Response types
For all responses in this section the Resp and RespErr fields have no meaning and must be set to zero.
CompAck
• Sent by the Requester on receipt of the Completion response.
• Used by Read, Dataless, and WriteUnique transactions.
See Transaction structure on page 2-39.
RetryAck
• Sent by a Completer to a Requester if the request is not accepted at the Completer due to lack
of appropriate resources.
• Response is permitted for any request transaction except PCrdReturn or PrefetchTgt.
See Transaction Retry sequence on page 2-66.
PCrdGrant
• Grants a Protocol Credit. A subsequent request, sent using the Protocol Credit, is guaranteed
to be accepted by the target.
See Transaction Retry sequence on page 2-66.
ReadReceipt
• Sent for a request that requires Request Order in the interconnect with respect to other
ordered requests from the same Requester.
• Sent by a Slave Node to indicate it has accepted a Read request and will not send a RetryAck
response.
• Applies to ReadNoSnp, ReadNoSnpSep, and ReadOnce* request transactions.
See ReadNoSnp, ReadOnce, ReadOnceCleanInvalid, ReadOnceMakeInvalid on page 2-44.
DBIDResp
• Response sent as part of a write and an Atomic transaction to signal to the Requester that
resources are available to accept the WriteData response.
See Transaction structure on page 2-39.
4-176 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.6 Silent cache state transitions
The legal silent cache state transitions are shown in Table 4-11. In some cases it is possible, but not required, to issue
a transaction to indicate that the transition has occurred. If such a transaction is issued then the cache state transition
is visible to the interconnect and is not classified as a silent transition.
The RN-F action described in Table 4-11 as Local sharing, describes the case where an RN-F specifies a Unique
cache line as Shared, effectively disregarding the fact that the cache line remains Unique to the RN-F. For example,
this can happen when the RN-F contains multiple internal agents and the cache line becomes shared between them.
• Cache eviction and Local sharing transitions can occur at any point and are IMPLEMENTATION DEFINED.
• Store and Cache Invalidate transitions can only occur as the result a deliberate action, which in the case of a
core is caused by the execution of a particular program instruction.
The Notes column in Table 4-11 indicates how a silent cache transition can be made non-silent or visible at the
interface.
Present Next
Local sharing UC SC -
UD SD -
Note
Sequences of silent transitions can also occur. Any silent transition that results in the cache line being in UD, UDP,
or SC state can undergo a further silent transition.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-177
ID082919 Non-Confidential
4 Coherence Protocol
4.7 Cache state transitions at a Requester
The cache state in the Data response to the Requester from the Slave Node is UC, that is, CompData_UC
irrespective of the original request type. The Requester must ignore the cache state in the CompData response to
ReadNoSnp, ReadOnce, ReadOnceCleanInvalid and ReadOnceMakeInvalid and implicitly assume the cache state
value to be I.
Note
In a non-DMT data transfer, where the CompData response is sent from the Slave to Home, the cache state in the
response can be either I or UC, but it is expected that typically a slave design can be simplified by always using UC.
Home then sends CompData to the Requester with the appropriate cache state value.
Table 4-12 Cache state transitions at the Requester for Read request transactions
UC CompData_UC RespSepData +
DataSepResp_UC
4-178 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.7 Cache state transitions at a Requester
Table 4-12 Cache state transitions at the Requester for Read request transactions (continued)
UC CompData_UC RespSepData +
DataSepResp_UC
UD CompData_UD_PD RespSepData +
DataSepResp_UD_PD
UC CompData_UC RespSepData +
DataSepResp_UC
SD CompData_SD_PD -
UD CompData_UD_PD RespSepData +
DataSepResp_UD_PD
UD CompData_UD_PD RespSepData +
DataSepRespUD_PD
Note
• The Other Permitted initial cache states in Table 4-12 on page 4-178 are the cache states that are permitted
while the transaction is in progress.
• For any of the transactions in Table 4-12 on page 4-178, it is legal to use the transaction if the cache line can
silently transition to any Expected or Other Permitted state. This silent transition must occur before the
transaction is issued.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-179
ID082919 Non-Confidential
4 Coherence Protocol
4.7 Cache state transitions at a Requester
Table 4-13 Cache state transitions at the Requester for Dataless request transactions
Initial Final
SC UC UC Comp_UC
SD UD UD Comp_UC
Evict I - I Comp_I
StashOnceUnique I - I Comp
StashOnceShared I - I Comp
Comp_I
CleanInvalid I - I Comp_I
MakeInvalid I - I Comp_I
Before a CleanInvalid, MakeInvalid or Evict transaction it is permitted for the cache state to be UC, UCE or SC.
However, it is required that the cache state transitions to the I state before the transaction is issued. Therefore
Table 4-13 shows I state as the only initial state.
Note
• The Other Permitted initial cache states in Table 4-13 are the cache states that are permitted while the
transaction is in progress.
• For any of the transactions in Table 4-13, it is legal to use the transaction if the cache line can silently
transition to any Expected or Other Permitted state. This silent transition must occur before the transaction
is issued.
4-180 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.7 Cache state transitions at a Requester
Table 4-14 Requester cache state transitions for Write request transactions
UC I CBWrData_UC CompDBIDResp
SC I CBWrData_SC CompDBIDResp
I I CBWrData_I CompDBIDResp
I I CBWrData_I CompDBIDResp
UC UC CBWrData_UC CompDBIDResp
SC SC CBWrData_SC CompDBIDResp
I I CBWrData_I CompDBIDResp
SC I CBWrData_SC CompDBIDResp
I I CBWrData_I CompDBIDResp
a. A snoop might be received while a write is pending and results in a cache line state change before the WriteData response.
b. NCBWrDataCompAck is not permitted prior to CHI Issue D.
c. NCBWrDataCompAck is not permitted prior to CHI Issue C.
Note
After completion of a WriteClean transaction, it is possible for the cache line in a Unique state to immediately
transition to a Dirty state.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-181
ID082919 Non-Confidential
4 Coherence Protocol
4.7 Cache state transitions at a Requester
Table 4-15 Requester cache state transitions for Atomic request transactions
Initial Final
4-182 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
A Snoopee, an RN-F that receives a snoop, performs two actions. One action is a state change of the cached line
and the second action is sending a response message either to the Home, or to both the Home and the Requester.
The cache state change depends on the snoop type, the initial state of the cache line and the value of DoNotGoToSD
in the snoop. See Do not transition to SD on page 4-199.
The Snoopee must send a response to Home either with Data or without Data. In addition, for Forwarding snoops
the Snoopee can also forward a Data response to the Requester.
The type of response sent is determined by the snoop type, initial cache state, cache state change, and the value of
RetToSrc. See Returning Data with Snoop response on page 4-198.
For stash type snoops, the response to the Home also depends on the DoNotDataPull value. See Snoop requests and
Data Pull on page 7-250 and DoNotDataPull on page 12-345.
SnpOnce
Table 4-16 on page 4-184 shows for SnpOnce, the initial, expected final, and other permitted final cache states at
the snooped Requester, the RetToSrc field value, and the valid completion response from a snooped RN-F.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-183
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
Table 4-16 Cache state transitions, RetToSrc value, and valid completion responses
Snoop request type Initial cache state Final cache state RetToSrca Snoop response
Others
Expected
permitted
SnpOnce I I - X SnpResp_I
UC UC I, SC 0 SnpResp_UC
SnpRespData_UC
1 SnpResp_UC
SnpRespData_UC
SC I 0 SnpResp_SC
SnpRespData_SC
1 SnpResp_SC
SnpRespData_SC
I - 0 SnpResp_I
SnpRespData_I
1 SnpResp_I
SnpRespData_I
I - X SnpResp_I
UD UD SD X SnpRespData_UD
SD - X SnpRespData_SD
SC I X SnpRespData_SC_PD
I - X SnpRespData_I_PD
UDP I - X SnpRespDataPtl_I_PD
UDP - X SnpRespDataPtl_UD
SC SC I 0 SnpResp_SC
1 SnpRespData_SC
I - 0 SnpResp_I
1 SnpRespData_I
SD SD - X SnpRespData_SD
SC I X SnpRespData_SC_PD
I - X SnpRespData_I_PD
a. X indicates that the protocol requirements apply for both states of RetToSrc.
4-184 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
Table 4-17 Cache state transitions, RetToSrc value, and valid completion responses
Snoop request type Initial cache state Final cache state RetToSrca Snoop response
Others
Expected
permitted
SnpClean, I I - X SnpResp_I
SnpShared,
UC SC I 0 SnpResp_SC
SnpNotSharedDirty
SnpRespData_SC
1 SnpResp_SC
SnpRespData_SC
I - 0 SnpResp_I
SnpRespData_I
1 SnpResp_I
SnpRespData_I
UCE I - X SnpResp_I
UD SDb - X SnpRespData_SD
SC I X SnpRespData_SC_PD
I - X SnpRespData_I_PD
UDP I - X SnpRespDataPtl_I_PD
SC SC I 0 SnpResp_SC
1 SnpRespData_SC
I - 0 SnpResp_I
1 SnpRespData_I
SD SDb - X SnpRespData_SD
SC I X SnpRespData_SC_PD
I - X SnpRespData_I_PD
a. X indicates that the protocol requirements apply for both states of RetToSrc.
b. This state transition is not permitted if DoNotGoToSD is set.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-185
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpUnique
Table 4-18 shows for SnpUnique, the initial, expected final, and other permitted final cache states at the snooped
Requester, the RetToSrc field value, and the valid completion response from a snooped RN-F for SnpUnique.
Table 4-18 Cache state transitions, RetToSrc value, and valid completion responses
Snoop request type Initial cache state Final cache state RetToSrca Snoop response
Others
Expected
permitted
SnpUnique I I - X SnpResp_I
UC I - 0 SnpResp_I
SnpRespData_I
1 SnpResp_I
SnpRespData_I
UCE I - X SnpResp_I
UD I - X SnpRespData_I_PD
UDP I - X SnpRespDataPtl_I_PD
SC I - 0 SnpResp_I
1 SnpRespData_I
SD I - X SnpRespData_I_PD
a. X indicates that the protocol requirements apply for both states of RetToSrc.
4-186 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
Table 4-19 Cache state transitions, RetToSrc value, and valid completion responses
Snoop request type Initial cache state Final cache state RetToSrc Snoop response
Others
Expected
permitted
SnpCleanShared I I - 0 SnpResp_I
UC UC I, SC 0 SnpResp_UC
SC I 0 SnpResp_SC
I - 0 SnpResp_I
UCE I - 0 SnpResp_I
SnpCleanShared UD UC I, SC 0 SnpRespData_UC_PD
SC I 0 SnpRespData_SC_PD
I - 0 SnpRespData_I_PD
UDP I - 0 SnpRespDataPtl_I_PD
SC SC I 0 SnpResp_SC
I - 0 SnpResp_I
SD SC I 0 SnpRespData_SC_PD
I - 0 SnpRespData_I_PD
SnpCleanInvalid I I - 0 SnpResp_I
UC I - 0 SnpResp_I
UCE I - 0 SnpResp_I
UD I - 0 SnpRespData_I_PD
UDP I - 0 SnpRespDataPtl_I_PD
SC I - 0 SnpResp_I
SD I - 0 SnpRespData_I_PD
SnpMakeInvalid I I - 0 SnpResp_I
UC I - 0 SnpResp_I
UCE I - 0 SnpResp_I
UD I - 0 SnpResp_I
UDP I - 0 SnpResp_I
SC I - 0 SnpResp_I
SD I - 0 SnpResp_I
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-187
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
The RetToSrc bit value must not be set to 1 in SnpUniqueStash and SnpMakeInvalidStash.
A Snoop response can include Data Pull only if the DoNotDataPull in the Snoop request is deasserted.
Table 4-20 shows the Snoopee cache state transitions and required Snoop responses. The Snoop responses do not
include the Data Pull options. Data Pull is permitted with any Snoop response.
Initial Final
Others
Expected
permitted
SnpUniqueStash I I - 0 SnpResp_I
UC I - 0 SnpRespData_I
SnpResp_I
UCE I - 0 SnpResp_I
UD I - 0 SnpRespData_I_PD
UDP I - 0 SnpRespDataPtl_I_PD
SC I - 0 SnpResp_I
SnpRespData_I
SD I - 0 SnpRespData_I_PD
4-188 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
The Snoopee is permitted to not perform a cache lookup before responding, in which case the Snoop response must
be SnpResp_I.
The Snoopee is permitted to include the precise cache state in the response.
A Snoop response can include Data Pull only if the cache state in the response is precise and DoNotDataPull in the
corresponding Snoop request is deasserted.
The inclusion of Data Pull in the Snoop response must ensure that the initial state must not violate the initial state
conditions permitted for the corresponding independent Read requests. See Read transactions on page 4-145.
Table 4-21 shows the Snoopee cache state transitions, the required Snoop responses, and Data Pull options for
SnpStashUnique.
Initial Final
Others
Expected
permitted
SnpStashUnique I I - 0 SnpResp_I
SnpResp_I_Read
UC UC - 0 SnpResp_UC
SnpResp_I
SnpResp_UC_Read
SnpResp_I
UD UD - 0 SnpResp_UD
SnpResp_I
SnpResp_I
SC SC - 0 SnpResp_SC
SnpResp_SC_Read
SnpResp_I
SD SD - 0 SnpResp_SD
SnpResp_SD_Read
SnpResp_I
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-189
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
Table 4-22 shows the Snoopee cache state transitions, the required Snoop responses, and Data Pull options for
SnpStashShared.
Initial Final
Others
Expected
permitted
SnpStashShared I I - 0 SnpResp_I_Read
SnpResp_I
UC UC - 0 SnpResp_UC
SnpResp_I
SnpResp_UC_Read
SnpResp_I
UD UD - 0 SnpResp_UD
SnpResp_I
SnpResp_I
SC SC - 0 SnpResp_SC
SnpResp_I
SD SD - 0 SnpResp_SD
SnpResp_I
4-190 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
• Must forward a copy to the Requester if the cache line is in one of the following states:
— UD.
— UC.
— SD.
— SC.
• Must not forward data in Unique state in response to a Non-invalidating type snoop.
• Snoopee receiving a Snoop request with the DoNotGoToSD bit set must not transition to SD, even if the
coherency conditions permit it.
• In certain cases, based on the Snoop type, the state of the cache line at the Snoopee, and the RetToSrc value
in the Snoop request, the Snoopee forwards a copy to Home along with a copy to the Requester.
For the rules that are specific to a particular Fwd type snoop see the following individual sub-sections.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-191
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpOnceFwd
The rules, in addition to the common rules, to be followed by a Snoopee that receives a SnpOnceFwd are:
• Snoopee must forward the cache line in I state.
— As a consequence, the Snoopee must not forward Pass Dirty to the Requester.
• Snoopee must return data to Home only when Dirty state is changed to Clean or Invalid.
• RetToSrc bit in the snoop must be set to zero.
• Snoopee can ignore the DoNotGoToSD value in the snoop.
Table 4-23 shows the Snoopee cache state transition and required Snoop responses for SnpOnceFwd.
Other
Expected
permitted
I I - 0 No Fwd SnpResp_I
UC UC - 0 CompData_I SnpResp_UC_Fwded_I
SC I 0 CompData_I SnpResp_SC_Fwded_I
I - 0 CompData_I SnpResp_I_Fwded_I
I - 0 No Fwd SnpResp_I
UD UD - 0 CompData_I SnpResp_UD_Fwded_I
SD - 0 CompData_I SnpResp_SD_Fwded_I
SC I 0 CompData_I SnpRespData_SC_PD_Fwded_I
I - 0 CompData_I SnpRespData_I_PD_Fwded_I
I - 0 No Fwd SnpRespDataPtl_I_PD
SC SC I 0 CompData_I SnpResp_SC_Fwded_I
I - 0 CompData_I SnpResp_I_Fwded_I
SD SD - 0 CompData_I SnpResp_SD_Fwded_I
SC I 0 CompData_I SnpRespData_SC_PD_Fwded_I
I - 0 CompData_I SnpRespData_I_PD_Fwded_I
4-192 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpCleanFwd
The rules, in addition to the common rules, to be followed by a Snoopee that receives a SnpCleanFwd are:
• Snoopee must forward the cache line in SC state.
• Snoopee must transition to either SD, SC or I state.
• For behavior related to the RetToSrc bit see Returning Data with Snoop response on page 4-198.
Table 4-24 shows the Snoopee cache state transitions and required Snoop responses for SnpCleanFwd.
Other
Expected
permitted
I I - Xa No Fwd SnpResp_I
UC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - Xa CompData_SC SnpRespData_I_PD_Fwded_SC
SC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - Xa CompData_SC SnpRespData_I_PD_Fwded_SC
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-193
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpNotSharedDirtyFwd
The rules, in addition to the common rules, to be followed by a Snoopee that receives a SnpNotSharedDirtyFwd are:
• Snoopee must forward the cache line in SC state.
• Snoopee must transition to SD, SC or I state.
• For behavior related to the RetToSrc bit see Returning Data with Snoop response on page 4-198.
Table 4-25 shows the Snoopee cache state transitions and required Snoop responses for SnpNotSharedDirtyFwd.
Other
Expected
permitted
I I - Xa No Fwd SnpResp_I
UC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - Xa CompData_SC SnpRespData_I_PD_Fwded_SC
SC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - Xa CompData_SC SnpRespData_I_PD_Fwded_SC
4-194 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpSharedFwd
The rules, in addition to the common rules, to be followed by a Snoopee that receives a SnpSharedFwd are:
• Snoopee is permitted to forward the cache line in either SD or SC state.
• Snoopee must transition to either SD, SC or I state.
• For behavior related to the RetToSrc bit see Returning Data with Snoop response on page 4-198.
Table 4-26 shows the Snoopee cache state transition and required Snoop responses for SnpSharedFwd.
Other
Expected
permitted
I I - Xa No Fwd SnpResp_I
UC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I 0 CompData_SD_PD SnpResp_SC_Fwded_SD_PD
1 CompData_SD_PD SnpRespData_SC_Fwded_SD_PD
Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - 0 CompData_SD_PD SnpResp_I_Fwded_SD_PD
1 CompData_SD_PD SnpRespData_I_Fwded_SD_PD
Xa CompData_SC SnpRespData_I_PD_Fwded_SC
SC SC I 0 CompData_SC SnpResp_SC_Fwded_SC
1 CompData_SC SnpRespData_SC_Fwded_SC
I - 0 CompData_SC SnpResp_I_Fwded_SC
1 CompData_SC SnpRespData_I_Fwded_SC
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-195
ID082919 Non-Confidential
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
Other
Expected
permitted
1 CompData_SC SnpRespData_SD_Fwded_SC
SC I 0 CompData_SD_PD SnpResp_SC_Fwded_SD_PD
1 CompData_SD_PD SnpRespData_SC_Fwded_SD_PD
Xa CompData_SC SnpRespData_SC_PD_Fwded_SC
I - 0 CompData_SD_PD SnpResp_I_Fwded_SD_PD
1 CompData_SD_PD SnpRespData_I_Fwded_SD_PD
Xa CompData_SC SnpRespData_I_PD_Fwded_SC
4-196 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.8 Cache state transitions at a Snoopee
SnpUniqueFwd
Use of the SnpUniqueFwd snoop is only permitted if the cache line is cached at a single RN-F:
• Home is permitted to send the SnpUniqueFwd snoop to an RN-F in Shared state if Home determines that the
invalidating snoop needs to be sent to only one cache.
The rules, in addition to the common rules, to be followed by a Snoopee that receives a SnpUniqueFwd are:
• Snoopee must forward the cache line in Unique state.
• Snoopee that has the cache line in Dirty state must Pass Dirty to the Requester not to Home.
• Snoopee must transition to I state.
• Snoopee must not return data to Home.
• RetToSrc bit in the snoop must be set to zero.
Table 4-27 shows the Snoopee cache state transitions and required Snoop responses for SnpUniqueFwd.
Other
Expected
permitted
I I - 0 No Fwd SnpResp_I
UC I - 0 CompData_UC SnpResp_I_Fwded_UC
UD I - 0 CompData_UD_PD SnpResp_I_Fwded_UD_PD
SC I - 0 CompData_UC SnpResp_I_Fwded_UC
SD I - 0 CompData_UD_PD SnpResp_I_Fwded_UD_PD
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-197
ID082919 Non-Confidential
4 Coherence Protocol
4.9 Returning Data with Snoop response
For Non-forwarding snoops, except SnpMakeInvalid, the rules for returning a copy of the cache line to the Home
are:
• Irrespective of the value of RetToSrc, must return a copy if the cache line is Dirty.
• Irrespective of the value of RetToSrc, optionally can return a copy if the cache line is Unique Clean.
• If the RetToSrc value is 1, must return a copy if the cache line is Shared Clean and the Snoopee retains a copy
of the cache line.
• If the RetToSrc value is 0, must not return a copy if the cache line is Shared Clean.
For forwarding snoops, the rules for returning a copy of the cache line to the Home are:
• Irrespective of the value of RetToSrc, must return a copy if a Dirty cache line cannot be forwarded or kept.
• If the RetToSrc value is 1, must return a copy if the cache line is Dirty or Clean.
• If the RetToSrc value is 0, must not return a copy if the cache line is Clean.
RetToSrc is applicable and can take any value in all other snoops except SnpDVMOp.
Home must only set RetToSrc on the Snoop request to a single Request Node.
4-198 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.10 Do not transition to SD
It specifies that the Snoopee must not transition to SD state as a result of the Snoop request.
Note
• A non-forced change or silent change from UD to SD is permitted irrespective of the value of
DoNotGoToSD.
• Any forced change from Unique to Shared must obey DoNotGoToSD.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-199
ID082919 Non-Confidential
4 Coherence Protocol
4.11 Hazard conditions
In addition to many Requesters issuing transactions at the same time, the protocol also permits each Requester to
make multiple outstanding requests, and to receive multiple outstanding snoop requests. It is the responsibility of
the interconnect, that is, ICN(HN-F, HN-I and MN), to ensure that there is a defined order in which transactions to
the same cache line can occur, and that the defined order is the same for all components.
If a pending request to the same cache line is present at the RN-F and the pending request has not received any Data
response packets:
• The cache state must transition as applicable for each snoop request type.
• The cached data or CopyBack request data must be returned with the snoop response, or forwarded to the
Requester, if required by the Snoop request type, Snoop request attributes, and cache state.
If a pending request to the same cache line is present at the RN-F and the pending request has received at least one
Data response packet:
• The RN-F must wait to receive all Data response packets before responding to the Snoop request.
If the pending request is a CopyBack request then the following additional requirements apply:
• The cache state in the WriteData response must be the state of the cache line after the snoop request is
processed, not the state at the time of sending the CopyBack request.
• An RN is permitted to not send valid CopyBack Data, if the cache line state after the Snoop response is sent
is I or SC. The cache state in the WriteData response, after CopyBack Data is taken away by the snoop, must
be I and all byte enables must be deasserted and the corresponding data must be set to zero.
• If data is included with WriteData it must be the same data that as sent with the Snoop response or more up
to date data.
Note
More recent data than that sent with the snoop response can only be provided if the snoop was a SnpOnce,
SnpOnceFwd, or SnpCleanShared and the Snoop response indicates that the cache line can be further
modified.
For non-ordered transactions, the RN can send CompAck without waiting for DataSepResp. For ordered
transactions, the RN can send CompAck as soon as the first packet of DataSepResp is received. In both cases, an
RN must not respond to a Snoop request before receiving all data packets.
4-200 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
4 Coherence Protocol
4.11 Hazard conditions
The RN-F might receive multiple snoop requests before it receives a response for a pending CopyBack request for
the same cache line, in which case the data response carries the cache line state after completion of the response to
the last snoop request. Such a scenario is possible because the CopyBack request can be queued behind multiple
Read and Dataless requests at the HN-F.
If a Response message that includes data requires multiple packets or beats of transfers over the interconnect, then
receiving or sending the message by Home implies sending or receiving all the packets corresponding to that
message. That is, when a Home starts sending the message, it must send all packets of the message without
dependence on completion of any other Request or Response message.
Similarly, a Home, when it accepts part of the data message, must accept the remaining packets of that message
without any dependence on forward progress of any other Request or Response message.
When a subsequent forwarding of data depends upon receiving a Data message, the forwarding of data action can
occur after receiving the first Data packet. A subsequent non-data forwarding action that is processing of a
subsequent request at Home as a consequence of sending or receiving of data by Home, must wait until all data is
sent or received.
While a Snoop transaction response is pending, the only transaction responses that are permitted to be sent to the
same address are:
• RetryAck for a CopyBack.
• RetryAck and DBIDResp for a WriteUnique and Atomics.
• RetryAck and, if applicable, a ReadReceipt for a Read request type.
• RetryAck for a Dataless request type.
Once a completion is sent for a transaction, the HN-F must not send a snoop request to the same cache line until it
receives:
• A CompAck for any Read and Dataless requests except for ReadOnce* and ReadNoSnp.
• A WriteData response for CopyBack and Atomic requests.
• For WriteUnique, a WriteData response and, if applicable, CompAck.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 4-201
ID082919 Non-Confidential
4 Coherence Protocol
4.11 Hazard conditions
4-202 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 5
Interconnect Protocol Flows
This chapter shows interconnect protocol flows for different transaction types, and interconnect hazard conditions.
The protocol flows are illustrated using Time-Space diagrams. It contains the following sections:
• Read transaction flows on page 5-204.
• Dataless transaction flows on page 5-215.
• Write transaction flows on page 5-219.
• Atomic transaction flows on page 5-222.
• Stash transaction flows on page 5-229
• Hazard handling examples on page 5-232.
See Time-Space diagrams on page xiii for details of the conventions used to illustrate protocol flow in this
specification.
• If the HN-F receives multiple data responses, that is, one response from a snooped RN-F and another from a
SN-F, then the data being forwarded to the Requester is highlighted in bold.
• There is no ICN cache at the HN-F, this results in all requests to the HN-F initiating a request to the SN-F.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-203
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
Figure 5-1 shows an example DMT transaction flow using the ReadShared transaction.
In this example a response from SN-F to HN-F is not required because CompAck from the Requester is used to
deallocate the request at Home.
4. RN-F sends CompAck to HN-F as the Request is ReadShared and requires CompAck to complete the
transaction.
ReadShared
ReadNoSnp
CompData_UC
UC
CompAck
5-204 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.1 Read transaction flows
Figure 5-2 shows an example DMT transaction flow using the ReadShared transaction.
In this example a response from SN-F to HN-F is not required because CompAck from the Requester is used to
deallocate the request at Home.
3. HN-F sends a Read request to SN-F after receiving the Snoop response from RN-F1, which guarantees that
RN-F1 has not responded with data.
• The ID field values in the Read request are based on where the Data response is to be sent. Data can
be sent to the Requester or to the HN-F. See Figure 2-24 on page 2-78 that shows an example of how
the ID field values are derived.
5. RN-F0 sends CompAck to HN-F as the Request is ReadShared and requires CompAck to complete the
transaction.
ReadShared
SnpShared
SnpResp_I
ReadNoSnp
CompData_UC
UC
CompAck
Figure 5-2 DMT Read transaction example with snoops and data from memory
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-205
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
6. After receiving the CompData response RN-F0 sends a CompAck response to HN-F to conclude the
transaction.
Note
Steps 4 and 5 in the DCT transaction flow can occur in any order as CompData and SnpResp are sent on different
channels.
5-206 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.1 Read transaction flows
ReadShared
(TxnID = A)
SnpSharedFwd
(FwdNID = RN-F0)
(FwdTxnID = A)
(TxnID = B)
UC->SC
CompData_SC
(HomeNID = HN-F) SnpResp_SC_Fwded_SC
(TxnID = A) (TxnID = B)
(DBID = B)
I->SC
CompAck
(TgtID = HN-F)
(TxnID = B)
5. RN-F1 also sends a SnpRespData_SC_PD_Fwded_SC Snoop response to HN-F that includes a copy of the
cache line and passes responsibility for the Dirty cache line to HN-F:
• The data was forwarded to the Requester.
• The final state of the cache line in the snooped cache is SC.
• The state in which the cache line can be cached at the Requester is SC.
6. The RN-F0 sends CompAck after it receives the Data response to conclude the transaction.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-207
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
ReadShared
SnpSharedFwd
UD->SC
CompData_SC SnpRespData_SC_PD_Fwded_SC
I->SC WriteNoSnp
CompAck
CompDBIDResp
NCBWriteData
5-208 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.1 Read transaction flows
The request does not generate any snoops and receives the data from a response to a memory read by the HN-F. The
steps in the ReadNoSnp transaction flow are:
1. RN-F0 issues a ReadNoSnp transaction.
2. HN-F receives and allocates the request.
Note
HN-F does not send snoops as the request is recognized as a Non-snoopable request type.
Figure 5-5 shows the transaction flow, the copy of data being transferred is marked in bold.
ReadNoSnp
ReadNoSnp
CompData_I
CompData_I
I->I
CompAck
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-209
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
5.1.5 Read transaction with snoop response with partial data and no memory update
An example of this type of flow is a ReadUnique transaction.
RN-F1 has the cache line in UDP state. RN-F1 responds to the snoop with a snoop response with partial cache line
data and passes responsibility for updating memory.
HN-F waits for the data response from memory, merges the partial snoop response data with the data response from
memory, and sends the resultant data to the Requester.
HN-F does not update memory because responsibility for updating memory is passed on to the Requester.
Figure 5-6 shows the transaction flow, the copy of data being transferred is marked in bold.
ReadUnique
ReadNoSnp
SnpUnique
SnpUnique
UDP->I
SnpRespDataPtl_I_PD SnpResp_I
CompData_I
Merge
data
CompData_UD_PD
I->UD
CompAck
5-210 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.1 Read transaction flows
5.1.6 Read transaction with snoop response with partial data and memory update.
An example of this type of flow is a ReadClean transaction.
RN-F1 has the cache line in UDP state. RN-F1 responds to the snoop with a snoop response with partial cache line
data and passes responsibility for updating memory.
HN-F waits for the data response from memory, merges the partial snoop response data with the data response from
memory, and sends the resultant data to the Requester.
HN-F updates memory as the responsibility for updating memory is not passed on to the Requester.
Figure 5-7 shows the transaction flow, the copy of data being transferred is marked in bold.
ReadClean
ReadNoSnp
SnpClean
SnpClean
UDP->I
SnpResp_I
SnpRespDataPtl_I_PD CompData_I
WriteNoSnp
CompData_UC Merge
data
I->UC
CompAck
CompDBIDResp
NCBWrData
NCBWrData = NonCopyBackWrData
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-211
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
ReadOnce
(ExpCompAck = 0)
(Order[1:0] = 0b00)
ReadNoSnp
(Order[1:0] = 0b01)
ReadReceipt
CompData_UC
Note
Use of a ReadNoSnp transaction from Home to Slave, in the case where CompAck is not required, avoids the need
to send a RespSepData response from Home to Requester.
5-212 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.1 Read transaction flows
5.1.8 ReadNoSnp transaction with DMT and separate Non-data and Data-only
Figure 5-9 shows an example DMT transaction flow with separate Non-data and Data-only.
In this example there is no ordering requirement and RN-F can send CompAck to HN-F to deallocate the request at
Home without waiting for DataSepResp.
ReadNoSnp
(ExpCompAck = 1)
(Order[1:0] = 0b00)
ReadNoSnpSep
RespSepData
ReadReceipt
CompAck
DataSepResp
Figure 5-9 DMT Read transaction example with separate Non-data and Data-only
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-213
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.1 Read transaction flows
5.1.9 ReadNoSnp transaction with DMT with ordering and separate Non-data and Data-only
Figure 5-10 shows an example DMT transaction flow with ordering and separate Non-data and Data-only.
This example, which has ReadNoSnp with non-zero Order field requires that:
• Next ordered request can be sent only after receiving of RespSepData.
• RN-F must wait for RespSepData and at least one packet of DataSepResp before sending CompAck.
• HN-F must not send next ordered request to SN-F until it receives CompAck.
ReadNoSnp
(ExpCompAck = 1)
(Order[1:0] = 0b10)
ReadNoSnpSep
(Order[1:0] = 0b01)
RespSepData
ReadReceipt
DataSepResp
CompAck
Figure 5-10 DMT Read transaction example with ordering and separate Non-data and Data-only
5-214 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.2 Dataless transaction flows
RN-F1 has the cache line in UC state. RN-F1 responds to the snoop with a snoop response without data and changes
the cache line state to I.
HN-F waits for all snoop responses and then sends a Comp_UC response to the Requester.
HN-F does not send a read request to SN-F because the request is a Dataless transaction.
MakeUnique
SnpMakeInvalid
SnpMakeInvalid
UC->I
SnpResp_I SnpResp_I
Comp_UC
I->UC
CompAck
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-215
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.2 Dataless transaction flows
RN-F1 has the cache line in SD state and responds to the snoop with a snoop response with data and PD asserted.
HN-F waits for all snoop responses and then sends a Comp_UC response to the Requester.
HN-F sends a write request to update memory with the data received from RN-F1.
CleanUnique
SnpCleanInvalid
SnpCleanInvalid
SD->I
SnpRespData_I_PD
SnpResp_I
WriteNoSnp
CompDBIDResp
Comp_UC
NCBWrData
SC->UC
CompAck
NCBWrData = NonCopyBackWrData
5-216 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.2 Dataless transaction flows
5.2.3 Persistent CMO with snoop and separate Comp and Persist
In this example of CleanSharedPersistSep transaction flow, the Point of Persistence (PoP) is at the SN-F.
RN-F1 has the cache line in SC state. RN-F1 responds to the snoop with a snoop response without data.
HN-F waits for all snoop responses and then sends a Comp_SC response to the Requester.
HN-F sends a CleanSharedPersistSep request to SN-F, only after completing the writing back of all snooped Dirty
data, if any, to the SN-F. SN-F responds to the request with Comp.
SNF sends a Persist response to RN-F0 to indicate that the request has reached the PoP, and data from any prior
writes to the same location is pushed to the PoP.
CleanSharedPersistSep
SnpCleanShared
SnpResp_SC
CleanSharedPersistSep
Comp_SC
Comp
Persist
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-217
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.2 Dataless transaction flows
RN-F0 moves the cache line to I state and issues an Evict transaction.
Note
The Evict request is a hint. A Comp response can be given by HN-F without updating the Snoop Filter or Snoop
Directory.
UC->I
Evict
Update
Snoop Filter or
Snoop Directory
Comp_I
Note
The cache state at the Requester must change to Invalid before the Evict message is sent.
5-218 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.3 Write transaction flows
6. RN-F0 waits for Comp from HN-F and deallocates its request.
Figure 5-15 shows the flow, the copy of data being transferred is marked in bold.
WriteNoSnp
DBIDResp
WriteNoSnp
NCBWrData
CompDBIDResp
NCBWrData
Comp
NCBWrData = NonCopyBackWrData
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-219
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.3 Write transaction flows
The Comp_I response from HN-F must be sent when the coherency activity is complete at HN-F.
Figure 5-16 shows the transaction flow, the copy of data being transferred is marked in bold.
WriteUniquePtl
SnpCleanInvalid
SnpCleanInvalid
DBIDResp
UD->I
SnpRespData_I_PD
SnpResp_I
NCBWrData
Merge
data
WriteNoSnp
Comp
CompDBIDResp
NCBWrData
NCBWrData = NonCopyBackWriteData
5-220 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.3 Write transaction flows
The data received from RN-F0 is written to SN-F by HN-F using a WriteNoSnp transaction.
Figure 5-17 shows the transaction flow, the copy of data being transferred is marked in bold.
WriteBackFull
CompDBIDResp
UD->I
CBWrData_UD_PD
WriteNoSnp
CompDBIDRresp
NCBWrData
CBWrData = CopyBackWrData
NCBWrData = NonCopyBackWrData
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-221
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
3. RN-F2 has the cache line in UD state and responds by sending data and invaliding its own cached copy.
• The response is SnpRespData_I_PD.
• This data is marked as (Old_Data) in Figure 5-18 on page 5-223 to distinguish it from both the data
sent by the Requester and the data written to SN-F after the atomic operation is executed.
• HN-F also receives a second Snoop response, SnpResp_I, from RN-F1.
4. After receiving all Snoop responses, HN-F sends CompData_I to the Requester.
• The data sent with Comp is the old copy of the data.
• This data must not be cached in a coherent state at RN-F0.
5. In response to the DBIDResp sent previously, HN-F receives the NonCopyBackWrData_I response from the
Requester.
• This data is marked as (Txn_Data) in Figure 5-18 on page 5-223 to distinguish it from the data sent by
RN-F2 in response to the Snoop request from HN-F,
6. Once HN-F receives the NonCopyBackWrData_I response from the Requester, and the Snoop response with
data from RN-F2, it executes the atomic operation.
7. The resulting value after atomic operation execution, marked as New_Data in the figure, is written to SN-F.
8. In this example, the read data received due to the speculative read is discarded by HN-F.
5-222 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
AtomicLoad
AtomicSwap
AtomicCompare
Speculative
Read
SnpUnique
ReadNoSnp
SnpUnique UD->I
DBIDResp
RespData_I
SnpResp_I SnpRespData_I_PD
(Old_Data)
NCBWrData
(Txn_Data)
Executes
Atomic operation
CompData_I WriteNoSnp
(Old_Data)
CompDBIDResp
NCBWrData
(New_Data)
NCBWrData = NonCopyBackWrData
Note
In Figure 5-18, the CompData_I response from HN-F can be sent as soon as all Snoop responses are received.
Alternatively, to aid error reporting, CompData_I can be delayed until NCBWrData is received from the Requester
and the atomic operation is executed.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-223
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
RN RN-F1 RN-F2 HN SN
I I I
AtomicLoad
AtomicSwap
AtomicCompare
ReadNoSnp
RespData_I
DBIDResp (Old_Data)
NCBWrData
(Txn_Data)
Executes
Atomic operation
CompData_I
(Old_Data) WriteNoSnp
CompDBIDResp
NCBWrData
(New_Data)
NCBWrData = NonCopyBackWrData
5-224 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
AtomicStore
SnpUnique
SnpUnique
DBIDResp
UD->I
SnpRespData_I_PD
SnpResp_I (Old_Data)
NCBWrData
(Txn_Data)
Executes
Atomic operation
WriteNoSnp
Comp
CompDBIDResp
NCBWrData
(New_Data)
NCBWrData = NonCopyBackWrData
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-225
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
RN RN-F1 RN-F2 HN SN
I I UD
AtomicStore
ReadNoSnp
DBIDResp
Comp RespData_I
(Old_Data)
NCBWrData
(Txn_Data)
Executes
Atomic operation
WriteNoSnp
CompDBIDResp
NCBWrData
(New_Data)
NCBWrData = NonCopyBackWrData
Note
• In Figure 5-21, the read from SN is required to obtain the Old_Data and is not speculative.
• The Comp response from HN can be combined with the DBIDResp response.
5-226 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
3. RN-F2 has the cache line in UD state and responds by sending data and invaliding its own cached copy.
• The response is SnpRespData_I_PD.
• This data is marked as (Old_Data) in Figure 5-22 on page 5-228 to distinguish it from both the data
sent by the Requester and the data written to SN-F after the atomic operation is executed.
• HN-F also receives a second Snoop response, SnpResp_I, from the other snooped RN-F.
5. In response to the DBIDResp sent previously, HN-F receives the NonCopyBackWrData response from the
Requester.
6. HN-F after sending the Snoop response data to SN-F, sends an AtomicStore transaction request to SN-F, and
executes the sequence of messages required to complete the Atomic transaction.
7. The HN-F deallocates the request once the Comp response is sent to the Requester and the Comp response
for the Atomic transaction is received from SN-F.
• The Comp response from HN-F can be sent as soon as all the Snoop responses are received.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-227
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.4 Atomic transaction flows
AtomicStore
(Normal, Snoopable)
DBIDResp
SnpUnique
SnpUnique
UD->I
SnpRespData_I_PD
(Old_Data)
NCBWrData
SnpResp_I
(Txn_Data)
WriteNoSnp
Comp CompDBIDResp
NCBWrData
(Old_Data)
AtomicStore
DBIDResp
NCBWrData
(Txn_Data)
Comp
NCBWrData = NonCopyBackWrData
5-228 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.5 Stash transaction flows
1. RN sends a WriteUniqueFullStash request to HN-F with the Stash target identified as RN-F1. Typically, the
reqesting RN is an RN-I.
3. RN-F1 and RN-F2 send SnpResp response to HN-F. The Snoop response from RN-F1 also includes a Read
request, that is, the Data Pull.
4. HN-F treats the Read request from RN-F1 as a ReadUnique, and sends a combined CompData to RN-F1.
CompData response includes the data written by RN.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-229
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.5 Stash transaction flows
WriteUniqueFullStash
(StashNID = RN-F1)
DBIDResp
SnpMakeInvalidStash SnpUnique
SC->I
SnpResp_I
SnpResp_I_Read
NCBWrData
Comp_I
CompData_UD_PD
CompAck
NCBWrData = NonCopyBackWriteData
1. RN sends a StashOnceShared request to HN-F with the Stash target identified as RN-F1.
2. HN-F sends a Comp response after establishing processing order for the received request that is guaranteeing
the request is processed before a request to the same address received later from any Requester.
3. HN-F sends a SnpStashShared snoop to RN-F1, and a ReadNoSnp request to SN-F to fetch Data.
5. HN-F treats the Read request from RN-F1 as a ReadNotSharedDirty, and sends a combined CompData to
RN-F1.
5-230 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.5 Stash transaction flows
StashOnceShared
(StashNID = RN-F1)
ReadNoSnp
SnpStashShared
SnpResp_I_Read
Comp
CompData_I
CompData_UC
I->UC
CompAck
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-231
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.6 Hazard handling examples
1. At time C:
• The SnpShared transaction ignores the hazard and reads the cache line data.
• The cache line state is changed from UD to SC.
2. At time D:
• The CompDBIDResp for the CopyBack is sent to RN-F0.
• RN-F0 sends back a CopyBackWrData_SC response.
• The cache line state is changed from SC to I.
The data is clean for coherence and is not required to be sent to the interconnect for correct functionality.
However, the protocol requires the CopyBack flow to be consistent irrespective of a snoop hazard.
The cache line state in the WriteData response is SC because that is the state of the cache line when the
WriteData response is sent.
5-232 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.6 Hazard handling examples
SnpShared
UD->SC Hazard detected
C Req2 progress
blocked
SnpRespData_SC_PD
Hazard with
CopyBack detected
but ignored
CompData_SC
I->SC
CompAck
B
SC->I
CompDBIDResp
D
CopyBackWrData_SC Req2 progress
(PS = SC, NS(implied) = I) un-blocked
CopyBack
Completed with a
WriteData response
PS = PresentState
NS = NextState
Note
• The response to a snoop request that hazards with an outstanding Evict must be SnpResp_I.
• During the period between receiving a snoop request and sending a snoop response, including data if
applicable, while a CopyBack request to the same address is pending, the only response that can be received
for the CopyBack request is a RetryAck.
Figure 5-26 on page 5-234 shows a further example of a snoop request hazarding with an outstanding CopyBack
request. In this example, the snoop request is a SnpOnce request generated as a result of a ReadOnce request from
RN-F1. The SnpOnce request receives a copy of the data with the snoop response but does not change the cache
line state. In this case, the final data response from RN-F0 indicates that the data is Dirty and that HN-F must write
the data back to memory.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-233
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.6 Hazard handling examples
UD I
ReadOnce
WriteBack
SnpOnce
UD->UD
Hazard detected
SnpRespData_UD WriteBack progress
Hazard detected blocked
but ignored
CompData_I
CompAck
ReadOnce
does not
write back
Data
WriteBack progress
CompDBIDResp
un-blocked
UD->I
CBWrData_UD
(PS=UD, NS[implied]=I)
CopyBack WrNoSnp
Completed with a
WriteData response
PS = PresentState
NS = NextState
5-234 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.6 Hazard handling examples
Figure 5-27 on page 5-236 shows an example where a ReadShared and a ReadUnique, for the same cache line,
arrive at the HN-F at approximately the same time. The steps required to resolve this hazard are:
1. At time A:
• ReadUnique from RN-F0 arrives and hazards a ReadShared request from RN-F2 for which the HN-F
has already sent snoop requests.
• ReadUnique progress is blocked at the HN-F.
2. At time B:
• The HN-F has completed the ReadShared transaction request from RN-F2.
• The ReadShared transaction is considered to be complete and the HN-F unblocks the ReadUnique
transaction request from RN-F0.
With the exception of ReadNoSnp, the flows will be similar if the two transactions, that Figure 5-27 on page 5-236
shows, are replaced by any Read request type, or Dataless request type:
• A Read transaction request without DMT or DCT or separate Comp and Data response is completed at the
HN-F when both of the following are true:
— All CompData is sent and, if applicable, CompAck is received. A CompAck is only required for
transactions that assert ExpCompAck in the original Request message.
— A memory update is completed if required.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-235
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.6 Hazard handling examples
SC I I
Req1: ReadShared
Req2: ReadUnique
ReadNoSnp
A
Hazard detected
Req2 progress
SnpShared SnpShared blocked
SnpResp_SC
SnpResp_I
CompData_I
CompData_SC
I->SC
CompAck Req2 progress
un-blocked
B
SnpUnique ReadNoSnp
SnpUnique
SnpResp_I SC->I
SnpResp_I
CompData_I
CompData_UC
SC->UC
CompAck
5-236 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
5 Interconnect Protocol Flows
5.6 Hazard handling examples
Figure 5-28 on page 5-238 shows the case where a ReadShared and a WriteBack, for the same cache line, arrive at
the HN-F at approximately the same time. The steps required to resolve this hazard are:
1. At time A:
• A WriteBack encounters a hazarding condition at the HN-F. The reason for the hazard is a ReadShared
transaction that is already in progress.
• The hazard detection results in the WriteBack being blocked.
• The ReadShared transaction receives data with the snoop response and needs to update memory in
addition to sending the data to the Requester.
2. At time B:
• The WriteBack is unblocked because the HN-F has sent the Data response to the Requester and a
WriteData response to memory for the ReadShared transaction.
If the ReadShared request reaches the HN-F, after the HN-F has started processing the WriteBack request, then the
ReadShared request will be blocked until completion of the WriteBack request.
A CopyBack request is completed at HN-F when both of the following are true:
• A Data message corresponding to the CopyBack request is received.
• A memory update is completed if required.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 5-237
ID082919 Non-Confidential
5 Interconnect Protocol Flows
5.6 Hazard handling examples
SnpShared
Hazard detected
UD->SC Req2 progress
blocked
SnpRespData_SC_PD
CompData_SC
WriteNoSnp
I->SC
CompAck
CompDBIDResp
B
CompDBIDResp NCBWrData
SC->I
CopyBackWrData_SC Req2 progress
(PS = SC, NS(implied) = I) un-blocked
PS = PresentState
NS = NextState
1. The regenerated request reaches the HN-F before the CompAck response associated with the earlier request.
2. The HN-F detects an address hazard and blocks the processing of the new request until the CompAck
response is received.
In such a scenario, upon arrival at HN-F, the CompAck response deallocates the previous request from the HN-F
and unblocks the processing of the new request.
5-238 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 6
Exclusive Accesses
This chapter describes the mechanisms that the architecture includes to support Exclusive accesses. It contains the
following sections:
• Overview on page 6-240.
• Exclusive monitors on page 6-241.
• Exclusive transactions on page 6-244.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 6-239
ID082919 Non-Confidential
6 Exclusive Accesses
6.1 Overview
6.1 Overview
The principles of Exclusive accesses are that a Logical Processor (LP) performing an exclusive sequence does the
following:
• Performs an Exclusive Load from a location.
• Calculates a value to store to that location.
• Performs an Exclusive Store to the location.
If the location is updated since the Exclusive Load, by a different LP, then the Exclusive Store must fail. In this case,
the store does not occur and the LP does not update the value held at the location.
Note
• The term Exclusive Load is used to describe the action of an LP executing an appropriate program instruction
such as LDREX. This action requires:
— Obtaining the data from the location to which it wants to perform an exclusive sequence.
— Indicating that it is starting an exclusive sequence.
• The term Exclusive Load transaction is used to describe a transaction issued on the interface to obtain data
for an Exclusive Load, if the data is not available in the cache at the LP. Not every Exclusive Load requires
an Exclusive Load transaction.
• The term Exclusive Store is used to describe the action of an LP executing an appropriate program instruction
such as STREX. This action requires:
— Determining if the exclusive sequence has passed or failed.
— If appropriate, updating the data at the location.
An Exclusive Store can pass or fail and this result is known to the executing processor. When an Exclusive
Store passes, the data value at the address location is updated. When an Exclusive Store fails, this indicates
that the data value at the address location has not been updated, and the Exclusive sequence must be restarted.
• The term Exclusive Store transaction is used to describe a transaction issued on the interface that might be
required to complete an Exclusive Store. Not every Exclusive Store requires an Exclusive Store transaction.
An Exclusive Store transaction can pass or fail and this result is made known to the LP using the transaction
response.
6-240 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
6 Exclusive Accesses
6.2 Exclusive monitors
LP monitor Each LP within an RN-F must implement an exclusive monitor that observes the location used by
an exclusive sequence. The LP monitor is set when the LP executes an Exclusive Load. The LP
monitor is reset when either:
• The location is updated by another LP, which is indicated by an invalidating snoop request to
the same address.
• There is a store to the location by the same LP. Resetting of the monitor if the store from the
same LP is non-exclusive is IMPLEMENTATION DEFINED.
PoC monitor An HN-F must implement a PoC monitor that can pass or fail an Exclusive Store transaction. A pass
indicates that the transaction has been propagated to other coherent RN-Fs. A fail indicates that the
transaction has not been propagated to other coherent RN-Fs and therefore the Exclusive Store
cannot pass.
The monitor is used to ensure that an Exclusive Store transaction from an LP is only successful if
that LP could not have received a snoop transaction, relating to an Exclusive Store to the same
address from another LP, after it issued its own Exclusive Store transaction.
The minimum requirement of the PoC monitor is to record when any LP performs a Snoopable
transaction related to an exclusive sequence.
If an LP has performed a transaction related to an Exclusive sequence, and it then performs an
Exclusive Store transaction before a successful Exclusive Store transaction from another LP is
scheduled, then the Exclusive Store transaction must be successful.
The monitor must support the parallel monitoring of all exclusive-capable LPs in the system.
When the HN-F receives a transaction associated with an Exclusive Load or an Exclusive Store, the
monitor registers that the LP is attempting an exclusive sequence.
When the HN-F receives an Exclusive Store transaction:
• If the PoC monitor has registered that the LP is performing an exclusive sequence, that is, it
has not been reset by an Exclusive Store transaction from another LP, then the Exclusive
Store transaction is successful and is permitted to proceed. In such a case, registered attempts
of all other LPs must be reset. This specification recommends, but does not require, that the
PoC monitor for the successful LP is left as registered.
• If the PoC monitor has not registered that the LP is performing an exclusive sequence, that
is, it has been reset by an Exclusive Store from another LP, then the Exclusive Store
transaction is failed and is not permitted to proceed. The monitor must register that the LP is
attempting an exclusive sequence.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 6-241
ID082919 Non-Confidential
6 Exclusive Accesses
6.2 Exclusive monitors
Note
A successful Exclusive Store transaction from an LP does not have to reset that the LP is
performing an exclusive sequence. The LP can continue to perform a sequence of Exclusive
Store transactions, which will all be successful, until another LP performs a successful
Exclusive Store transaction. For store transactions in which the LP is not identifiable, the
store must be handled as from a different LP than the one which set the monitor.
From initial system reset, the first LP to perform an Exclusive Store transaction can be
successful, but this specification does not require it. At that point, all other LPs must then
register the start of their exclusive sequence for their Exclusive Store transaction to be
successful.
When an Exclusive Store transaction from one LP passes and the registered attempts of all
other LPs is reset, the other LPs can only register a new exclusive sequence after the
CompAck response is observed for the Exclusive Store transaction that passed.
Note
An LP and PoC monitor pair are required to support an Exclusive access to a Snoopable memory location.
A monitor that includes additional address comparison must still include a minimum monitor of a single bit for
every Exclusive-capable LP to ensure forward progress.
• The address monitor has registered an exclusive sequence for a matching address from the same LP and has
not been reset by an Exclusive Store transaction from a different LP with a matching address.
• The minimum single-bit monitor has been set by an exclusive sequence from the same LP, and it has not been
reset by an Exclusive Store transaction from a different LP to any address.
Note
• The term matching address is used to describe where a monitor only records a subset of address bits. The
address bits that are recorded are identical, but the address bits that are not recorded can be different.
• An implementation does not require an address monitor for each Exclusive-capable LP. Because the address
monitor provides a performance enhancement it is acceptable to have fewer address monitors and for the use
of these to be IMPLEMENTATION DEFINED. For example, additional address monitors can be used on a
first-come first-served basis, or by allocation to particular LPs. Alternatively, a more complex algorithm
might be implemented.
• Additional PoC exclusive monitor functionality can be provided to prevent interference, or denial of service,
caused by one agent in the system issuing a large number of Exclusive access transactions. This specification
recommends that Secure Exclusive accesses are permitted to make forward progress independently of the
progress of Non-secure accesses.
6-242 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
6 Exclusive Accesses
6.2 Exclusive monitors
System monitor The System monitor tracks Exclusive accesses to a Non-snoopable region. This monitor
type is set by a ReadNoSnp(Excl) transaction and reset by an update to the location by
another LP.
System monitors can be placed at a PoS or at endpoint devices. Potentially, the number of
devices in the system is much larger than the number of PoS and placing System monitors
at a PoS can:
• Reduce System monitor duplication.
• Reduce the time taken for the system to detect failure of an Exclusive access.
A System monitor must be located so it can observe all transactions to the monitored
location.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 6-243
ID082919 Non-Confidential
6 Exclusive Accesses
6.3 Exclusive transactions
An exclusive transaction must use the correct LPID value, See Logical Processor Identifier on page 2-98.
However, the response must also indicate if the exclusive request has passed or failed. The RespErr field in the
response is used for this purpose. See RespErr on page 12-349. The RespErr field value of 0b01, Exclusive Okay,
indicates a pass and a RespErr field value of 0b00, Normal Okay, indicates an Exclusive access failure.
The Exclusive Okay response must only be given for a transaction that has the Excl attribute set.
Not all memory locations are required to support Exclusive accesses. An Exclusive Load transaction to a location
that does not support Exclusive accesses must not be given an Exclusive Okay response.
Whether or not an Exclusive Store transaction to a location that does not support Exclusive accesses will update that
location is IMPLEMENTATION DEFINED.
This specification recommends that an Exclusive Store transaction is not performed to a location that does not
support Exclusive accesses.
6-244 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
6 Exclusive Accesses
6.3 Exclusive transactions
Table 6-1 shows the Snoopable attributes of the request, the relevant monitor type and possible reasons for fail
conditions and response requirements.
ReadNoSnp(Excl) No System Target does not support Target must return a data
Exclusive accesses response
ReadClean(Excl) Yes LP, PoC Target does not support Target must return a data
ReadNotSharedDirty(Excl) Exclusive accesses response
ReadShared(Excl)
CleanUnique(Excl) Yes LP, PoC Address content modified Target must return a Comp
response
Address not present due to
monitor overflow
• Should include a monitor per LP for the efficient handling of Exclusive accesses.
• Must have a starvation prevention mechanism for all exclusive requests, whether using the monitor
mechanism or some other means.
• This specification recommends that progress on Secure Exclusive requests is independent of progress on
Non-secure Exclusive requests.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 6-245
ID082919 Non-Confidential
6 Exclusive Accesses
6.3 Exclusive transactions
An LP wanting to perform an Exclusive access to a Snoopable location might already hold the cache line in its local
cache:
• If the LP holds the cache line in a Unique state, then it is permitted, but not recommended by this
specification, that it performs an Exclusive Load transaction.
• If the LP holds the cache line in a Shared state, then it is permitted, but not required by this specification, that
it performs an Exclusive Load transaction.
• If the LP does not hold a copy of the cache line, this specification recommends that the LP uses an Exclusive
Load transaction to obtain the cache line, but is permitted to use ReadClean or ReadShared or
ReadNotSharedDirty without the Excl attribute asserted.
It is not required that an LP always completes an exclusive sequence. For example, the value obtained by the
Exclusive Load can indicate that a semaphore is held by another LP and that the value cannot be changed until the
semaphore is released by the other LP. Therefore, a new exclusive sequence can be started with no attempt to
complete the current exclusive sequence.
During the time between the Exclusive Load and the Exclusive Store the LP exclusive monitor must monitor the
location to determine whether another LP might have updated the location.
• If the LP exclusive monitor has been reset the Exclusive Store must fail and the LP must not issue an
Exclusive Store transaction. The LP must restart the exclusive sequence.
Note
When the LP monitor has been reset, not issuing a transaction for an Exclusive Store that must eventually fail
avoids unnecessary invalidation of other copies of the cache line.
• If the cache line is held in a Unique state and the LP exclusive monitor is set then the Exclusive Store has
passed and it can update the location without issuing a transaction.
6-246 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
6 Exclusive Accesses
6.3 Exclusive transactions
• If the cache line is held in a Shared state and the LP exclusive monitor is set then the LP must issue an
Exclusive Store transaction. A CleanUnique transaction with the Excl attribute asserted must be used. The
LP exclusive monitor must continue to operate and check that the cache line is not updated while the
CleanUnique transaction is in progress.
The transaction will receive a Normal Okay or an Exclusive Okay response.
If the transaction receives an Exclusive Okay response, then this indicates that the transaction has passed and
has completed invalidating all other copies of the cache line. After an exclusive transaction completes with
an Exclusive Okay response the LP must again check the LP exclusive monitor:
— If the LP exclusive monitor is set then the Exclusive Store has passed and the update is performed.
— If the LP exclusive monitor is not set, it indicates that an update to the cache line has occurred between
the point that the Exclusive Store transaction was issued and the point that it completed. The Exclusive
Store must fail and the exclusive sequence must be restarted.
— If the LP has not been able to track the exclusive nature of the cache line, because the cache line has
been evicted, then the Exclusive Store must fail and the exclusive sequence must be restarted.
If the Exclusive Store transaction receives a Normal Okay response then this indicates another LP has been
permitted to progress a transaction associated with an Exclusive Store. The transaction associated with the
Exclusive Store, from this LP, has failed and has not propagated to other LPs in the system. When an
Exclusive Store transaction completes with a Normal Okay response the options are:
— The LP can fail the Exclusive Store and restart the exclusive sequence with or without checking the
state of the cache line when the access completed.
— The LP can check the LP exclusive monitor, and if the LP exclusive monitor has been reset, then the
LP must fail the Exclusive Store and restart the exclusive sequence.
— The LP can check the LP exclusive monitor, and if the LP exclusive monitor is set, then the LP can
repeat the Exclusive Store transaction.
• The address of an Exclusive access must be aligned to the total number of bytes in the transaction.
• The number of bytes to be transferred in an Exclusive access must be a legal data transfer size, that is, 1, 2,
4, 8, 16, 32, or 64 bytes.
• The addresses of the Exclusive read and the Exclusive write must be identical.
• The value of the control signals, that is MemAttr and SnpAttr of the Exclusive read and the Exclusive write
transaction, must be identical.
• The data size in the Exclusive read and the Exclusive write must be identical.
• The LPID value of the Exclusive read must match the LPID value of the Exclusive write transaction.
The minimum number of bytes to be monitored during an exclusive operation is defined by the transaction size. The
System monitor can monitor a larger number of bytes, up to 64, which is the maximum size of an Exclusive access.
However, this can result in a successful Exclusive access being indicated as failing because a neighboring byte was
updated while the Exclusive access was in progress.
Multiple Exclusive transactions to Non-snoopable memory locations, either read or write, to the same or different
addresses, from the same LP must not be outstanding at the same time.
If the SN does not support Exclusive accesses, as indicated by an Exclusive Fail on the Exclusive ReadNoSnp, then
the write will update the location if the write is given an Exclusive Fail response.
If the SN does support Exclusive accesses, as indicated by an Exclusive Pass on the Exclusive ReadNoSnp, then the
write will not update the location if the write is given an Exclusive Fail response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 6-247
ID082919 Non-Confidential
6 Exclusive Accesses
6.3 Exclusive transactions
6-248 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 7
Cache Stashing
This chapter describes the cache stashing mechanism whereby data that is written from an RN can be installed in a
peer cache. It contains the following sections:
• Overview on page 7-250.
• Write with Stash hint on page 7-252.
• Independent Stash request on page 7-253.
• Stash target identifiers on page 7-255.
• Stash messages on page 7-256.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 7-249
ID082919 Non-Confidential
7 Cache Stashing
7.1 Overview
7.1 Overview
Cache stashing is a mechanism to install data within particular caches in a system. Cache stashing ensures that data
is located close to its point of use, therefore improving the system performance.
Both forms of cache stashing can target installation of data at different cache levels. The Stash target cache can be
a peer cache, specified by using the peer cache target NodeID, or a logical processor cache within the peer node, if
the peer node has multiple logical processors. The logical processor is identified by the LPID in the target cache
field. See Stash target identifiers on page 7-255.
The cache stashing requests can also target the cache below the peer cache in the cache hierarchy, which can be an
interconnect cache or a system cache. This is done by not specifying the peer cache NodeID. See Stash target not
specified on page 7-255.
In all cases of cache stashing, the stashing is only a performance hint and it is permitted for the Stash request receiver
to not perform the stashing behavior.
Table 7-1 shows the Snoop requests associated with each of the Stash requests.
WriteUniquePtlStash SnpUniqueStash
WriteUniqueFullStash SnpMakeInvalidStash
StashOnceUnique SnpStashUnique
StashOnceShared SnpStashShared
7-250 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
7 Cache Stashing
7.1 Overview
A Snoopee that receives a Stash type Snoop request does one of the following:
• Provides a Snoop response that also acts as a Read request for the associated cache line. Including a Read
request with Snoop response is referred to as a Data Pull. Data Pull can only be used if the DoNotDataPull
field in the Snoop request is deasserted. Table 7-2 shows the type of Read request that is implied by a Data
Pull in the response to each Stash type Snoop request.
SnpUniqueStash ReadUnique
SnpMakeInvalidStash ReadUnique
SnpStashUnique ReadUnique
SnpStashShared ReadNotSharedDirty
• Provides a Snoop response without a Data Pull response so ignoring the cache stash hint.
The value of the DataPull field in the SnpResp and SnpRespData responses indicates if Data Pull is requested. See
DataPull on page 12-343 for legal values for DataPull.
The use of Data Pull to complete a Snoop request with Stash is optional and can be controlled by both sides of the
interface:
• If Home is not able to support the Data Pull transaction flow then it must assert the DoNotDataPull field
within the Snoop request.
• If the Snoopee is not able to support the Data Pull transaction flow then it is permitted to ignore the stash
operation.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 7-251
ID082919 Non-Confidential
7 Cache Stashing
7.2 Write with Stash hint
Requester responsibilities:
Home responsibilities:
• Permitted to send a RetryAck response to a WriteUniqueStash request and follow the Retry transaction flow.
• Sends SnpUnique to all other Requesters that share the cache line.
• Permitted to ignore the stash hint in the Write request and process the request as a regular WriteUnique.
• Handles a request without a Stash target in the manner described in Stash target not specified on page 7-255.
• Permitted to use DMT to get data from SN-F to the Stash target in response to a Data Pull request, when the
data is neither available at Home nor obtained from any caches.
• Permitted to use separate Non-data and Data-only response to the Stash target in response to a Data Pull
request.
• Permitted to ignore the Stash hint and handle the snoop as SnpUnique.
7-252 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
7 Cache Stashing
7.3 Independent Stash request
• When the data that is being written is not required by the target immediately. This delayed stash avoids
polluting the cache with data that is not used immediately.
• When the data is already in the system and the data has to be prefetched into caches.
• When the process using the data being written is not scheduled when the data is written, and therefore the
precise target of the Stash data is not known until later.
In these cases, a Requester can use StashOnce requests to request Home or a peer node to fetch a cache line.
The rules for sending and processing an independent Stash request at the Stash requester, Home, and the Stash target
are as follows:
• Sends either StashOnceUnique or StashOnceShared to Home, based on whether the stashed cache line is to
be modified.
• The StashOnce request provides a Stash target when the data is to be stashed in a peer cache.
• The StashOnce request does not provide a Stash target when the data is to be allocated to the next level cache.
• Permitted to send a RetryAck response to a StashOnce request and follow the Retry transaction flow.
• Must send a Comp only after establishing processing order for the received request that is guaranteeing that
any request to the same address received later from any Requester is ordered behind this request.
• Fetches the addressed cache line from memory into the shared system cache when a StashOnce request
without a Stash target is received.
• Permitted to send Comp after receiving the StashOnce request, and before sending any SnpStash or receiving
the Snoop response.
• Send Comp_[X], where [X] is not I state, if the request hit the cache line at Home.
The [X] state is permitted only when it matches the cache state of the cache line at Home.
• Send a Comp_I response if either the cache look up at Home is a miss or Home did not look up the cache
before responding.
• Permitted to use DMT to get data from SN-F to the Stash target in response to a Data Pull request.
• Permitted to use separate Non-data and Data-only response to the Stash target in response to a Data Pull
request.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 7-253
ID082919 Non-Confidential
7 Cache Stashing
7.3 Independent Stash request
• The snoop must not change the state of the cache line at the Stash target.
• The snoop is treated as a hint at the Stash target to obtain a copy of the cache line.
• A DataPull request can be sent, but is not required to be sent, when the snoop is SnpStashUnique and a shared
copy is present.
• The Stash target is permitted, but not required, to wait until it completes the local cache lookup before sending
the Snoop response.
Note
• For StashOnceShared or StashOnceUnique transactions, care is needed to avoid any action that could result
in the deallocation of the cache line from the cache where it is expected to be used.
• A StashOnceUnique transaction can cause the invalidation of a copy of the cache line and care must be taken
to ensure such transactions do not interfere with Exclusive access sequences.
7-254 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
7 Cache Stashing
7.4 Stash target identifiers
• If the cache line is cached in a Unique state at an RN, then Home can treat that RN as the Stash target.
• If the cache line is not cached in a Unique state then Home must only send SnpUnique as required, and must
not send SnpUniqueStash to any RN.
• For WriteUniquePtlStash, if the cache line is not in any cache then this specification recommends Home to
prefetch and allocate the cache line in the system cache. It is permitted, but not recommended, to perform a
partial write to main memory.
• For WriteUniqueFullStash, if the cache line is not in any cache then Home is permitted to allocate the cache
line in the shared system cache.
The Home Node that receives a StashOnceUnique or StashOnceShared request without a Stash target does the
following:
• If the cache line is not cached in any peer cache then this specification recommends that the cache line is
allocated in the shared system cache.
• If the cache line is cached in a peer cache then it is IMPLEMENTATION DEFINED if a snoop is sent to transfer a
copy of the cache line and allocate it in the shared system cache. For StashOnceUnique, it is also
IMPLEMENTATION DEFINED if all cached copies are invalidated before allocating the cache line in the shared
system cache.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 7-255
ID082919 Non-Confidential
7 Cache Stashing
7.5 Stash messages
• DataPull.
• DataPull.
7-256 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 8
DVM Operations
This chapter describes Distributed Virtual Memory (DVM) operations that the protocol uses to manage virtual
memory. It contains the following sections:
• DVM transaction flow on page 8-258.
• DVM Operation types on page 8-268.
• DVM Operations on page 8-271.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-257
ID082919 Non-Confidential
8 DVM Operations
8.1 DVM transaction flow
DVMOp(Non-sync)
DBIDResp
NCBWrData
SnpDVMOp_P1
SnpDVMOp_P1
Snoop sent SnpDVMOp_P2
to core SnpDVMOp_P2
SnpResp_I
SnpResp_I
NCBWrData = NonCopyBackWrData
8-258 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.1 DVM transaction flow
The required steps that Figure 8-1 on page 8-258 shows are:
1. RN-F0 sends a DVMOp(Non-sync) to the MN using the appropriate write semantics for the DVMOp type.
4. The MN broadcasts the SnpDVMOp snoop request to all the RN-F and RN-D nodes in the system. The
SnpDVMOp is sent on the snoop channel, and requires two snoop requests. The two parts of the SnpDVMOp
are labeled by the suffix _P1 and _P2 respectively.
Note
• Both parts of the message must carry the same Transaction ID (TxnID).
• RN must have resources available to accept the SnpDVMOp. See Flow control on page 8-261.
5. After completing the required actions, each recipient of the SnpDVMOp sends a single SnpResp response to
the MN.
Note
Sending of a SnpResp implies that the target RN has forwarded the SnpDVMOp to the required RN structures
and has freed up the resources needed to accept another DVM operation. It does not imply that the requested
DVM operation has completed. See Sync type DVM transaction flow on page 8-260.
6. After receiving all the SnpResp responses, the MN sends a Comp response to the requesting node.
An MN that is enabled to send early Comp for a Non-sync DVMOp is permitted to opportunistically combine Comp
and DBIDResp responses into a single CompDBIDResp response.
Note
• Prior to CHI Issue D, an MN was not permitted to send a Comp for Non-sync DVMOp until it completed all
snoops generated by that request.
• Sending of a Comp response early for Non-sync DVMOp reduces round-trip latency for DVMOp
completion. This enables a greater number of DVMOp transactions to be pipelined from a single source.
• Such an early completion also enables a Sync DVMOp, which is waiting for completions of all related
DVMOp transactions sent earlier from the same RN.
The MN must still wait for the Snoop response for a Sync DVMOp to be received before sending a Comp to the
Requester for that Sync DVMOp.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-259
ID082919 Non-Confidential
8 DVM Operations
8.1 DVM transaction flow
DVMOp(Sync)
DBIDResp
NCBWrData
SnpDVMOp_P1
SnpDVMOp_P2
Comp
NCBWrData = NonCopyBackWrData
8-260 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.1 DVM transaction flow
The required steps that Figure 8-2 on page 8-260 shows are:
Note
All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have
received a Comp response before the RN can send a DVMOp(Sync).
2. The MN accepts the DVMOp(Sync) request and sends a DBIDResp response to the Requester.
3. The RN-F0 sends a data packet on the data channel with a data size of 8 bytes.
4. The MN sends the SnpDVMOp to RN-F1. The SnpDVMOp is sent on the snoop channel, and requires two
snoop requests. The two parts of a SnpDVMOp are labeled by the suffix _P1 and _P2 respectively.
5. After completing the DVM Sync operation, RN-F1 sends a SnpResp response to the MN.
Note
Sending of a SnpResp implies that all DVM related operations have completed at the RN structures and the
target RN has freed up the resources needed to accept another SnpDVMOp.
• A DVMOp that receives a RetryAck response must wait for a PCrdGrant response from the MN that has the
appropriate PCrdType.
• All previous DVMOp requests whose completion needs to be guaranteed by the DVMOp(Sync) must have
received a Comp response before the RN can send the DVMOp(Sync).
• The interconnect must guarantee forward progress on DVMOp(Non-Sync), which implies that there should
be at least one tracker entry in MN reserved for DVMOp(Non-Sync).
• It is permitted to overlap a DVMOp(Non-sync) and a DVMOp(Sync), from the same RN, if the
DVMOp(Sync) is not required to guarantee completion of the DMVOp(Non-sync).
• Both SnpDVMOp request packets corresponding to a single transaction must use the same TxnID.
• The two SnpDVMOp request packets corresponding to a single transaction can be sent or received in any
order.
• To prevent deadlocks, due to the two part SnpDVMOp requests that uses the snoop channel, a SnpDVMOp
transaction must only be sent when the receiving RN has pre-allocated resources to accept both parts of the
SnpDVMOp transaction.
• An RN must provide a response to a SnpDVMOp transaction only after it has received both SnpDVMOp
request packets corresponding to that transaction.
• An RN must provide a response to a SnpDVMOp only when it can accept a further SnpDVMOp from an MN.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-261
ID082919 Non-Confidential
8 DVM Operations
8.1 DVM transaction flow
• Each RN-F and RN-D in the system specifies the number of SnpDVMOp transactions it can accept
concurrently.
• Each RN-F and RN-D in the system must be able to accept at least one SnpDVMOp(Non-Sync) transaction
in addition to a SnpDVMOp(Sync) transaction.
• The minimum number of SnpDVMOp transactions that must be accepted concurrently is two. This is the
default number for RNs that do not specify a number.
8-262 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.1 DVM transaction flow
TxnID An ID generated by the Requester. Must follow the same rules as any other
transaction.
NS Must be zero.
PCrdType Must be 0b0000 if AllowRetry is asserted, otherwise the credit type value.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-263
ID082919 Non-Confidential
8 DVM Operations
8.1 DVM transaction flow
TraceTag None.
TraceTag None.
Data Unused bits must be zero for Data[63:0] and Data[n:64] = Don’t Care.
8-264 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.1 DVM transaction flow
NS Must be zero.
TraceTag None.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-265
ID082919 Non-Confidential
8 DVM Operations
8.1 DVM transaction flow
TraceTag None.
TraceTag None.
8-266 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.1 DVM transaction flow
TraceTag None.
TraceTag None.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-267
ID082919 Non-Confidential
8 DVM Operations
8.2 DVM Operation types
The various fields in the payload and their encodings are shown in Table 8-2.
VMID Valid 1 0b1 indicates that the Virtual Machine IDentifier (VMID) or Virtual Index (VI) is valid
ASID Valid 1 0b1 indicates that the Address Space IDentifier (ASID) or VI is valid
8-268 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.2 DVM Operation types
Leaf Entry Invalidation 1 0b1 indicates that only leaf level translation invalidation is required
VA or 49 to 53 Virtual address
PA 44 to 52 Physical address
a. DVMv8 only.
b. When used as Virtual Index, the upper 8-bits of ASID are Don’t Care.
In the DVMOp, the combination of the address field in the request and the 8-byte write data transports the complete
payload. Addr[3] is not used in the request and must be set to zero.
In the two SnpDVMOp requests the combination of the two address fields transports the complete payload. Addr[3]
is used in a SnpDVMOp request to indicate which part of the payload is being transported.
The valid combinations of Maximum PA (MPA) and Maximum VA (MVA) address bits are:
• MPA = 44 : MVA = 49.
• MPA = 45 : MVA = 51.
• MPA = 46 to 52 : MVA = 53.
Note
In Table 8-3 on page 8-270, the number given shows which Address or Data bit is replaced by the DVMOp field.
For example, the VA Valid field is placed in the same position that Addr[4] normally occupies. In a Request packet,
this would be the fifth bit position in the Addr field, but in a Snoop packet it would be the second bit position because
the Snoop packet does not include the three least significant address bits.
Also, PA[6] is placed in the same position that Data[4] normally occupies in a write data packet, and in the same
position that Addr[4] normally occupies in a Snoop packet. PA[6] is provided in the Part 2 Snoop packet, while VA
Valid is provided in the Part 1 Snoop packet.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-269
ID082919 Non-Confidential
8 DVM Operations
8.2 DVM Operation types
Table 8-3 DVMOp and SnpDVMOp request payloads using a 49-bit VA and 44-bit PA
Part 1 Part 2
Part Num 1 [3] - [3] [3] Must be 0b0 for the Request
and Snoop Part 1.
Must be 0b1 for Snoop Part 2.
8-270 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.3 DVM Operations
Table 8-4 shows the values for the Part Num field in all supported DVM Operations.
Part 1 Part 2
[3] Part Num 0b0 0b0 0b1 Not utilized in the Request
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-271
ID082919 Non-Confidential
8 DVM Operations
8.3 DVM Operations
Addr Operation
0b000 0b10 0b10 0b0 0b0 0b0 0b00a 0b0 Secure TLB Invalidate all
TLBI All Guest OS Secure Ignore Ignore Ignore Ignore
0b10 0b11 0b0 0b0 0b0 0b00a 0b0 All Guest OS TLB Invalidate
All Guest OS Non-secure Ignore Ignore Ignore Ignore all
8-272 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.3 DVM Operations
Addr Operation
0b000 0b11 0b11 0b0 0b0 0b0 0b00a 0b0 Hypervisor TLB Invalidate all
TLBI Hypervisor Non-secure Ignore Ignore Ignore Ignore
0b01 0b10 0b0 0b0 0b0 0b00a 0b1 EL3 TLB Invalidate by VA
EL3 Secure Ignore Ignore Ignore Match
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-273
ID082919 Non-Confidential
8 DVM Operations
8.3 DVM Operations
Table 8-6 shows the fixed value fields in the Branch Predictor Invalidate operation.
Bits Field
Note
The use of Branch Predictor Invalidate with a 16-bit ASID is not supported.
Addr Operation
[13:11] [4]
DVMOp type VA valid
8-274 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.3 DVM Operations
Table 8-8 shows the fixed value fields in the Physical Instruction Cache Invalidate operation.
Bits Field
Table 8-9 shows the operations supported by Physical Instruction Cache Invalidate.
Note
When Virtual Index is 0b11, then VA[19:12] and VA[27:20], at Addr[29:22] and Addr[21:14] respectively, are used
as part of the Physical Address. Addr[37:30] are not used, and are Don’t Care values.
0b010 0b10 0b00 0b0 Secure Physical Address Cache Invalidate all
PICI Secure Ignore
0b00 0b1 Secure Physical Address Cache Invalidate by PA without Virtual Index
Match
0b11 0b1 Secure Physical Address Cache Invalidate by PA with Virtual Index
Match
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-275
ID082919 Non-Confidential
8 DVM Operations
8.3 DVM Operations
Table 8-10 shows the fixed value fields in the Virtual Instruction Cache Invalidate operation.
Bits Field
Table 8-11 shows the operations supported by Virtual Instruction Cache Invalidate.
Addr Operation
0b011 0b00 0b00 0b0 0b0 0b0 Invalidate all. Applies to Secure and Non-secure.
VICI Hypervisor and Secure and Ignore Ignore Ignore Applies to Hypervisor and all Guest OS.
all Guest OS Non-secure
0b10 0b10 0b1 0b0 0b1 Secure Invalidate by ASID and VA.
Guest OS Secure Match Ignore Match
8-276 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
8 DVM Operations
8.3 DVM Operations
8.3.5 Synchronization
This section shows the DVMSync Synchronization operation.
Table 8-12 shows the fixed value fields in the Sync operation.
Bits Field
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 8-277
ID082919 Non-Confidential
8 DVM Operations
8.3 DVM Operations
8-278 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 9
Error Handling
This chapter describes the error handling requirements. It contains the following sections:
• Error types on page 9-280.
• Error response fields on page 9-281.
• Errors and transaction structure on page 9-282.
• Error response use by transaction type on page 9-283.
• Poison on page 9-290.
• Data Check on page 9-291.
• Use of interface parity on page 9-292.
• Interoperability of Poison and DataCheck on page 9-295.
• Hardware and software error categories on page 9-296.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-279
ID082919 Non-Confidential
9 Error Handling
9.1 Error types
Note
An error in data being evicted from Home, or received in a Snoop response as a result of the
request, are examples of the request resulting in a DERR.
9-280 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.2 Error response fields
Table 9-1 shows the encoding of the RespErr field. See Responses to exclusive requests on page 6-244 for more
details on the Exclusive Okay response.
0b01 EXOK Exclusive Okay. Indicates that either the read or write portion of an
Exclusive access has been successful.
The mixing of OK, DERR, and NDERR responses within a single transaction is permitted.
The mixing of EXOK, DERR and NDERR responses within a single transaction is permitted.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-281
ID082919 Non-Confidential
9 Error Handling
9.3 Errors and transaction structure
Error handling for a transaction that utilizes DMT is the same as the error handling for the same request without
DMT.
Because there is no mechanism to propagate errors on requests or snoops, a request must not use DMT or DCT if
an error is detected at the interconnect.
If the transaction contains data packets then the source of the data packets is required to send the correct number of
packets, but the data values are not required to be valid.
The Resp field gives the cache states associated with a transaction and can be influenced by an error condition. See
Response types on page 4-166 for more details on the legal Resp field values. If a response to a transaction does not
have a legal cache state, then the RespErr field must indicate a Non-data Error for all data packets. A Snoop response
with error that does not have a legal cache state must not include data with the response.
The Resp field in a response must have the same value for every packet of a data message regardless of whether or
not there is an error condition.
9-282 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.4 Error response use by transaction type
The tables that follow show the Data and Response packets associated with the following transaction types:
• Read Transactions.
• Dataless transactions on page 9-284.
• Write transactions on page 9-285.
• Atomic transactions on page 9-285.
• Other transactions on page 9-287.
• Cache Stashing transactions on page 9-287.
• Snoop transactions on page 9-288.
When RespSepData includes a Non-data Error, all corresponding DataSepResp packets must be marked with
Non-data Error.
Table 9-2 Read transaction’s Data and Response packets legal RespErr field values
ReadNoSnp OK Y Y Y Y OK
ReadNoSnpSep OK - - - - -
ReadOnce OK Y N Y Y OK
ReadOnceCleanInvalid
ReadOnceMakeInvalid
ReadClean - Y Y Y Y OK
ReadNotSharedDirty
ReadShared
ReadUnique - Y N Y Y OK
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-283
ID082919 Non-Confidential
9 Error Handling
9.4 Error response use by transaction type
Table 9-3 Read transaction’s Data-only and Non-data packets legal RespErr field values
DataSepResp RespSepData
ReadNoSnp Y N Y Y Y N N Y
ReadNoSnpSep Y N Y Y - - - -
ReadOnce Y N Y Y Y N N Y
ReadOnceCleanInvalid
ReadOnceMakeInvalid
ReadClean Y N Y Y Y N N Y
ReadNotSharedDirty
ReadShared
ReadUnique Y N Y Y Y N N Y
Table 9-4 shows the Dataless transaction packets legal RespErr field values.
NDERR
NDERR
EXOK
DERR
EXOK
DERR
EXOK
DERR
OK
OK
OK
CleanUnique Y Y Y Y - - - - - - - - OK
MakeUnique Y N Y Y - - - - - - - - OK
CleanShared Y N Y Y - - - - - - - - -
CleanSharedPersist Y N Y Y - - - - - - - - -
CleanSharedPersistSep Y N Y Y Y N Y Y Y N Y Y -
CleanInvalid Y N Y Y - - - - - - - - -
MakeInvalid
Evict Y N N Y - - - - - - - - -
StashOnceUnique Y N Y Y - - - - - - - - -
StashOnceShared
9-284 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.4 Error response use by transaction type
For a Write transaction an error can be signalled from the Completer back to the Requester using either the
combined CompDBIDResp or using the Comp response. It is permitted for the Completer to signal an error even
before it has observed the WriteData for the transaction and this can occur when the processing of the transaction,
such as the cache lookup, encounters a data corruption error.
Table 9-5 shows the Write transaction Response packets legal RespErr field values.
Table 9-5 Write transaction Response packets legal RespErr field values
Write
Associated Response packets
transaction
WriteNoSnp OK Y Y Y Y Y Y Y Y OK
WriteUnique OK Y N Y Y Y N Y Y OK
WriteBack - - - - - Y N Y Y -
WriteClean
WriteEvictFull
A Requester that detects an error in the write data to be sent can include an error indication with the write data
packet. This indicates that the data value is known to be corrupt.
Table 9-6 shows the Write transaction Data packets legal RespErr field values.
Table 9-6 Write transaction Data packets legal RespErr field values
Write
Associated Data packets
transaction
WriteNoSnp Y N Y N Y N Y N Y N Y N
WriteUnique Y N Y N Y N Y N Y N Y N
WriteBack Y N Y N - - - - - - - -
WriteClean
WriteEvictFull
A Data Error or Non-data Error can be signaled at the following points within a transaction:
• With the DBIDResp response.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-285
ID082919 Non-Confidential
9 Error Handling
9.4 Error response use by transaction type
Note
If a read data at Home due to a non-store Atomic request results in a Data Error or Non-data Error, then such an
error can be propagated onto the DBIDResp or CompDBIDResp response for that request.
For Atomic transactions that are not able to complete, a Non-data Error must be used. The transaction structure,
including all write data transfers, read data transfers, and other responses must still take place.
There is no need to specify an error associated with the execution of an atomic operation, such as overflow. All
atomic operations are fully specified for all input combinations.
A transaction includes both outbound and inbound data, but only has a single Error field. For Atomic transactions
it is permitted for the Error field to indicate an error on either write data or read data. There is no mechanism
supported within the transaction to differentiate between the potential different causes of an error. A fault log, or a
similar structure, might be able to provide such information, but this is not a requirement of this specification.
The permitted RespErr values in Atomic transactions are an amalgamation of those permitted in Read and Write
transactions.
Table 9-7 shows the Atomic transaction Response packets legal RespErr field values
Table 9-7 Atomic transaction Response packets legal RespErr field values
AtomicStore OK Y N Y Y Y N Y Y
AtomicLoad OK Y N Y Y - - - -
AtomicSwap
AtomicCompare
Table 9-8 shows the Atomic transaction Data packets legal RespErr field values.
Table 9-8 Atomic transaction Data packets legal RespErr field values
WriteData CompData
AtomicStore Y N Y N - - - -
AtomicLoad Y N Y N Y N Y Y
AtomicSwap
AtomicCompare
9-286 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.4 Error response use by transaction type
DVMOp
A DVMOp transaction can include a Non-data Error in the Comp response. The interconnect must consolidate error
responses from all the snoop responses for a DVMOp and include a single error response in the final Comp message
to the Requester. The DBIDResp packet must only use the OK response. Even though the Sender of a WriteData
response might not use DERR, the packet can be marked as DERR if it encounters errors during transmission. See
Interoperability of Poison and DataCheck on page 9-295.
Table 9-9 shows the DVM transaction Response packets legal RespErr field values.
Table 9-9 DVM transaction Response packets legal RespErr field values
DVMOp OK Y N Y Y Y N Y Y
Table 9-10 shows the DVM transaction Data packets legal RespErr field values.
Table 9-10 DVM transaction Data packets legal RespErr field values
NCBWrData
DVMOp Y N Y N
PrefetchTgt
A PrefetchTgt transaction request to a non-supporting address must be discarded.
Note
A component is permitted to record and report such an error.
If the Home does not support Stash requests, it must complete the transaction in a protocol-compliant manner
without signaling an error.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-287
ID082919 Non-Confidential
9 Error Handling
9.4 Error response use by transaction type
A snoop transaction response that does not include data can indicate a Non-data Error.
Table 9-11 shows the Snoop request Response packets legal RespErr field values.
Table 9-11 Snoop request Response packets legal RespErr field values
SnpResp SnpRespData
SnpOnce Y N N Y Y N Y N
SnpClean
SnpNotSharedDirty
SnpShared
SnpUnique
SnpUniqueStash
SnpCleanShared
SnpCleanInvalid
SnpStashUnique Y N N Y - - - -
SnpStashShared
SnpMakeInvalid
SnpMakeInvalidStash
SnpDVMOp
It is recommended, but not required, that a DERR on a Clean cache line is dropped, and the error is not propagated
to the memory, nor included in the response to the Requester.
A DERR on a Dirty cache line must be propagated to the memory, and in the response to the Requester.
A DERR in response to the Data Pull request is not expected to be transferred to the Comp response to the Stash
request.
A fowarding Snoop transaction can include an error indication similar to those in a snoop as well as in a completion
with data from the Snoopee to the Requester. When simultaneously forwarding data to the Requester and returning
Data to Home, it is permitted for only one response to include an indication of a Data Error if the other response
does not encounter the error.
The Non-data Error in SnpRespFwded is permitted to include the case where the error is detected after the data is
forwarded to the Requester but before the response is sent to Home. FwdState in the SnpRespFwded response with
Non-data Error must be the RESP state in the CompData to the Requester.
9-288 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.4 Error response use by transaction type
Table 9-12 shows the Forward Snoop Response packets legal RespErr field values.
Table 9-12 Forward Snoop Response packets legal RespErr field values
SnpResp SnpRespFwded
SnpOnceFwd Y N N Y Y N Y Y
SnpCleanFwd
SnpNotSharedDirtyFwd
SnpSharedFwd
SnpUniqueFwd
Table 9-13 shows the Forward Snoop Data Response packets legal RespErr field values.
Table 9-13 Forward Snoop Data Response packets legal RespErr field values
SnpRespData
CompData
SnpRespDataFwded
SnpOnceFwd Y N Y N Y N Y N
SnpCleanFwd
SnpNotSharedDirtyFwd
SnpSharedFwd
SnpUniqueFwd
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-289
ID082919 Non-Confidential
9 Error Handling
9.5 Poison
9.5 Poison
The Poison bit is used to indicate that a set of data bytes have previously been corrupted. Passing the Poison bit
alongside the data in the DAT packet permits any future user of the data to be notified that the data is corrupt.
Poison must be accurate if there are any valid bytes in the 64-bit chunk, which is Poison granularity, Otherwise, the
Poison bit is a Don’t Care, that is, when all 8 bytes in the 64-bit chunk are invalid, then it is a Don’t Care.
9-290 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.6 Data Check
Note
Interface parity optionally extends the error detection provided on the DAT channel by the DataCheck field.
The protection scheme employed on an interface is defined by the property Check_Type. See Interface properties
and parameters on page 15-382.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-291
ID082919 Non-Confidential
9 Error Handling
9.7 Use of interface parity
An error in a system component can propagate and cause multiple errors within connected components. Error
detection and correction (EDC) is required to operate end-to-end, covering all logic and wires from source to
destination.
One way to implement end-to-end protection, is to employ customized EDC schemes in components and implement
a simple error detection scheme between components. Between these components there is no logic and connections
are relatively short. This section describes a parity scheme for detecting single-bit errors on the interface between
components. Multi-bit errors may be detected if they occur in different parity signal groups. Figure 9-1 shows
locations where parity can be used.
Interconnect
AMBA AMBA
Source Destination
Parity check
Parity generation Parity check and EDC EDC check and Parity
generation generation
AMBA parity optionally extends the error detection provided on the DAT channel by the DataCheck field to cover
the complete flit and control signals on all channels.
The protection scheme employed on an interface is defined by the property Check_Type. See Interface properties
and parameters on page 15-382.
• Parity signals covering data and payload are defined such that there are no more than 8 bits per group.
This limitation assumes that there is a maximum of 3 logic levels available in the timing budget for generating
each parity bit.
• Parity signals covering critical control signals, which are likely to have a smaller timing budget available, are
defined with a single odd parity bit.
• The least significant check bit of the check signal covers the least significant byte of payload.
• If the bits in a payload does not fill the most significant byte, the most significant bit of the check signal
covers fewer than 8 bits.
9-292 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.7 Use of interface parity
• Check signals must be driven correctly in every cycle that the Check Enable term is True, see Table 9-14 on
page 9-294.
• Parity signals must be driven appropriate to all the bits in the associated payload, irrespective of whether
those bits are applicable.
• Terminate or propagate the transaction. It is permitted, but not required, to be protocol compliant when the
transaction is terminated.
• Update its memory or leave untouched. It is permitted, but not required, to mark the location as poisoned.
• Signal an error response through other means, for example, with an interrupt.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-293
ID082919 Non-Confidential
9 Error Handling
9.7 Use of interface parity
9-294 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
9 Error Handling
9.8 Interoperability of Poison and DataCheck
If support for the Poison and DataCheck features is not similar across an interface, then the following rules apply:
• Poison must be mapped to DataCheck or DERR if Poison is not supported across the interface. At such an
interface, Poison is expected but not required to be mapped to DataCheck instead of DERR, if DataCheck is
supported.
When converting from Poison to DataCheck, when an 8-byte chunk is marked as Poisoned, all 8 bits of
DataCheck corresponding to that chunk must be manipulated to generate a parity error.
• DataCheck must be mapped to Poison or DERR if DataCheck is not supported across the interface. At such
an interface, DataCheck is expected but not required to be mapped to Poison instead of DERR, if Poison is
supported.
When converting from DataCheck to Poison, if one or more DataCheck bits in a given 8-byte chunk generates
a parity error, then the Poison bit corresponding to that chunk must be set.
Note
The difference between the handling of Poison and DERR is that a Poison error in a received Data packet is typically
deferred by the receiver, but a DERR error is typically not deferred by the receiver.
It is sufficient for the Sender of a Data packet that detects a Poison error to indicate this in the Poison bits. It is not
a requirement that the Sender sets the RespErr field value to DERR.
It is sufficient for the Sender of a Data packet that detects a DataCheck error to indicate this in the DataCheck field
and is not required to set RespErr field value to DERR.
As Poison and DataCheck fields are independently set, one type of error does not require setting of the other.
In a Data packet that has the RespErr field value set to DERR or NDERR the value of the Poison and DataCheck
fields are Don’t Care.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 9-295
ID082919 Non-Confidential
9 Error Handling
9.9 Hardware and software error categories
A software based error can cause a loss of coherency and the corruption of data values. This specification requires
that the system does not deadlock for a software based error, and that transactions always progress through a system
in a timely manner.
A software based error, for an access within one 4KB memory region, must not cause data corruption within a
different 4KB memory region.
For locations held in Normal memory, the use of appropriate stores and software cache maintenance can be used to
return memory locations to a defined state.
When accessing a peripheral device the correct operation of the peripheral cannot be guaranteed. The only
requirement is that the peripheral continues to respond to transactions in a protocol compliant manner. The sequence
of events that might be required to return a peripheral device that has been accessed incorrectly to a known working
state is IMPLEMENTATION DEFINED.
Warning
If a hardware based error occurs then recovery from the error is not guaranteed. The system might crash, lock-up,
or suffer some other non-recoverable failure.
9-296 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 10
Quality of Service
This chapter describes the mechanisms in the CHI protocol to support Quality of Service (QoS). It contains the
following sections:
• Overview on page 10-298.
• QoS priority value on page 10-299.
• Repeating a transaction with higher QoS value on page 10-300.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 10-297
ID082919 Non-Confidential
10 Quality of Service
10.1 Overview
10.1 Overview
A system might utilize a QoS scheme to achieve:
• A guaranteed maximum latency for transactions in a particular stream.
• Minimum bandwidth guarantees for a stream of requests.
• Best effort value of bandwidth and latency provided to requests of a particular stream.
The low latency, or guaranteed throughput requirements, required to meet system QoS demands are primarily the
responsibility of the transaction end points with support from the intermediate interconnect. The protocol supports
this by defining a QoS priority value for packets and controlling request flow using a defined credit mechanism.
10-298 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
10 Quality of Service
10.2 QoS priority value
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 10-299
ID082919 Non-Confidential
10 Quality of Service
10.3 Repeating a transaction with higher QoS value
In this situation, if one of the transactions receives a RetryAck response, then it is permitted to cancel the transaction
and return the credit. See Credit Return on page 2-130.
10-300 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 11
System Debug, Trace, and Monitoring
This chapter describes mechanisms that provide additional support for the debugging and tracing of systems, and
the monitoring of systems to enhance performance. It contains the following sections:
• Data Source indication on page 11-302.
• MPAM on page 11-305.
• Completer Busy on page 11-307.
• Trace Tag on page 11-308.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 11-301
ID082919 Non-Confidential
11 System Debug, Trace, and Monitoring
11.1 Data Source indication
• Fixed values are used for DataSource when Data comes from memory and are used to indicate the following:
— 0b0110 PrefetchTgt memory prefetch was useful.
Read data was obtained from Slave with lower latency as the PrefetchTgt request already
read or initiated a read of data from memory.
— 0b0111 PrefetchTgt memory prefetch was not useful.
Read request went through a complete memory access and therefore did not have any
latency reduction due to the PrefetchTgt request sent earlier.
The precise reason for signaling that a prefetch was not useful is IMPLEMENTATION
DEFINED.
Note
There are several reasons why the PrefetchTgt request might not be useful. Examples are that the
prefetch was dropped by the Slave, the data obtained by the prefetch was replaced in the buffer, or the
Read request arrived at the Slave before the prefetch.
• For a response not from memory, that is, from a cache, the DataSource value is IMPLEMENTATION DEFINED.
This specification recommends, but does not require, settings for DataSource in these cases.
A component is permitted to have software programmability to override the DataSource value to:
— Change the groupings to more suitable specific configuration settings.
— Change the values where the values are not correct.
Example approaches that the chip interface module might take are:
• Group the remote caches into a single encoding, as Figure 11-1 on page 11-303 shows.
• Have a maximum size of an eight entry table, to remap the implementation values of the DataSource field in
the incoming Data packet to new values.
11-302 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
11 System Debug, Trace, and Monitoring
11.1 Data Source indication
• Each chip in the system has two processors per cluster, with a three level cache hierarchy.
• The cache in the chip-to-chip interface module is identified as part of the interconnect caches.
• All the caches in the remote peer chip are grouped together.
• A non-memory component that is not programmed to identify itself as the source of data can return the
default value of 0b0000.
0b0000 Non-memory default. Source does not support sending a useful DataSource value
Chip Peer
Cluster Peer Cluster Cluster Peer Cluster
Chip
Processor Processor Processor Processor Processor Processor Processor Processor
Cache Cache Cache Cache Cache Cache Cache Cache
Cache Cache Cache Cache
Cache
Cache
Cache
Cache
Interconnect Interconnect
Cache Cache Cache Cache Cache Cache Cache Cache
= 0101
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 11-303
ID082919 Non-Confidential
11 System Debug, Trace, and Monitoring
11.1 Data Source indication
• Can be used by performance profiling and debug software to evaluate and optimize the data sharing pattern.
11-304 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
11 System Debug, Trace, and Monitoring
11.2 MPAM
11.2 MPAM
Memory System Performance Resource Partitioning and Monitoring (MPAM) is a mechanism to efficiently utilize
the memory resources among users and to monitor the utilization of those resources. The resources are partitioned
among users by Partition ID (PartID) and Performance Monitoring Group (PerfMonGroup). A Requester that
supports MPAM includes in each request it sends a label, identifying the partition to which it belongs, together with
the performance monitoring group within that partition. The Home or the Slave use this information to allocate their
resources to this request.
The MPAM field is applicable only in the REQ and SNP channels:
• On the REQ channel, when a sender does not want to use MPAM for a request, the MPAM values must be
set to default settings. See Default values for MPAM sub-fields on page 11-306.
• On the SNP channel, MPAM values are only applicable in Stash type snoops.
In Non-stash type snoops, MPAM values are inapplicable and must be set to default values.
• The width is 11 bits on interfaces that support MPAM. The field is further divided into the sub-fields:
— PartID = 9 bits.
— PerfMonGroup = 1 bit.
— MPAMNS = 1 bit.
10 9 1 0
PartID
PerfMonGroup MPAMNS
MPAM field
How the MPAM field values are used by the receiver is IMPLEMENTATION DEFINED.
11.2.1 MPAMNS
A Non-secure bit in the MPAM field, this is in addition to and different from the NS bit of the request.
The polarity of the MPAMNS bit encoding is the same as that of the NS bit.
MPAMNS Description
0 Secure partition
1 Non-secure partition
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 11-305
ID082919 Non-Confidential
11 System Debug, Trace, and Monitoring
11.2 MPAM
MPAM field values must be propagated onto an interface that supports MPAM.
It is permitted, but not required, to propagate MPAM field values onto an interface that does not support MPAM.
Table 11-4 shows the default values for MPAM fields when not supported or not propagated.
PerfMonGroup 0
PartID 0
For responses to Stash type snoops, when the response includes a Data Pull request, the Home must assume the
MPAM values in the Data Pull request are the same as in the original Stash request.
11-306 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
11 System Debug, Trace, and Monitoring
11.3 Completer Busy
CBusy Completer Busy. A 3-bit field that is applicable in the appropriate DAT and RSP packets.
When separate Data and Comp responses are used for a single Read request, the Busy indication in
each response can be independently set.
Note
DataSource can be used as a qualifier to the Completer Busy indication such that some data sources, for example a
forwarding snoop, do not influence the busy indication.
CBusy[2] When asserted indicates multiple cores are actively making requests.
CBusy[1:0] Indicates the degree of fullness of the tracker at the Completer as:
• 00 = Less than 50% full.
• 01 = Greater than 50% full.
• 10 - Greater than 75% full.
• 11 = Greater than 90% full.
The prefetcher at the Requester can use the CBusy field values and fine tune the prefetcher in the following manner:
• If CBusy[2] = 1 and CBusy[1:0] = 11: Disable inaccurate prefetchers.
• If CBusy[1:0] = 10: Very conservative mode on inaccurate prefetchers.
• If CBusy[2] = 1 and CBusy[1:0] = 01: Moderately aggressive mode on inaccurate prefetchers.
• If CBusy[1:0] = 00: Fully aggressive mode on inaccurate prefetchers.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 11-307
ID082919 Non-Confidential
11 System Debug, Trace, and Monitoring
11.4 Trace Tag
• The TraceTag bit can be set by the transaction initiator or an interconnect component.
• A component that receives a packet with a TraceTag bit set in every received packet must preserve and reflect
the value back in any response packet or spawned packet generated in response to the received packet.
• If a received packet spawns multiple responses, such as a Write request resulting in separate Comp and
DBIDResp responses, or a Read request generating separate DataSepResp and RespSepData responses, all
such spawned responses are required to have the TraceTag bit set if the spawning packet has the TraceTag bit
set. If the spawning packet does not have the TraceTag bit set then the value of the TraceTag bit in a spawned
packet is independent of the value of the bit in other related spawned packets.
• If a component can receive multiple packets that are associated with a single transaction, then for each packet
that it, in turn, generates, the TraceTag value is only required to be set if it is set in the associated received
packet. For example:
— A Write transaction flow at RN might have write data and CompAck as two responses for received
packets DBIDResp and Comp respectively. As CompAck is in response to the received Comp only,
its TraceTag bit value is only required to be dependent on the TraceTag bit value in the Comp packet
and similarly for the write data and DBIDResp Response-Received Packet pair.
A Request that receives separate DataSepResp and RespSepData responses and generates a CompAck,
is only required to have the TraceTag bit set in CompAck if RespSepResp has the TraceTag bit set.
— The TraceTag bit in the NCBWrDataCompAck response from RN must be set if either one of Comp
or DBIDResp that caused the WriteData response have the TraceTag bit set.
• When an interconnect receives a packet with the TraceTag bit set, it must preserve the value and not reset the
value.
Note
• Propagating the value of the TraceTag bit on a resulting cache eviction is IMPLEMENTATION DEFINED.
• The precise mechanism to trigger and utilize the TraceTag bit is IMPLEMENTATION DEFINED.
• It is expected that the TraceTag bit will be limited to single system wide use at any time.
Some of the ways the trace tag mechanism can be used are:
— Debug, by tracing transaction flows through the system.
— Performance counting.
— Latency measurement.
11-308 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
11 System Debug, Trace, and Monitoring
11.4 Trace Tag
Note
Examples of Request-Response pairs are:
• Snoop response, with or without data, in response to a Snoop request.
• A Snoop response in response to a SnpDVMOp request.
• Data response from SN in response to a Read request.
• Spawned requests from HN-F:
— Snoops generated in response to a request from RN.
— Request to SN-F generated in response to a request from RN.
• Spawned request from HN-I:
— Read or Write request to SN-I generated in response to a request from RN.
• A CompAck from RN in response to CompData, Comp or RespSepData.
• A RetryAck response from HN or SN to any request.
• A ReadReceipt response from HN or SN to a Read request or from SN to a ReadNoSnpSep request.
• A DBIDResp response to a Write request.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 11-309
ID082919 Non-Confidential
11 System Debug, Trace, and Monitoring
11.4 Trace Tag
11-310 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 12
Link Layer
This chapter describes the Link layer that provides a streamlined mechanism for packet based communication
between nodes and the interconnect across links. It contains the following sections:
• Introduction on page 12-312.
• Link on page 12-313.
• Flit on page 12-314.
• Channel on page 12-315.
• Port on page 12-317.
• Node interface definitions on page 12-318.
• Channel interface signals on page 12-320.
• Flit packet definitions on page 12-324.
• Protocol flit fields on page 12-329.
• Link flit on page 12-353.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-311
ID082919 Non-Confidential
12 Link Layer
12.1 Introduction
12.1 Introduction
The Link layer provides a streamlined mechanism for packet based communication between nodes and the
interconnect.
Tx Rx Tx Rx Tx Rx
Interconnect Links
Tx Rx Tx Rx Tx Rx
Rx Tx Rx Tx Rx Tx
Node 4 Node 5 Node 6
Interface parity signals, which are discussed in Use of interface parity on page 9-292 are not included in this chapter.
12-312 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.2 Link
12.2 Link
Flit communication occurs between a transmitter and a receiver pair.
Two-way communication between a node and the interconnect requires a pair of links. Figure 12-2 shows the link
requirements.
Node Interconnect
Transmitter Receiver
Link 1
(TX) (RX)
Receiver Transmitter
Link 2
(RX) (TX)
The link used by a receiver to receive packets is defined as the inbound link.
Figure 12-3 shows the outbound and inbound links at a node. The interface at the interconnect has a complementary
pair of links.
Node
Transmitter
Outbound Link
(TX)
Receiver
Inbound Link
(RX)
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-313
ID082919 Non-Confidential
12 Link Layer
12.3 Flit
12.3 Flit
A flit is the basic unit of transfer in the Link layer.
Packets are formatted into flits and transmitted across a link. There are two types of flits:
Protocol flit A Protocol flit carries a protocol packet in its payload. In this specification, every protocol packet
is mapped into exactly one protocol flit.
Link flit A Link flit carries messages associated with link maintenance. For example, a transmitter uses a
Link flit to return a Link layer Credit, also referred to as an L-Credit, to the receiver during a link
deactivation sequence.
Link flits originate at a link transmitter and terminate at the link receiver connected at the other side
of the link.
12-314 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.4 Channel
12.4 Channel
In this specification, the Link layer provides a set of channels for flit communication.
Each channel has a defined flit format that has multiple fields and some of the field widths have multiple possible
values. In some cases, the defined flit format can be used on both an inbound and an outbound channel.
Table 12-1 shows the channels, and the mapping onto the RN and SN component channels.
REQ The request channel transfers flits associated All Requests TXREQ RXREQ
Request with request messages such as Read
Requests and Write Requests. See REQ
channel on page 12-320.
RSP The response channel transfers flits Responses from the Completer RXRSP TXRSP
Response associated with response messages that do
not have a data payload such as write Snoop Response and Completion TXRSP -
completion messages. See RSP channel on Acknowledge
page 12-321.
SNP The snoop channel transfers flits associated All Snoop requests RXSNP -
Snoop with Snoop and SnpDVMOp Request
messages. See SNP channel on page 12-322.
DAT The data channel transfers flits associated Write data, and Snoop response data TXDAT RXDAT
Data with protocol messages that have a data from an RN
payload such as read completion and write
data messages. See DAT channel on Read data RXDAT TXDAT
page 12-323.
For RN:
• An RN must make forward progress on the inbound SNP channel without requiring forward progress on
outbound REQ channel.
• An RN is permitted to wait for forward progress on the outbound RSP channel before making forward
progress on the inbound SNP channel.
• An RN is permitted to wait for forward progress on the outbound DAT channel before making forward
progress on the inbound SNP channel.
• An RN must make forward progress on the inbound RSP channel without requiring forward progress on any
other channel.
• An RN must make forward progress on the inbound DAT channel without requiring forward progress on any
other channel.
Note
The requirement that an RN must make forward progress on the inbound RSP and DAT channel, without requiring
forward progress on any other channel, means that an RN must be able to accept all Comp and CompData responses
for outstanding transactions without sending any CompAck responses.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-315
ID082919 Non-Confidential
12 Link Layer
12.4 Channel
For SN:
• An SN is permitted to wait for forward progress on the outbound RSP channel before making forward
progress on the inbound REQ channel.
• An SN must make forward progress on the inbound REQ channel without requiring forward progress on the
outbound DAT channel.
• An SN must make forward progress on the inbound DAT channel without requiring forward progress on any
other channel.
12-316 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.5 Port
12.5 Port
A Port is defined as the set of all links at the interface of a node.
Figure 12-4 shows the relationship between links, channels, and port. See Node interface definitions on page 12-318
for the specific node requirements, See Channel interface signals on page 12-320, and Chapter 13 Link Handshake
for signal details.
Port
RN-F
TXSACTIVE
RXSACTIVE
Outbound Link
TXLINKACTIVEREQ
TXLINKACTIVEACK
REQ channel
TXREQFLITPEND
TXREQFLITV
TXREQFLIT
TXREQLCRDV
TX
RSP channel
TXRSPFLITPEND
TXRSPFLITV
TXRSPFLIT
TXRSPLCRDV
DAT channel
TXDATFLITPEND
TXDATFLITV
Inbound Link TXDATFLT
TXDATLCRDV
RXLINKACTIVEREQ
RXLINKACTIVEACK
RSP channel
RXRSPFLITPEND
RXRSPFLITV
RXRSPFLT
RXRSPLCRDV
RX
DAT channel
RXDATFLITPEND
RXDATFLITV
RXDATFLIT
RXDATLCRDV
SNP channel
RXSNPFLITPEND
RXSNPFLITV
RXSNPFLIT
RXSNPLCRDV
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-317
ID082919 Non-Confidential
12 Link Layer
12.6 Node interface definitions
Note
The LINKACTIVE interface pins and signals used by each node for link management are described in Chapter 13
Link Handshake.
RN-F
The RN-F interface uses all channels and is used by a fully coherent Requester such as a core or cluster. Figure 12-5
shows the RN-F interface.
ICN
RN-F
TXREQ REQ RXREQ
RXRSP RSP TXRSP
RXDAT DAT TXDAT
RXSNP SNP TXSNP
TXRSP RSP RXRSP
TXDAT DAT RXDAT
RN-D
The RN-D interface uses all channels and is used by an IO coherent node that processes DVM messages. Use of the
SNP channel is limited to DVM transactions. See DVM transaction flow on page 8-258 for details. Figure 12-6
shows the RN-D interface.
ICN
RN-D
TXREQ REQ RXREQ
RXRSP RSP TXRSP
RXDAT DAT TXDAT
RXSNP SNP(DVM) TXSNP
TXRSP RSP RXRSP
TXDAT DAT RXDAT
12-318 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.6 Node interface definitions
RN-I
The RN-I interface uses all channels, with the exception of the SNP channel, and is used by an IO coherent Request
Node such as a GPU or IO bridge. A SNP channel is not required because an RN-I node does not include a
hardware-coherent cache or TLB. Figure 12-7 shows the RN-I interface.
ICN
RN-I
TXREQ REQ RXREQ
RXRSP RSP TXRSP
RXDAT DAT TXDAT
TXRSP RSP RXRSP
TXDAT DAT RXDAT
ICN
SN-F - SN-I
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-319
ID082919 Non-Confidential
12 Link Layer
12.7 Channel interface signals
Transmitter Receiver
TXREQFLITPEND REQFLITPEND RXREQFLITPEND
TXREQFLITV REQFLITV RXREQFLITV
TXREQFLIT REQFLIT[(R-1):0] RXREQFLIT
Signal Description
REQFLITPEND Request Flit Pending. Early indication that a request flit might be transmitted in the following
cycle. See Flit level clock gating on page 13-359.
REQFLITV Request Flit Valid. The transmitter sets this signal HIGH to indicate when REQFLIT[(R-1):0] is
valid.
REQFLIT[(R-1):0] Request Flit. See Request flit on page 12-324 for a description of the request flit format.
REQLCRDV Request L-Credit Valid. The receiver sets this signal HIGH to return a request channel L-Credit to
a transmitter. See L-Credit flow control on page 13-357.
12-320 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.7 Channel interface signals
Transmitter Receiver
TXRSPFLITPEND RSPFLITPEND RXRSPFLITPEND
TXRSPFLITV RSPFLITV RXRSPFLITV
TXRSPFLIT RSPFLIT[(T-1):0] RXRSPFLIT
Signal Description
RSPFLITPEND Response Flit Pending. Early indication that a response flit might be transmitted in the following
cycle. See Flit level clock gating on page 13-359.
RSPFLITV Response Flit Valid. The transmitter sets this signal HIGH to indicate when RSPFLIT[(T-1):0] is
valid.
RSPFLIT[(T-1):0] Response Flit. See Response flit on page 12-325 for a description of the response flit format.
RSPLCRDV Response L-Credit Valid. The receiver sets this signal HIGH to return a response channel L-Credit
to a transmitter. See L-Credit flow control on page 13-357.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-321
ID082919 Non-Confidential
12 Link Layer
12.7 Channel interface signals
Transmitter Receiver
TXSNPFLITPEND SNPFLITPEND RXSNPFLITPEND
TXSNPFLITV SNPFLITV RXSNPFLITV
TXSNPFLIT SNPFLIT[(S-1):0] RXSNPFLIT
Signal Description
SNPFLITPEND Snoop Flit Pending. Early indication that a snoop flit might be transmitted in the following cycle.
See Flit level clock gating on page 13-359.
SNPFLITV Snoop Flit Valid. The transmitter sets this signal HIGH to indicate when SNPFLIT[(S-1):0] is
valid.
SNPFLIT[(S-1):0] Snoop Flit. See Snoop flit on page 12-326 for a description of the snoop flit format.
SNPLCRDV Snoop L-Credit Valid. The receiver sets this signal HIGH to return a snoop channel L-Credit to a
transmitter. See L-Credit flow control on page 13-357.
12-322 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.7 Channel interface signals
Transmitter Receiver
TXDATFLITPEND DATFLITPEND RXDATFLITPEND
TXDATFLITV DATFLITV RXDATFLITV
TXDATFLIT DATFLIT[(D-1):0] RXDATFLIT
Signal Description
DATFLITPEND Data Flit Pending. Early indication that a data flit might be transmitted in the following cycle. See
Flit level clock gating on page 13-359.
DATFLITV Data Flit Valid. The transmitter sets this signal HIGH to indicate when DATFLIT[(D–1):0] is
valid.
DATFLIT[(D-1):0] Data Flit. See Data flit on page 12-327 for a description of the data flit format.
DATLCRDV Data L-Credit Valid. The receiver sets this signal HIGH to return a data channel L-Credit to a
transmitter. See L-Credit flow control on page 13-357.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-323
ID082919 Non-Confidential
12 Link Layer
12.8 Flit packet definitions
REQFLIT[(R-1):0] format
QoS 4 -
TxnID 10 -
Opcode 6 -
Size 3 -
NS 1 -
LikelyShared 1 -
AllowRetry 1 -
Order 2 -
PCrdType 4 -
MemAttr 4 -
SnpAttr 1 -
12-324 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.8 Flit packet definitions
REQFLIT[(R-1):0] format
ExpCompAck 1 -
TraceTag 1 -
M = 11 -
RSPFLIT[(T-1):0] format
QoS 4 -
TxnID 10 -
Opcode 4 -
RespErr 2 -
Resp 3 -
CBusy 3 -
DBID[9:0] 10 -
{0b00000, SBZ
PGroupID} Used in CleanSharedPersistSep transaction
PCrdType 4 -
TraceTag 1 -
Total T = 58 to 66 -
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-325
ID082919 Non-Confidential
12 Link Layer
12.8 Flit packet definitions
SNPFLIT[(S-1):0] format
QoS 4 -
TxnID 10 -
Opcode 5 -
NS 1 -
DoNotGoToSD 1 -
DoNotDataPull
RetToSrc 1 -
TraceTag 1 -
M = 11 -
Total S = 88 to 104 + M -
12-326 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.8 Flit packet definitions
The number of data flits required is dependent on the number of data bytes, and the data bus width. See Data
packetization on page 2-120.
The data channel interface supports a 128-bit, 256-bit, and 512-bit data bus width. There are three data flit formats
defined, one for each of the three data bus widths supported at the data channel interface.
DataCheck (DC) field width is either zero or equal to the width of the Data field divided by 8.
Poison (P) field width is either zero or equal to the width of the Data field divided by 64.
DATFLIT[D-1:0] format
QoS 4 -
TxnID 10 -
RespErr 2 -
Resp 3 -
{0b0, 4 SBZ
FwdState} Used for DCT
{0b0, SBZ
DataPull} Used in Stash transactions
DataSource[3:0] Indicates Data source in a response
CBusy 3 -
DBID[9:0] 10 -
CCID 2 -
DataID 2 -
TraceTag 1 -
BE 16, 32, 64 -
Poison P = 0, 2, 4, 8 -
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-327
ID082919 Non-Confidential
12 Link Layer
12.8 Flit packet definitions
DATFLIT[D-1:0] format
12-328 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-329
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.1 TgtID
Target Identifier associated with the message. The node ID of the component to which the message is targeted. This
is used by the interconnect to determine the port to which the message is sent. See Details of transaction identifier
fields on page 2-74.
12.9.2 SrcID
Source Identifier associated with the message. The node ID of the component from which the message is sent. This
is used by the interconnect to determine the port from which the message has been sent. See Details of transaction
identifier fields on page 2-74.
12.9.3 HomeNID
Home Identifier associated with the original request. The Requester uses the value in this field to determine the
TgtID of the CompAck to be sent in response to CompData. See Details of transaction identifier fields on page 2-74.
12.9.4 ReturnNID
Return NID. Identifies the node to which the Slave sends a CompData response, or a DataSepResp response, or a
Persist response. The value can be either the NID of Home or the Requester that originated the transaction. See
Details of transaction identifier fields on page 2-74.
Applicable from Home to Slave in ReadNoSnp, ReadNoSnpSep, CleanSharedPersistSep and non-store Atomics.
Inapplicable and must be zero for all other requests. For Stash requests, the same bits in the packet are used for
StashNID.
12.9.5 FwdNID
Forward NID. Identifies the Requester to which the CompData response can be forwarded. The value must be the
NID of the Requester that initiated the transaction. See Details of transaction identifier fields on page 2-74.
12.9.6 LPID
Logical Processor Identifier. Used in conjunction with the SrcID to uniquely identify the logical processor that
generated the request. See Logical Processor Identifier on page 2-98.
For Persistent CMO requests, the same bits in the packet are used for PGroupID.
12-330 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.7 PGroupID
Persistence Group ID. Used by a Requester to process different sets of CleanSharedPersistSep transactions by
grouping them together and identifying each using PGroupID.
Applicable in the CleanSharedPersistSep request and the Persist and CompPersist responses.
Inapplicable and must be set to zero in all other requests and responses.
In requests, when applicable, the same bits in the packet are used for LPID.
In responses, when applicable, the same bits in the packet are used for DBID.
12.9.8 StashNID
Stash NID. Identifies the target of the stash request. Provides a valid stash target value when the corresponding
StashNIDValid bit is asserted. See Stash target identifiers on page 7-255.
Inapplicable and must be zero for all other requests. For ReadNoSnp and ReadNoSnpSep requests, the same bits in
the packet are used for ReturnNID.
12.9.9 StashNIDValid
Stash NID valid. Indicates if StashNID field has a valid value. See Stash target identifiers on page 7-255.
Applicable in Stash requests, inapplicable and must be set to zero in all other requests.
StashNIDValid Description
12.9.10 StashLPID
Stash Logical Processor ID. Provides a valid Logical Processor target value within the Request Node specified by
StashNID. See Stash target identifiers on page 7-255.
Inapplicable and must be zero for all other requests. For ReadNoSnp requests the same bits in the packet are used
for ReturnTxnID.
Inapplicable and must be zero for all other snoop requests. For Fwd snoops the same bits in the packet are used for
FwdTxnID and for SnpDVMOp snoops the same bits in the packet are used for VMIDExt.
12.9.11 StashLPIDValid
Stash LPID valid. Indicates if the StashLPID field has a valid value. See Stash target identifiers on page 7-255.
Applicable in Stash requests and Stash type snoop requests, inapplicable and must be set to zero in all other requests.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-331
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
StashLPIDValid Description
0 1 Reserved
12.9.12 TxnID
Transaction Identifier associated with the message. When there are multiple outstanding transactions from a given
source node they will each use a unique transaction ID. See Details of transaction identifier fields on page 2-74.
Link flits do not have a unique ID. Table 12-13 shows the link flit TxnID field value encodings.
TxnID Description
0x001 to Reserved
0x3FF
12.9.13 ReturnTxnID
Return TxnID. Identifies the value the Slave must use in the TxnID field of the CompData, and DataSepResp
response. It can be either the TxnID generated by Home for this transaction or the TxnID in the Request packet from
the Requester that originated the transaction. See Details of transaction identifier fields on page 2-74.
Applicable only in ReadNoSnp, ReadNoSnpSep and non-store Atomics from Home to Slave.
Inapplicable and must be set to zero for all other requests. For Stash requests the same bits in the packet are used
for StashLPID.
12.9.14 FwdTxnID
Identifies the TxnID of the original Request associated with the Snoop transaction. See Details of transaction
identifier fields on page 2-74.
Inapplicable and must be set to zero in all other snoop requests. For Stash snoops the same bits in the packet are
used for StashLPID and for SnpDVMOp snoops the same bits in the packet are used for VMIDExt.
12-332 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.15 DBID
Data Buffer Identifier. The DBID field value in the response packet from a Completer is used as the TxnID for
CompAck or WriteData sent from the Requester. In Snoop responses with data pull, this field value indicates the
value to be used in the TxnID field of data pull response messages. See Details of transaction identifier fields on
page 2-74.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-333
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.16 Opcode
Specifies the operation to be carried out. The Opcode encodings are specific to each channel. See:
• REQ channel opcodes.
• RSP channel opcodes on page 12-336.
• SNP channel opcodes on page 12-337.
• DAT channel opcodes on page 12-338.
0x00 ReqLCrdReturn
0x01 ReadShared
0x02 ReadClean
0x03 ReadOnce
0x04 ReadNoSnp
0x05 PCrdReturn
0x06 Reserved
0x07 ReadUnique
0x08 CleanShared
0x09 CleanInvalid
0x0A MakeInvalid
0x0B CleanUnique
0x0C MakeUnique
0x0D Evict
0x10 Reserved
0x11 ReadNoSnpSep
0x12 Reserved
0x13 CleanSharedPersistSep
0x14 DVMOp
0x15 WriteEvictFull
0x17 WriteCleanFull
0x18 WriteUniquePtl
12-334 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
0x19 WriteUniqueFull
0x1A WriteBackPtl
0x1B WriteBackFull
0x1C WriteNoSnpPtl
0x1D WriteNoSnpFull
0x20 WriteUniqueFullStash
0x21 WriteUniquePtlStash
0x22 StashOnceShared
0x23 StashOnceUnique
0x24 ReadOnceCleanInvalid
0x25 ReadOnceMakeInvalid
0x26 ReadNotSharedDirty
0x27 CleanSharedPersist
0x38 AtomicSwap
0x39 AtomicCompare
0x3A PrefetchTgt
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-335
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
AtomicStore AtomicLoad
001 CLR
010 EOR
011 SET
100 SMAX
101 SMIN
110 UMAX
111 UMIN
0x0 RespLCrdReturn
0x1 SnpResp
0x2 CompAck
0x3 RetryAck
0x4 Comp
0x5 CompDBIDResp
0x6 DBIDResp
0x7 PCrdGrant
0x8 ReadReceipt
0x9 SnpRespFwded
0xA Reserved
0xB RespSepData
0xC Persist
0xD CompPersist
12-336 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
0x00 SnpLCrdReturn
0x01 SnpShared
0x02 SnpClean
0x03 SnpOnce
0x04 SnpNotSharedDirty
0x05 SnpUniqueStash
0x06 SnpMakeInvalidStash
0x07 SnpUnique
0x08 SnpCleanShared
0x09 SnpCleanInvalid
0x0A SnpMakeInvalid
0x0B SnpStashUnique
0x0C SnpStashShared
0x0D SnpDVMOp
0x10 Reserved
0x11 SnpSharedFwd
0x12 SnpCleanFwd
0x13 SnpOnceFwd
0x14 SnpNotSharedDirtyFwd
0x17 SnpUniqueFwd
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-337
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
0x0 DataLCrdReturn
0x1 SnpRespData
0x2 CopyBackWrData
0x3 NonCopyBackWrData
0x4 CompData
0x5 SnpRespDataPtl
0x6 SnpRespDataFwded
0x7 WriteDataCancel
0x8-0xA Reserved
0xB DataSepResp
0xC NCBWrDataCompAck
0xD-0xF Reserved
12.9.17 Deep
Deep persistence. Used by the Requester to indicate that the Persist response must not be sent until all earlier writes
are written to the final destination.
• The Completer must send Persist response after all the earlier writes have reached the Point of
Persistence(PoP).
— The PoP is the point at which it is guaranteed that sufficient time is available to make the data
persistent after loss of power.
• The Completer must send the Persist response only after all earlier writes are written to the final destination,
not just the PoP.
— The final destination is the point at which no time is required to make the data persistent after loss of
power, thus preserving data even when battery failure occurs.
If the receiver of the request does not support the Deep attribute, then it can ignore the attribute value and treat the
request as having the Deep attribute deasserted.
An error response must not be given to indicate that deep persistence is not supported.
12-338 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.18 Addr
Address. Specifies the address associated with the message.
This specification supports a Physical Address (PA) of 44 to 52 bits. This permits the REQ and SNP packets to
support 49 to 53 bits of Virtual Address (VA) in DVM operations.
• Request messages support a 44 to 52 bit address field, Addr[(43-51):0].
• Snoop messages support a 41 to 49 bit address field, Addr[(43-51):3]:
— Addr[(43-51):6] specifies the aligned address of the 64-byte cache line.
— Addr[5:4] indicates the 16-byte critical chunk within the cache line. See Critical Chunk Identifier on
page 2-123.
— Addr[3] is relevant in SnpDVMOp, for all other Snoop packets it is Don’t Care and can take any value.
12.9.19 NS
Non Secure. Indicates a Non-secure access or a Secure access. See Non-secure bit on page 2-110.
NS Description
0 Secure access
1 Non-secure access
12.9.20 Size
Size. Specifies the size of the data associated with the transaction. See Data size on page 2-118.
Size[2:0] Bytes
0b000 1
0b001 2
0b010 4
0b011 8
0b100 16
0b101 32
0b110 64
0b111 Reserved
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-339
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.21 MemAttr
Memory Attribute. Memory attribute associated with the transaction.
MemAttr[3:0] Description
[3] Allocate hint bit. Indicates whether or not the cache receiving the transaction is recommended
to allocate the transaction:
0 Recommend that it does not allocate.
1 Recommend that it allocates.
[2] Cacheable bit. Indicates a Cacheable transaction for which the cache, when present, must be
looked up in servicing the transaction:
0 Non-cacheable. Looking up a cache is not required.
1 Cacheable. Looking up a cache is required.
[1] Device bit. Indicates if the memory type associated with the transaction is Device or Normal:
0 Normal memory type.
1 Device memory type.
[0] Early Write Acknowledge bit. Specifies the Early Write Acknowledge status for the
transaction:
0 Early Write Acknowledge not permitted.
1 Early Write Acknowledge permitted.
12.9.22 SnpAttr
Snoop Attribute. Specifies the snoop attribute associated with the transaction.
0 Non-snoopable
1 Snoopable
12-340 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.23 LikelyShared
Likely Shared. Indicates whether the requested data is likely to be shared with another RN. See Likely Shared on
page 2-115.
LikelyShared Description
12.9.24 Order
Specifies the ordering requirements for a transaction. See Ordering on page 2-99 for more information on the
ordering requirements.
0b11 Endpoint Order, which also includes Request Order Not applicable in requests from
HN-F to SN-F.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-341
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.25 Excl
Exclusive. Indicates that the corresponding transaction is an Exclusive type transaction. The Exclusive bit must only
be used with the following transactions:
• ReadNotSharedDirty.
• ReadShared.
• ReadClean.
• CleanUnique.
• ReadNoSnp.
• WriteNoSnp.
Excl Description
0 Normal transaction
1 Exclusive transaction
12.9.26 Endian
Endian. Indicates the endianness of Data in an Atomic transaction. See Endianness on page 2-122.
Applicable in Atomic requests, inapplicable in all other requests and must be set to zero.
Endian Description
0 Little Endian
1 Big Endian
12.9.27 AllowRetry
Allow Retry. Specifies that the request is being sent without a P-Credit and that the target can determine if a retry
response is given. See Transaction Retry mechanism on page 2-131.
AllowRetry Description
12-342 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.28 ExpCompAck
Expect CompAck. Indicates that the transaction will include a CompAck response.
ExpCompAck Description
12.9.29 SnoopMe
SnoopMe. Indicates that Home must determine whether to send a snoop to the Requester. See Atomics on page 2-62.
SnoopMe Description
1 Home must send a Snoop to the Requester if it determines the cache line might be present at the
Requester.
12.9.30 RetToSrc
Return to Source. Requesting Snoopee to return a copy of the cache line to Home.
For RetToSrc bit semantics see Returning Data with Snoop response on page 4-198.
12.9.31 DataPull
Data Pull. Indicates the inclusion of a Read request, also referred to as a Data Pull, in the Snoop response. See Snoop
requests and Data Pull on page 7-250.
Applicable in SnpResp and SnpRespData response to a Stash request, not applicable in all other Snoop responses.
When the DataPull bit is set in a SnpRespData message it must be set in all packets of that response message.
0b001 Read
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-343
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.32 DoNotGoToSD
Do not transition to SD state. An attribute in a snoop request indicating if a Snoopee is required to not transition to
SD state. See Do not transition to SD on page 4-199.
When inapplicable must be set to zero. For Stash snoop requests the same bits in the packet are used for
DoNotDataPull.
DoNotGoToSD Description
12-344 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.33 DoNotDataPull
Do not Data Pull. Do not combine a Read request with Snoop response.
DoNotDataPull shares the SNP packet field with DoNotGoToSD. See Snoop flit on page 12-326.
This field is not present in Non-stash snoops. For Non-stash requests except SnpDVMOp, the same bit in the packet
is used for DoNotGoToSD.
DoNotDataPull Description
0 Data Pull with Stash snoop response is permitted but not required.
12.9.34 QoS
Quality of Service priority level. Ascending values of QoS indicate higher priority levels. See Chapter 10 Quality
of Service for more information.
12.9.35 PCrdType
Protocol Credit Type. Indicates the type of credit being granted or returned. See Transaction Retry mechanism on
page 2-131.
PCrdType Description
12.9.36 TraceTag
Trace Tag. A bit in a packet used to tag the packets associated with a transaction for tracing purposes.
TraceTag Description
1 Packet is tagged.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-345
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.37 MPAM
Memory System Performance Resource Partitioning and Monitoring. It is used to efficiently utilize the memory
resources among users and to monitor their use. See MPAM on page 11-305.
12.9.38 VMIDExt
Virtual Machine Identifier extension. It is used to extend VMID value from 8-bits to 16-bits. See DVMOp payload
on page 8-268.
12.9.39 Resp
Response Status. The Resp field must have the same value in all data flits of a multi-flit data transfer.
Resp[2:0] Description
Resp[2] PassDirty. Indicates that the data included in the response message is Dirty with
respect to memory and that the responsibility of writing back the cache line is being
passed to the recipient of the response message.
0 Returned data is not Dirty.
1 Returned data is Dirty and the responsibility of writing back the
cache line is being passed on.
Resp[1:0] For snoop responses, this field indicates the final state of the snooped RN-F.
For completion responses, this field indicates the final state in the RN.
For write data responses, this field indicates the state of the data in the RN when
the data is sent.
Table 12-36 Valid Resp value encodings for different message types
0b001 SC
0b010 UC, UD
0b011 SD
0b110 UC_PD
0b111 - Reserved.
12-346 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
Table 12-36 Valid Resp value encodings for different message types (continued)
0b001 SC
0b010 UC
0b011 - Reserved.
0b100 -
0b101 -
WriteData responses 0b000 I State of the cache line at the RN-F when data is sent.
0b001 SC
0b010 UC
0b011 - Reserved.
0b100 -
0b101 -
0b110 UD_PD State of the cache line at the RN-F when data is sent.
Responsibility for updating memory is passed to
0b111 SD_PD Home.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-347
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.40 FwdState
Forward State. Indicates the state in the CompData sent from the Snoopee to the Requester. Applicable in
SnpRespFwded and SnpRespDataFwded, inapplicable in all other Snoop responses and must be set to zero.
FwdState[2:0] Description
FwdState[2] PassDirty.
0 Forwarded data is not Dirty.
1 Forwarded data is Dirty and the responsibility of writing back the cache line
is passed on to the Requester.
FwdState[1:0] Indicates the final state at the Requester. See Table 12-38.
0b001 SC
0b010 UC
0b011 - Reserved.
0b100 -
0b101 -
12.9.41 CBusy
Completer Busy. A mechanism for the Completer of a transaction to indicate its current level of activity. The CBusy
value encodings are IMPLEMENTATION DEFINED. See Completer Busy on page 11-307.
12-348 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.42 RespErr
Response Error. This field indicates the error status of the response. See Chapter 9 Error Handling.
RespErr[1:0] Description
0b01 Exclusive Okay. Indicates that either the read or write portion of an Exclusive access was successful.
12.9.43 Data
Data payload. This is the data payload that is being transported in a Data packet.
12.9.44 CCID
Critical Chunk Identifier. The CCID indicates the critical 128-bit chunk of the data that is being requested. See
Critical Chunk Identifier on page 2-123.
0b00 Data[127:0]
0b01 Data[255:128]
0b10 Data[383:256]
0b11 Data[511:384]
12.9.45 DataID
Data Identifier. The DataID indicates the relative position of the data chunk within the 512-bit cache line that is
being transferred. See Data packetization on page 2-120.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-349
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
Table 12-41 DataID and the bytes within a packet for different data widths
12-350 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.9 Protocol flit fields
12.9.46 BE
Byte Enable. Indicates if the byte of data corresponding to this byte enable bit is valid. The BE field is defined for
write data, DVM payload, and snoop response data transfers. For read response data transfers, this field is
inapplicable and can take any value. It consists of a bit for each data byte in the DAT flit. See Byte Enables on
page 2-119.
BE Byte enable
0 Corresponding byte of data is not valid.
1 Corresponding byte of data is valid.
12.9.47 DataCheck
Data Check. Used to supply the DataCheck bit for the corresponding byte of Data. See Data Check on page 9-291.
12.9.48 Poison
Indicates if the 64-bit chunk of data corresponding to a Poison bit is poisoned, that is, has an error, and must not be
consumed. See Poison on page 9-290.
12.9.49 DataSource
Data Source. Identifies the Sender of the data response. See DataSource value assignment on page 11-302.
Applicable in CompData and DataSepResp responses in Read and Atomic transactions, and SnpRespData and
SnpRespDataPtl responses in Non-stash type Snoop transactions. DataSource is not applicable, and must be set to
zero, in all other responses.
0b0001 - 0b0101 IMPLEMENTATION DEFINED See Suggested DataSource values on page 11-303
0b0110 PrefetchTgt was useful Indication from memory that the earlier sent prefetch was useful or
memory received a prefetch.
0b0111 PrefetchTgt was not useful Indication from memory that the earlier sent prefetch was not useful
or memory did not receive a prefetch.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-351
ID082919 Non-Confidential
12 Link Layer
12.9 Protocol flit fields
12.9.50 RSVDC
Reserved for customer use. Any value is valid in a Protocol flit. Propagation of this field through the interconnect
is IMPLEMENTATION DEFINED.
When connecting TX and RX flit interfaces that have mismatched RSVDC widths:
• The corresponding lower-order bits of the RSVDC field must be connected at each side of the interface.
• The higher-order RSVDC bits at the RX interface that do not have corresponding bits at the TX interface
must be tied LOW.
12-352 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
12 Link Layer
12.10 Link flit
A link flit is identified by a zero value in the Opcode field. The TxnID field of the link flit is required to be zero.
The remaining fields are not used and can be any value. See Opcode on page 12-334 for the link flit type encoding.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 12-353
ID082919 Non-Confidential
12 Link Layer
12.10 Link flit
12-354 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 13
Link Handshake
This chapter describes the link handshake requirements. It contains the following sections:
• Clock, and initialization on page 13-356.
• Link layer Credit on page 13-357.
• Low power signaling on page 13-358.
• Flit level clock gating on page 13-359.
• Interface activation and deactivation on page 13-360.
• Transmit and receive link Interaction on page 13-366.
• Protocol layer activity indication on page 13-372.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-355
ID082919 Non-Confidential
13 Link Handshake
13.1 Clock, and initialization
13.1.1 Clock
This architecture specification does not define a specific clocking microarchitecture, but it is expected that all
devices, interconnects, etc. will include one or more clocks that can be relied upon by other Link layer functions
that require synchronous communication. A generic clock signal is referred to as CLK in the following sections,
where applicable.
13.1.2 Reset
This architecture specification does not define a specific reset microarchitecture, but it is expected that all devices,
interconnects, etc will include a specific reset deassertion event that can be relied upon by other Link layer
functions. A generic reset signal is referred to as RESETn in the following sections, where applicable.
13.1.3 Initialization
During reset the following interface signals must be deasserted by the component:
• TX***LCRDV.
• TX***FLITV.
• TXLINKACTIVEREQ and RXLINKACTIVEACK.
The earliest point after reset that it is permitted to begin driving these signals HIGH is at a rising CLK edge after
RESETn is HIGH.
13-356 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.2 Link layer Credit
Each transfer of a flit from the transmitter to the receiver consumes one L-Credit.
The minimum number of L-Credits that a receiver can provide is one. The maximum number of L-Credits that a
receiver can provide is 15.
A receiver must guarantee that it can accept all the flits for which it has issued L-Credits.
When the link is active, the receiver must provide L-Credits in a timely manner without requiring any action on the
part of the transmitter.
Note
An L-Credit cannot be used in the cycle it is received.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-357
ID082919 Non-Confidential
13 Link Handshake
13.3 Low power signaling
Link Activation
Link activation and deactivation is supported to permit the interface to be taken to a safe state, so
that both-sides of the interface can enter a low power state that permits them to be either clock-gated
or power-gated.
13-358 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.4 Flit level clock gating
CLK
FLITPEND
FLITV
FLIT
flit flit
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-359
ID082919 Non-Confidential
13 Link Handshake
13.5 Interface activation and deactivation
On exit from reset, or when moving to a full running operational state, the interface will start in an idle state and the
transfer of flits can only commence when L-Credits have been exchanged. L-Credits can only be exchanged when
the Sender of the credits knows the receiver is ready to receive them.
A two signal, four phase, handshake mechanism is used. This two signal interface is used for all channels traveling
in the same direction, rather than being required for each individual channel. An entire interface uses a total of four
signals, two signals are used for all the transmit channels and two signals are used for all the receive channels.
This section describes the operation of the LINKACTIVEREQ and LINKACTIVEACK handshake pairs for all
channels moving in one direction. Transmit and receive link Interaction on page 13-366 describes the interaction
between the handshake pairs for the transmit channels and those for the receive channels.
For a single channel, or group of channels traveling in the same direction, Figure 13-2 shows the relationship
between the Payload, Credit, LINKACTIVEREQ and LINKACTIVEACK signals.
LINKACTIVEREQ
LINKACTIVEACK
Transmitter Receiver
Payload
Credit
As Figure 13-2 shows, during normal operation the transmitter, which sends the payload flits, requires a credit
before it can send a flit. A credit is passed from the receiver when it has resources available to accept a flit:
• On exit from reset, credits are held by the receiver and must be passed to the transmitter before flit transfer
can begin.
• During normal operation, there is an ongoing exchange of flits and credits between the two sides of the
interface.
• Before entering a low power state, the sending of payload flits must be stopped and all credits must be
returned to the receiver, this effectively returns the interface to the same state that it was at immediately after
reset.
13-360 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.5 Interface activation and deactivation
RUN There is an ongoing exchange of flits and credits between the two components.
STOP The interface is in a low power state and it is not operational. All credits are held by the
receiver and the transmitter is not permitted to send any flits.
ACTIVATE This state is used when moving from the STOP state to the RUN state.
DEACTIVATE This state is used when moving from the RUN state to the STOP state.
RUN and STOP are stable states and when one of these states is entered a channel can remain in this state for an
indefinite period of time.
DEACTIVATE and ACTIVATE are transient states and it is expected that when one of these states is entered a
channel will move to the next stable state in a relatively short period of time.
Note
The specification does not define a maximum period of time in a transient state, but it is expected that for any given
implementation it is deterministic.
The state is determined by the LINKACTIVEREQ and LINKACTIVEACK signals. Figure 13-3 shows the
relationship between the four states.
STOP
00 10
DEACTIVATE ACTIVATE
01 11
RUN
LINKACTIVEREQ LINKACTIVEACK
STOP 0 0
ACTIVATE 1 0
RUN 1 1
DEACTIVATE 0 1
Table 13-2 on page 13-362 describes the behavior of both the transmitter and the receiver of a single link for each
of the four states.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-361
ID082919 Non-Confidential
13 Link Handshake
13.5 Interface activation and deactivation
STOP The transmitter has no credits and must not send any flits. The receiver is guaranteed not to receive any flits.
The transmitter is guaranteed not to receive any credits. The receiver must not send any credits.
The transmitter must assert LINKACTIVEREQ to
move to the ACTIVATE state if it has flits to send.
ACTIVATE The transmitter must not send any flits. The receiver is guaranteed not to receive any flits.
(ACT) The transmitter must be prepared to receive credits in this The receiver must not send any credits.
state, although it must not use them until in the RUN The ACTIVATE state is a transient state and the
state. receiver controls the move to the RUN state by
The transmitter remains in the ACTIVATE state while it asserting LINKACTIVEACK.
is waiting for the receiver to acknowledge the move to The receiver must assert LINKACTIVEACK and
the RUN state. move to the RUN state before sending credits. It is
Note permitted to assert LINKACTIVEACK and send a
credit in the same cycle.
The transmitter will only receive credits in the
ACTIVATE state when there is a race between the Note
receiver sending credits and asserting It can appear that a receiver has sent credits in the
LINKACTIVEACK to move to the RUN state. ACTIVATE state if there is a race between the receiver
sending credits and asserting LINKACTIVEACK to
move to the RUN state.
RUN The transmitter can receive credits. The receiver can receive flits corresponding to the
The transmitter can send flits when it has credits credits it has sent.
available. The receiver sends credits when it has resources
The transmitter deasserts LINKACTIVEREQ to exit available to accept further flits.
from this state if it wants to move to a low power state. The receiver must remain in the RUN state until it
observes the deassertion of LINKACTIVEREQ.
DEACTIVATE The transmitter must return credits using Protocol flits or During this state the receiver stops sending credits and
(DEACT) L-Credit return flits. collects all returned credits.
It is recommended that the transmitter enters the The receiver must be prepared to receive flits, other
DEACTIVATE state only when it has no more Protocol than Link flits to return credits, in this state. This is not
flits to send. Therefore, it is expected that the transmitter expected, but can occur.
will return credits using only L-Credit return flits. The receiver is permitted to send credits when first
The transmitter must be prepared to continue receiving entering this state. However, it must have stopped
credits. For each additional credit received it must send sending credits and had all credits returned before
an L-Credit return flit to return the credit. exiting this state.
The transmitter remains in the DEACTIVATE state while The receiver will receive L-Credit return flits until all
it is waiting for the receiver to acknowledge the move to credits are returned.
the STOP state. At this point, it will be guaranteed to The receiver must wait for all credits to be returned
receive no more credits. before deasserting LINKACTIVEACK.
Note
The receiver will only receive flits in the
DEACTIVATE state when there is a race between the
transmitter sending the last remaining flits and
deasserting LINKACTIVEREQ to move to the
DEACTIVATE state.
13-362 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.5 Interface activation and deactivation
Table 13-5 on page 13-370 summarizes the required behavior described in detail in Table 13-2 on page 13-362.
Table 13-3 Summary of behavior for each Request and Acknowledge state
Transmitter Receiver
DEACT Must not send flits, except for credit return flits. Must accept flits.
Must accept credits. Must stop sending credits.
Must return credits.
Race conditions
There are two situations where one side of the interface performs two actions at or around the same time:
• Changing the LINKACTIVEREQ or LINKACTIVEACK signal to change the state of the interface.
• Sending an associated credit or flit around the time of the state change.
• When the receiver is asserting LINKACTIVEACK, to move from ACTIVATE to RUN, it is also permitted
to start sending credits:
— A race can occur between the sending of a credit, which is expected in the new state, and the assertion
of the LINKACTIVEACK signal indicating the state change.
— This is acceptable because the transmitter is required to be able to accept the credit in the previous state
as well as in the new state.
— For the receiver, it is permitted to send a credit in the same cycle that LINKACTIVEACK is asserted.
— For the transmitter, it is required to accept a credit both before and after the assertion of
LINKACTIVEACK.
• When the transmitter is deasserting LINKACTIVEREQ, to move from RUN to DEACTIVATE, it must stop
sending flits, other than L-Credit return flits:
— A race can occur between the last flit sent, which is expected in the previous state, and the deassertion
of the LINKACTIVEREQ signal indicating the state change.
— This is acceptable because the receiver is required to be able to accept the flit in the next state, as well
as in the previous state.
— For the transmitter, it is permitted to send a flit in the last cycle that LINKACTIVEREQ is asserted.
— For the receiver, it is required to accept flits both before and after the deassertion of
LINKACTIVEREQ.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-363
ID082919 Non-Confidential
13 Link Handshake
13.5 Interface activation and deactivation
If the state change requires a component to start sending flits or credits, then there is no defined limit on the time
taken for the component to start the new behavior. This new behavior will only occur in the new state.
If the state change requires a component to stop sending flits or credits, then the component is permitted to take
some time to respond. In this scenario, it is possible to see behavior when first entering a new state which is not
expected within that state.
The state change from RUN to DEACTIVATE is the point at which flits and credits stop being sent.
Flits are sent by the transmitter, which is also the component that determines the state change, and therefore the
transmitter can ensure flits are not sent after the state change. However, a race condition might still occur as
described in Race conditions on page 13-363.
Credits are sent by the receiver, but that component does not determine the state change. The receiver might take
some time to react to the state change and therefore it is possible for credits to be sent when first entering the
DEACTIVATE state.
The protocol requires that the receiver has stopped sending credits and has had all credits returned before it signals
the change from DEACTIVATE to STOP.
The transmitter itself can determine that a state change is needed. This can happen through a number of mechanisms.
The following examples are not exhaustive:
• The transmitter can determine that it has flits to send, so must move from STOP to RUN.
• The transmitter can determine that it has no activity to perform for a significant period of time, so can move
from RUN to STOP.
• The transmitter can observe an independent sideband signal that indicates it should move either from RUN
to STOP, or from STOP to RUN.
• The transmitter can determine that a transaction is not fully complete and therefore the channels should
remain in RUN state until all activity has completed.
• The transmitter can observe a state change on the channel, or set of channels, that are used in the opposite
direction. See Transmit and receive link Interaction on page 13-366.
13-364 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.5 Interface activation and deactivation
LINKACTIVEREQ
LINKACTIVEACK
Payload flit
Credit
Transmitter Receiver
Payload flit
Credit
Payload flit
Credit
The rules regarding the relationship between the LINKACTIVEREQ and LINKACTIVEACK signals must be
applied appropriately across all channels:
• When a state change requires the transmitter to be able to accept credits it must be able to accept credits on
all channels.
• When a state change requires the receiver to be able to accept flits it must be able to accept flits on all
channels.
• When the sending of flits must stop before a state change the sending of flits must stop on all channels.
• When the sending of credits must stop before a state change the sending of flits must stop on all channels.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-365
ID082919 Non-Confidential
13 Link Handshake
13.6 Transmit and receive link Interaction
13.6.1 Introduction
A single component has a number of different channels, some of which are inputs and some of which are outputs.
This specification requires that the activation and deactivation of the TXLINK and RXLINK are coordinated.
When the TXLINK and RXLINK are both in the stable STOP state:
• If the RXLINK moves to the ACTIVATE state, which is controlled by the component on the other side of the
interface, then it is required that the TXLINK also moves to the ACTIVATE state, in a timely manner.
• If a component moves the TXLINK to the ACTIVATE state, which it controls, then it can expect the
RXLINK to also move to the ACTIVATE state, in a timely manner.
When the TXLINK and RXLINK are both in the stable RUN state:
• If the RXLINK moves to the DEACTIVATE state, which is controlled by the component on the other side of
the interface, then it is required that the TXLINK also moves to the DEACTIVATE state, in a timely manner.
• If a component moves the TXLINK to the DEACTIVATE state, which it controls, then it can expect the
RXLINK to also move to the DEACTIVATE state, in a timely manner.
When the TXLINK and RXLINK are changing states, the rules about the sending and receiving of credits and flits
can be considered independently for each link.
13-366 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.6 Transmit and receive link Interaction
Banned
TxStop Remote TxStop TxStop
TxStop RxStop Initiate RxAct
Output
RxRun+
Race
Local
TXREQ Initiate
Async
TxAct TxAct TxAct TxAct
TxAct RxStop RxAct RxRun
Input
RxDeact+
Race
Async Pe
rm
TXACK Input itt
Race ed
Banned
TxRun+ TxRun TxRun Remote TxRun TxRun
TxRun RxStop RxAct RxRun Initiate RxDeact
Output
RxStop+
Race
Banned Pe Pe
TXREQ rm Local rm
Output itt itt
ed Initiate ed
Race
Async
TxDeact+ TxDeact TxDeact TxDeact TxDeact
TxDeact RxAct RxRun RxDeact RxStop
Input
RxAct+
Race
Async Pe Pe
TXACK rm rm
Input itt itt
Race ed ed
Banned Pe
rm
TXREQ Output itt
Race ed
TxAct+ TxAct
TxAct RxDeact RxStop
Figure 13-5 shows the combined Tx and Rx state machines for a single component:
• For clarity, shortened state names and signal names are used.
• A green arrow represents a transition that the local agent can control.
• A blue arrow represents a transition that is under the control of the remote agent on the other side of the
interface.
• A black arrow represents a transition that is made when both the local and remote agents make a transition
at the same time.
• Around the edge of Figure 13-5 is an indication of the individual Tx and Rx states, the green and blue arrows
show which agent controls the transition. There is also an indication of the signal change that causes the state
transition.
• A vertical or horizontal arrow is a state change caused by just one signal change, that is, only the Rx state
machine or the Tx state machine changes state, not both.
• A diagonal arrow is a state change caused by two signals changing at the same time. If the diagonal arrow is
green or blue then the same agent is changing both signals.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-367
ID082919 Non-Confidential
13 Link Handshake
13.6 Transmit and receive link Interaction
• There are a few cases where, by coincidence, a state change occurs due to two events, one on each side of the
link, occurring at the same time. This is always a diagonal path and is shown by a black arrow.
• The stub-lines show dead-end paths where an exit from a state is not permitted. The color of a stub-line
indicates which agent is responsible for ensuring that the path is not taken.
• The TxStop/RxStop and TxRun/RxRun states are expected to be stable states, and are typically the states
where the state machines stay for long periods of time. These states are highlighted with a bold outline. All
other states are considered transient states that are exited in a timely manner.
• The grey states, on the bottom right of Figure 13-5 on page 13-367, are replications of those on the top left.
They are shown to aid clarity and maintain the symmetry of the diagram.
• The yellow states can only be reached by observing a race between two input signals. The transition into these
states is labeled with Async Input Race. See Asynchronous race condition on page 13-370.
• The red states can only be reached by observing a race between two output signals. A race between two
outputs is not permitted at the edge of a component and therefore the transition into these states is labeled
with Banned Output Race. These states can only be observed at a midpoint between two components. See
Asynchronous race condition on page 13-370.
• The bold arrows are used to indicate the expected transitions around the state machine. These are described
in more detail in Expected transitions on page 13-369.
• The arrows labeled Permitted are state transactions that would not normally be expected, but they are
permitted by the protocol.
State naming
Figure 13-5 on page 13-367 shows the full set of states, including those that can only be reached through race
conditions. A more detailed discussion of race conditions can be found in Asynchronous race condition on
page 13-370.
There are two different TxStop/RxRun states, and two different TxRun/RxStop states. These states differ in how
they are reached and how it is permitted to exit from them. To differentiate between these states, a [+] suffix is used
to indicate which state machine, that is, Tx or Rx, is running ahead. For example:
• TxStop/RxRun+ indicates that the Tx state machine has remained in the previous Stop state, while the Rx
state machine has advanced to the next Run state.
• TxStop+/RxRun indicates that the Tx state machine has advanced to the next Stop state, while the Rx state
machine remains in the previous Run state.
13-368 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.6 Transmit and receive link Interaction
Banned
TxStop Remote TxStop TxStop
TxStop RxStop Initiate RxAct
Output
RxRun+
Race
Local
TXREQ Initiate
Async
TxAct TxAct TxAct TxAct
TxAct RxStop RxAct RxRun
Input
RxDeact+
Race
Async Pe
rm
TXACK Input itt
Race ed
Banned
TxRun+ TxRun TxRun Remote TxRun TxRun
TxRun RxStop RxAct RxRun Initiate RxDeact
Output
RxStop+
Race
Banned Pe Pe
TXREQ rm Local rm
Output itt itt
ed Initiate ed
Race
Async
TxDeact+ TxDeact TxDeact TxDeact TxDeact
TxDeact RxAct RxRun RxDeact RxStop
Input
RxAct+
Race
Async Pe Pe
TXACK rm rm
Input itt itt
Race ed ed
Banned Pe
rm
TXREQ Output itt
Race ed
TxAct+ TxAct
TxAct RxDeact RxStop
The difference between the two routes moving from TxStop/RxStop to TxRun/RxRun states compared to moving
from TxRun/RxRun to TxStop/RxStop states is due to the requirement to return Link layer Credits (L-Credits) in
the latter case. The differences are detailed in the following sections.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-369
ID082919 Non-Confidential
13 Link Handshake
13.6 Transmit and receive link Interaction
The annotations on the diagram arrows in Figure 13-6 on page 13-369 are:
Local Initiate Indicates that the local agent has initiated the process of leaving one stable state towards the
other stable state.
Remote Initiate Indicates that the remote agent on the other side of the interface has initiated the process of
leaving one stable state towards the other stable state.
There are four expected routes from a stable Run/Run to Stop/Stop state. Table 13-5 shows, in terms of the state
transitions, the four expected paths.
In the majority of cases, moving to the stable Run/Run or Stop/Stop state would be expected.
The most likely use case for wanting to move quickly out of one of the stable states is when an interface has started
to enter a low power state, but there is still some activity required. It might be that the low power state was entered
prematurely, or it might be that some new activity arose, by coincidence, while the low power state was being
entered. In this use case, it is desirable to be able to move back to the Run/Run state as quickly as possible.
• Output X must change after or at the same time as output Y, but it is not permitted to change before output Y.
In Figure 13-5 on page 13-367, these transitions are labeled as Banned Output Race and the resultant state is shown
in red.
It is possible to observe these states if monitoring the output signals at a point in the system where asynchronous
race conditions can result in two signals, that are asserted within the same cycle, are observed in different clock
cycles.
A component that is on the other side of the interface, and has the two signals as inputs, can see the state transition
if an asynchronous input race occurs. These transitions are labeled on the diagram as Aysnc Input Race and the
resultant state is shown in yellow.
13-370 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.6 Transmit and receive link Interaction
For all input race conditions, a component that observes the input race is required to wait for both signals before
changing any output signals. This is represented in Figure 13-5 on page 13-367 by the fact that the only permitted
output transition from a race state is caused by the arrival of the other signal associated with the race condition.
Local
TXREQ Initiate
Pe
rm
TXACK itt
ed
Pe Pe
TXREQ rm Local rm
itt Initiate itt
ed ed
Pe Pe
TXACK rm rm
itt itt
ed ed
Pe
rm
TXREQ itt
ed
TxAct
TxAct RxStop
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-371
ID082919 Non-Confidential
13 Link Handshake
13.7 Protocol layer activity indication
13.7.1 Introduction
SACTIVE signaling indicates that there are transactions in progress.
TXSACTIVE is an output signal that is asserted by an interface where there is a transaction either in progress or
about to start:
• TXSACTIVE must be asserted before or in the same cycle in which the first flit relating to a transaction is
sent.
• TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.
This means that the deassertion of TXSACTIVE on an interface implies that the component has completed all
transactions in progress and does not need to send or receive any further flits.
A transaction that is given a RetryAck response is considered to be in progress, so TXSACTIVE must remain
asserted until the associated credit has been supplied and used or returned.
RXSACTIVE is an input signal which indicates that the other side of the interface has ongoing Protocol layer
activity. When RXSACTIVE is asserted a component must respond to Protocol layer activity in a timely manner.
SACTIVE signals must be synchronous to CLK and therefore are not required to be synchronized. If they cross a
clock domain, the clock domain crossing bridge is required to synchronize the signals.
• A component that asserts TXSACTIVE must also, if required, initiate the link activation sequence. It is not
permitted for a component to assert the TXSACTIVE signal and then wait for the other side of the interface
to initiate the link activation sequence.
• TXSACTIVE must remain asserted until after the last flit relating to all transactions is sent or received.
• It is permitted for TXSACTIVE to be deasserted while transmitting link flits as part of the link deactivation
sequence.
Note
To ensure an efficient power-down sequence, ARM recommends not to assert a deasserted TXSACTIVE signal
during a link deactivation sequence.
It is permitted for the interface on an interconnect component to use the RXSACTIVE input signal to directly
generate the TXSACTIVE output signal. This behavior is only permitted on the interconnect interface and it is not
permitted on any attached component.
Except for an interconnect interface of a link, no other interface of a link is permitted to loop-back the incoming
RXSACTIVE onto the outgoing TXSACTIVE.
13-372 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.7 Protocol layer activity indication
Figure 13-8 shows the requirements for TXSACTIVE assertion during the life of a transaction.
ReadUnique
ReadNoSnp
SnpUnique
SnpUnique
SnpResp_I CompData
SnpResp_I
CompData_UC
I->UC
CompAck
Interconnect
=TXSACTIVE
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-373
ID082919 Non-Confidential
13 Link Handshake
13.7 Protocol layer activity indication
The type of flit that completes a transaction initiated by an RN will depend on both the transaction type and the
manner in which the transaction progresses. For example, a ReadNoSnp transaction might typically complete with
the receipt of the last CompData flit, but could equally complete with a ReadReceipt, if this is later than the last
CompData flit.
Table 13-6 shows the flit types that can complete a transaction. The PrefetchTgt transaction does not include an
explicit completion message, the transaction is considered completed the cycle after it is sent.
An RN-F or RN-D component must also assert TXSACTIVE while a Snoop transaction is in progress.
TXSACTIVE must be asserted after receiving an initiating Snoop or SnpDVMOp flit, and no later than when its
first Response flit is sent. It must keep TXSACTIVE asserted until after the final completing flit is sent for all
Snoop transactions.
For an RN-F or RN-D the TXSACTIVE output is the logical OR of the requirements for the Request interface and
the Snoop interface.
It must assert TXSACTIVE after receiving a transaction initiating flit and it must be asserted before or in the same
cycle in which its first Response flit is sent. It must keep TXSACTIVE asserted until after the final completing flit
is sent or received.
13-374 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
13 Link Handshake
13.7 Protocol layer activity indication
• On receiving a transaction initiating flit, it must be asserted before or in the same cycle in which its first
Response flit is sent. It must keep TXSACTIVE asserted until after the final completing flit is sent or
received.
• Before or in the same cycle in which its initiating Snoop or SnpDVMOp flit is sent. It must keep
TXSACTIVE asserted until after the final completing flit is sent, which will be either SnpResp or
SnpRespData.
Note
The deassertion of RXSACTIVE does not indicate that all Protocol layer activity has completed. It is possible for
a receiver to receive a Protocol flit, which corresponds to a transaction that was in progress while RXSACTIVE
was asserted, after RXSACTIVE is deasserted.
RXSACTIVE can be used in combination with a knowledge of the ongoing transactions, which will be indicated
by the components TXSACTIVE output, to indicate that no further transactions are required. This can be used to
control entry to a low power state.
LINKACTIVE state is an indication of the Link layer activity. The Link layer at a node, or interconnect, can be
considered inactive when its receiver is in TxStop state and its receiver is in RxStop state.
SACTIVE signaling is orthogonal to the LINKACTIVE states with one constraint as specified in RXSACTIVE
signal.
A node, or interconnect, should only enable higher level clock gating and low power optimizations when both its
Protocol and Link layers are inactive.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 13-375
ID082919 Non-Confidential
13 Link Handshake
13.7 Protocol layer activity indication
13-376 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 14
System Coherency Interface
This chapter describes the interface signals that support connecting and disconnecting an RN-F from both the
Coherency and DVM domains and an RN-D from the DVM domain. It contains the following sections:
• Overview on page 14-378.
• Handshake on page 14-379.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 14-377
ID082919 Non-Confidential
14 System Coherency Interface
14.1 Overview
14.1 Overview
The system coherency interface signals are:
SYSCOREQ Master coherency request.
SYSCOACK Interconnect coherency acknowledge.
Both SYSCOREQ and SYSCOACK signals must be synchronous to CLK and therefore are not required to be
synchronized. If they cross a clock domain, the clock domain crossing bridge is required to synchronize the signals.
RN-F or RN-D
SYSCOREQ SYSCOACK
Interconnect
Note
In this chapter:
• Coherency when stated, includes the DVM domain, unless explicitly stated otherwise.
• Snoop when stated, includes SnpDVMOp, unless explicitly stated otherwise.
14-378 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
14 System Coherency Interface
14.2 Handshake
14.2 Handshake
A Request Node, an RN-F or an RN-D, requests connection to system coherency by setting SYSCOREQ HIGH.
The interconnect indicates that coherency is enabled by setting SYSCOACK HIGH.
The Request Node requests disconnection from system coherency by setting SYSCOREQ LOW. The interconnect
indicates that coherency is disabled by setting SYSCOACK LOW.
Requests to enter and exit coherency are always initiated by the Request Node.
t0 t1 t2 t3 t4
SYSCOREQ
SYSCOACK
Coherency Disabled Coherency Connect Coherency Enabled Coherency Disconnect Coherency Disabled
As Figure 14-2 shows, the interface signaling obeys four-phase handshake rules:
• SYSCOREQ can only change when SYSCOACK is at the same logic state.
• SYSCOACK can only change when SYSCOREQ is at the opposite logic state.
14.2.1 RN rules
Referring to Figure 14-2, an RN must:
• Be able to service Snoop requests when it sets SYSCOREQ HIGH at t1.
• Not issue a transaction that permits it to cache a coherent location until SYSCOACK goes HIGH at t2.
• Ensure all transactions that permit it to cache a coherent location are complete before it sets SYSCOREQ
LOW at t3.
SYSCOREQ can only be deasserted on the cycle after all of the following:
— All data packets are received for Reads.
— All data packets are sent for CopyBack.
— All data packets are sent for Snoops and forwarding snoops.
• Keep servicing Snoop requests until SYSCOACK is sampled LOW at t4.
SACTIVE must be asserted during coherency connect transition periods to guarantee the SYSCOACK transition
will occur. See Protocol layer activity indication on page 13-372.
Note
The transactions that permit a coherent location to be cached are:
• ReadUnique.
• ReadClean.
• ReadNotSharedDirty.
• ReadShared.
• CleanUnique.
• MakeUnique.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 14-379
ID082919 Non-Confidential
14 System Coherency Interface
14.2 Handshake
• Set SYSCOACK HIGH without waiting for responses to any Snoop requests that it has sent after
SYSCOREQ goes HIGH.
• Be able to service coherent data accesses from the interface when it sets SYSCOACK HIGH at t2.
14-380 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Chapter 15
Properties, Parameters, and Broadcast Signals
This chapter describes the properties, parameters, and optional broadcast signals that specify the behavior supported
by an interface. It contains the following sections:
• Interface properties and parameters on page 15-382.
• Optional interface broadcast signals on page 15-385.
• Atomic transaction support on page 15-387.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 15-381
ID082919 Non-Confidential
15 Properties, Parameters, and Broadcast Signals
15.1 Interface properties and parameters
The properties and parameters that specify the interface behavior are:
Atomic_Transactions
An Atomic_Transactions property is used to indicate if a component supports Atomic transactions:
• When not specified, or set to False, Atomic transactions are not supported.
• When set to True, Atomic transactions are supported.
A component that supports Atomic transactions must support all Atomic transactions. However, it
is not required that a component that supports Atomic transactions supports the targeting of all
memory types.
Cache_Stash_Transactions
A Cache_Stash_Transactions property is used to indicate if a component supports Cache Stashing
transactions:
• When not specified, or set to False, Cache Stashing transactions are not supported.
• When set to True, Cache Stashing Transactions are supported.
Direct_Memory_Transfer
A Direct_Memory_Transfer property is used to indicate if a component supports Direct Memory
Transfer transactions:
• When not specified, or set to False, Direct Memory Transfer transactions are not supported.
• When set to True, Direct Memory Transfer transactions are supported.
• The Direct_Memory_Transfer property is defined at each HN for each SN.
Direct_Cache_Transfer
A Direct_Cache_Transfer property is used to indicate if a component supports Direct Cache
Transfer transactions:
• When not specified, or set to False, Direct Cache Transfer transactions are not supported.
• When set to True, Direct Cache Transfer transactions are supported.
• It is the responsibility of the HN-F to determine the correct snoop type to use.
Data_Check The Data Check property is used to indicate if Data Check is supported:
• When not specified, or set to False, Data Check is not supported and the DataCheck field is
not present in the DAT packet.
• When set to Odd_Parity, Data Check is supported and the DataCheck field is present in the
DAT packet.
See Data Check on page 9-291.
15-382 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
15 Properties, Parameters, and Broadcast Signals
15.1 Interface properties and parameters
Check_Type The Check Type property is used to indicate the protection scheme employed on an interface:
• When not specified or set to False, no checking signals are present on the interface.
• When set to Odd_Parity_Byte_Data, Odd parity checking is included for data signals only.
Each parity signal covers up to 8 bits.
Note
Only the DataCheck field is present.
• When set to Odd_Parity_Byte_All, Odd parity checking is included for all functionally
important signals. Each parity signal covers up to 8 bits.
Note
A ParityCheck field covering the complete packet and control signals replaces the DataCheck
field.
CleanSharedPersistSep_Request
The CleanSharedPersistSep_Request property is used to indicate if a component supports
CleanSharedPersistSep:
• When not specified, or set to False, the component does not support CleanSharedPersistSep
and the component must not be sent a CleanSharedPersistSep request.
• When set to True, the component supports CleanSharedPersistSep.
• A Home that receives a CleanSharedPersistSep request must support such a request.
• A Home can track if a connected Slave supports CleanSharedPersistSep.
• If a Slave does not support CleanSharedPersistSep:
— The Home must send a CleanSharedPersist instead of a CleanSharedPersistSep
request to that Slave.
— Home must take the responsibility of sending the Persist response to the Requester.
This Persist response must only be sent after receiving the Comp response from the
Slave.
• A Requester that does not support CleanSharedPersistSep will generate CleanSharedPersist
instead.
MPAM_Support
The MPAM_Support property is used to indicate whether an interface supports MPAM.
• When not specified, or set to False, MPAM is not supported:
— The interface is not MPAM enabled.
— No MPAM signals are present on the interface.
• When set to MPAM_9_1, the interface is enabled for partitioning and monitoring:
— It must include the MPAM signal on all address channels.
— The width of PartID is 9 bits and the width of PerfMonGroup is 1bit.
How the MPAM field values are used by a receiver is IMPLEMENTATION DEFINED.
CCF_Wrap_Order
See Critical chunk first wrap order on page 2-123.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 15-383
ID082919 Non-Confidential
15 Properties, Parameters, and Broadcast Signals
15.1 Interface properties and parameters
Req_Addr_Width
This parameter specifies the maximum physical address supported by a component:
• Legal values for this parameter are 44 to 52.
• When Req_Addr_Width is not specified, the default value is 44.
NodeID_Width
This parameter specifies the width of NodeID fields supported by a component, which determines
the maximum permitted NodeID value in the system:
• The width specified is uniformly applied to all NodeID related fields.
• Legal values of NodeID_Width are 7 to 11.
• When NodeID_Width is not specified, the default value is 7.
Data_Width This parameter specifies the data width in the DAT channel packet supported by a component:
• Legal values for Data_Width are 128, 256, and 512.
• When Data_Width is not specified, the default value is 128.
Enhanced_Features
The Enhanced_Features property describes the combined support for some of the miscellaneous
features in the CHI specification that do not have an explicit property or parameter defined.
When the Enhanced_Features property is True, the component supports all the following enhanced
features:
• Data return from SC state.
• I/O Deallocation transactions.
• ReadNotSharedDirty transaction.
• CleanSharedPersist transaction.
• Receiving of Forwarding snoops.
When not specified, or set to False, the component does not support the enhanced features that do
not have an explicitly defined property or parameter.
15-384 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
15 Properties, Parameters, and Broadcast Signals
15.2 Optional interface broadcast signals
An implementation that includes these signals at the interface must ensure that the signal values are stable when
Reset is deasserted.
BROADCASTINNER and BROADCASTOUTER determine respectively if inner and outer domain transactions
must be broadcast. This specification requires that these two pins must be set to the same value. When set to zero
none of the inner and outer transactions are broadcast except for Cache Maintenance Operations (CMO).
BROADCASTCACHEMAINTENANCE
• When asserted:
— CMO transactions must be broadcast beyond the interface for maintenance of
downstream caches.
— CleanSharedPersist* must be converted to CleanShared before broadcasting to
downstream caches if BROADCASTPERSIST is deasserted.
• When deasserted:
— Non-persistent CMO transactions are not required to be broadcast beyond the
interface.
— Broadcasting of Persistent CMO, that is CleanSharedPersist*, beyond the interface is
determined by the assertion of the BROADCASTPERSIST signal.
BROADCASTPERSIST
• When asserted, CleanSharedPersist* must be broadcast beyond the interface for maintenance
of downstream caches. This requirement is independent of the
BROADCASTCACHEMAINTENANCE signal value.
• When deasserted, broadcasting of the Persistent CMO beyond the interface as a
Non-persistent CMO is determined by the BROADCASTCACHEMAINTENANCE
signal value.
The direction of the signal at the RN to ICN interface is input to RN and at the ICN to SN interface it is input to ICN.
Table 15-1 on page 15-386 shows the broadcast signal encodings using the following keys:
BI BROADCASTINNER.
BO BROADCASTOUTER.
BCM BROADCASTCACHEMAINTENANCE.
BP BROADCASTPERSIST.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 15-385
ID082919 Non-Confidential
15 Properties, Parameters, and Broadcast Signals
15.2 Optional interface broadcast signals
BI = BO BCM BP
0 0 0 None.
BROADCASTATOMIC
• When asserted, the interface is permitted to generate Atomic transactions.
• When deasserted, the interface must not generate Atomic transactions.
An RN is not required to make use of Atomic transactions. An RN that does not make use of Atomic transactions
itself, needs no added functionality to be compatible with an interconnect that supports Atomic transactions.
An RN that supports atomic operations but does not include support for the execution of atomic operations must be
able to send Atomic transactions.
BROADCASTICINVAL
• When asserted, DVMOp for ICache Invalidations must be sent to the interconnect.
• When deasserted, DVMOp for ICache invalidations are not required to be sent to the
interconnect.
The BROADCASTICINVAL signal at each RN is used to inform the RN that broadcasting of Instruction Cache
(ICache) invalidations using the DVM mechanism is required.
In a system where all Instruction caches are fully coherent the hardware coherency mechanism automatically
invalidates all ICache copies on a cache line update, In such systems, it is not necessary to broadcast ICache
invalidation operations.
If a system contains one or more Instruction caches that are not updated by the hardware coherency mechanism,
then it is necessary for ICache invalidation operations to be broadcast using DVM transactions.
15-386 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
15 Properties, Parameters, and Broadcast Signals
15.3 Atomic transaction support
An RN is not required to make use of Atomic transactions. An RN that does not make use of Atomic transactions
itself, needs no added functionality to be compatible with an interconnect that supports Atomic transactions.
An RN that supports atomic operations but does not include support for the execution of atomic operations must be
able to send Atomic transactions.
For an RN that supports both the execution of atomic operations as well as the sending of Atomic transactions the
following applies:
• For cacheable locations, both Snoopable and Non-snoopable, an RN is able to perform an atomic operation
locally without generating an Atomic transaction at its interface. To achieve this, the Requester obtains a copy
of the location in its local cache, in the same manner that it would for a store operation, and then performs
the atomic operation within its local cache. For cacheable locations that are Snoopable, if the contents of the
cache line are updated and the cache line was not previously Dirty, then the cache line must be marked as
Dirty.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. 15-387
ID082919 Non-Confidential
15 Properties, Parameters, and Broadcast Signals
15.3 Atomic transaction support
The Atomic_Transactions property is used to indicate that an interconnect supports Atomic transactions.
If Atomic transactions are not supported by the interconnect, all attached RNs must be configured to not generate
Atomic transactions. The BROADCASTATOMIC pin can be used for this purpose, when implemented. See
Request Node support on page 15-387.
For interconnects that support Atomic transactions, atomic operation execution can be supported at any point within
an interconnect, including passing an Atomic transaction downstream to a Slave Node.
Atomic transactions are not required to be supported for every address location.
If Atomic transactions are supported for a given Snoopable address location, then they must be supported for the
complete Snoopable address range.
If Atomic transactions are not supported for a given address location, then an appropriate error response can be
given for the Atomic transaction. See Atomic transactions on page 9-285.
For transactions to a Device the Atomic transaction must be passed to the appropriate endpoint slave. If the slave is
configured to indicate that it does not support Atomic transactions, then the interconnect must return an Error
response for the transaction.
• Perform the atomic operation required by an Atomic transaction within the interconnect.
— This requires that the interconnect performs the appropriate Read, Write and Snoop transactions to
complete the Atomic transaction.
• If the appropriate endpoint slave is configured to indicate that it supports Atomic transactions, then the
interconnect can pass the Atomic transaction to the slave.
— The interconnect is still required to perform the appropriate Snoop and Write transactions before
issuing the Atomic transaction to the Slave.
If an SN supports Atomic transactions for particular memory types, or for particular address regions, then on
receiving an Atomic transaction that it does not support, the SN must give an appropriate Error response.
15-388 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix A
Message Field Mappings
This appendix shows the field mappings for the request, response, data, and snoop request messages. It contains the
following sections:
• Request message field mappings on page A-391.
• Response message field mappings on page A-393.
• Data message field mappings on page A-394.
• Snoop Request message field mappings on page A-395.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. A-389
ID082919 Non-Confidential
Appendix A Message Field Mappings
Table A-1 shows the conventions used in the field mapping tables.
Symbol Description
A-390 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix A Message Field Mappings
A.1 Request message field mappings
AllowRetry
PCrdType
TraceTag
Opcode
RSVDC
Request message
MPAM
TxnID
SrcID
TgtID
Qos
ReqLCrdReturn X X X 0 Y X X X X X
PrefetchTgt Y Y Y X Y 0 X Y Y Y
PCrdReturn Y Y Y 0a Y 0a Y Y Y 0a
DVMOp Y Y Y Y Y Y Y Y Y 0a
ReadNoSnp Y Y Y Y Y Y Y Y Y Y
ReadNoSnpSep Y Y Y Y Y Y Y Y Y Y
ReadShared Y Y Y Y Y Y Y Y Y Y
ReadClean Y Y Y Y Y Y Y Y Y Y
ReadOnce Y Y Y Y Y Y Y Y Y Y
ReadUnique Y Y Y Y Y Y Y Y Y Y
ReadNotSD Y Y Y Y Y Y Y Y Y Y
CleanShared Y Y Y Y Y Y Y Y Y Y
CleanSharedPersist Y Y Y Y Y Y Y Y Y Y
CleanSharedPersistSep Y Y Y Y Y Y Y Y Y Y
CleanInvalid Y Y Y Y Y Y Y Y Y Y
MakeInvalid Y Y Y Y Y Y Y Y Y Y
ReadOnceCleanInvalid Y Y Y Y Y Y Y Y Y Y
ReadOnceMakeInvalid Y Y Y Y Y Y Y Y Y Y
CleanUnique Y Y Y Y Y Y Y Y Y Y
MakeUnique Y Y Y Y Y Y Y Y Y Y
Evict Y Y Y Y Y Y Y Y Y Y
WriteNoSnpPtl Y Y Y Y Y Y Y Y Y Y
WriteNoSnpFull Y Y Y Y Y Y Y Y Y Y
WriteEvictFull Y Y Y Y Y Y Y Y Y Y
WriteCleanFull Y Y Y Y Y Y Y Y Y Y
WriteBackPtl Y Y Y Y Y Y Y Y Y Y
WriteBackFull Y Y Y Y Y Y Y Y Y Y
WriteUniquePtlStash Y Y Y Y Y Y Y Y Y Y
WriteUniqueFullStash Y Y Y Y Y Y Y Y Y Y
WriteUniquePtl Y Y Y Y Y Y Y Y Y Y
WriteUniqueFull Y Y Y Y Y Y Y Y Y Y
StashOnceUnique Y Y Y Y Y Y Y Y Y Y
StashOnceShared Y Y Y Y Y Y Y Y Y Y
AtomicLoad Y Y Y Y Y Y Y Y Y Y
AtomicStore Y Y Y Y Y Y Y Y Y Y
AtomicCompare Y Y Y Y Y Y Y Y Y Y
AtomicSwap Y Y Y Y Y Y Y Y Y Y
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. A-391
ID082919 Non-Confidential
Appendix A Message Field Mappings
A.1 Request message field mappings
MemAttr CF CF CF CF CF
StashLPIDValid
StashNIDValid
ExpCompAck
LikelyShared
ReturnTxnID
Cacheable
StashLPID
ReturnNID
PGroupID
SnoopMe
StashNID
Request message
Allocate
SnpAttr
Endian
Device
Order
Deep
Addr
EWA
LPID
Excl
Size
NS
ReqLCrdReturn X X X X X X X X X X X X X X X X
PrefetchTgt Y Y X X X X X X X X X - 0a Y - 0a X 0a
PCrdReturn 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0 0a 0a 0a 0a
DVMOp Y 0a 8B 0a 0a 0a 0a 0a 0a 0a 0a 0 Y - 0a 0a 0a
ReadNoSnp Y Y Y Y Y Y Y 0 Y 0 Y - Y Y - Y - 0a Y - -
ReadNoSnpSep Y Y Y Y Y Y Y 0 Y 0 0 - 0 Y - Y - 0a Y - -
ReadShared Y Y 64B Y 1 0 1 1 0 Y Y - 1 Y - 0a 0a 0a
ReadClean Y Y 64B Y 1 0 1 1 0 Y Y - 1 Y - 0a 0a 0a
ReadOnce Y Y 64B Y 1 0 1 1 Y 0 0 - Y Y - 0a 0a 0a
ReadUnique Y Y 64B Y 1 0 1 1 0 0 0 - 1 Y - 0a 0a 0a
ReadNotSD Y Y 64B Y 1 0 1 1 0 Y Y - 1 Y - 0a 0a 0a
CleanShared Y Y 64B Y Y Y Y Y 0a 0 0 - 0 Y - 0a 0a 0a
CleanSharedPersist Y Y 64B Y Y Y Y Y 0a 0 0 - 0 0a 0a - - Y 0a
CleanSharedPersistSep Y Y 64B Y Y Y Y Y 0a 0 0 - 0 - Y Y - - - Y 0a
CleanInvalid Y Y 64B Y Y Y Y Y 0a 0 0 - 0 Y - 0a 0a 0a
MakeInvalid Y Y 64B Y Y Y Y Y 0a 0 0 - 0 Y - 0a 0a 0a
ReadOnceCleanInvalid Y Y 64B Y 1 0 1 1 Y 0 0 - Y Y - 0a 0a 0a
ReadOnceMakeInvalid Y Y 64B 0 1 0 1 1 Y 0 0 - Y Y - 0a 0a 0a
CleanUnique Y Y 64B Y 1 0 1 1 0 0 Y - 1 Y - 0a 0a 0a
MakeUnique Y Y 64B Y 1 0 1 1 0 0 0 - 1 Y - 0a 0a 0a
Evict Y Y 64B 0 1 0 1 1 0 0 0 - 0 Y - 0a 0a 0a
WriteNoSnpPtl Y Y Y Y Y Y Y 0 Y 0 Y - Y Y - 0a 0a 0a
WriteNoSnpFull Y Y 64B Y Y Y Y 0 Y 0 Y - Y Y - 0a 0a 0a
WriteEvictFull Y Y 64B 1 1 0 1 1 0 Y 0 - 0 Y - 0a 0a 0a
WriteCleanFull Y Y 64B Y 1 0 1 1 0 Y 0 - 0 Y - 0a 0a 0a
WriteBackPtl Y Y 64B Y 1 0 1 1 0 0 0 - 0 Y - 0a 0a 0a
WriteBackFull Y Y 64B Y 1 0 1 1 0 Y 0 - 0 Y - 0a 0a 0a
WriteUniquePtlStash Y Y Y Y 1 0 1 1 Y Y 0 - Y Y - - Y Y - - - Y Y
WriteUniqueFullStash Y Y 64B Y 1 0 1 1 Y Y 0 - Y Y - - Y Y - - - Y Y
WriteUniquePtl Y Y Y Y 1 0 1 1 Y Y 0 - Y Y - 0a 0a 0a
WriteUniqueFull Y Y 64B Y 1 0 1 1 Y Y 0 - Y Y - 0a 0a 0a
StashOnceUnique Y Y 64B Y 1 0 1 1 0 Y 0 - 0 Y - - Y Y - - - Y Y
StashOnceShared Y Y 64B Y 1 0 1 1 0 Y 0 - 0 Y - - Y Y - - - Y Y
AtomicLoad Y Y Y Y Y Y Y Y Y 0 - Y 0 Y - Y - - Y - Y - -
AtomicStore Y Y Y Y Y Y Y Y Y 0 - Y 0 Y - 0a - Y - 0a
AtomicCompare Y Y Y Y Y Y Y Y Y 0 - Y 0 Y - Y - - Y - Y - -
AtomicSwap Y Y Y Y Y Y Y Y Y 0 - Y 0 Y - Y - - Y - Y - -
A-392 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix A Message Field Mappings
A.2 Response message field mappings
CF CF
PGroupID
PCrdType
FwdState
TraceTag
Response message
DataPull
RespErr
Opcode
CBusy
TxnID
SrcID
TgtID
Resp
DBID
QoS
RspLCrdReturn X X X 0 Y X X X X X X X
SnpResp Y Y Y Y Y Y Y Y Y - 0a - Y Y
SnpRespFwded Y Y Y Y Y Y Y Y X 0a Y - Y
CompAck Y Y Y Y Y 0 0a 0a X 0a 0a Y
RetryAck Y Y Y Y Y 0 0a Y X Y 0a Y
Comp Y Y Y Y Y Y Y Y Y - 0a 0a Y
Persist Y Y Y 0a Y Y 0a Y - Y 0a 0a X
CompPersist Y Y Y Y Y Y Y Y - Y 0a 0a Y
RespSepData Y Y Y Y Y Y Y Y Y - 0a 0a Y
CompDBIDResp Y Y Y Y Y Y 0 Y Y - 0a 0a Y
DBIDResp Y Y Y Y Y 0 0a Y Y - 0a 0a Y
PCrdGrant Y Y Y 0a Y 0 0a Y 0a Y 0a Y
ReadReceipt Y Y Y Y Y 0 0a Y X 0a 0a Y
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. A-393
ID082919 Non-Confidential
Appendix A Message Field Mappings
A.3 Data message field mappings
Common Field
DataSource
DataCheck
HomeNID
FwdState
TraceTag
DataPull
RespErr
Opcode
RSVDC
Data message
Poison
CBusy
DataID
TxnID
SrcID
TgtID
Resp
DBID
CCID
Data
QoS
BE
DatLCrdReturn X X X 0 Y X X X X X X X X X X X X X X
SnpRespData Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0a - Y Y Y Y Y
SnpRespDataFwded Y Y Y Y Y Y Y Y X Y Y Y Y Y 0a Y - - Y Y Y
CopyBackWrData Y Y Y Y Y Y Y 0a X Y Y Y Y Y 0a 0a Y Y Y
NonCopyBackWrData Y Y Y Y Y Y Y 0a X Y Y Y Y Y 0a 0a Y Y Y
NCBWrDataCompAck Y Y Y Y Y Y Y 0a X Y Y Y Y Y 0a 0a Y Y Y
CompData Y Y Y Y Y Y Y Y Y Y Y Y X Y Y - - Y Y Y Y
DataSepResp Y Y Y Y Y Y Y Y Y Y Y Y X Y Y - - Y Y Y Y
SnpRespDataPtl Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0a - Y Y Y Y Y
WriteDataCancel Y Y Y Y Y Y Y 0a X Y Y Y 0 Y 0a 0a Y Y Y
A-394 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix A Message Field Mappings
A.4 Snoop Request message field mappings
Common Field CF
StashLPIDValid
Addr[(43-51):3]
DoNotDataPull
DoNotGoToSD
Snoop Request message
StashLPID
FwdTxnID
RetToSrc
TraceTag
VMIDExt
Opcode
FwdNID
MPAM
TxnID
SrcID
QoS
NS
SnpLCrdReturn X X 0 Y X X X X X X X X X X X X
SnpShared Y Y Y Y Y Y 0a 0a Y - Y Y D
SnpClean Y Y Y Y Y Y 0a 0a Y - Y Y D
SnpOnce Y Y Y Y Y Y 0a 0a Y - Y Y D
SnpNotSharedDirty Y Y Y Y Y Y 0a 0a Y - Y Y D
SnpUnique Y Y Y Y Y Y 0a 0a 1 - Y Y D
SnpCleanShared Y Y Y Y Y Y 0a 0a 1 - 0 Y D
SnpCleanInvalid Y Y Y Y Y Y 0a 0a 1 - 0 Y D
SnpMakeInvalid Y Y Y Y Y Y 0a 0a 1 - 0 Y D
SnpSharedFwd Y Y Y Y Y Y Y Y - - - Y - Y Y D
SnpCleanFwd Y Y Y Y Y Y Y Y - - - Y - Y Y D
SnpOnceFwd Y Y Y Y Y Y Y Y - - - Y - 0 Y D
SnpNotSharedDirtyFwd Y Y Y Y Y Y Y Y - - - Y - Y Y D
SnpUniqueFwd Y Y Y Y Y Y Y Y - - - 1 - 0 Y D
SnpUniqueStash Y Y Y Y Y Y 0a - Y Y - - Y 0 Y Y
SnpMakeInvalidStash Y Y Y Y Y Y 0a - Y Y - - Y 0 Y Y
SnpStashUnique Y Y Y Y Y Y 0a - Y Y - - Y 0 Y Y
SnpStashShared Y Y Y Y Y Y 0a - Y Y - - Y 0 Y Y
SnpDVMOp Y Y Y Y Y 0a 0a - - - Y 0a 0a Y 0a
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. A-395
ID082919 Non-Confidential
Appendix A Message Field Mappings
A.4 Snoop Request message field mappings
A-396 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix B
Communicating Nodes
This appendix specifies, for each packet type, the nodes that communicate using that packet type. It contains the
following sections:
• Request communicating nodes on page B-398.
• Snoop communicating nodes on page B-400.
• Response communicating nodes on page B-401.
• Data communicating nodes on page B-402.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. B-397
ID082919 Non-Confidential
Appendix B Communicating Nodes
B.1 Request communicating nodes
For some Requests, both an expected target and a permitted target are given. The use of the permitted target can
occur in the case of a software based error. The permitted target must complete the transaction in a protocol
compliant manner, this might require the use of an error response.
Request From To
Expected Permitted
ICN(HN-I) SN-I -
ICN(HN-F) SN-F -
ICN(HN-I) SN-I -
B-398 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix B Communicating Nodes
B.1 Request communicating nodes
Request From To
Expected Permitted
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. B-399
ID082919 Non-Confidential
Appendix B Communicating Nodes
B.2 Snoop communicating nodes
Snoop From To
B-400 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix B Communicating Nodes
B.3 Response communicating nodes
Response From To
SN-I ICN(HN-I)
SN-F ICN(HN-F)
SN-I ICN(HN-I)
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. B-401
ID082919 Non-Confidential
Appendix B Communicating Nodes
B.4 Data communicating nodes
For some Data, both an expected target and a permitted target are given. The use of the permitted target can occur
in the case of an incorrect address decode. The permitted target must complete the transaction in a protocol
compliant manner.
Data From To
Expected Permitted
ICN(HN-F) SN-F -
ICN(HN-I) SN-I -
ICN(HN-F) SN-F -
ICN(HN-I) SN-I -
B-402 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix C
Revisions
This appendix describes the technical changes between released issues of this specification.
Change Location
Change Location
New feature: Response after receiving first Data packet. Snoopable Reads excluding ReadOnce* on page 2-39.
ReadNoSnp, ReadOnce, ReadOnceCleanInvalid,
ReadOnceMakeInvalid on page 2-44.
New feature: Separate Non-data and Data-only response. Reads with separate Non-data and Data-only
responses on page 2-50 and multiple related locations.
New feature: Combined CompAck with WriteData. WriteUnique transaction on page 2-92 and multiple
related locations.
Clarification: Regarding byte enables for Write transactions. Byte Enables on page 2-119.
Update: Concerning the list of fields that can change value from Request Retry on page 2-129.
the original request in the retried request.
Clarification: Concerning the transaction responses permitted to At the RN-F node on page 4-200.
be sent to the same address when a Snoop transaction response
is pending.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. C-403
ID082919 Non-Confidential
Appendix C Revisions
Change Location
Additional information: Concerning Legal RespErr field values Table 9-6 on page 9-285.
for WriteDataCancel.
Clarification: Regarding TraceTag field value propagation. TraceTag usage and rules on page 11-308.
Corrections and additions: Concerning message field mappings. Table A-2 on page A-391, Table A-4 on page A-393,
and Table A-5 on page A-394.
Change Location
New feature: Persistent CMO with two part response. Dataless on page 2-55.
Dataless transactions on page 2-86.
Cache maintenance transactions on page 4-150.
Use of Persistence Group ID on page 4-151.
Persistent CMO with snoop and separate Comp and
Persist on page 5-217.
Interface properties and parameters on page 15-382.
Dataless transactions on page 9-284.
New feature: Deep Persistent cache maintenance. Cache maintenance transactions on page 4-150.
Deep on page 12-338.
New feature: Memory System Performance Resource Partitioning and MPAM on page 11-305.
Monitoring (MPAM). Interface properties and parameters on page 15-382.
New feature: ICache Invalidation broadcast signal. Optional interface broadcast signals on page 15-385.
Additional requirement: Concerning SACTIVE synchronization to CLK. Protocol layer activity indication on page 13-372.
Additional requirement: Concerning SYSCOREQ and SYSCOACK Chapter 14 System Coherency Interface.
synchronization to CLK.
Correction: Concerning the use of RXSACTIVE to directly generate the TXSACTIVE signal on page 13-372.
TXSACTIVE signal.
Update: Concerning Ordered Write Observation flow enhancements. Streaming Ordered Write transactions on page 2-106.
Update: Concerning the relaxation of the order requirement between cache Cache maintenance transactions on page 4-150.
maintenance transactions and any other transaction to the same address.
Update: Concerning UD_PD state is permitted on a DataSepResp Read and Atomic transaction completion on
response. page 4-166.
Update: Concerning DVM early Comp. DVM early Comp for Non-sync DVMOps on
page 8-259.
C-404 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Appendix C Revisions
Change Location
Update: Concerning increased TXID width. Flit packet definitions on page 12-324.
Clarification: Regarding when a RespSepData response includes a Read Transactions on page 9-283.
Non-data Error.
Clarification: Regarding when the DataPull bit is set in a SnpRespData DataPull on page 12-343.
message.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. C-405
ID082919 Non-Confidential
Appendix C Revisions
C-406 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Glossary
This glossary describes some of the technical terms used in AMBA 5 CHI documentation.
Aligned A data item stored at an address that is divisible by the highest power of 2 that divides into its size in bytes. Aligned
halfwords, words, and doublewords therefore have addresses that are divisible by 2, 4, and 8 respectively.
An aligned access is one where the address of the access is aligned to the size of each element of the access.
Blocking Describes an operation that prevents following actions from continuing until the operation completes.
Cache Any cache, buffer, or other storage structure that can hold a copy of the data value for a particular address location.
Cache hierarchy
The organization of different size caches in a hierarchy, typically with the cache with faster access and smaller size
closer to the core and larger and slower access ones farther away from the core. The last level of this hierarchy might
be connected to the memory. In this specification, in relation to a referenced cache, above refers to caches closer to
the core, and below refers to caches farther from the core.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. Glossary-407
ID082919 Non-Confidential
Glossary
Cache line The basic unit of storage in a cache. Its size in words is always a power of two. A cache line must be aligned to the
size of the cache line.
Cache state State of a block of data in a cache, of 64-byte size in this specification. The state determines if the block is cached
in any other caches in the system and also if it is different from the copy of the block in memory. See Cache state
model on page 1-26 for a description of the cache states supported in this specification.
Channel A set of signals grouped together to communicate a particular set of messages between a transmitter and receiver
pair. For example Request channel is used to communicate request messages.
A channels consist of a set of information signals and a separate Valid and Credit signal to provide the channel
handshake mechanism.
Coherent Data accesses from a set of observers to a memory location are coherent accesses to that memory location by the
members of the set of observers are consistent with there being a single total order of all writes to that memory
location by all members of the set of observers.
Coherency granule
The minimum size of the block of memory affected by any coherency consideration. For example, an operation to
make two copies of an address coherent makes the two copies of a block of memory coherent, where that block of
memory is:
• At least the size of the coherency granule.
• Aligned to the size of the coherency granule.
Component A distinct functional unit that has at least one AMBA interface. Component can be used as a general term for master,
slave, peripheral, and interconnect components.
See also Interconnect component, Master component, Memory slave component, Peripheral slave component,
Slave component.
Deprecated Something that is present in the specification for backwards compatibility. Whenever possible you must avoid using
deprecated features. These features might not be present in future versions of the specification.
Downstream A transaction operates between a master component and one or more slave components, and can pass through one
or more intermediate components. At any intermediate component, for a given transaction, downstream means
between that component and a destination slave component, and includes the destination slave component.
Downstream and upstream are defined relative to the transaction as a whole, not relative to individual data flows
within the transaction.
Downstream Cache
See Downstream cache on page 1-21.
Final Destination
Final destination for a Memory transaction is a peripheral or physical memory, also called an Endpoint.
Glossary-408 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Glossary
In a timely manner
See In a timely manner on page 1-22.
IMPLEMENTATION DEFINED
Behavior that is not defined by the architecture, but is defined and documented by individual implementations.
IMPLEMENTATION SPECIFIC
Behavior that is not architecturally defined, and might not be documented by an individual implementation. Used
when there are a number of implementation options available and the option chosen does not affect software
compatibility.
IO Coherent node
See IO Coherent node on page 1-22.
Link A Link is the connection used for communicating between a transmitter and receiver pair.
Load The action of a master component reading the value held at a particular address location. For a processor, a load
occurs as the result of executing a particular instruction. Whether the load results in the master issuing a Read
transaction depends on whether the accessed cache line is held in the local cache.
Main memory can be referred to as memory when the context makes the intended meaning clear.
Master component
A component that initiates transactions.
It is possible that a single component can act as both a master component and as a slave component. For example,
a Direct Memory Access (DMA) component can be a master component when it is initiating transactions to move
data, and a slave component when it is being programmed.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. Glossary-409
ID082919 Non-Confidential
Glossary
Observer A processor or other master component, such as a peripheral device, that can generate reads from or writes to
memory.
Outstanding Request
A transaction is outstanding from the cycle that the Request is first issued until either:
• The transaction is fully completed, as determined by the return of all ReadReceipt, CompData, DBIDResp,
Comp, CompDBIDResp responses that are expected for the transaction.
Peer node A protocol node of the same type with reference to itself. For example, the peer node for a Request Node is another
Request Node.
Peer to Peer Communication between the same type of nodes. For example, from one RN to another RN.
Permission to store
A component has permission to store if it can perform a store to the associated cache line without informing any
other components or the interconnect.
Glossary-410 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919
Glossary
Prefetching Prefetching refers to speculatively fetching instructions or data from the memory system. In particular, instruction
prefetching is the process of fetching instructions from memory before the instructions that precede them, in simple
sequential execution of the program, have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
In this specification, references to instruction or data fetching apply also to prefetching, unless the context explicitly
indicates otherwise.
It is possible that a single component can act as both a slave component and as a master component. For example,
a Direct Memory Access (DMA) component can be a slave component when it is being programmed and a master
component when it is initiating transactions to move data.
See also Master component, Memory slave component, Peripheral slave component.
Snoop filter A snoop filter is able to track the cache lines that might be allocated within a master.
Speculative read
A transaction that a component issues when it might not need the transaction to be performed because it already has
a copy of the accessed cache line in its local cache. Typically, a speculative read is performed in parallel with a local
cache lookup. This gives lower latency than looking in the local cache first, and then issuing a Read transaction only
if the required cache line is not found in the local cache.
Stash The action of placing data in a cache closer to the agent that is expected to be the next user of the data.
Store The action of a master component changing the value held at a particular address location. For a processor, a store
occurs as the result of executing a particular instruction. Whether the store results in the master issuing a Read or
Write transaction depends on whether the accessed cache line is held in the local cache, and if it is in the local cache,
the state it is in.
Synchronization barrier
See Barrier.
ARM IHI 0050D Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. Glossary-411
ID082919 Non-Confidential
Glossary
See also System Memory Management Unit (SMMU), Translation table, Translation table walk.
Translation table
A table held in memory that defines the properties of memory areas of various sizes from 1KB.
Upstream A transaction operates between a master component and one or more slave components, and can pass through one
or more intermediate components. At any intermediate component, for a given transaction, upstream means
between that component and the originating master component, and includes the originating master component.
Downstream and upstream are defined relative to the transaction as a whole, not relative to individual data flows
within the transaction.
Write-Back cache
A cache in which, when a store is permitted to store, the data is only written to the cache. Data in the cache can
therefore be more up-to-date than data in main memory. Any such data is written back to next level cache or main
memory when the cache line is cleaned or re-allocated. Another common term for a Write-Back cache is a
Copy-Back cache.
Write-Invalidate protocol
See Write-Invalidate protocol on page 1-22.
Glossary-412 Copyright © 2014, 2017, 2018, 2019 Arm Limited or its affiliates. All rights reserved. ARM IHI 0050D
Non-Confidential ID082919