Hi3518E V20X/Hi3516C V200 Hardware Design

Checklist

Issue 01

Date 2016-10-28
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 Hi3518E V20X/Hi3516C V200 Hardware Design
Checklist About This Document

About This Document

Purpose
This document describes the check items for Hi3518E V20X/Hi3516C V200 solutions.

Related Versions
The following table lists the product versions related to this document.

Product Name Version

Hi3518E V200
Hi3518E V201
Hi3516C V200

Intended Audience
This document is intended for:
 Technical support engineers
 Board hardware development engineers

Change History
Changes between document issues are cumulative. Therefore, the latest document issue
contains all changes made in previous issues.

Issue 01 (2016-10-28)
This issue is the first official release, which incorporates the following changes:
Section 1.13 is modified.

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Issue 00B03 (2016-05-16)

This issue is the third draft release, which incorporates the following changes:
Section 1.3 and section 1.13 are modified.

Issue 00B02 (2015-12-10)

This issue is the second draft release, which incorporates the following changes:
Section 1.1, section 1.5, section 1.6, and section 1.8 are modified.

Issue 00B01 (2015-09-14)

This issue is the first draft release.

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 Hi3518E V20X/Hi3516C V200 Hardware Design
Checklist Contents

Contents

About This Document......................................................................................................................i

1 Checklist..........................................................................................................................................1
1.1 Design Requirements on Power Supplies and GND.........................................................................................1
1.2 Design Requirements on the Clock Circuit of the Master Chip and RTC.........................................................3
1.3 Design Requirements on the Reset Circuit........................................................................................................4
1.4 Design Requirements on the DDR Circuit........................................................................................................4
1.5 Design Requirements on the SPI Flash Circuit.................................................................................................6
1.6 Design Requirements on the eMMC Circuit.....................................................................................................7
1.7 Design Requirements on the I2C Circuit............................................................................................................7
1.8 Design Requirements on the Video Circuit.......................................................................................................8
1.9 Design Requirements on the Audio Circuit.....................................................................................................10
1.10 Design Requirements on the USB Circuit.....................................................................................................13
1.11 Design Requirements on the ETH Circuit.....................................................................................................14
1.12 Design Requirements on JTAG and System Control Circuits.......................................................................15
1.13 Design Requirements on the SD Card Circuit...............................................................................................15
1.14 Design Requirements on the UART Circuit..................................................................................................16
1.15 Design Requirements on Heat Dissipation....................................................................................................17
1.16 Design Requirements on the Sensor..............................................................................................................17

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1 Checklist

NOTE
This document uses Hi3518E V20X as an example. Unless otherwise specified, the contents of Hi3518E
V200 also apply to Hi3518E V201 and Hi3516C V200.

1.1 Design Requirements on Power Supplies and GND

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The core power pin (DVDD11) connects to the

1.1 V digital power. It is required that the DC-
DC with the loading capability no less than 1 A
be used.
Turn on the 3.3 V, 1.8 V, 1.5 V, and 1.1 V
power supplies in sequence (note the power-on
time interval requirements on the 3.3 V and 1.1
V power supplies. For details, see the power-on
timing requirements in the Hi3518E
V20X/Hi3516C V200 Hardware Design User
Guide).
Turn off the 3.3 V and 1.1 V power supplies in
sequence (note the power-off time interval
requirements on the 3.3 V and 1.1 V power
supplies. For details, see the power-off timing
requirements in the Hi3518E V20X/Hi3516C
V200 Hardware Design User Guide).
The system phase-locked loop (PLL) power
supplies AVDD11_PLL and AVDD33_PLL are
isolated from the digital power supplies
DVDD11 and DVDD33 respectively by using
the 1 kΩ@100 MHz electromagnetic
interference (EMI) beads, and the π-shaped
filtering design is required. For details about the

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schematic diagram and printed circuit board

(PCB) design requirements, see Figure 1-1 to
Figure 1-3.

Figure 1-1 Schematic diagram of the PLL power supply and GND pins

Figure 1-2 PCB design of the AVDD11_PLL power supply and GND pins

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Figure 1-3 PCB design of the AVDD33_PLL power supply and GND pins

During the PCB design, the 100 nF decoupling capacitors (C33 and C34) must be placed
close to the corresponding pins (AVDD11_PLL and AVDD33_PLL). The GND of the
decoupling capacitors must be isolated from other modules especially the digital GND (the
GND of the decoupling capacitors cannot share the GND vias with the GND of other
modules) and directly connects to the AVSS_PLL ball.

1.2 Design Requirements on the Clock Circuit of the

Master Chip and RTC
√ Item Customer Confirmation Remarks
(PASS/NO PASS)

A 24 MHz external crystal is required for

the system clock of the master chip. The
load capacitors must match the crystal, and
the maximum frequency deviation of the 24
MHz system clock is 30 ppm.
The timing precision of the embedded real-
time clock (RTC) depends on the external
crystal. Select an appropriate crystal based
on its frequency error and temperature drift.
If high timing precision is required, the
external high-precision RTC is
recommended.
During the PCB design, the 24 MHz system
clock and RTC are placed close to the chip.
The Xin/Xout and RTC_Xin/RTC_Xout

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signal traces are surrounded with GND

traces to guarantee a complete reference
plane. High-speed signals cannot be routed
under the crystal circuit, and the spacing
between the Xin/Xout and
RTC_Xin/RTC_Xout signal traces is greater
than 30 mils.

1.3 Design Requirements on the Reset Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

Hi3518E V20X supports only internal

power-on reset (POR). The high-level
voltage of SYS_RSTN_OUT is the same as
that of the power supply of
DVDD3318_EMMC. Therefore, the
interface levels must be consistent during
peripheral reset.
Peripherals (such as the SPI flash) are reset
before Hi3518E V20X or they are reset at
the same time.
During power-off, the 3.3 V power is turned
off first. The core power is turned off after
the level of the 3.3 V power is decreased to
the POR power-off threshold and the POR is
triggered.

1.4 Design Requirements on the DDR Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The quantity, capacitance, and layout of the

filter capacitor for VDDIO_DDR (1.8 V
power for Hi3518E V200/V201 and 1.5
V/1.35 V power for Hi3516C V200) of the
Hi3518E V20X DDR must be designed by
following the PCB design of the
corresponding demo board.

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The DDR_Vref power for Hi3518E V20X is

obtained by dividing the VDDIO_DDR
power using two 1 kΩ±1% voltage division
resistors in series.
The design of the AVDD_DDRPLL power
for Hi3518E V20X is the same as that of the
system PLL power, as shown in Figure 1-4
and Figure 1-5.
A 100 Ω±1% matched resistor is connected
between DDR_CLK_N and DDR_CLK_P
(DDR_CLK is a differential clock for
Hi3516C V200), and is placed close to the
CLK pin of the DDR SDRAM on the PCB.
A 240 Ω±1% external resistor is used as the
ZQ calibration resistor for Hi3516C V200,
and is placed close to Hi3516C V200 on the
PCB.
The DDR routing (including the trace width,
spacing as well as length, GND surrounding
design, and filter matching mode) of
Hi3516C V200 must be designed by
completely following the PCB design of the
Hi3516CV200DMEB.

Figure 1-4 Schematic diagram of AVDD_DDRPLL

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Figure 1-5 PCB design of AVDD_DDRPLL

During the PCB design of AVDD_DDRPLL, the 100 nF filter capacitor (C14) must be placed
close to the AVDD_DDRPLL pin, and must connect to the GND through separate vias (it
cannot share the GND via with the GNDs of the other modules).

1.5 Design Requirements on the SPI Flash Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The master chip boots from the SPI flash (that

stores the U-boot) connected to the
SFC_CSN0 pin by default. The CS0 and
HOLD signals connect to 4.7 kΩ pull-up
resistors, and the WP signal connects to a 4.7
kΩ pull-down resistor.
It is recommended that the SPI flash with the
reset function be used.
The I/O level of the SPI flash connected to
Hi3518E V20X must be the consistent with
the level of the DVDD3318_EMMC power.

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1.6 Design Requirements on the eMMC Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

EMMC_CLK connects to a 22 Ω resistor in

series at the source end. EMMC_DAT[0:7]
connect to 47 kΩ pull-up resistors.
EMMC_CMD connects to a 10 kΩ pull-up
resistor. EMMC_DS connects to a 22 Ω
resistor in series at the source end and a 47
kΩ pull-down resistor (this resistor is
removable if a pull-down resistor is integrated
in the eMMC).
When Hi3518E V20X interconnects with the
embedded multimedia card (eMMC), the I/O
interface voltage of the selected eMMC must
be the same as the voltage of the power
supply for the DVDD3318_EMMC pin of the
master chip.
The DVDD3318_EMMC pin of Hi3518E
V20X must be always supplied with power,
and its power-on and power-off cannot be
controlled by EMMC_POWER_EN.
When Hi3518E V200 connects to the eMMC
and the Wi-Fi module of the secure digital
input/output (SDIO) interface at the same
time, it can only use the SDIO interface
multiplexed with the MAC to connect to the
Wi-Fi module.

1.7 Design Requirements on the I2C Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The inter-integrated circuit (I2C) signals SCL

and SDA are output from open drain (OD)
pins and need to connect to external pull-up
resistors. The resistance is selected based on
the bus load. The 1 kΩ pull-up resistor is
recommended.
The addresses of components on the I2C bus
cannot conflict with each other.

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1.8 Design Requirements on the Video Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

When the video interface interconnects with

the mobile industry processor interface
(MIPI)/high-speed serial pixel interface
(HiSPI)/low-voltage differential signaling
(LVDS) sensor:
The level of DVDD3318_SENSOR needs to
be compatible with the I/O level of the
connected sensor. When the sensor with the
1.8 V I/O level is connected, the 1.8 V power
can be provided for both
DVDD3318_SENSOR and
AVDD3318_MIPI.
MIPI_D[0:3] can interconnect with the sensor
data lanes in any sequence (the default
sequence is MIPI_D0 to MIPI_D3), whereas
MIPI CLK interconnects with the sensor data
lane in a fixed sequence and does not support
the out-of-order mode.
When the interconnected sensor has fewer
than four lanes, the remaining data lane pins
can be floated.
When the video interface interconnects with
the sensor of the parallel complementary
metal-oxide-semiconductor (CMOS)
interface:
The power supplies of DVDD3318_SENSOR,
AVDD3318_MIPI, and DVDD3318_VI can
be combined into a 1.8 V or 3.3 V power
supply (the level must be consistent with the
I/O level of the interconnected sensor).
It is recommended that the 14-bit sensor be
connected to D0−D13 in sequence (the
reverse order D13−D0 is also supported).
It is recommended that the 12-/10-bit sensor
be connected to D0−D11/D0−D9 in sequence
(the interconnection of any consecutive 12/10
bits is supported).
The horizontal sync (HS) and vertical sync
(VS) signals must be those multiplexed by
GPIO1_5 and GPIO1_4.
The software configuration must match the
hardware design. The unused pins need to be
configured as general-purpose input/output
(GPIO) outputs and be floated.
When the video interface interconnects with

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the BT.1120 data signals:

 The Y data signal and the C data signal
interconnect with the upper eight bits and
lower eight bits of the VI interface
respectively (Y and C data signals can be
switched).
 The HS and VS signals are those
multiplexed by GPIO0_6 and GPIO0_7.
 The software configuration must match the
hardware design. The unused pins need to
be configured as GPIO outputs and floated.
The BT.656/BT.601 data signals interconnect
with the VI interface in the sequence of
D0−D7 (any consecutive eight bits). The
remaining VI pins can be configured as GPIO
outputs and floated.
The I/O level of the GPIO1_0 to GPIO1_6
pins is consistent with that of DVDD3318_VI.
When the seven pins are used as GPIO pins,
the interface level of the interconnected
component must be consistent with the pin
level.
The PCB design requirements on the video
input unit (VIU) are as follows:
The VI interface needs to support the
interconnection with the sensor of the
differential and single-ended interfaces. For
the five pairs of MIPI differential signal
traces, the length deviation of each pair of
differential signal traces must be within ±5
mils, the length deviation between two pairs
of differential signal traces must be within
±300 mils based on the clock signal, and the
impedance of each pair of differential signal
traces must be 100 Ω±10%. The impedance of
other single-ended signal traces must be 50
Ω±10%. See Figure 1-7.
The VI interface supports the 3.3 V and 1.8 V
levels. The I/O level of the chip must be
consistent with that of the interconnected VI
module regardless of the mode.
The video output (VO) interface supports one
video BT.656 output or liquid crystal display
(LCD) RGB565 output.
The unused VO pins can be configured as
GPIO outputs and floated.

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Figure 1-6 VI HS and VS signals

Figure 1-7 PCB design of the VIU

In Figure 1-7, the yellow signal traces indicate the five pairs of MIPI differential signal traces,
the green ones indicate other single-ended data signal traces, and the light blue ones indicate
the sensor configuration interface, reset, and clock signal traces.

1.9 Design Requirements on the Audio Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The chip provides one analog audio coder/decoder

(CODEC) and one inter-IC sound (I2S) interface, which

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cannot be used at the same time. The I2S signals can be

output through three groups of pins.
AC_VREF of the audio CODEC connects to a 10 µF
external capacitor and a 100 nF external capacitor and
then to the GND, and the 100 nF capacitor is placed
close to the chip. See Figure 1-8.
The AVDD33_AC power pin and AVSS_AC GND pin
of the audio CODEC are isolated from the 3.3 V digital
power and digital GND respectively, and these pins
cannot share the GND vias with other modules. See
Figure 1-9.
The vias on the GND traces for surrounding the audio
signal traces are isolated from other high-speed signal
traces to prevent audio crosstalk introduced through
these vias. See Figure 1-11.
When dual microphone (MIC) inputs are used, to ensure
audio quality, it is recommended that the signal be
divided into two channels at the near end of the
AC_MICBIAS output pin and the signals correspond to
the bias levels of the audio-left and audio-right channels.
For details, see the latest schematic diagram of the
Hi3518EV20X DMEB board.
The DC blocking capacitors connected to AC_INR and
AC_INL in series are placed as close to Hi3518E V20X
as possible. For details about the design of interface
resistors and capacitors, see the latest schematic diagram
of the Hi3518EV20XPERB board.
To ensure the audio quality, it is recommended that the
audio amplifier and filter circuit connect to the audio
output pins AC_OUTL and AC_OUTR. For details, see
the latest schematic diagram of the Hi3518E V20X
PERB board.
To ensure the audio quality, the AC input/output signal
traces are surrounded with GND traces and isolated from
other digital signal traces. Isolation is also required for
the audio input and output signal traces to avoid
crosstalk. The signal traces must be routed by
referencing the GND plane. See Figure 1-10 and Figure
1-11.
MCLK of the I2S interface connects to a 33 Ω resistor in
series at the near end of the chip to ensure the signal
quality.

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Figure 1-8 PCB design of the AC_Vref power

In Figure 1-8, the yellow areas indicate the signal traces of AC_Vref, and the blue areas
indicate the GND copper plane of AC_Vref.

Figure 1-9 PCB design of AVDD33_AC and AVSS_AC

In Figure 1-9, the yellow areas indicate the power signals of AVDD33_AC, the blue areas
indicate the GND copper plane, and the green areas indicate LB6 and C8.

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Figure 1-10 Core board PCB design of the audio input and output signal traces

In Figure 1-10, the yellow lines indicate the audio input signals, the white lines indicate the
audio output signals, the green lines indicate the MIC_bias signals, and the blue lines indicate
the GND copper plane. The traces on the top layer are routed by using the GND plane as the
reference plane and are isolated from adjacent high-speed digital signal traces.

Figure 1-11 Mother board PCB design of the audio input and output signal traces

In Figure 1-11, the yellow lines indicate the audio input signals, the white lines indicate the
audio output signals, the green lines indicate the MIC_bias signals, and the blue lines indicate
the GND copper plane. The traces on the top layer are routed by using the GND plane as the
reference plane and are isolated from adjacent high-speed digital signal traces.

1.10 Design Requirements on the USB Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The USB_REXT pin connects to a 135

Ω±1% external resistor and then to the
GND, and the resistor is placed as close to

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the chip as possible.

The USB differential traces cannot be
routed across plane splits. The impedance of
the differential signal trace is 90 Ω±10%,
and the length deviation of each pair of USB
differential traces falls within ±5 mils.
The parasitic capacitance of the ESD
components for the USB port is less than 2
pF.

1.11 Design Requirements on the ETH Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

It is recommended that the MDIO pin

connect to a 1.5 kΩ pull-up resistor.
It is recommended that the MDCK signal
connect to a 22 Ω resistor in series at the
source end to ensure the signal quality.
The I/O power of the network port PHY is
consistent with the power of the
DVDDIO_RMII pin for Hi3518E V20X.
The MAC interface of Hi3518E V20X
supports only the reduced media
independent interface (RMII) mode, and
therefore the mode of the network port PHY
must be the RMII mode.
RMII_CLK can be output by Hi3518E
V20X or the network port PHY, which can
be specified based on the features of the
network port PHY and as required. A 22 Ω
resistor needs to be connected in series at
the output end of RMII_CLK.
The connection mode of the transformer
center tap varies according to ETH PHY
vendors. It is recommended that the
transformer center tap be connected by
following the application notes and
reference designs provides by ETH PHY
vendors.

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1.12 Design Requirements on JTAG and System Control

Circuits
√ Item Customer Confirmation Remarks
(PASS/NO PASS)

TDI, TDO, and TMS connect to 4.7 kΩ

pull-up resistors. TCK connects to a 4.7 kΩ
pull-down resistor. TRST connects to a 10
kΩ pull-down resistor, and a 10 kΩ pull-up
resistor is reserved.
The pull-up and pull-down resistors of the
TRST signal are designed based on the
requirements of the selected simulator. The
pull-up and pull-down resistors cannot be
soldered at the same time.
If the JTAG pin is not used, it can be
multiplexed as a GPIO pin by changing the
pull-up/pull-down status of the JTAG_EN
pin.
The TEST_MODE pin connects to a 4.7 kΩ
pull-down resistor.

1.13 Design Requirements on the SD Card Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

It is recommended that the power-on and

power-off of the secure digital (SD) card
power be controlled by the metal–oxide–
semiconductor field-effect transistor
(MOSFET). The control signal is active
high.
When the board needs to support the secure
digital extended capacity (SDXC) card, the
DVDD18_SDIO pin must connect to a 1.8
V power.
When the board needs to support only the
secure digital high capacity (SDHC) card,
the DVDD18_SDIO pin can be floated.
When the board needs to support the SDXC
card, the DATA and CMD signals of the
SDIO must connect to 10 kΩ pull-up
resistors and then to SDIO_VOUT. The

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SDIO_CARD_DETECT signal connects to

a 10 kΩ pull-up resistor and then to the 3.3
V power.
When the board needs to support only the
SDHC card, the DATA and CMD signals of
the SDIO can connect to 10 kΩ pull-up
resistors and then to SDIO_VOUT or the 3.3
V power.
When the level of the
SDIO0_CARD_DETECT signal is low,
card detection is enabled; when the level of
the SDIO0_CARD_DETECT signal is high,
card detection is disabled. The pull-up and
pull-down resistors of the circuit need to be
designed based on the circuit function
requirements.
When the level of the SDIO0_CWPR signal
is low, write protection of the SD card
circuit is disabled; when the level of the
SDIO0_CWPR signal is high, write
protection of the SD card circuit is enabled.
The pull-up and pull-down resistors of the
circuit need to be designed based on the
circuit function requirements.
During the PCB layout, the components that
consume much power should not be placed
on the back side of the SD card. This
prevents the SD card from being damaged at
high temperatures.
For details about how to use SDIO
interfaces that function as the GPIO
interfaces, see the description of GPIO
interfaces in the Hi3518E V20X/Hi3516C
V200 Economical HD IP Camera SoC Data
Sheet.

1.14 Design Requirements on the UART Circuit

√ Item Customer Confirmation Remarks
(PASS/NO PASS)

The debugging serial port must be led out.

Universal asynchronous receiver transmitter
0 (UART0) is used for debugging by

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default.
The level of UART1/UART2 is consistent
with that of DVDD3318_EMMC, which can
be 3.3 V or 1.8 V. The interface level of the
interconnected component must be
consistent with the level of
UART1/UART2.

1.15 Design Requirements on Heat Dissipation

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The product structure is considered during

the heat dissipation design of the board. The
size of the heat dissipation layer is as large
as possible when the space is sufficient.

1.16 Design Requirements on the Sensor

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To ensure picture quality, it is recommended

that the low dropout regulator (LDO) be
used to supply power to the sensor. Special
attention needs to be paid to the sensor
analog power and PLL power filtering. The
current of the sensor core power is large in
general. Therefore, the LDO efficiency and
heat dissipation performance need to be
considered during sensor design.
Decoupling capacitors are placed close to
the sensor power pins. A high-impedance
decoupling capacitor and a low-impedance
decoupling capacitor are connected to each
analog power pin, and one decoupling
capacitor is connected to at most two other
power pins.
If the sensor board is connected to the main
board by using a connector, to avoid signal

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 Hi3518E V20X/Hi3516C V200 Hardware Design
Checklist 1 Checklist

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quality deterioration, ensure that current

return GNDs are sufficient for the data
signals from the connector during connector
design.

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Technologies Co., Ltd.