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320 Functions of Combinational Logic

Solution
For n = 1: A1 = 0, B1 = 0, and C n - 1 = 0. From the 1st row of the table,
© 1 = 0 and C 1 = 0
For n = 2: A2 = 0, B2 = 0, and C n - 1 = 0. From the 1st row of the table,
© 2 = 0 and C 2 = 0
For n = 3: A3 = 1, B3 = 1, and C n - 1 = 0. From the 4th row of the table,
© 3 = 0 and C 3 = 1
For n = 4: A4 = 1, B4 = 1, and C n - 1 = 1. From the last row of the table,
© 4 = 1 and C 4 = 1
C4 becomes the output carry; the sum of 1100 and 1100 is 11000.

Related Problem
Use the truth table (Table 6–3) to find the result of adding the binary numbers 1011
and 1010.

Implementation: 4-Bit Parallel Adder

Fixed-Function Device   The 74HC283 and the 74LS283 are 4-bit parallel ­adders with
identical package pin configurations. The logic symbol and package pin configuration are
shown in Figure 6–10. Go to ti.com for data sheet information.

VCC

(16)
(5) Σ
Σ2 1 16 VCC 1
(3)
2
B2 2 15 B3 (14) A
3 (4)
1
A2 3 14 A3 (12) (1)
4 2
Σ (13)
Σ1 4 13 Σ3 (6) 3
1
(2) (10)
A1 5 12 A4 2 4
(15) B
B1 6 11 B4 3
(11)
4
C0 7 10 Σ4
(7) C0 (9)
C4 C4
GND 8 9
(8)

GND
(a) Pin diagram (b) Logic symbol

FIGURE 6–10 The 74HC283/74LS283 4-bit parallel adder.

fg06_01000
Programmable Logic Device (PLD)   A 4-bit adder can be described using VHDL and
implemented in a PLD. First, the data flow approach is used to describe the full adder,
which is shown in Figure 6–4(b), for use as a component. (Blue text comments are not part
of the program.)
entity FullAdder is
port (A, B, CIN: in bit; SUM, COUT: out bit); Inputs and outputs declared
end entity FullAdder;
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Parallel Binary Adders 321

architecture LogicOperation of FullAdder is

begin
SUM 6= (A xor B) xor CIN;

˛˝¸
Boolean expressions for
COUT 6= ((A xor B) and CIN) or (A and B); the outputs
end architecture LogicOperation;
Next, the FullAdder program code is used as a component in a VHDL structural approach
to the 4-bit full-adder in Figure 6–9(a).
entity 4BitFullAdder is
A1-A4: inputs port (A1, A2, A3, A4, B1, B2, B3, B4, C0: in bit; S1, S2, S3, S4, C4: out bit);
B1-B4: inputs end entity 4bitFullAdder;
C0: carry input
architecture LogicOperation of 4BitFullAdder is
S1-S4: sum outputs
component FullAdder is

˛˚˝˚¸
C4: carry output
   port (A, B, CIN: in bit; SUM, COUT: out bit); Full-adder component
­declaration
end component FullAdder;
signal Cl, C2, C3: bit;
begin
FA1: FullAdder port map (A =7 A1, B =7 B1, CIN =7 C0, SUM =7 S1, COUT =7 Cl);
¸˚˝˚˛

Instantiations for each of FA2: FullAdder port map (A =7 A2, B =7 B2, CIN =7 C1, SUM =7 S2, COUT =7 C2);
the four full adders FA3: FullAdder port map (A =7 A3, B =7 B3, CIN =7 C2, SUM =7 S3, COUT =7 C3);
FA4: FullAdder port map (A =7 A4, B =7 B4, CIN =7 C3, SUM =7 S4, COUT =7 C4);
end architecture LogicOperation;

Adder Expansion
The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by Adders can be expanded to handle
using two 4-bit adders. The carry input of the low-order adder (C0) is connected to ground more bits by cascading.
because there is no carry into the least significant bit position, and the carry output of the
low-order adder is connected to the carry input of the high-order adder, as shown in Fig-
ure 6–11. This process is known as cascading. Notice that, in this case, the output carry is
designated C8 because it is generated from the eighth bit position. The low-order adder is

B8 B7 B 6 B5 A8 A7 A6 A 5 B 4 B3 B2 B1 A 4 A3 A2 A1

C0

4 3 2 1 4 3 2 1 Cin 4 3 2 1 4 3 2 1 Cin

B A B A
Σ Σ

Cout 4 3 2 1 Cout 4 3 2 1

C8 Σ8 Σ7 Σ6 Σ5 Σ4 Σ3 Σ2 Σ1

FIGURE 6–11 Cascading of two 4-bit adders to form an 8-bit adder.

fg06_01200