Chapter 4

Metal Oxide Semiconductor Field

Effect Transistors (FET)
MOSFET DC Analysis
By
Wan Rosmaria Wan Ahmad
for ELE424/ELE422
March – Aug 2023

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Subtopic in MOSFET DC Analysis
1. Introduction
2. NMOS Common Source Circuit
3. PMOS Common Source Circuit
4. Design Examples
5. Load Line

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Introduction
Why is dc biasing required?
• As was stated in earlier topics, an amplifier system is able to amplify an ac input signal.
• MOSFET can function as an amplifying device.
• The biasing circuit is required to ensure that the MOSFET operates at the intended Q-point in
the output characteristics.
• Before doing ac analysis, we need to bias the MOSFET and do the necessary dc analysis first.

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MOSFET and other components
• In most of the circuits presented in this chapter, resistors are used in conjunction with the
MOS transistors.
• In a real MOSFET integrated circuit, however, the resistors are generally replaced by other
MOSFETs, so the circuit is composed entirely of MOS devices. In general, a MOSFET device
requires a much smaller area than a resistor.
• Integrated circuit refers to a circuit that is entirely built on a common substrate and is
miniaturized.
• If designing circuits on PCB with MOSFETs as individually packaged component,
components may be as individually packaged components. But if MOSFETs exists in an
integrated circuits, other components can be constructed using the MOSFET construction –
resistors, capacitors and inductors.

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NMOS Common Source Circuit:
Basic Circuit
• One of the basic MOSFET circuit
configurations is called the common-source
circuit.
• Shown: common-source circuit, using
NMOS enhancement mode.
• The S terminal is at ground potential and is
common to both the input and output
portions of the circuit.
• The coupling capacitor CC acts as an open
circuit to dc but it allows the signal voltage
to be coupled to the gate of the MOSFET.

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 Common-Source Circuit
DC Equivalent Circuit
• DC Equivalent circuit have coupling capacitors replaced as open
circuits.
• Since the gate current into the transistor is zero, the voltage at
the gate VG is given by a voltage divider, which can be written as

• Assuming that the VGS>VTN and that VDS>VGS-VTN, and that the
transistor is biased in the saturation region, the drain current
is

• The drain-to-source voltage using Ohm’s Law:

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Common-Source Circuit
DC Analysis
• We had assumed that dc analysis was functioning
in saturation region to find iD.
• With iD, we can use Ohm’s Law to give us vD
hence VDS. We then check backwards, with the VDS
found, if the MOSFET is operating in saturation
region by comparing it with VGS - VTN. If it is not,
then it will be in nonsaturation region (triode
region) and the relevant expression will have to be
used.
• The power dissipated in the transistor, since there
is no gate current, is simply given by PT = IDVDS

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Example: NMOS Common Source
Circuit
• Calculate iD and vDS. Find the power dissipated in
the transistor. Given that R1 = 30 kΩ, R2 = 20 k Ω,
RD = 20 kΩ, VDD = 5 V, VTN = 1 V, and Kn = 0.1
mA/V2.

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 To find ID;
• Calculate iD and vDS. Find the power dissipated in Assume transistor operates in saturation region
the transistor. Given that R1 = 30 kΩ, R2 = 20 k Ω, ID = KN(VGS – VTN)2
RD = 20 kΩ, VDD = 5 V, VTN = 1 V, and Kn = 0.1 = 0.1m(2 - 1)2
mA/V2.
= 0.1mA
To find VDS at output;
VDS = VDD – IDRD = VD-VS
= 5 – (0.1m)(20k)
= 3V
Checking assumption;
Assume transistor operates in saturation
region
VDS(sat) = (VGS – VTN)
= (2 - 1)
To find VGS; (VS=0, R1 in series with R2) = 1V
Use VDR
Since VDS≥ VDS(sat);
𝑅2 20𝑘
𝑉𝐺𝑆 = 𝑉𝐷𝐷 = 5 = 2𝑉 VDS=3V ≥ 1V → The analysis is valid that
𝑅1 + 𝑅2 30𝑘 + 20𝑘 the transistor operates in saturation
Or; region
VGS = VG – VS = 2 – 0 = 2V
Since VDS≥ VDS(sat);
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PT=IDVDS = (0.1m)(3) = 0.3 mW
 Exercise

When the bias condition may not be obvious, which means that we have to do an initial
guess:
1. Assume that the transistor is biased in the saturation region, in which case VGS > VTN ,
ID > 0, and VDS ≥ VDS(sat).
2. Analyze the circuit using the saturation current-voltage relations.
3. Evaluate the resulting bias condition of the transistor. If the assumed parameter values
in step 1 are valid, then the initial assumption is correct.
4. If the initial assumption is proved incorrect, then a new assumption must be made and
the circuit reanalyzed. Step 3 must then be repeated.

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PMOS Common Source Circuit: Basic
Circuit
• Figure shows a dc equivalent circuit of a common-source circuit with a
PMOS.
• The source terminal is tied to +VDD, which becomes signal ground in the
ac equivalent circuit. Thus, the terminology common-source applies to
this circuit.
• VG is given by a voltage divider:

• Assuming that the VSG>|VTP | and that VSD>VSG+VTP, and that the
transistor is biased in the saturation region, the drain current is

• The drain-to-source voltage using Ohm’s Law:

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Example: Common Source Circuit with
PMOS To find V ; (I =0, R in series with R ) SG G 1 2
Use VDR
Calculate iD and vSD. Find the power dissipated in
the transistor. Given that R1 = 50 k Ω, R2 = 50 𝑅2 50𝑘
𝑉𝐺 = 𝑉𝐷𝐷 = 5 = 2.5𝑉
kΩ, RD= 7.5 kΩ, VDD = 5V, VTP = -0.8 V, and Kp 𝑅1 + 𝑅2 50𝑘 + 50𝑘
= 0.2 mA/V2.
Or;
VSG = VS – VG = 5 – 2.5 = 2.5V

To find ID;
Assume transistor operates in saturation region
ID = KP(VSG – VTP)2
= 0.2m(2.5 – 0.8)2
Note: This example is = 0.578mA
purposely selected to
To find VSD at output;
show what happens
VD = IDRD = (0.578m)(7.5k) = 4.335V
when the assumption
VSD = VS –VD (VS = VDD = 5V)
is wrong.
= 5 – 4.335
= 0.665V
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Checking assumption; ID in triode region expression;
Assume transistor operates in saturation region
VSD(sat) = (VSG – VTN)
= (2.5 – 0.8) ID = 0.2 [2(2.5-0.8)(5-7.5ID) - (5-7.5ID)2]
= 1.7V
Solving ID using quadratic equation,
Since VSD(0.665V) ≥ VDS(sat)(1.7V) → The ID = 0.515mA
assumption is not valid. The PMOS transistor
not operates in saturation region. We need to VSD = VS – VD
reanalyse using triode expression. =VDD – IDRD
= 5 – 7.5ID
= 5 – 7.5(0.515m)
= 1.4V

Checking assumption again;

VSD ≤ VSDsat
1.4 < 1.7V
It is verified that this PMOS operates in triode
region.

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Design Examples

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Design Example:
NMOS Common-Source Circuit with dual supply
Objective:
Design a MOSFET circuit biased with both positive and
negative voltages to meet a set of specifications.
Specifications:
The circuit configuration to be designed is as shown.
Design the circuit such that IDQ= 0.5 mA and VDSQ=4V.
Choices:
Standard resistors are to be used in the final design.
A transistor with nominal parameters of kn’ = 80μA/V2,
(W/L) = 6.25, and VTN = 1.2 V is available.
Task: find values of RD and RS to achieve the Q-point.

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Solution:
Find RD,
Transistor process specification and size are given, find
VDD=IDRD+VDS+ISRS+VDDneg
transconductance parameter, KN
𝑉𝐷𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆 − 𝑉𝐷𝐷𝑛𝑒𝑔
𝐾𝑁′ 𝑊 0.08 𝑅𝐷 =
𝐾𝑁 = = 6.25 = 0.25𝑚 𝐴ൗ 2 𝐼𝐷
2 𝐿 2 𝑉
5 − 4 − 0.5𝑚 4.772𝑘 − −5
𝑅𝐷 = = 7.228𝑘Ω
Find VGS, assume transistor operates in saturation region, 0.5𝑚
ID = KN(VGS – VTN)2
Find VS;
𝐼𝐷 0.5𝑚 VS=IDRS+VDDneg
𝑉𝐺𝑆 = + 𝑉𝑇𝑁 = + 1.2 = 2.614𝑉 =(0.5m)(4.772k)-5
𝐾𝑁 0.25𝑚
=2.386-5
= -2.614V
Find Vs then RS,
(IG=0, VG=0)
Find VD;
VGS = VG – ISRS-VDDneg
VD=VDS+VS
−𝑉𝐺𝑆 − 𝑉𝐷𝐷 −2.614 − −5 = -2.614 +4
𝑅𝑆 = = = 4.772𝑘Ω = 1.386V
𝐼𝐷 0.5𝑚

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Checking assumption; Saturation equation Solving ID;
Assume transistor operates in saturation ID = KN(VGS – VTN)2 5 − 2.6224
region ID = 0.25m(VGS – 1.2)2 → (eq. 2) 𝐼𝐷 =
4.7𝑘
= 0.5059𝑚𝐴
VDS(sat) = (VGS – VTN)
= (2.614 – 1.2) Substitute (eq. 2) →(eq. 1) Solving VDS;
= 1.414V VDS = VDD – ID(RD+RS) -VDDneg
Since VDS=4V, transistor is in saturation 5 − 𝑉𝐺𝑆 2 = 5 – (0.5059m)(4.7k+7.5k)-(-5)
= 0.25𝑚 𝑉𝐺𝑆 − 1.2
region because VDS>VDSsat. The assumption 4.7𝑘 = 3.828V
is valid. 2
5 − 𝑉𝐺𝑆 = 1.175 𝑉𝐺𝑆 − 2.4𝑉𝐺𝑆 + 1.44
Finding the standard resistor value 2
1.175𝑉𝐺𝑆 − 1.82𝑉𝐺𝑆 − 3.308 = 0
For calculated resistor
RS = 4.712 kΩ → RS = 4.7 kΩ
RD= 7.23 kΩ → RD = 7.5 kΩ Using Quadratic equation, solve VGS.

With chosen value, −𝑏 ± 𝑏2 − 4𝑎𝑐

𝑉𝐺𝑆 =
VG=VGS+IDRS+VDDneg 2𝑎
Since IG=0, VG=0, − −1.182 ± −1.182 2 − 4 1.175 −3.308
VGS=VG – IDRS - VDDneg 𝑉𝐺𝑆 =
2 1.175
= 0 – ID (4.7k) – (-5) 1.82 ± 18.86
VGS = 5 – ID (4.7k) 𝑉𝐺𝑆 = = 2.6224𝑉
2.35
5 − 𝑉𝐺𝑆
𝐼𝐷 = →(eq. 1) VGS=2.6224V 23
4.7𝑘
Design Example: PMOS Common-Source Circuit, with 4
resistors and limitation to value R, with process
variation.

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Assume saturation. Use ID in saturation formula.

Check saturation assumption

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Finding VG, where Deciding R1 or R2 is 200k Ω, we need to find current, Ibias,
VSG=VS-VG and VRS=VDD-VS so that the other resistor can be found using Ohm’s Law.
In this case we cannot use VDR because With VG>0, the resistor R2 will be greater /larger than the
R1 & R2 unknown. two bias resistors, so let set R2 = 200k Ω.
Either one needs to be 200kΩ
Therefore, The current through R2 is,
V+ = VRS + VSG + VG Ibias R2 = VG – V-
VG = V+ - VRS - VSG Ibias = VG – V- = 0.3 – (-2.5) = 0.014mA
= 2.5-0.8-1.4 R2 200k
= 0.3V
VS=VSG+ VG = 1.4 + 0.3 = 1.7V Knowing Ibias, we can find R1 using Ohm’s Law

VS=VDS+IDRD+VDDneg Ibias R1 =V+ - VG

RD= VS-VDS-VDDneg R1 = V+ –VG = 2.5 – (0.3) = 157 kΩ
ID Ibias 0.014m
= 1.7 – 3 – (-2.5)
100µ
= 15 kΩ
VRD=IDRS
Rs= VRS_= _0.8_ = 8kΩ
ID 100µ
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Finding RS using Ohm’s Law. What happens if Kp varies 5%? With values found for RS, RD,
R1 and R2, the resulting variation on VGSQ, IDQ and VSDQ can
be found.

Finding VD from VSD where VSD=VS-VD and

VRS=VDD-VS.
** I cannot use Ohm’s Law yet because I do not
know RD.

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MOSFET Common Source Load Line
for MOSFET DC Analysis

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MOSFET Common Source Load Line
Finding Load Line in Common Source Circuits KVL:

• Writing a Kirchhoff ’s voltage law equation around the

output loop with iD and vDS will give the load line.

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Load Line: Transition Point
• Following the load line established, If VGS<VTN,
iD is zero and the transistor is in cutoff.
• As VGS becomes just greater than VTN, the
transistor turns on and is biased in the saturation
region.
• As VGS increases, the Q-point moves up the load
line.
• The transition point is the boundary between the
saturation and non-saturation regions and is
defined as the point where;
VDS = VDS(sat) = VGS − VTN
• As VGS increases above the transition point
value, the transistor becomes biased in the non-
saturation region.

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Example: Transition Point
The transition point (ID, VGS, VDS)
Determine the transition point
parameters for the common-source At transition point (saturation);
circuit with VTN = 1V and Kn = 0.1 Assume transistor operates in saturation region
mA/V2.
VDS = VDS(sat) = (VGS – VTN) → eq. (1)
KVL at output
VDD = IDRD + VDS + VS (VS = 0)
VDS = VDD – IDRD = 5 – ID(20k) → eq. (2)

Saturation Region Current

ID = KN(VGS – VTN)2
= 0.1m(VGS - 1)2 → eq. (3)

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Subs eq. (1) & (3) into eq. (2)
(VGS – VTN) = 1.35V, VTN = 1V,
VGS = 1.35 + 1V = 2.35V
(VGS – VTN) = VDD – KN(VGS – VTN)2RD
RD KN(VGS – VTN)2 + (VGS – VTN) - VDD = 0 From eq. (3),
(0.1)(20) (VGS – VTN)2 - (VGS – VTN) – 5 =0 ID = KN(VGS – VTN)2
2 (VGS – VTN)2 - (VGS – VTN) – 5 =0
= 0.1m(VGS - 1)2
= 0.1m(2.35 - 1)2
Using Quadratic equation, find (VGS – VTN) = 0.182 mA
a=2, b=1, c= -5
VDS = VDS(sat) = (VGS – VTN) = 1.35V
−𝑏 ± 𝑏2 − 4𝑎𝑐
𝑉𝐺𝑆 − 𝑉𝑇𝑁 = For the given loadline, The transition point is;
2𝑎
ID = 0.182 mA
−1 ± 12 − 4 2 −5
𝑉𝐺𝑆 − 𝑉𝑇𝑁 = VGS = 2.35V
2 2 VDS = 1.35V
𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 1.35𝑉
If the given loadline:
If VGS < 2.35V, transistor is in saturation,
If VGS > 2.35V, transistor is in non-saturation (triode
region)

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Next: MOSFET AC Analysis
for Common Source Circuits

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