Analysis of different Adders using CMOS, CPL and

DPL logic
∗ S.Nagaraj † Dr. G.M.Sreerama Reddy ‡ Dr. S.Aruna Mastani
Research Scholar Prof and Head Asistant Professor
Department of ECE Department of ECE Department of ECE
JNTUA Anantapuramu,AP CBIT Kolar,KA JNTUA Anantapuramu,AP
Email:[email protected] Email:[email protected] Email:aruna [email protected]

Abstract—In this paper we design and analyse different 3. Carry Save Adder
types of adders using CMOS, Complementary Pass Transistor 4. Carry Incremental Adder
Logic(CPL), Double Pass Transistor Logic(DPL) logics. Ripple 5. Carry Skip Adder
Carry Adder, Carry Look Ahead Adder, Carry Save Adder,
Carry Incremental Adder, Carry Skip Adder, Carry Select Adder, 6. Carry Select Adder
Conditional Sum Adder are designed using CMOS, Comple- 7. Conditional Sum Adder
mentary Pass Transistor Logic(CPL), Double pass transistor
logic(DPL) logics for 16-bit, 32-bit and their speed, area and
power are compared. A. Ripple Carry Adder
Index Terms—Ripple Carry Adder,Carry Look Ahead Adder,
Carry Incremental Adder, Carry Skip Adder, Carry Select Adder, Ripple Carry Adder(RCA) is the basic Adder. Ripple Carry
Conditional Sum Adder, CMOS, Complementary Pass Transistor Adder which takes two N-bit numbers and produces 1-bit
Logic, Double Pass Transistor Logic.
carryout, N-bit sum and total of (N+1) bits as output. Ripple
I. INTRODUCTION Carry Adder of N-bit requires N number of Full Adders.
Ripple Carry Adder(RCA) is formed by connecting full adders
Adders play an important role in many Arithmetic opera- in series. Let the operands be A and B each full adder receives
tions. Adders are used in addition, subtraction, multiplication carry called input carry (Cin) and gives out carry called output
and division basic operations. Adders are also used in Arith- carry (Cout). The output carry(Cout) of each full adder acts
metic Logic Unit(ALU), general microprocessors and digital as input to the next full adder input carry(Cin). The input
signal processors. Thus the performance of Adders is predomi- carry(Cin) for the first full adder is zero. The output carry
nant in the entire operation. So we need efficient adders which (Cout) of the last full adder is the overall carry output(Cout).
has high speed, low power and occupy small area. Researches The result is overall carry out (Cout) and sum output of each
has been carried out to develop adder circuits that decrease full adder. Since each carry bit gets rippled to next stage it is
carry propagation delay [1] [2] [3]. Researches has developed called Ripple Carry Adder.
method for fast propagation of carry [4]. Carry Skip and Carry
The Figure 1 shows 4-bit Ripple Carry Adder which uses
select adders are used and analyzed for optimization in [8]
four full adders FA1-FA4 and takes 4-bit inputs A3-A0 and
[9]and [10]. As the VLSI technology is growing low power
B3-B0,Cin=0 and produces output Carry Cout, Sum S3-S0.
is important factor. Low power can be acheived at circuit,
architecture, layout and process technology [11]. There are
different transistor circuit level logic styles [12]. The works
of [19], [20], [21], [22], [23], [24], [25], [26] shows that
CPL or Pass Transistor Logic styles are preffered for Low
power. By choosing proper logic styles at circuit level we
can acheive considerable amount of power savings for Adders.
In this project different Adders are simulated using HSPICE
for 180nm technology and their speed, area and power are
compared.
II. ADDERS
The following adders are simulated and analysed using
CMOS, Complementary Pass Transistor Logic(CPL), Double
Pass Transistor Logic(DPL). Fig. 1. Ripple Carry Adder
1. Ripple Carry Adder
2. Carry Look Ahead Adder

978-1-5386-4318-1/17/$31.00 ©2017 IEEE

B. Carry Look Ahead Adder time delay is reduced at the cost of 4 extra full adders.
Carry Look Ahead Adder(CLA) is fast adder compared to
Ripple Carry Adder. In Ripple Carry Adder the delay depends
on the length of Adder and the number of bits. The carry out
time contributes largely to the time delay. The Carry Look
Ahead Adder has generate signal gi and propagate signal pi .
The equations of gi , propagate signal pi sum and carryout are
g i = ai b i
pi = a i ⊕ b i
si = pi ⊕ ci
ci+1 = gi + pi ∗ ci
The Figure 2 shows 4-bit Carry Look Ahead Adder.If we
consider 4-bit Ripple Carry Adder the equations are as
follows
s0 = p0 ⊕ c0
c 1 = g 0 + p0 c 0
s1 = p1 ⊕ c1
c 2 = g 1 + p1 c 1
c 2 = g 1 + p1 g 0 + p1 p 0 c 0 Fig. 3. Carry Save Adder
s2 = p2 ⊕ c2
c 3 = g 2 + p2 c 2
c 3 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p1 p 0 c 0 D. Carry Incremental Adder
s3 = p3 ⊕ c3
c 4 = g 3 + p3 c 3 Carry Incremental Adder uses different logic to perform the
c 4 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p2 p 1 g 0 + p 3 p2 p1 p 0 c 0 addition operation. Figure 4 shows 8-bit Carry Incremental
Adder which uses two Ripple Carry Adders (RCA) of 4-bit
each. The first Ripple Carry Adder (RCA) carry out (Cout)
acts as input to conditional increment block.The first Ripple
Carry Adder(RCA) gives sum which is the first 4-bit sum
output. The conditional increment block contains Ripple Carry
Adder(RCA) 4-bit and half adders.These half adders take the
sum of second Ripple Carry Adder(RCA) and the previous
stage carry as shown in the Figure 4. The output of half adder
gives the resultant sum and the carry is forwaded to next half
adder. The last half adder carry is overall carry out(Cout).
Carry Look Ahead Adder can also be used in place of Ripple
Carry Adder for better performance.

E. Carry Skip Adder

Carry Skip Adder is also known as Carry Bypass Adder.
Fig. 2. Carry Look Ahead Adder Carry Skip Adder also has full adders cascaded in series like
Ripple Carry Adder (RCA) in addition to that it has 2x1
Multiplexer as shown in the Figure 5 . The full adders has
the inputs and produces propagate signal (P) and carry out
C. Carry Save Adder
(Cout). The propagate signal (P) acts as output sum where
Carry Save Adder reduces time delay of operation by as the overall output carry (Cout) is obtained from the 2x1
adding carry in next stage. Carry Save Adder for 4-bit is Multiplexer. The logic here is if the all the propagate signals
shown in the Figure 3. This adder uses 8 Full Adders, 4 Full (P) are ’1’ then the overall output carry (Cout) is same as
Adders in the first stage and 4 Full Adders in second stage. overall intput carry (Cin) or else overall output carry (Cout)
The first stage 4 Full Adders gives sum and carry at a time is the last full adder output carry.
and the carry generated in this stage are added to next stage
4 Full Adders as shown in the Figure 3. Where as in Ripple F. Carry Select Adder
Carry Adder(RCA) each Full Adder has to wait for the carry Carry Select Adder is also fast adder. It can be used for
generated from the earlier Full Adder. This wait time for faster arithmetic operations The Figure 6 shows 8-bit Carry
carry is eliminated by adding carry in the next stage.Thus the Select Adder.It consists of three Ripple Carry Adders, the first
 Fig. 4. Carry Incremental Adder Fig. 6. Carry Select Adder

group size reaches 1. The Figure 7 shows a 4-bit conditional

sum adder and this can be extended.

Fig. 5. Carry Skip Adder

Ripple Carry Adder input carry(Cin) is ’0’ and inputs A[3-

0],B[3-0] .The other two Ripple Carry Adders has the inputs
A[4-7],B[4-7] the sum is calculated by assuming input carry
(Cin) as ’1’ and by assuming input carry (Cin) as ’0’ and then
the sum is choosen between these two results based on first Fig. 7. Conditional Sum Adder
Ripple Carry Adder COUT1. Multiplexer 2x1 is used to select
the sum based on COUT1. The overall result is the output of
2x1 Multiplexer. Carry Select Adder divides adder into blocks
III. CMOS L OGIC
and the operation is performed.
CMOS Logic is most popular MOSFET technology. CMOS
G. Conditional Sum Adder technology has the main advantage of much smaller power
Conditional Sum Adder consist of full adders here two sets dissipation and also CMOS has almost no static power dissi-
of output are calculated for given group of operands. One pation. When there is switching then only power is dissipated.
output is calculated for carry input (Cin) ’0’ and for carry input This allows us to integrate more CMOS gates on IC than bipo-
(Cin) ’1’. For a n-bit operand it is divided into two groups of lar or NMOS technology and resulting in better performance.
n/2 bits each. Each of these groups are further divided into CMOS technology uses NMOS and PMOS transisitors to
two groups of n/4 bits each. This process is done until the implement logic functions. A signal turns on transistor of
one type and turns off transistor of other type. CMOS design
is implemented using simple switches without using pull up
resistor.
CMOS logic gates consists of NMOS transistors in pull
down network between lower voltage power supply and out-
put. CMOS logic gates have collection of PMOS transistors
in pull up network between output and higher voltage. Input
is connected to both PMOS and NMOS and when PMOS
transistor is on then NMOS transistor is off and vice versa
.
The Figure 8 shows a CMOS inverter circuit when the input
IN is low the PMOS tansistor in on, NMOS transistor is off
and thus output OUT is high. When the input IN is high PMOS
transistor is off, NMOS transistor is on and thus output OUT
is low.
Fig. 9. Complementary Pass Transistor Logic(CPL)

to NMOS transistor gives full swing operation. Double Pass

Transistor Logic(DPL) meets reduced supply voltage design
requirements. Double Pass Transistor Logic(DPL) is the mod-
ified version of Complementary Pass Transistor Logic(CPL)
that solves problems of speed degradation and noise margins
at reduced supply voltages.The Figure 10 shows DPL AND
gate circuit.

Fig. 8. CMOS INVERTER

IV. C OMPLEMENTARY PASS T RANSISTOR L OGIC (CPL)

Complementary Pass Transistor Logic(CPL) uses only
NMOS transistors for logic organization. Complementary Pass
Transistor Logic(CPL) consists complementary inputs/outputs
and NMOS pass transistor network and CMOS output inverters
.Inverted and non-inverted inputs are required to drive gates
of pass transistor. PMOS transistors can be used in place of
Fig. 10. Double Pass Transistor Logic(DPL)
CMOS inverters. The output of pass transistor is less than
the supply voltage and this reduction output voltage is pulled
up by CMOS output inverter or PMOS Latches. The CMOS VI. R ESULTS
inverter or PMOS latches at output makes sure that the ouput
16-bit, 32-bit Ripple Carry Adder, Carry Look Ahead
has voltage swing same as input signal and maintains high
Adder, Carry Save Adder, Carry Skip Adder, Carry Incremen-
speed switching.Complementary Pass Transistor Logic(CPL)
tal Adder, Carry Select Adder, Conditional Sum Adder are
input voltage levels are same as standard CMOS levels which
implemented using CMOS, Complementary Pass Transistor
is disadvantage of having voltage swing equal to Vdd. Comple-
Logic(CPL), Double pass transistor logic(DPL) low power
mentary Pass Transistor Logic(CPL) also has spikes on power
logics. Speed,area and power of these adders are simulated
supply during switching which is not desired. The Figure 9
using HSPICE for 180nm. Table I shows the CMOS, CPL and
shows CPL AND/NAND gate circuit.
DPL 16-bit adders results whereas Table II shows the CMOS,
V. D OUBLE PASS T RANSISTOR L OGIC (DPL) CPL and DPL 32-bit adders results.
In Double Pass Transistor Logic(DPL) PMOS transistor
is added in parallel to NMOS transistor in comparison to VII. CONCLUSION
Complementary Pass Transistor Logic(CPL) which uses only The simulation results has shown that in CMOS logic carry
NMOS pass transistors . Adding PMOS transistor in parallel look ahead adder uses less no of transistors and also has
 TABLE I
16-BIT ADDERS

NAME CMOS CPL DPL

SNO
OF POWER POWER POWER
NO OF NO OF NO OF
ADDER DISSIPA- DELAY DISSIPA- DELAY DISSIPA- DELAY
TRAN- TRAN- TRAN-
TION in in Sec TION in in Sec TION in in Sec
SISTORS SISTORS SISTORS
Watts Watts Watts
RIPPLE CARRY
1 864 25.2280n 0.13595n 864 35.6613n 9.1865n 704 29.1971n 0.11598n
ADDER
CARRY LOOK
2 672 19.0662n 0.13077n 864 35.6613n 9.0084n 704 29.1971n 0.11736n
AHEAD ADDER
CARRY SAVE
3 1728 50.4562n 0.14455n 1664 68.4078n 0.10357n 1344 55.4794n 0.12447n
ADDER
CARRY
4 INCREMENTAL 1020 29.4767n 0.13592n 1044 43.1350n 9.1782n 848 35.0725n 0.11595n
ADDER
CARRY
INCREMENTAL
5 828 23.3030n 0.13046n 1044 43.0850n 9.0576n 848 34.9726n 0.1178n
ADDER USING
CLA
CARRY SELECT
6 1788 53.2679n 0.13602n 1620 4.1555m 9.1664n 1382 55.6100n 0.11601n
ADDER
CARRY SKIP
7 1016 29.2188n 0.13765n 1024 1.0701m 9.3254n 832 32.3971n 0.11716n
ADDER
CONDITIONAL
8 2560 79.7119n 0.15108n 2984 126.0350n 0.22888n 2400 94.2735n 0.13681n
SUM ADDER

TABLE II
32-BIT ADDERS

NAME CMOS CPL DPL

SNO
OF POWER POWER POWER
NO OF NO OF NO OF
ADDER DISSIPA- DELAY DISSIPA- DELAY DISSIPA- DELAY
TRAN- TRAN- TRAN-
TION in in Sec TION in in Sec TION in in Sec
SISTORS SISTORS SISTORS
Watts Watts Watts
RIPPLE CARRY
1 1728 50.4562n 0.13595n 1728 71.3225n 9.2152n 1408 58.3941n 0.11599n
ADDER
CARRY LOOK
2 1344 38.1324n 0.13077n 1728 71.3226n 9.0084n 1408 58.3941n 0.11736n
AHEAD ADDER
CARRY SAVE
3 3456 100.9133n 0.14455n 3328 136.8160n 0.10357n 2688 110.9588n 0.12447n
ADDER
CARRY
4 INCREMENTAL 2040 58.9536n 0.13592n 2088 86.2700n 9.1782n 1696 70.1450n 0.11595n
ADDER
CARRY
INCREMENTAL
5 1656 46.6060n 0.13046n 2088 86.1700n 9.0576n 1696 69.9451n 0.1178n
ADDER USING
CLA
CARRY SELECT
6 3884 115.8831n 0.13603n 3492 9.7313m 9.2029n 2990 120.0244n 0.11605n
ADDER
CARRY SKIP
7 2032 58.4378n 0.13765n 2048 2.1402m 9.3254n 1664 64.7941n 0.11715n
ADDER
CONDITIONAL
8 5120 159.4241n 0.15108n 5968 252.0702n 0.22888n 4800 188.5474n 0.13681n
SUM ADDER

less power dissipation. But carry look ahead adder does not CMOS, CPL and DPL Logics. It can also be concluded that
have the less time delay when compared to other adders.Carry DPL adders are better than CMOS and CPL logic in terms of
Incremental Adder using carry look ahead adder has less time area, speed and power.
delay with optimum no of transistors and power dissipation.
For CPL logic the results show that carry look ahead adder
uses less no of transistors and also has less power dissipation
but at the cost of time delay, Carry Save Adder has least time
delay at the cost of more no of transistors and power. For DPL
logic carry look ahead adder uses less no of transistors and
also has less power dissipation but has more time delay.Carry
Incremental adders has less time delay with optimum no of
transistors and power dissipation. It is seen that carry look
ahead adder is better in terms of area and power for all the
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