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16 views

Chapter 1

presentation of chapter one

Uploaded by

sanchariguha1996
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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You are on page 1/ 21

Chapter 1

By
Sanchari Guha
Contents
• Introduction
• Scaling
• MOSFET
• Logic gates
• Multiplexer
• Sequential circuits
• CMOS Fabrication
• Fabrication steps
• Stick Diagram
• Behavioral, Structural, and Physical Domains
• MIPS Microprocessor
• Logic Design
• Physical Design
• Design verification
• Packaging and testing
Introduction
• 1947: First functioning point contact transistor at Bell Laboratories by John Bardeen and Walter Brattain.
• 1958: First integrated circuit was Flip-flop using two transistors built by Jack Kilby at Texas Instruments.
• 1960: MOSFET began to manufacture.
• 2008: Intel Itanium 2billion transistors. 16gb flash memory contains 4billion transistors.
• 53% compound annual growth rate over 50 years.
• Miniaturization of transistors.
• Smaller is cheaper, faster, lower in power.
Scaling
1965: Gordon Moore observed that plotting the number of transistors that can be most economically
manufactured on a chip gives a straight line on a semilogarithmic scale. He found transistor count doubling
every 18 months. This observation has been called Moore’s Law. A corollary of Moore’s law is Dennard’s Scaling
Law.
MOSFET
• Metal Oxide Semiconductor Field Effect Transistors
• They draw almost zero control current while idle. They are of two types: nMOS and pMOS, using n-type and
p-type silicon.
• Fairchild’s gates used both nMOS and pMOS transistors, earning the name Complementary Metal Oxide
Semiconductor (CMOS).
• In the 1980s as hundreds of thousands of transistors were integrated onto a single die.

nMOS Transistor pMOS Transistor


Logic Gates
NAND Gate
NOT Gate/ Inverter

1
0 1
1
1 0 1
GND
0
NOR Gate Tristates Buffer

/EN
/1 Z
/1 Z
/0 0
/0 1
Multiplexer
Multiplexers are key components in CMOS.
A 2-input, or 2:1 multiplexer, chooses input D0 when the select is 0 and input D1 when the
select is 1.
The logic function is Y = S · D0 + S · D1.

0
1
0
1
Sequential Circuit
D latch built from a 2-input multiplexer and two inverters
CMOS Fabrication
The fabrication sequence consists of a series of steps in which layers of the chip are defined through a process
called photolithography.
Fabrication steps
Fabrication steps
Fabrication steps
Stick diagram
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

• A wiring track is the space required for a wire


– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch

• Wells must surround transistors by 6 λ


– Implies 12 λ between opposite transistor flavors
– Leaves room for one wire track

• Estimate area by counting wiring tracks


– Multiply by 8 to express in λ
Behavioral, Structural, and Physical Domains
MIPS Microprocessor
• MIPS32 architecture is a simple 32-bit RISC architecture.
• Uses 32-bit instruction encodings but only eight 8-bit general-purpose registers named 0–7.
• The instructions are ADD, SUB, AND, OR, SLT, ADDI, BEQ, J, LB, and SB.
• Each instruction is encoded using one of three templates: R, I, and J.
 R-type instructions (register-based) are used for arithmetic and specify two source registers and a
destination register.
 I-type instructions are used when a 16-bit constant (also known as an immediate) and two
registers must be specified.
 J-type instructions ( jumps) dedicate most of the instruction word to a 26-bit jump destination.
Logic Design
The logic design by defining the top-level chip interface and block diagram. We specify the logic with a
Hardware Description Language (HDL), which provides a higher level of abstraction than schematics or layout.
The Register Transfer Level (RTL) description.
Physical Design
• Floorplanning: The floorplan estimates the area of major units in the chip and defines their relative
placements. The floorplan is essential to determine whether a proposed design will fit in the chip area
budgeted and to estimate wiring lengths and wiring congestion.
• Pitch Matching: Snap-together cells require more design and layout effort but lead to smaller area and
shorter (i.e., faster) wires. The key issue in designing snap-together cells is pitch-matching.
• Slice Plans: It makes easy to calculate wire lengths and evaluate wiring congestion before laying out the
datapath. The slice plan is also critical for estimating area of datapaths. Each wordslice is anno_x0002_tated
with its width, measured in tracks. This information can be obtained by looking at the cell library layouts.
• Arrays: A programmable logic array (PLA) used for the control finite abstract state machines(FSM) next state
and output logic. A PLA can compute any function expressed in sum of products form. The structure is
catpgized into the AND plane the OR plane.
• Area Estimation: A good floorplan depends on reasonable area estimates, which may be difficult to make
before logic is finalized.
Physical Design

Pitch matching PLA


MIPS layout
Design Verification
Packaging and Testing
Most fabrication plants are optimized for wafer throughput rather than latency,
leading to turnaround times of up to 10 weeks.
Clean rooms are filtered to eliminate most dust and other particles that could damage
a partially processed wafer. Wear a “bunny suit” to avoid contaminating the clean
room.
Processed wafers are sliced into dice (chips) and packaged. This wire-bonded package
uses thin gold wires to connect the pads on the die to the lead frame in the center
cavity of the package. More advanced packages offer different trade-offs between
cost, pin count, pin bandwidth, power handling, and reliability.
Even tiny defects in a wafer or dust particles can cause a chip to fail. Chips are tested
before being sold. Testers capable of handling high-speed chips cost millions of
dollars, so many chips use built-in self-test features to reduce the tester time
required.

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