Journal of Electronic Materials (2023) 52:7534–7540

https://doi.org/10.1007/s11664-023-10652-y

ORIGINAL RESEARCH ARTICLE

Maskless Direct‑Write Lithography‑Patterned Molybdenum

Metal‑Contacted Indium Silicon Oxide Thin‑Film Transistors
S. Arulkumar1 · K. Shyaam1 · S. Parthiban1 · Jang‑Yeon Kwon2

Received: 25 November 2022 / Accepted: 28 July 2023 / Published online: 1 September 2023
© The Minerals, Metals & Materials Society 2023

Abstract
In this work, indium silicon oxide (ISO) thin-film transistors (TFT) were developed with molybdenum as the source and drain
contact using sputtering and lithography techniques. The influence of channel length on the electrical properties of the ISO
TFTs was studied by varying the channel length from ultra-short 5 µm to 100 µm. The highest mobility of 13.23 ­cm2/V s
with an on/off ratio of 1­ 08 order was obtained for the ISO TFT post-annealed at 150°C with a channel length of 5 µm and
width of 250 µm. In addition, the bias stress stability of the ISO TFT was measured.
Graphical Abstract

Keywords Indium silicon oxide · thin-film transistor · sputtering process · photolithography process · channel dimensions

Introduction of the active channel layer cannot turn off the transistors,
which significantly affects switching speed. To overcome
The development of ultra-high-definition (UHD) flat panel these problems, various dopants have been added to the
displays requires the fabrication of thin film transistors indium oxide matrix to control the carrier concentration in
(TFT) with small feature size, very high mobility and wide the metal oxide active channel layers.4,8–15 Among them,
optical band gap.1 Indium oxide with spatially spread 5s indium silicon oxide (ISO) is showing major interest owing
orbital is known to have high mobility with a low process- to its excellent mobility and stable operation and low-tem-
ing temperature.2–7 However, the high carrier concentration perature process.11,16–19 The high bond dissociation energy
of silicon improves the stability of the ISO TFT while the
* S. Parthiban smaller ionic size of silicon is expected to reduce the ionic
[email protected]; [email protected] scattering in the indium oxide matrix, thereby improving the
1
Advanced Materials and Devices Laboratory, PSG Institute
electron mean free path for conduction.11 A high-mobility
of Advanced Studies, Peelamedu, Coimbatore 641004, India (31.7 ­cm2/V s) ISO TFT was reported for an ISO TFT fab-
2
School of Integrated Technology, Yonsei University,
ricated using a metal stencil mask with a low processing
Incheon 406‑840, Republic of Korea temperature.20,21 TFT fabrication for display application

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Maskless Direct‑Write Lithography‑Patterned Molybdenum Metal‑Contacted Indium Silicon… 7535

involves the deposition of multiple layers (gate, dielectric, Experimental Section

active channel, source/drain contact and passivation layer)
and hence could lead to alignment issues when using a metal The ISO TFT was fabricated using heavily doped p-type
shadow mask. For industrial applications, it is preferable to silicon wafer [(100) orientation, resistivity: 0.005 Ω cm]
use the photolithography process to pattern and deposit the with thermally grown S ­ iO2 layer (thickness: 100 nm) as the
various layers of the TFT. Since the number of pixels in a substrate. Heavily doped silicon acts as the gate whereas
unit area in a UHD display increases, it is essential to reduce the thermally grown ­SiO2 acts as the dielectric layer for the
the dimensions of the TFTs which act as the driving unit, fabrication of the TFT. A purchased wafer was cleaved into
which can be achieved by the photolithography process. Fab- smaller substrates with a dimension of 1.5 cm × 1.5 cm. The
rication of TFT with the photolithography process enables wafer was cleaned by ultrasonication for 10 min in distilled
the downscaling of TFT feature size to the range of µm. In water, acetone, isopropyl alcohol and again in distilled water,
particular, the maskless writing photolithography process respectively to remove the organic residues on the surface.
allows for the transfer of a high-resolution pattern with a The ISO thin film was deposited on top of the ­SiO2 layer
small feature size (~1 µm), which is not possible when using by radio frequency (RF) sputtering using a 3-inch 1 wt.%
a physical mask. Moreover, the pattern design can be easily silicon-doped indium oxide target with a copper backing
changed using computer-aided design software without the plate. The RF sputtering process was carried out using an
need for generating a new mask for each design. A technol- ATS 500 (HHV, India), and a target-to-substrate distance of
ogy comparison table of commonly used patterning tech- 10 cm was maintained for all depositions. Prior to the sput-
nologies for TFT fabrication is shown in Table I. However, tering process, the chamber was evacuated to 3.5 × ­10−4 Pa
downscaling of the TFT dimensions affects the electrical to remove the atmospheric gases. Argon and oxygen were
properties such as mobility, turn-on voltage and saturation supplied to the chamber such that oxygen partial pressure
behaviour, which need to be taken into account.22,23 ­[O2/(Ar + ­O2)] was kept at 5% to maintain the chamber pres-
Likewise, the charge trapping and charge accumulation sure at 0.4 Pa for the RF sputtering process. A sputtering
in the metal–oxide interface restricts the performance of the power of 60 W was used to deposit ~8 nm of ISO thin film
TFT. These effects can be decreased with the use of a suit- on top of the ­SiO2 layer.
able metal contact with a similar work function as that of The deposited ISO thin film was patterned using a stand-
the semiconductor oxide layer. Molybdenum with a work ard photolithography process. A positive photoresist (AR-P
function of 4.36–4.95 eV, which is equivalent to the work 3510 T) and corresponding developer (AR 300-44) were
function of indium oxide (4.4–4.5 eV), is expected to be used for the patterning process. The positive photoresist
more effective than aluminium (4.06–4.26 eV) for establish- was spin-coated over the samples at 4000 rpm for 60 s and
ing contact with ISO thin film.24–26 prebaked at 100°C for 90 s. The active channel layer pat-
The effect of channel dimensions on the ISO TFT and tern was designed using CleWin software and was exposed
the reactivity of the photoresist and other influences of the over the photoresist layer using a microwriter (ML3, Dur-
patterning process need to be studied for the utilisation of ham Magneto Optics Ltd, UK). The samples were pro-
the ISO TFT for industrial applications. In this work, the cessed in the developer solution and cleaned with distilled
effect of channel downscaling on ISO TFTs was studied water. The pattern was verified using an optical microscope
using various channel dimensions prepared by a photoli- before immersion in diluted hydrochloric acid (0.1 M) solu-
thography process with molybdenum metal contact. The tion, which acts as etchant. After the etching process, the
obtained electrical properties are compared as a function remaining photoresist was stripped using acetone followed
of the channel length and width to determine the impact of by cleaning with distilled water. In a similar manner, the pat-
channel dimensions. tern for the deposition of the metal contact was transferred
over the ISO thin film using the photolithography process.

Table I  Comparison of Factor Maskless writer Photolithography Shadow mask Inkjet printing
commonly used patterning
technologies for TFT fabrication Cost High High Low Low
Resolution Very high High Low Medium
Mask Not needed Needed Needed Not needed
Photoresist Needed Needed Not needed Not needed
Process Multistep Multistep One-step One-step
Material consumption Large Large Medium Low

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7536 S. Arulkumar et al.

A molybdenum metal (3-inch) target was used to deposit pressure of 3.5 × ­10−4 Pa was achieved prior to deposition
~200 nm of molybdenum to act as source and drain con- and the sputtering process was carried out at a sputtering
tact using the RF magnetron sputtering process. The base power of 150 W while maintaining a pressure of 0.4 Pa in
an argon atmosphere. The residual photoresist was stripped
using acetone and the samples were cleaned with distilled
water. The channel length of the active channel layer was
varied from 5 µm to 100 µm whereas the channel width
was maintained at 250 µm for fabrication of the ISO TFT.
Finally, the ISO TFTs were annealed at 150°C for 1 h in air
atmospheric conditions. The structural and optical proper-
ties of the ISO thin film were discussed in our earlier work
and are not repeated here.20,21 The process flow diagram and
optical microscope image of the patterned ISO TFT along
with a schematic representation of the working of the ISO
TFT is shown in Figs. 1 and 2, respectively.

Results and Discussion

The electrical properties of the ISO TFT devices were ana-

lysed using a Keysight B1500A semiconductor device ana-
lyser coupled with a Microtech Cascade probe station. The
effect of the channel dimensions on the electrical properties
of the ISO TFT was studied by measuring the transfer char-
acteristics, i.e. the dependence of drain current on the gate
voltage. Figure 3 shows the transfer characteristics of the
ISO TFT with a fixed channel width of 250 µm, while the
channel length is increased from 5 µm to 100 µm, respec-
tively. It was observed that the increase in the channel length
leads to a gradual shift in the turn-on voltage towards 0 V.
The ISO TFT with the ultrashort channel length of 5 µm
has a turn-on voltage at around −22 V, and an increase in
channel length to 10 µm leads directly to a shift in turn-
on voltage to −15 V. Further, the increase in the channel
Fig. 1  Process flow diagram of ISO TFT fabrication. length leads to a decrease in the hysteresis of the transfer

Fig. 2  (a) Optical microscope images of molybdenum metal contact deposited over patterned ISO thin film and (b) schematic representation for
formation of conduction pathway between source and drain electrode.

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Maskless Direct‑Write Lithography‑Patterned Molybdenum Metal‑Contacted Indium Silicon… 7537

characteristics, while the maximum current of the ISO voltage. Application of a potential between the source and
TFT decreases with the increase in the channel length. The drain leads to the accumulation of charge carriers near the
rapid change in turn-on voltage with an increase in channel source terminal, which stretches towards the drain terminal.
length is explained by the formation of charge accumulation The accumulated charge carriers act as the conduction chan-
between the source and drain. nel between the source and drain contacts which affects the
Figure 2b shows a schematic representation for the forma- effective channel length. For a fixed drain–source voltage,
tion of charge accumulation and depletion regions between the conduction channel established between the source and
the source and drain electrodes for a fixed drain-source drain contacts remains constant. In the case of a decrease in
the physical channel length, this effect is amplified, which is
reflected by the drastic shift in the turn-on voltage towards
the negative region at lower channel length. Conductivity
through the charge accumulation region between source and
drain contacts results in the high drain current at short chan-
nel length, which in turn influences the maximum mobil-
ity and on/off ratio. The large hysteresis that was observed
in the ISO TFT was assumed to be due to the presence of
organic impurities between the metal–semiconductor inter-
face that was not removed during the removal of the pho-
toresist. This effect is clearly visible in short-channel-length
devices where the influence of the contact interface is clearly
emphasised.
These results indicate that the influence of downscaling
of channel dimensions is more dependent on the channel
length. However, unlike the previously reported results
where the mobility decreases with a decrease in chan-
Fig. 3  Transfer characteristics of ISO TFT with channel length nel length, it was observed that the maximum mobility of
increased from 5 µm to 100 µm for a fixed channel width of 250 µm. 13.23 ­cm2/V s with an on/off ratio on the order of ­108 was
obtained for the ISO TFT fabricated with channel dimen-
Table II  Electrical parameters of ISO TFT extracted from the transfer sions of 5 µm × 250 µm, and the mobility values obtained
characteristics for the ISO TFT fabricated with various channel dimensions
Channel Channel Ion/Ioff ratio Mobility, Turn-on
were between 8 ­cm2/V s and 10 ­cm2/V s for most of the
width (W) length (L), ­cm2/V s voltage, V channel dimensions. The electrical parameters extracted
(µm) µm from the transfer characteristics of the ISO TFT are shown
in Table II. It was observed that the conduction through the
250 5 8.24 × ­108 13.23 ± 0.27 −22.0
channel accumulation region resulted in increased off-state
250 10 2.88 × ­107 11.19 ± 0.31 −15.0
current for short-channel devices, which resulted in a reduc-
250 20 1.39 × ­107 10.43 ± 0.28 −6.0
tion in the on/off ratio for short-channel devices compared
250 30 9.66 × ­108 8.81 ± 0.24 −6.0
to other devices even when the on-state current of short-
250 40 8.17 × ­108 9.02 ± 0.26 −6.0
channel devices was higher than that of the other devices.
250 50 3.55 × ­108 8.86 ± 0.23 −6.0
These results are higher than those previously reported for
250 75 2.55 × ­108 8.34 ± 0.25 −5.5
a photolithography-patterned ISO TFT (5 ­cm2/V s) as seen
250 100 1.93 × ­108 8.52 ± 0.24 −5.5
in Table III.16

Table III  Comparison of obtained results with previous reports

Material Mobility, Dielectric layer Patterning method Processing tem- Source
­cm2/V s perature

ISO (1 wt.% doping) 13.2 100 nm ­SiO2 Maskless writer (5 µm × 250 µm) 150°C This work
ISO (10%) 5 120 nm ­AlOx Photolithography (20 µm × 100 µm) 150°C 16
ISO (3%) – 5 nm + ISO 19.6 250 nm ­SiO2 Metal stencil mask (350 µm × 1000 µm) 250°C 17
(20%) – 5 nm
ISO (1 wt.% doping) 31.7 100 nm ­SiO2 Metal stencil mask (60 µm × 500 µm) 100°C 20

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7538 S. Arulkumar et al.

The output characteristics of the ISO TFT with a chan-

nel length of 5 µm and channel width of 250 µm are shown
in Fig. 4. The absence of current crowding phenomenon at
low drain voltage indicates the formation of ohmic contact
between the ISO thin film and the Mo metal contact and a
clear saturation of drain current with higher drain voltage
is observed.
The electrical stability of the ISO TFT fabricated with
channel dimensions of 50 µm × 50 µm was studied under
positive bias stress (VGS = +30 V) and negative bias stress
(VGS = −30 V) conditions. It was observed that there was
a continuous shift in the turn-on voltage with application
of positive bias stress in the positive direction, whereas a
shift in the negative direction was observed for negative bias
stress as shown in Fig. 5. Under positive bias stress, diffu-
Fig. 4  Output characteristics of ISO TFT with channel length of 5 µm sion of oxygen from the atmosphere into the semiconductor
and channel width of 250 µm. layer leads to the formation of weakly bonded oxygen states,

Fig. 5  Bias stress analysis measurement of ISO TFT for a duration of 60 min, (a) positive bias stress transfer characteristics (VGS = +30 V), (b)
negative bias stress transfer characteristics (VGS = −30 V), (c) change in threshold voltage with bias stress and (d) bias stress instability model.

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Maskless Direct‑Write Lithography‑Patterned Molybdenum Metal‑Contacted Indium Silicon… 7539

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Acknowledgments Dr. S. Parthiban thanks DST SERB (Grant No. Indium silicon oxide TFT fully photolithographically processed
CRG/2019/002107) for the financial support. for circuit integration. IEEE J. Electron Devices Soc. 8, 1162
(2020).
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