S32K148 IO_Signal_Description_Input

exing
S32K148_100 LQFP S32K148_144 LQFP S32K148_176 LQFP S32K148_BGA Pin Name
1 PTA18
2 PTA19
3 PTA20
1 1 4 A2 PTE16
2 2 5 B2 PTE15
6 PTA21
3 3 7 B1 PTD1
4 4 8 C2 PTD0
9 PTA22
5 5 10 A1 PTE11
6 6 11 C1 PTE10
7 7 12 D3 PTE13
13 PTA23
8 8 14 D2 PTE5
9 9 15 D1 PTE4
16 PTA24
10 17 PTA25
32 18 VDD
66 19 VSS
11 13 20 E4 VDDA
12 14 21 E3 VREFH
13 15 22 E2 VREFL
31 23 VSS
15 17 24 E1 PTB7
16 18 25 F1 PTB6
19 26 PTA26
17 20 27 F3 PTE14
18 21 28 F2 PTE3
22 29 PTA27
19 23 30 F4 PTE12
24 31 PTA28
20 25 32 G1 PTD17
26 33 PTA29
27 34 PTA30
21 28 35 G2 PTD16
22 29 36 G3 PTD15
23 30 37 H1 PTE9
14 16 38 D4 VSS
10 11 39 E5 VDD
33 40 PTA31
24 34 41 H2 PTD14
25 35 42 J1 PTD13
36 43 PTB18
44 PTB19
37 45 PTB20
38 46 PTB21
26 39 47 H3 PTE8
27 40 48 K1 PTB5
28 41 49 K2 PTB4
29 42 50 J2 PTC3
30 43 51 J3 PTC2
31 44 52 K3 PTD7
32 45 53 J4 PTD6
33 46 54 K4 PTD5
34 47 55 H4 PTD12
35 48 56 G5 PTD11
36 49 57 K5 PTD10
12 58 VSS
67 59 VDD
39 52 60 H5 PTC1
40 53 61 J5 PTC0
41 54 62 K6 PTD9
42 55 63 J6 PTD8
43 56 64 K7 PTC17
44 57 65 J7 PTC16
58 66 PTB22
45 59 67 H6 PTC15
60 68 PTB23
69 PTB24
46 61 70 G6 PTC14
62 71 PTB25
72 PTB26
47 63 73 H7 PTB3
64 74 PTB27
65 75 PTB28
37 50 76 G4 VSS
38 51 77 F5 VDD
48 68 78 K8 PTB2
69 79 PTB29
80 PTB30
49 70 81 J8 PTC13
82 PTB31
83 PTC18
50 71 84 K9 PTC12
72 85 PTC19
86 PTC20
87 PTC21
88 PTC22
73 89 PTC23
90 PTC24
91 PTC25
51 74 92 H8 PTC11
93 PTC26
52 75 94 K10 PTC10
76 95 PTC27
53 77 96 J9 PTB1
54 78 97 J10 PTB0
79 98 PTC28
55 80 99 H9 PTC9
56 81 100 G8 PTC8
82 101 PTC29
57 83 102 H10 PTA7
84 103 PTC30
58 85 104 G9 PTA6
86 105 PTC31
59 87 106 G10 PTE7
88 107 PTD18
89 108 PTD19
109 VSS
110 VDD
62 92 111 F7 PTA17
63 93 112 E7 PTB17
113 PTD20
64 94 114 F8 PTB16
65 95 115 F9 PTB15
66 96 116 F10 PTB14
117 PTD21
67 97 118 E8 PTB13
68 98 119 E9 PTB12
99 120 PTD22
69 100 121 E10 PTD4
70 101 122 D10 PTD3
71 102 123 D9 PTD2
103 124 PTD23
72 104 125 D8 PTA3
73 105 126 C10 PTA2
106 127 PTD24
74 107 128 C9 PTB11
61 91 129 F6 VDD
60 90 130 G7 VSS
75 108 131 B10 PTB10
132 PTD25
76 109 133 C8 PTB9
134 PTD26
110 135 PTD27
77 111 136 A10 PTB8
112 137 PTD28
78 113 138 B9 PTA1
114 139 PTD29
79 115 140 A9 PTA0
116 141 PTD30
142 PTD31
80 117 143 B8 PTC7
81 118 144 C7 PTC6
145 PTE17
82 119 146 A8 PTA16
147 PTE18
83 120 148 B7 PTA15
84 121 149 A7 PTE6
85 122 150 B6 PTE2
86 123 151 D7 VSS
87 124 152 E6 VDD
 125 153 PTE19
126 154 PTE20
88 127 155 C6 PTA14
128 156 PTE21
129 157 PTE22
89 130 158 A6 PTA13
131 159 PTE23
132 160 PTE24
133 161 PTE25
90 134 162 A5 PTA12
91 135 163 B5 PTA11
92 136 164 C5 PTA10
93 137 165 A4 PTE1
94 138 166 B4 PTE0
167 PTE26
95 139 168 D6 PTC5
96 140 169 D5 PTC4
97 141 170 C4 PTA5
171 VSS
172 VDD
98 142 173 C3 PTA4
174 PTE27
99 143 175 A3 PTA9
100 144 176 B3 PTA8
100 144 176 100
* NOTE: QSPI NOT AVAILABLE IN 100 LQFP PACKAGE
 DEFAULT ALT0 ALT1 ALT2 ALT3
DISABLED PTA18 FTM4_CH0 LPUART1_TX
DISABLED PTA19 FTM4_CH1 LPUART1_RX
DISABLED PTA20 FTM4_CH2
DISABLED PTE16 LPUART1_RTS LPSPI2_SIN
DISABLED PTE15 LPUART1_CTS LPSPI2_SCK
DISABLED PTA21 FTM4_CH3 FXIO_D0
DISABLED PTD1 FTM0_CH3 LPSPI1_SIN
DISABLED PTD0 FTM0_CH2 LPSPI1_SCK
DISABLED PTA22 FTM4_CH4 FXIO_D1
DISABLED PTE11 LPSPI2_PCS0 LPTMR0_ALT1
DISABLED PTE10 CLKOUT LPSPI2_PCS1
DISABLED PTE13 FTM4_CH5 LPSPI2_PCS2
DISABLED PTA23 FTM4_CH6 FXIO_D2
DISABLED PTE5 TCLK2 FTM2_QD_PHA
DISABLED PTE4 ETM_TRACE_D1 FTM2_QD_PHB
DISABLED PTA24 FTM4_CH7 FXIO_D3
DISABLED PTA25 FTM5_CH0
VDD VDD
VSS VSS
VDDA VDDA
VREFH VREFH
VREFL VREFL
VSS VSS
EXTAL EXTAL PTB7 LPI2C0_SCL
XTAL XTAL PTB6 LPI2C0_SDA
DISABLED PTA26 FTM5_CH1 LPSPI1_PCS0
DISABLED PTE14 FTM0_FLT1
DISABLED PTE3 FTM0_FLT0 LPUART2_RTS
DISABLED PTA27 FTM5_CH2 LPSPI1_SOUT
DISABLED PTE12 FTM0_FLT3 LPUART2_TX
DISABLED PTA28 FTM5_CH3 LPSPI1_SCK
DISABLED PTD17 FTM0_FLT2 LPUART2_RX
DISABLED PTA29 FTM5_CH4
DISABLED PTA30 FTM5_CH5 LPUART2_RX
DISABLED PTD16 FTM0_CH1 ETM_TRACE_D2
DISABLED PTD15 FTM0_CH0 ETM_TRACE_D3
DISABLED PTE9 FTM0_CH7 LPUART2_CTS
VSS VSS
VDD VDD
DISABLED PTA31 FTM5_CH6
DISABLED PTD14 FTM2_CH5 LPUART1_TX
DISABLED PTD13 FTM2_CH4 LPUART1_RX
ADC0_SE16 ADC0_SE16 PTB18 FTM5_CH7
DISABLED PTB19 FTM5_CH7
ADC0_SE17 ADC0_SE17 PTB20 FTM6_CH0
ADC0_SE18 ADC0_SE18 PTB21 FTM6_CH1
CMP0_IN3 CMP0_IN3 PTE8 FTM0_CH6
DISABLED PTB5 FTM0_CH5 LPSPI0_PCS1
DISABLED PTB4 FTM0_CH4 LPSPI0_SOUT
ADC0_SE11/CMP0_IN4 ADC0_SE11/CMP0_IN4 PTC3 FTM0_CH3 CAN0_TX
ADC0_SE10/CMP0_IN5 ADC0_SE10/CMP0_IN5 PTC2 FTM0_CH2 CAN0_RX
CMP0_IN6 CMP0_IN6 PTD7 LPUART2_TX
CMP0_IN7 CMP0_IN7 PTD6 LPUART2_RX
DISABLED PTD5 FTM2_CH3 LPTMR0_ALT2
DISABLED PTD12 FTM2_CH2 LPI2C1_HREQ
DISABLED PTD11 FTM2_CH1 FTM2_QD_PHA
DISABLED PTD10 FTM2_CH0 FTM2_QD_PHB
VSS VSS
VDD VDD
ADC0_SE9 ADC0_SE9 PTC1 FTM0_CH1 LPSPI2_SOUT
ADC0_SE8 ADC0_SE8 PTC0 FTM0_CH0 LPSPI2_SIN
DISABLED PTD9 LPI2C1_SCL FXIO_D0
DISABLED PTD8 LPI2C1_SDA MII_RXD3
ADC0_SE15 ADC0_SE15 PTC17 FTM1_FLT3 CAN2_TX
ADC0_SE14 ADC0_SE14 PTC16 FTM1_FLT2 CAN2_RX
ADC0_SE19 ADC0_SE19 PTB22 FTM6_CH2 MII_CRS
ADC0_SE13 ADC0_SE13 PTC15 FTM1_CH3 LPSPI2_SCK
ADC0_SE20 ADC0_SE20 PTB23 FTM6_CH3 LPUART1_RX
DISABLED PTB24 FTM6_CH4
ADC0_SE12 ADC0_SE12 PTC14 FTM1_CH2 LPSPI2_PCS0
ADC0_SE21 ADC0_SE21 PTB25 FTM6_CH5
DISABLED PTB26 FTM6_CH6
ADC0_SE7 ADC0_SE7 PTB3 FTM1_CH1 LPSPI0_SIN
ADC0_SE22 ADC0_SE22 PTB27 FTM6_CH7
ADC0_SE23 ADC0_SE23 PTB28 FTM7_CH0
VSS VSS
VDD VDD
ADC0_SE6 ADC0_SE6 PTB2 FTM1_CH0 LPSPI0_SCK
ADC0_SE24 ADC0_SE24 PTB29 FTM7_CH1
DISABLED PTB30 FTM7_CH2
DISABLED PTC13 FTM3_CH7 FTM2_CH7
DISABLED PTB31 FTM7_CH3
DISABLED PTC18 FTM7_CH4
DISABLED PTC12 FTM3_CH6 FTM2_CH6
ADC0_SE25 ADC0_SE25 PTC19 FTM7_CH5
DISABLED PTC20 FTM7_CH6
DISABLED PTC21 FTM7_CH7
DISABLED PTC22 FTM7_FLT1
ADC0_SE26 ADC0_SE26 PTC23 LPSPI0_SCK
DISABLED PTC24 FTM4_CH0
DISABLED PTC25 FTM4_CH1
DISABLED PTC11 FTM3_CH5 FTM4_CH2
DISABLED PTC26 FTM4_CH3
DISABLED PTC10 FTM3_CH4
ADC0_SE27 ADC0_SE27 PTC27 FTM4_CH4
ADC0_SE5/ADC1_SE15 ADC0_SE5/ADC1_SE15 PTB1 LPUART0_TX LPSPI0_SOUT
ADC0_SE4/ADC1_SE14 ADC0_SE4/ADC1_SE14 PTB0 LPUART0_RX LPSPI0_PCS0
ADC0_SE28 ADC0_SE28 PTC28 FTM4_CH7
DISABLED PTC9 LPUART1_TX FTM1_FLT1
DISABLED PTC8 LPUART1_RX FTM1_FLT0
ADC0_SE29 ADC0_SE29 PTC29 FTM5_CH2
 ADC0_SE3 ADC0_SE3 PTA7 FTM0_FLT2 FTM5_CH3
ADC0_SE30 ADC0_SE30 PTC30 FTM5_CH4 FXIO_D0
ADC0_SE2 ADC0_SE2 PTA6 FTM0_FLT1 LPSPI1_PCS1
ADC0_SE31 ADC0_SE31 PTC31 FTM5_CH6 FXIO_D1
DISABLED PTE7 FTM0_CH7 FTM3_FLT0
ADC1_SE16 ADC1_SE16 PTD18 FTM5_CH7 FXIO_D2
ADC1_SE17 ADC1_SE17 PTD19 FTM6_CH0 FXIO_D3
VSS VSS
VDD VDD
DISABLED PTA17 FTM0_CH6 FTM3_FLT0
DISABLED PTB17 FTM0_CH5 LPSPI1_PCS3
DISABLED PTD20 FTM6_CH1
ADC1_SE15 ADC1_SE15 PTB16 FTM0_CH4 LPSPI1_SOUT
ADC1_SE14 ADC1_SE14 PTB15 FTM0_CH3 LPSPI1_SIN
ADC1_SE9/ADC0_SE9 ADC1_SE9/ADC0_SE9 PTB14 FTM0_CH2 LPSPI1_SCK
DISABLED PTD21 FTM6_CH2
ADC1_SE8/ADC0_SE8 ADC1_SE8/ADC0_SE8 PTB13 FTM0_CH1 FTM3_FLT1
ADC1_SE7 ADC1_SE7 PTB12 FTM0_CH0 FTM3_FLT2
ADC1_SE18 ADC1_SE18 PTD22 FTM6_CH3
ADC1_SE6 ADC1_SE6 PTD4 FTM0_FLT3 FTM3_FLT3
ADC1_SE3 ADC1_SE3 PTD3 FTM3_CH5 LPSPI1_PCS0
ADC1_SE2 ADC1_SE2 PTD2 FTM3_CH4 LPSPI1_SOUT
ADC1_SE19 ADC1_SE19 PTD23 FTM6_CH4
ADC1_SE1 ADC1_SE1 PTA3 FTM3_CH1 LPI2C0_SCL
ADC1_SE0 ADC1_SE0 PTA2 FTM3_CH0 LPI2C0_SDA
ADC1_SE20 ADC1_SE20 PTD24 FTM6_CH5
DISABLED PTB11 FTM3_CH3 LPI2C0_HREQ
VDD VDD
VSS VSS
DISABLED PTB10 FTM3_CH2 LPI2C0_SDAS
DISABLED PTD25 FTM6_CH6
DISABLED PTB9 FTM3_CH1 LPI2C0_SCLS
DISABLED PTD26 FTM6_CH7 FXIO_D7
ADC1_SE21 ADC1_SE21 PTD27 FTM7_CH0
DISABLED PTB8 FTM3_CH0
ADC1_SE22 ADC1_SE22 PTD28 FTM7_CH1
ADC0_SE1/CMP0_IN1 ADC0_SE1/CMP0_IN1 PTA1 FTM1_CH1 LPI2C0_SDAS
ADC1_SE23 ADC1_SE23 PTD29 FTM7_CH2
ADC0_SE0/CMP0_IN0 ADC0_SE0/CMP0_IN0 PTA0 FTM2_CH1 LPI2C0_SCLS
ADC1_SE24 ADC1_SE24 PTD30 FTM7_CH3 FTM6_FLT1
DISABLED PTD31 FTM7_CH4 FXIO_D6
ADC1_SE5 ADC1_SE5 PTC7 LPUART1_TX CAN1_TX
ADC1_SE4 ADC1_SE4 PTC6 LPUART1_RX CAN1_RX
DISABLED PTE17 FTM7_CH5 FXIO_D5
ADC1_SE13 ADC1_SE13 PTA16 FTM1_CH3 LPSPI1_PCS2
DISABLED PTE18 FTM7_CH6 FXIO_D4
ADC1_SE12 ADC1_SE12 PTA15 FTM1_CH2 LPSPI0_PCS3
ADC1_SE11 ADC1_SE11 PTE6 LPSPI0_PCS2 FTM7_FLT1
ADC1_SE10 ADC1_SE10 PTE2 LPSPI0_SOUT LPTMR0_ALT3
VSS VSS
VDD VDD
 ADC1_SE25 ADC1_SE25 PTE19 FTM7_CH7
ADC1_SE26 ADC1_SE26 PTE20 FTM4_CH0
DISABLED PTA14 FTM0_FLT0 FTM3_FLT1
ADC1_SE27 ADC1_SE27 PTE21 FTM4_CH1
ADC1_SE28 ADC1_SE28 PTE22 FTM4_CH2
DISABLED PTA13 FTM1_CH7 CAN1_TX
ADC1_SE29 ADC1_SE29 PTE23 FTM4_CH3
ADC1_SE30 ADC1_SE30 PTE24 FTM4_CH4 CAN2_TX
ADC1_SE31 ADC1_SE31 PTE25 FTM4_CH5 CAN2_RX
DISABLED PTA12 FTM1_CH6 CAN1_RX
DISABLED PTA11 FTM1_CH5
JTAG_TDO/noetm_TRACE_SWO PTA10 FTM1_CH4
DISABLED PTE1 LPSPI0_SIN LPI2C0_HREQ
DISABLED PTE0 LPSPI0_SCK TCLK1
DISABLED PTE26 FTM4_CH6
JTAG_TDI PTC5 FTM2_CH0 RTC_CLKOUT
JTAG_TCLK/SWD_CLK CMP0_IN2 PTC4 FTM1_CH0 RTC_CLKOUT
RESET_b PTA5 TCLK1
VSS VSS
VDD VDD
JTAG_TMS/SWD_DIO PTA4
DISABLED PTE27 FTM4_CH7
DISABLED PTA9 LPUART2_TX LPSPI2_PCS0
DISABLED PTA8 LPUART2_RX LPSPI2_SOUT
 ALT4 ALT5 ALT6 ALT7
LPSPI1_SOUT FTM6_CH0
LPSPI1_SCK
LPSPI1_SIN
FTM2_CH7 FTM4_FLT0 FXIO_D3 TRGMUX_OUT7
FTM2_CH6 FTM4_FLT1 FXIO_D2 TRGMUX_OUT6
LPSPI1_PCS0
FTM2_CH1 SAI0_MCLK FXIO_D1 TRGMUX_OUT2
FTM2_CH0 ETM_TRACE_D0 FXIO_D0 TRGMUX_OUT1
LPSPI1_PCS1
FTM2_CH5 FXIO_D5 TRGMUX_OUT5
FTM2_CH4 FXIO_D4 TRGMUX_OUT4
FTM2_FLT0

FTM2_CH3 CAN0_TX FXIO_D7 EWM_IN

FTM2_CH2 CAN0_RX FXIO_D6 EWM_OUT_b

LPSPI0_PCS0
FTM2_FLT1
FTM2_FLT0 TRGMUX_IN6 CMP0_OUT
LPUART0_TX CAN0_TX
FTM5_FLT0
LPUART0_RX CAN0_RX
FTM5_FLT1
LPUART2_TX LPSPI1_SIN
LPSPI0_SOUT
LPSPI0_SIN CMP0_RRT ETM_TRACE_CLKOUT
LPSPI0_SCK ENET_TMR2
ENET_TMR3

LPSPI0_PCS1
ENET_TMR0 CLKOUT
ENET_TMR1 RTC_CLKOUT
LPSPI1_PCS1

MII_RMII_MDC
LPSPI0_PCS0 CLKOUT TRGMUX_IN0 MII_RMII_MDC
MII_RMII_MDIO TRGMUX_IN1 QSPI_B_IO0 *
LPUART0_TX MII_TX_ER QSPI_A_CS * QSPI_B_IO3 *
 LPUART0_RX MII_RMII_TXD[0] ETM_TRACE_CLKOUT QSPI_A_IO3 *
FTM2_FLT3 MII_RMII_TXD[1] ETM_TRACE_D0 QSPI_A_IO1 *
FTM2_FLT2 MII_TXD2 QSPI_B_IO1 *
FTM2_FLT1 MII_TXD3 TRGMUX_IN7 QSPI_B_IO2 *
ETM_TRACE_D1 MII_RMII_TX_EN LPUART2_RTS QSPI_A_IO2 *
ETM_TRACE_D2 MII_RMII_TX_CLK LPUART2_CTS QSPI_A_IO0 *
ETM_TRACE_D3 MII_RX_CLK CLKOUT QSPI_A_SCK *

MII_RMII_RXD[1] MII_RMII_RXD[0] FTM1_CH7 QSPI_B_SCK *

MII_RMII_RXD[1] MII_RMII_RXD[0] FTM1_CH6 QSPI_B_RWDS *
FTM2_FLT3 MII_RXD2 FTM1_CH5 QSPI_B_IO4 *
FTM2_FLT2 FXIO_D1 FTM1_CH4 QSPI_B_IO5 *
LPI2C1_SCLS MII_RMII_RX_DV QSPI_B_IO6 *
LPI2C1_SDAS MII_RMII_RX_ER QSPI_B_IO7 *
LPUART1_TX
MII_CRS TRGMUX_IN8 QSPI_B_CS *
MII_COL

MII_COL TRGMUX_IN9
LPSPI2_PCS0

FTM1_QD_PHA TRGMUX_IN2
LPSPI2_SOUT
LPSPI2_SIN

FTM1_QD_PHB TRGMUX_IN3
LPSPI2_SCK

LPUART2_RTS

LPUART2_CTS
LPSPI2_PCS1

FTM7_FLT0

TRGMUX_IN10

TRGMUX_IN11

TCLK0 CAN0_TX FTM4_CH5

LPTMR0_ALT3 CAN0_RX FTM4_CH6

FTM5_CH0 LPUART0_RTS
FTM5_CH1 LPUART0_CTS
 RTC_CLKIN LPUART1_RTS
LPI2C1_SDAS
FTM5_CH5 LPUART1_CTS
LPI2C1_SDA

LPI2C1_SCLS
LPI2C1_SCL

EWM_OUT_b FTM5_FLT0
FTM5_FLT1

CAN2_TX FTM6_FLT0
CAN2_RX FTM6_FLT1

FXIO_D5 FXIO_D7 TRGMUX_IN4 NMI_b

FXIO_D4 FXIO_D6 TRGMUX_IN5

EWM_IN FXIO_D5 LPUART0_TX

EWM_OUT_b FXIO_D4 LPUART0_RX

SAI1_MCLK

SAI1_D0

SAI1_BCLK

FXIO_D3 FTM1_QD_PHA LPUART0_RTS TRGMUX_OUT0

FXIO_D2 FTM2_QD_PHA LPUART0_CTS TRGMUX_OUT3

FTM6_FLT0
FTM3_CH3 FTM1_QD_PHA
FTM3_CH2 FTM1_QD_PHB

LPSPI2_PCS3 FTM7_FLT0
FTM3_CH7 LPUART1_RTS
FTM3_CH6 LPUART1_CTS SAI1_SYNC
 EWM_IN FTM1_FLT0 SAI0_D3

LPI2C1_SCLS FTM2_QD_PHA SAI0_D0

LPI2C1_SDAS FTM2_QD_PHB SAI0_BCLK

FXIO_D1 CMP0_RRT SAI0_SYNC
FXIO_D0 JTAG_TDO/noetm_TRACE_SWO
LPI2C1_SCL LPSPI1_PCS0 FTM1_FLT1 SAI0_D1
LPI2C1_SDA LPSPI1_SOUT FTM1_FLT2 SAI0_D2

LPI2C1_HREQ FTM2_QD_PHB JTAG_TDI

EWM_IN FTM1_QD_PHB JTAG_TCLK/SWD_CLK
RESET_b

CMP0_OUT EWM_OUT_b JTAG_TMS/SWD_DIO

FXIO_D7 FTM3_FLT2 FTM1_FLT3 FTM4_FLT0

FXIO_D6 FTM3_FLT3 FTM4_FLT1
 Composite Pin Name
PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0
PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK
PTA20/FTM4_CH2/LPSPI1_SIN
PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7
PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6
PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0
PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2
PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/ETM_TRACE_D0/FXIO_D0/TRGMUX_OUT1
PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1
PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5
PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4
PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0
PTA23/FTM4_CH6/FXIO_D2
PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN
PTE4/ETM_TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT_b
PTA24/FTM4_CH7/FXIO_D3
PTA25/FTM5_CH0
VDD
VSS
VDDA
VREFH
VREFL
VSS
PTB7/LPI2C0_SCL/EXTAL
PTB6/LPI2C0_SDA/XTAL
PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0
PTE14/FTM0_FLT1/FTM2_FLT1
PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT
PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX
PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0
PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX
PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1
PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN
PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT
PTD16/FTM0_CH1/ETM_TRACE_D2/LPSPI0_SIN/CMP0_RRT/ETM_TRACE_CLKOUT
PTD15/FTM0_CH0/ETM_TRACE_D3/LPSPI0_SCK/ENET_TMR2
PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3
VSS
VDD
PTA31/FTM5_CH6/LPSPI0_PCS1
PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT
PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT
PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16
PTB19/FTM5_CH7
PTB20/FTM6_CH0/ADC0_SE17
PTB21/FTM6_CH1/ADC0_SE18
PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3
PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC
PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0
PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4
PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD[0]/ETM_TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CM
PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD[1]/ETM_TRACE_D0/QSPI_A_IO1/CMP0_IN6
PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7
PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2
PTD12/FTM2_CH2/LPI2C1_HREQ/ETM_TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2
PTD11/FTM2_CH1/FTM2_QD_PHA/ETM_TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0
PTD10/FTM2_CH0/FTM2_QD_PHB/ETM_TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK
VSS
VDD
PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH7/QSPI_B_SCK/ADC0_SE9
PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8
PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4
PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5
PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15
PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14
PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19
PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13
PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20
PTB24/FTM6_CH4
PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12
PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21
PTB26/FTM6_CH6
PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7
PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22
PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23
VSS
VDD
PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6
PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24
PTB30/FTM7_CH2
PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS
PTB31/FTM7_CH3
PTC18/FTM7_CH4
PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS
PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25
PTC20/FTM7_CH6
PTC21/FTM7_CH7/FTM7_FLT0
PTC22/FTM7_FLT1
PTC23/LPSPI0_SCK/ADC0_SE26
PTC24/FTM4_CH0
PTC25/FTM4_CH1
PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10
PTC26/FTM4_CH3
PTC10/FTM3_CH4/TRGMUX_IN11
PTC27/FTM4_CH4/ADC0_SE27
PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15
PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14
PTC28/FTM4_CH7/ADC0_SE28
PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS
PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS
PTC29/FTM5_CH2/ADC0_SE29
 PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3
PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30
PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2
PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31
PTE7/FTM0_CH7/FTM3_FLT0
PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16
PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17
VSS
VDD
PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT_b/FTM5_FLT0
PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1
PTD20/FTM6_CH1
PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15
PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14
PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9
PTD21/FTM6_CH2
PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8
PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7
PTD22/FTM6_CH3/ADC1_SE18
PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6
PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI_b/ADC1_SE3
PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2
PTD23/FTM6_CH4/ADC1_SE19
PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT_b/FXIO_D4/LPUART0_RX/ADC1_SE0
PTD24/FTM6_CH5/ADC1_SE20
PTB11/FTM3_CH3/LPI2C0_HREQ
VDD
VSS
PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK
PTD25/FTM6_CH6
PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0
PTD26/FTM6_CH7/FXIO_D7
PTD27/FTM7_CH0/ADC1_SE21
PTB8/FTM3_CH0/SAI1_BCLK
PTD28/FTM7_CH1/ADC1_SE22
PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_
PTD29/FTM7_CH2/ADC1_SE23
PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_
PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24
PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0
PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5
PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4
PTE17/FTM7_CH5/FXIO_D5
PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13
PTE18/FTM7_CH6/FXIO_D4
PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12
PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11
PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10
VSS
VDD
 PTE19/FTM7_CH7/ADC1_SE25
PTE20/FTM4_CH0/ADC1_SE26
PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3
PTE21/FTM4_CH1/ADC1_SE27
PTE22/FTM4_CH2/ADC1_SE28
PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0
PTE23/FTM4_CH3/ADC1_SE29
PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30
PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31
PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK
PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC
PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO/noetm_TRACE_SWO
PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1
PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2
PTE26/FTM4_CH6
PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI
PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2
PTA5/TCLK1/RESET_b
VSS
VDD
PTA4/CMP0_OUT/EWM_OUT_b/JTAG_TMS/SWD_DIO
PTE27/FTM4_CH7
PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0
PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1
 PAD NAME
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_pwr_mv
p_gnd_mv
p_vdda_mv
p_vdda_mv
p_io_ae_mv
p_gnd_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_gnd_mv
p_pwr_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_quadspi_mv
p_io_quadspi_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_quadspi_mv
p_io_quadspi_mv
p_io_quadspi_mv
p_gnd_mv
p_pwr_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_gnd_mv
p_pwr_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_gnd_mv
p_pwr_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_rst_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_pwr_mv
p_gnd_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_gnd_mv
p_pwr_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_20ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_rst_mv
p_gnd_mv
p_pwr_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
p_io_5ma_mv
 PTD13
PTD14
PTE14
PTB6
PTB7
VREFL
PTE13
PTE10
PTE11
PTD0
PTD1
PTE15
PTE16

PTE9
PTD15
PTD16
PTD17
PTE12
PTE3
PTE4
PTE5

VSS
VREFH
VDDA
VDD
9
8
7
6
5
4
3
2
1

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
PTE8 26 100 PTA8
PTB5 27 99 PTA9
PTB4 28 98 PTA4
PTC3 29 97 PTA5
PTC2 30 96 PTC4
PTD7 31 95 PTC5
PTD6 32 94 PTE0
PTD5 33 93 PTE1
PTD12 34 92 PTA10
PTD11 35 91 PTA11
PTD10 36 90 PTA12
VSS 37 89 PTA13
VDD 38 88 PTA14
PTC1 39 87 VDD
PTC0 40 86 VSS
PTD9 41 85 PTE2
PTD8 42 84 PTE6
PTC17 43 83 PTA15
PTC16 44 82 PTA16
PTC15 45 81 PTC6
NOTE: QSPI NOT AVAILABLE IN 100 LQFP PACKAGE

PTC14 46 80 PTC7
PTB3 47 79 PTA0
PTB2 48 78 PTA1
PTC13 49 77 PTB8
PTC12 50 76 PTB9

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Alpha 8 - Full Signal Model pinout S32K148_100lqfp (pack
48_100lqfp (package 100lqfp)

PTB10
PTB11
PTA2
PTA3
PTD2
PTD3
PTD4
PTB12
PTB13
PTB14
PTB15
PTB16
PTB17
PTA17
VDD
VSS
PTE7
PTA6
PTA7
PTC8
PTC9
PTB0
PTB1
PTC10
PTC11
 Alpha 8 - Full Signal Model pinout S32K

1 2 3 4 5 6 7 8 9
A PTE11 PTE16 PTA9 PTE1 PTA12 PTA13 PTE6 PTA16 PTA0

B PTD1 PTE15 PTA8 PTE0 PTA11 PTE2 PTA15 PTC7 PTA1

C PTE10 PTD0 PTA4 PTA5 PTA10 PTA14 PTC6 PTB9 PTB11

D PTE4 PTE5 PTE13 VSS PTC4 PTC5 VSS PTA3 PTD2

E PTB7 VREFL VREFH VDDA VDD VDD PTB17 PTB13 PTB12

F PTB6 PTE3 PTE14 PTE12 VDD VDD PTA17 PTB16 PTB15

G PTD17 PTD16 PTD15 VSS PTD11 PTC14 VSS PTC8 PTA6

H PTE9 PTD14 PTE8 PTD12 PTC1 PTC15 PTB3 PTC11 PTC9

J PTD13 PTC3 PTC2 PTD6 PTC0 PTD8 PTC16 PTC13 PTB1

K PTB5 PTB4 PTD7 PTD5 PTD10 PTD9 PTC17 PTB2 PTC12

1 2 3 4 5 6 7 8 9
l Model pinout S32K148_BGA (package 100 BGA)

10
PTB8 A

PTB10 B

PTA2 C

PTD3 D

PTD4 E

PTB14 F

PTE7 G

PTA7 H

PTB0 J

PTC10 K
10
 Alpha 8 - Full Signal Model pinout S32K148_144lqfp (pack

136 PTA10
135 PTA11
134 PTA12

130 PTA13

127 PTA14

120 PTA15
119 PTA16
133 PTE25
132 PTE24
131 PTE23

129 PTE22
128 PTE21

126 PTE20
125 PTE19
144 PTA8
143 PTA9
142 PTA4
141 PTA5
140 PTC4
139 PTC5
138 PTE0
137 PTE1

122 PTE2
121 PTE6
124 VDD
123 VSS
PTE16 1
PTE15 2
PTD1 3
PTD0 4
PTE11 5
PTE10 6
PTE13 7
PTE5 8
PTE4 9
PTA25 10
VDD 11
VSS 12
VDDA 13
VREFH 14
VREFL 15
VSS 16
PTB7 17
PTB6 18
PTA26 19
PTE14 20
PTE3 21
PTA27 22
PTE12 23
PTA28 24
PTD17 25
PTA29 26
PTA30 27
PTD16 28
PTD15 29
PTE9 30
VSS 31
VDD 32
PTA31 33
PTD14 34
PTD13 35
PTB18 36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PTB20
PTB21
PTE8
PTB5
PTB4
PTC3
PTC2
PTD7
PTD6
PTD5
PTD12
PTD11
PTD10
VSS
VDD
PTC1
PTC0
PTD9
PTD8
PTC17
PTC16
PTB22
PTC15
PTB23
PTC14
PTB25
148_144lqfp (package 144lqfp)
116 PTD30

114 PTD29

112 PTD28

110 PTD27
115 PTA0

113 PTA1

111 PTB8

109 PTB9
118 PTC6
117 PTC7

108 PTB10
107 PTB11
106 PTD24
105 PTA2
104 PTA3
103 PTD23
102 PTD2
101 PTD3
100 PTD4
99 PTD22
98 PTB12
97 PTB13
96 PTB14
95 PTB15
94 PTB16
93 PTB17
92 PTA17
91 VDD
90 VSS
89 PTD19
88 PTD18
87 PTE7
86 PTC31
85 PTA6
84 PTC30
83 PTA7
82 PTC29
81 PTC8
80 PTC9
79 PTC28
78 PTB0
77 PTB1
76 PTC27
75 PTC10
74 PTC11
73 PTC23
63
64
65
66
67
68
69
70
71
72
 PTB3
PTB27
PTB28
VSS
VDD
PTB2
PTB29
PTC13
PTC12
PTC19
 Alpha 8 - Full Signal Model pinout S32K148_176lqfp (pack

164 PTA10
163 PTA11
162 PTA12

158 PTA13

155 PTA14
174 PTE27

167 PTE26

161 PTE25
160 PTE24
159 PTE23

157 PTE22
156 PTE21

154 PTE20
153 PTE19
176 PTA8
175 PTA9

173 PTA4

170 PTA5
169 PTC4
168 PTC5

166 PTE0
165 PTE1
172 VDD

152 VDD
171 VSS

151 VSS
PTA18 1
PTA19 2
PTA20 3
PTE16 4
PTE15 5
PTA21 6
PTD1 7
PTD0 8
PTA22 9
PTE11 10
PTE10 11
PTE13 12
PTA23 13
PTE5 14
PTE4 15
PTA24 16
PTA25 17
VDD 18
VSS 19
VDDA 20
VREFH 21
VREFL 22
VSS 23
PTB7 24
PTB6 25
PTA26 26
PTE14 27
PTE3 28
PTA27 29
PTE12 30
PTA28 31
PTD17 32
PTA29 33
PTA30 34
PTD16 35
PTD15 36
PTE9 37
 PTB19
PTB18
PTA31

PTD13
PTD14
VSS
VDD

44
43
42
41
40
39
38

PTB20 45
PTB21 46
PTE8 47
PTB5 48
PTB4 49
PTC3 50
PTC2 51
PTD7 52
PTD6 53
PTD5 54
PTD12 55
PTD11 56
PTD10 57
VSS 58
VDD 59
PTC1 60
PTC0 61
PTD9 62
PTD8 63
PTC17 64
PTC16 65
PTB22 66
PTC15 67
PTB23 68
PTB24 69
PTC14 70
148_176lqfp (package 176lqfp)

142 PTD31
141 PTD30

139 PTD29

137 PTD28

135 PTD27
134 PTD26
148 PTA15

146 PTA16
147 PTE18

145 PTE17

140 PTA0

138 PTA1

136 PTB8

133 PTB9
144 PTC6
143 PTC7
150 PTE2
149 PTE6

132 PTD25
131 PTB10
130 VSS
129 VDD
128 PTB11
127 PTD24
126 PTA2
125 PTA3
124 PTD23
123 PTD2
122 PTD3
121 PTD4
120 PTD22
119 PTB12
118 PTB13
117 PTD21
116 PTB14
115 PTB15
114 PTB16
113 PTD20
112 PTB17
111 PTA17
110 VDD
109 VSS
108 PTD19
107 PTD18
106 PTE7
105 PTC31
104 PTA6
103 PTC30
102 PTA7
101 PTC29
100 PTC8
99 PTC9
98 PTC28
97 PTB0
96 PTB1
PTB25 71
PTB26 72
PTB3 73
PTB27 74
PTB28 75
VSS 76
VDD 77
PTB2 78
PTB29 79
PTB30 80
PTC13 81
PTB31 82
PTC18 83
PTC12 84
PTC19 85
PTC20 86
PTC21 87
PTC22 88
89
90
91
92
93
94
95

PTC23
PTC24
PTC25
PTC11
PTC26
PTC10
PTC27
Port CR SSS Function Module
PTA0 PCR_PTA0 0000_0000 DISABLED
0000_0001 PTA0 PTA
0000_0010 FTM2_CH1 FTM2
0000_0011 LPI2C0_SCLS LPI2C0
0000_0100 FXIO_D2 FXIO
0000_0101 FTM2_QD_PHA FTM2
0000_0110 LPUART0_CTS LPUART0
0000_0111 TRGMUX_OUT3 TRGMUX
- - ADC0_SE0 ADC0
- - CMP0_IN0 CMP0
PTA1 PCR_PTA1 0000_0000 DISABLED
0000_0001 PTA1 PTA
0000_0010 FTM1_CH1 FTM1
0000_0011 LPI2C0_SDAS LPI2C0
0000_0100 FXIO_D3 FXIO
0000_0101 FTM1_QD_PHA FTM1
0000_0110 LPUART0_RTS LPUART0
0000_0111 TRGMUX_OUT0 TRGMUX
- - ADC0_SE1 ADC0
- - CMP0_IN1 CMP0
PTA2 PCR_PTA2 0000_0000 DISABLED
0000_0001 PTA2 PTA
0000_0010 FTM3_CH0 FTM3
0000_0011 LPI2C0_SDA LPI2C0
0000_0100 EWM_OUT_b EWM
0000_0101 FXIO_D4 FXIO
0000_0110 LPUART0_RX LPUART0
- - ADC1_SE0 ADC1
PTA3 PCR_PTA3 0000_0000 DISABLED
0000_0001 PTA3 PTA
0000_0010 FTM3_CH1 FTM3
0000_0011 LPI2C0_SCL LPI2C0
0000_0100 EWM_IN EWM
0000_0101 FXIO_D5 FXIO
0000_0110 LPUART0_TX LPUART0
- - ADC1_SE1 ADC1
PTA4 PCR_PTA4 0000_0000 DISABLED
0000_0001 PTA4 PTA
0000_0100 CMP0_OUT CMP0
 0000_0101 EWM_OUT_b EWM
0000_0111 JTAG_TMS/SWD_DIO JTAG/SWD
PTA5 PCR_PTA5 0000_0000 DISABLED
0000_0001 PTA5 PTA
0000_0011 TCLK1 FTM
0000_0111 RESET_b SYSTEM
PTA6 PCR_PTA6 0000_0000 DISABLED
0000_0001 PTA6 PTA
0000_0010 FTM0_FLT1 FTM0
0000_0011 LPSPI1_PCS1 LPSPI1
0000_0100 FTM5_CH5 FTM5
0000_0110 LPUART1_CTS LPUART1
- - ADC0_SE2 ADC0
PTA7 PCR_PTA7 0000_0000 DISABLED
0000_0001 PTA7 PTA
0000_0010 FTM0_FLT2 FTM0
0000_0011 FTM5_CH3 FTM5
0000_0100 RTC_CLKIN RTC
0000_0110 LPUART1_RTS LPUART1
- - ADC0_SE3 ADC0
PTA8 PCR_PTA8 0000_0000 DISABLED
0000_0001 PTA8 PTA
0000_0010 LPUART2_RX LPUART2
0000_0011 LPSPI2_SOUT LPSPI2
0000_0100 FXIO_D6 FXIO
0000_0101 FTM3_FLT3 FTM3
0000_0110 FTM4_FLT1 FTM4
PTA9 PCR_PTA9 0000_0000 DISABLED
0000_0001 PTA9 PTA
0000_0010 LPUART2_TX LPUART2
0000_0011 LPSPI2_PCS0 LPSPI2
0000_0100 FXIO_D7 FXIO
0000_0101 FTM3_FLT2 FTM3
0000_0110 FTM1_FLT3 FTM1
0000_0111 FTM4_FLT0 FTM4
PTA10 PCR_PTA10 0000_0000 DISABLED
0000_0001 PTA10 PTA
0000_0010 FTM1_CH4 FTM1
0000_0100 FXIO_D0 FXIO
0000_0111 JTAG_TDO/noetm_TRACE_SWO JTAG/TRACEnoETM
PTA11 PCR_PTA11 0000_0000 DISABLED
0000_0001 PTA11 PTA
0000_0010 FTM1_CH5 FTM1
0000_0100 FXIO_D1 FXIO
0000_0101 CMP0_RRT CMP0
0000_0110 SAI0_SYNC SAI0
PTA12 PCR_PTA12 0000_0000 DISABLED
0000_0001 PTA12 PTA
 0000_0010 FTM1_CH6 FTM1
0000_0011 CAN1_RX CAN1
0000_0100 LPI2C1_SDAS LPI2C1
0000_0110 FTM2_QD_PHB FTM2
0000_0111 SAI0_BCLK SAI0
PTA13 PCR_PTA13 0000_0000 DISABLED
0000_0001 PTA13 PTA
0000_0010 FTM1_CH7 FTM1
0000_0011 CAN1_TX CAN1
0000_0100 LPI2C1_SCLS LPI2C1
0000_0110 FTM2_QD_PHA FTM2
0000_0111 SAI0_D0 SAI0
PTA14 PCR_PTA14 0000_0000 DISABLED
0000_0001 PTA14 PTA
0000_0010 FTM0_FLT0 FTM0
0000_0011 FTM3_FLT1 FTM3
0000_0100 EWM_IN EWM
0000_0110 FTM1_FLT0 FTM1
0000_0111 SAI0_D3 SAI0
PTA15 PCR_PTA15 0000_0000 DISABLED
0000_0001 PTA15 PTA
0000_0010 FTM1_CH2 FTM1
0000_0011 LPSPI0_PCS3 LPSPI0
0000_0100 LPSPI2_PCS3 LPSPI2
0000_0101 FTM7_FLT0 FTM7
- - ADC1_SE12 ADC1
PTA16 PCR_PTA16 0000_0000 DISABLED
0000_0001 PTA16 PTA
0000_0010 FTM1_CH3 FTM1
0000_0011 LPSPI1_PCS2 LPSPI1
- - ADC1_SE13 ADC1
PTA17 PCR_PTA17 0000_0000 DISABLED
0000_0001 PTA17 PTA
0000_0010 FTM0_CH6 FTM0
0000_0011 FTM3_FLT0 FTM3
0000_0100 EWM_OUT_b EWM
0000_0101 FTM5_FLT0 FTM5
PTA18 PCR_PTA18 0000_0000 DISABLED
0000_0001 PTA18 PTA
0000_0010 FTM4_CH0 FTM4
0000_0011 LPUART1_TX LPUART1
0000_0100 LPSPI1_SOUT LPSPI1
0000_0101 FTM6_CH0 FTM6
PTA19 PCR_PTA19 0000_0000 DISABLED
0000_0001 PTA19 PTA
0000_0010 FTM4_CH1 FTM4
0000_0011 LPUART1_RX LPUART1
0000_0100 LPSPI1_SCK LPSPI1
PTA20 PCR_PTA20 0000_0000 DISABLED
0000_0001 PTA20 PTA
0000_0010 FTM4_CH2 FTM4
0000_0100 LPSPI1_SIN LPSPI1
PTA21 PCR_PTA21 0000_0000 DISABLED
0000_0001 PTA21 PTA
0000_0010 FTM4_CH3 FTM4
0000_0011 FXIO_D0 FXIO
0000_0100 LPSPI1_PCS0 LPSPI1
PTA22 PCR_PTA22 0000_0000 DISABLED
0000_0001 PTA22 PTA
0000_0010 FTM4_CH4 FTM4
0000_0011 FXIO_D1 FXIO
0000_0100 LPSPI1_PCS1 LPSPI1
PTA23 PCR_PTA23 0000_0000 DISABLED
0000_0001 PTA23 PTA
0000_0010 FTM4_CH6 FTM4
0000_0011 FXIO_D2 FXIO
PTA24 PCR_PTA24 0000_0000 DISABLED
0000_0001 PTA24 PTA
0000_0010 FTM4_CH7 FTM4
0000_0011 FXIO_D3 FXIO
PTA25 PCR_PTA25 0000_0000 DISABLED
0000_0001 PTA25 PTA
0000_0010 FTM5_CH0 FTM5
PTA26 PCR_PTA26 0000_0000 DISABLED
0000_0001 PTA26 PTA
0000_0010 FTM5_CH1 FTM5
0000_0011 LPSPI1_PCS0 LPSPI1
0000_0100 LPSPI0_PCS0 LPSPI0
PTA27 PCR_PTA27 0000_0000 DISABLED
0000_0001 PTA27 PTA
0000_0010 FTM5_CH2 FTM5
0000_0011 LPSPI1_SOUT LPSPI1
0000_0100 LPUART0_TX LPUART0
0000_0101 CAN0_TX CAN0
PTA28 PCR_PTA28 0000_0000 DISABLED
0000_0001 PTA28 PTA
0000_0010 FTM5_CH3 FTM5
0000_0011 LPSPI1_SCK LPSPI1
0000_0100 LPUART0_RX LPUART0
0000_0101 CAN0_RX CAN0
PTA29 PCR_PTA29 0000_0000 DISABLED
0000_0001 PTA29 PTA
0000_0010 FTM5_CH4 FTM5
0000_0100 LPUART2_TX LPUART2
0000_0101 LPSPI1_SIN LPSPI1
PTA30 PCR_PTA30 0000_0000 DISABLED
 0000_0001 PTA30 PTA
0000_0010 FTM5_CH5 FTM5
0000_0011 LPUART2_RX LPUART2
0000_0100 LPSPI0_SOUT LPSPI0
PTA31 PCR_PTA31 0000_0000 DISABLED
0000_0001 PTA31 PTA
0000_0010 FTM5_CH6 FTM5
0000_0100 LPSPI0_PCS1 LPSPI0
PTB0 PCR_PTB0 0000_0000 DISABLED
0000_0001 PTB0 PTB
0000_0010 LPUART0_RX LPUART0
0000_0011 LPSPI0_PCS0 LPSPI0
0000_0100 LPTMR0_ALT3 LPTMR0
0000_0101 CAN0_RX CAN0
0000_0110 FTM4_CH6 FTM4
- - ADC0_SE4 ADC0
- - ADC1_SE14 ADC1
PTB1 PCR_PTB1 0000_0000 DISABLED
0000_0001 PTB1 PTB
0000_0010 LPUART0_TX LPUART0
0000_0011 LPSPI0_SOUT LPSPI0
0000_0100 TCLK0 FTM
0000_0101 CAN0_TX CAN0
0000_0110 FTM4_CH5 FTM4
- - ADC0_SE5 ADC0
- - ADC1_SE15 ADC1
PTB2 PCR_PTB2 0000_0000 DISABLED
0000_0001 PTB2 PTB
0000_0010 FTM1_CH0 FTM1
0000_0011 LPSPI0_SCK LPSPI0
0000_0100 FTM1_QD_PHB FTM1
0000_0110 TRGMUX_IN3 TRGMUX
- - ADC0_SE6 ADC0
PTB3 PCR_PTB3 0000_0000 DISABLED
0000_0001 PTB3 PTB
0000_0010 FTM1_CH1 FTM1
0000_0011 LPSPI0_SIN LPSPI0
0000_0100 FTM1_QD_PHA FTM1
0000_0110 TRGMUX_IN2 TRGMUX
- - ADC0_SE7 ADC0
PTB4 PCR_PTB4 0000_0000 DISABLED
0000_0001 PTB4 PTB
0000_0010 FTM0_CH4 FTM0
0000_0011 LPSPI0_SOUT LPSPI0
0000_0101 MII_RMII_MDIO ENET
0000_0110 TRGMUX_IN1 TRGMUX
0000_0111 QSPI_B_IO0 QuadSPI
PTB5 PCR_PTB5 0000_0000 DISABLED
 0000_0001 PTB5 PTB
0000_0010 FTM0_CH5 FTM0
0000_0011 LPSPI0_PCS1 LPSPI0
0000_0100 LPSPI0_PCS0 LPSPI0
0000_0101 CLKOUT SYSTEM
0000_0110 TRGMUX_IN0 TRGMUX
0000_0111 MII_RMII_MDC ENET
PTB6 PCR_PTB6 0000_0000 DISABLED
0000_0001 PTB6 PTB
0000_0010 LPI2C0_SDA LPI2C0
- - XTAL OSC
PTB7 PCR_PTB7 0000_0000 DISABLED
0000_0001 PTB7 PTB
0000_0010 LPI2C0_SCL LPI2C0
- - EXTAL OSC
PTB8 PCR_PTB8 0000_0000 DISABLED
0000_0001 PTB8 PTB
0000_0010 FTM3_CH0 FTM3
0000_0100 SAI1_BCLK SAI1
PTB9 PCR_PTB9 0000_0000 DISABLED
0000_0001 PTB9 PTB
0000_0010 FTM3_CH1 FTM3
0000_0011 LPI2C0_SCLS LPI2C0
0000_0100 SAI1_D0 SAI1
PTB10 PCR_PTB10 0000_0000 DISABLED
0000_0001 PTB10 PTB
0000_0010 FTM3_CH2 FTM3
0000_0011 LPI2C0_SDAS LPI2C0
0000_0100 SAI1_MCLK SAI1
PTB11 PCR_PTB11 0000_0000 DISABLED
0000_0001 PTB11 PTB
0000_0010 FTM3_CH3 FTM3
0000_0011 LPI2C0_HREQ LPI2C0
PTB12 PCR_PTB12 0000_0000 DISABLED
0000_0001 PTB12 PTB
0000_0010 FTM0_CH0 FTM0
0000_0011 FTM3_FLT2 FTM3
0000_0100 CAN2_RX CAN2
0000_0101 FTM6_FLT1 FTM6
- - ADC1_SE7 ADC1
PTB13 PCR_PTB13 0000_0000 DISABLED
0000_0001 PTB13 PTB
0000_0010 FTM0_CH1 FTM0
0000_0011 FTM3_FLT1 FTM3
0000_0100 CAN2_TX CAN2
0000_0101 FTM6_FLT0 FTM6
- - ADC1_SE8 ADC1
- - ADC0_SE8 ADC0
PTB14 PCR_PTB14 0000_0000 DISABLED
0000_0001 PTB14 PTB
0000_0010 FTM0_CH2 FTM0
0000_0011 LPSPI1_SCK LPSPI1
- - ADC1_SE9 ADC1
- - ADC0_SE9 ADC0
PTB15 PCR_PTB15 0000_0000 DISABLED
0000_0001 PTB15 PTB
0000_0010 FTM0_CH3 FTM0
0000_0011 LPSPI1_SIN LPSPI1
- - ADC1_SE14 ADC1
PTB16 PCR_PTB16 0000_0000 DISABLED
0000_0001 PTB16 PTB
0000_0010 FTM0_CH4 FTM0
0000_0011 LPSPI1_SOUT LPSPI1
- - ADC1_SE15 ADC1
PTB17 PCR_PTB17 0000_0000 DISABLED
0000_0001 PTB17 PTB
0000_0010 FTM0_CH5 FTM0
0000_0011 LPSPI1_PCS3 LPSPI1
0000_0100 FTM5_FLT1 FTM5
PTB18 PCR_PTB18 0000_0000 DISABLED
0000_0001 PTB18 PTB
0000_0010 FTM5_CH7 FTM5
0000_0100 LPSPI1_PCS1 LPSPI1
- - ADC0_SE16 ADC0
PTB19 PCR_PTB19 0000_0000 DISABLED
0000_0001 PTB19 PTB
0000_0010 FTM5_CH7 FTM5
PTB20 PCR_PTB20 0000_0000 DISABLED
0000_0001 PTB20 PTB
0000_0010 FTM6_CH0 FTM6
- - ADC0_SE17 ADC0
PTB21 PCR_PTB21 0000_0000 DISABLED
0000_0001 PTB21 PTB
0000_0010 FTM6_CH1 FTM6
- - ADC0_SE18 ADC0
PTB22 PCR_PTB22 0000_0000 DISABLED
0000_0001 PTB22 PTB
0000_0010 FTM6_CH2 FTM6
0000_0011 MII_CRS ENET
0000_0101 LPUART1_TX LPUART1
- - ADC0_SE19 ADC0
PTB23 PCR_PTB23 0000_0000 DISABLED
0000_0001 PTB23 PTB
0000_0010 FTM6_CH3 FTM6
0000_0011 LPUART1_RX LPUART1
0000_0100 MII_COL ENET
 - - ADC0_SE20 ADC0
PTB24 PCR_PTB24 0000_0000 DISABLED
0000_0001 PTB24 PTB
0000_0010 FTM6_CH4 FTM6
PTB25 PCR_PTB25 0000_0000 DISABLED
0000_0001 PTB25 PTB
0000_0010 FTM6_CH5 FTM6
0000_0101 LPSPI2_PCS0 LPSPI2
- - ADC0_SE21 ADC0
PTB26 PCR_PTB26 0000_0000 DISABLED
0000_0001 PTB26 PTB
0000_0010 FTM6_CH6 FTM6
PTB27 PCR_PTB27 0000_0000 DISABLED
0000_0001 PTB27 PTB
0000_0010 FTM6_CH7 FTM6
0000_0101 LPSPI2_SOUT LPSPI2
- - ADC0_SE22 ADC0
PTB28 PCR_PTB28 0000_0000 DISABLED
0000_0001 PTB28 PTB
0000_0010 FTM7_CH0 FTM7
0000_0101 LPSPI2_SIN LPSPI2
- - ADC0_SE23 ADC0
PTB29 PCR_PTB29 0000_0000 DISABLED
0000_0001 PTB29 PTB
0000_0010 FTM7_CH1 FTM7
0000_0101 LPSPI2_SCK LPSPI2
- - ADC0_SE24 ADC0
PTB30 PCR_PTB30 0000_0000 DISABLED
0000_0001 PTB30 PTB
0000_0010 FTM7_CH2 FTM7
PTB31 PCR_PTB31 0000_0000 DISABLED
0000_0001 PTB31 PTB
0000_0010 FTM7_CH3 FTM7
PTC0 PCR_PTC0 0000_0000 DISABLED
0000_0001 PTC0 PTC
0000_0010 FTM0_CH0 FTM0
0000_0011 LPSPI2_SIN LPSPI2
0000_0100 MII_RMII_RXD[1] ENET
0000_0101 MII_RMII_RXD[0] ENET
0000_0110 FTM1_CH6 FTM1
0000_0111 QSPI_B_RWDS QuadSPI
- - ADC0_SE8 ADC0
PTC1 PCR_PTC1 0000_0000 DISABLED
0000_0001 PTC1 PTC
0000_0010 FTM0_CH1 FTM0
0000_0011 LPSPI2_SOUT LPSPI2
0000_0100 MII_RMII_RXD[1] ENET
0000_0101 MII_RMII_RXD[0] ENET
 0000_0110 FTM1_CH7 FTM1
0000_0111 QSPI_B_SCK QuadSPI
- - ADC0_SE9 ADC0
PTC2 PCR_PTC2 0000_0000 DISABLED
0000_0001 PTC2 PTC
0000_0010 FTM0_CH2 FTM0
0000_0011 CAN0_RX CAN0
0000_0100 LPUART0_RX LPUART0
0000_0101 MII_RMII_TXD[0] ENET
0000_0110 ETM_TRACE_CLKOUT TRACE
0000_0111 QSPI_A_IO3 QuadSPI
- - ADC0_SE10 ADC0
- - CMP0_IN5 CMP0
PTC3 PCR_PTC3 0000_0000 DISABLED
0000_0001 PTC3 PTC
0000_0010 FTM0_CH3 FTM0
0000_0011 CAN0_TX CAN0
0000_0100 LPUART0_TX LPUART0
0000_0101 MII_TX_ER ENET
0000_0110 QSPI_A_CS QuadSPI
0000_0111 QSPI_B_IO3 QuadSPI
- - ADC0_SE11 ADC0
- - CMP0_IN4 CMP0
PTC4 PCR_PTC4 0000_0000 DISABLED
0000_0001 PTC4 PTC
0000_0010 FTM1_CH0 FTM1
0000_0011 RTC_CLKOUT RTC
0000_0101 EWM_IN EWM
0000_0110 FTM1_QD_PHB FTM1
0000_0111 JTAG_TCLK/SWD_CLK JTAG/SWD
- - CMP0_IN2 CMP0
PTC5 PCR_PTC5 0000_0000 DISABLED
0000_0001 PTC5 PTC
0000_0010 FTM2_CH0 FTM2
0000_0011 RTC_CLKOUT RTC
0000_0100 LPI2C1_HREQ LPI2C1
0000_0110 FTM2_QD_PHB FTM2
0000_0111 JTAG_TDI JTAG
PTC6 PCR_PTC6 0000_0000 DISABLED
0000_0001 PTC6 PTC
0000_0010 LPUART1_RX LPUART1
0000_0011 CAN1_RX CAN1
0000_0100 FTM3_CH2 FTM3
0000_0110 FTM1_QD_PHB FTM1
- - ADC1_SE4 ADC1
PTC7 PCR_PTC7 0000_0000 DISABLED
0000_0001 PTC7 PTC
0000_0010 LPUART1_TX LPUART1
 0000_0011 CAN1_TX CAN1
0000_0100 FTM3_CH3 FTM3
0000_0110 FTM1_QD_PHA FTM1
- - ADC1_SE5 ADC1
PTC8 PCR_PTC8 0000_0000 DISABLED
0000_0001 PTC8 PTC
0000_0010 LPUART1_RX LPUART1
0000_0011 FTM1_FLT0 FTM1
0000_0100 FTM5_CH1 FTM5
0000_0110 LPUART0_CTS LPUART0
PTC9 PCR_PTC9 0000_0000 DISABLED
0000_0001 PTC9 PTC
0000_0010 LPUART1_TX LPUART1
0000_0011 FTM1_FLT1 FTM1
0000_0100 FTM5_CH0 FTM5
0000_0110 LPUART0_RTS LPUART0
PTC10 PCR_PTC10 0000_0000 DISABLED
0000_0001 PTC10 PTC
0000_0010 FTM3_CH4 FTM3
0000_0110 TRGMUX_IN11 TRGMUX
PTC11 PCR_PTC11 0000_0000 DISABLED
0000_0001 PTC11 PTC
0000_0010 FTM3_CH5 FTM3
0000_0011 FTM4_CH2 FTM4
0000_0110 TRGMUX_IN10 TRGMUX
PTC12 PCR_PTC12 0000_0000 DISABLED
0000_0001 PTC12 PTC
0000_0010 FTM3_CH6 FTM3
0000_0011 FTM2_CH6 FTM2
0000_0100 LPUART2_CTS LPUART2
PTC13 PCR_PTC13 0000_0000 DISABLED
0000_0001 PTC13 PTC
0000_0010 FTM3_CH7 FTM3
0000_0011 FTM2_CH7 FTM2
0000_0100 LPUART2_RTS LPUART2
PTC14 PCR_PTC14 0000_0000 DISABLED
0000_0001 PTC14 PTC
0000_0010 FTM1_CH2 FTM1
0000_0011 LPSPI2_PCS0 LPSPI2
0000_0100 MII_COL ENET
0000_0110 TRGMUX_IN9 TRGMUX
- - ADC0_SE12 ADC0
PTC15 PCR_PTC15 0000_0000 DISABLED
0000_0001 PTC15 PTC
0000_0010 FTM1_CH3 FTM1
0000_0011 LPSPI2_SCK LPSPI2
0000_0100 MII_CRS ENET
0000_0110 TRGMUX_IN8 TRGMUX
 0000_0111 QSPI_B_CS QuadSPI
- - ADC0_SE13 ADC0
PTC16 PCR_PTC16 0000_0000 DISABLED
0000_0001 PTC16 PTC
0000_0010 FTM1_FLT2 FTM1
0000_0011 CAN2_RX CAN2
0000_0100 LPI2C1_SDAS LPI2C1
0000_0101 MII_RMII_RX_ER ENET
0000_0111 QSPI_B_IO7 QuadSPI
- - ADC0_SE14 ADC0
PTC17 PCR_PTC17 0000_0000 DISABLED
0000_0001 PTC17 PTC
0000_0010 FTM1_FLT3 FTM1
0000_0011 CAN2_TX CAN2
0000_0100 LPI2C1_SCLS LPI2C1
0000_0101 MII_RMII_RX_DV ENET
0000_0111 QSPI_B_IO6 QuadSPI
- - ADC0_SE15 ADC0
PTC18 PCR_PTC18 0000_0000 DISABLED
0000_0001 PTC18 PTC
0000_0010 FTM7_CH4 FTM7
PTC19 PCR_PTC19 0000_0000 DISABLED
0000_0001 PTC19 PTC
0000_0010 FTM7_CH5 FTM7
0000_0101 LPSPI2_PCS1 LPSPI2
- - ADC0_SE25 ADC0
PTC20 PCR_PTC20 0000_0000 DISABLED
0000_0001 PTC20 PTC
0000_0010 FTM7_CH6 FTM7
PTC21 PCR_PTC21 0000_0000 DISABLED
0000_0001 PTC21 PTC
0000_0010 FTM7_CH7 FTM7
0000_0100 FTM7_FLT0 FTM7
PTC22 PCR_PTC22 0000_0000 DISABLED
0000_0001 PTC22 PTC
0000_0010 FTM7_FLT1 FTM7
PTC23 PCR_PTC23 0000_0000 DISABLED
0000_0001 PTC23 PTC
0000_0010 LPSPI0_SCK LPSPI0
- - ADC0_SE26 ADC0
PTC24 PCR_PTC24 0000_0000 DISABLED
0000_0001 PTC24 PTC
0000_0010 FTM4_CH0 FTM4
PTC25 PCR_PTC25 0000_0000 DISABLED
0000_0001 PTC25 PTC
0000_0010 FTM4_CH1 FTM4
PTC26 PCR_PTC26 0000_0000 DISABLED
0000_0001 PTC26 PTC
 0000_0010 FTM4_CH3 FTM4
PTC27 PCR_PTC27 0000_0000 DISABLED
0000_0001 PTC27 PTC
0000_0010 FTM4_CH4 FTM4
- - ADC0_SE27 ADC0
PTC28 PCR_PTC28 0000_0000 DISABLED
0000_0001 PTC28 PTC
0000_0010 FTM4_CH7 FTM4
- - ADC0_SE28 ADC0
PTC29 PCR_PTC29 0000_0000 DISABLED
0000_0001 PTC29 PTC
0000_0010 FTM5_CH2 FTM5
- - ADC0_SE29 ADC0
PTC30 PCR_PTC30 0000_0000 DISABLED
0000_0001 PTC30 PTC
0000_0010 FTM5_CH4 FTM5
0000_0011 FXIO_D0 FXIO
0000_0100 LPI2C1_SDAS LPI2C1
- - ADC0_SE30 ADC0
PTC31 PCR_PTC31 0000_0000 DISABLED
0000_0001 PTC31 PTC
0000_0010 FTM5_CH6 FTM5
0000_0011 FXIO_D1 FXIO
0000_0100 LPI2C1_SDA LPI2C1
- - ADC0_SE31 ADC0
PTD0 PCR_PTD0 0000_0000 DISABLED
0000_0001 PTD0 PTD
0000_0010 FTM0_CH2 FTM0
0000_0011 LPSPI1_SCK LPSPI1
0000_0100 FTM2_CH0 FTM2
0000_0101 ETM_TRACE_D0 TRACE
0000_0110 FXIO_D0 FXIO
0000_0111 TRGMUX_OUT1 TRGMUX
PTD1 PCR_PTD1 0000_0000 DISABLED
0000_0001 PTD1 PTD
0000_0010 FTM0_CH3 FTM0
0000_0011 LPSPI1_SIN LPSPI1
0000_0100 FTM2_CH1 FTM2
0000_0101 SAI0_MCLK SAI0
0000_0110 FXIO_D1 FXIO
0000_0111 TRGMUX_OUT2 TRGMUX
PTD2 PCR_PTD2 0000_0000 DISABLED
0000_0001 PTD2 PTD
0000_0010 FTM3_CH4 FTM3
0000_0011 LPSPI1_SOUT LPSPI1
0000_0100 FXIO_D4 FXIO
0000_0101 FXIO_D6 FXIO
0000_0110 TRGMUX_IN5 TRGMUX
 - - ADC1_SE2 ADC1
PTD3 PCR_PTD3 0000_0000 DISABLED
0000_0001 PTD3 PTD
0000_0010 FTM3_CH5 FTM3
0000_0011 LPSPI1_PCS0 LPSPI1
0000_0100 FXIO_D5 FXIO
0000_0101 FXIO_D7 FXIO
0000_0110 TRGMUX_IN4 TRGMUX
0000_0111 NMI_b SYSTEM
- - ADC1_SE3 ADC1
PTD4 PCR_PTD4 0000_0000 DISABLED
0000_0001 PTD4 PTD
0000_0010 FTM0_FLT3 FTM0
0000_0011 FTM3_FLT3 FTM3
- - ADC1_SE6 ADC1
PTD5 PCR_PTD5 0000_0000 DISABLED
0000_0001 PTD5 PTD
0000_0010 FTM2_CH3 FTM2
0000_0011 LPTMR0_ALT2 LPTMR0
0000_0100 FTM2_FLT1 FTM2
0000_0101 MII_TXD3 ENET
0000_0110 TRGMUX_IN7 TRGMUX
0000_0111 QSPI_B_IO2 QuadSPI
PTD6 PCR_PTD6 0000_0000 DISABLED
0000_0001 PTD6 PTD
0000_0010 LPUART2_RX LPUART2
0000_0100 FTM2_FLT2 FTM2
0000_0101 MII_TXD2 ENET
0000_0111 QSPI_B_IO1 QuadSPI
- - CMP0_IN7 CMP0
PTD7 PCR_PTD7 0000_0000 DISABLED
0000_0001 PTD7 PTD
0000_0010 LPUART2_TX LPUART2
0000_0100 FTM2_FLT3 FTM2
0000_0101 MII_RMII_TXD[1] ENET
0000_0110 ETM_TRACE_D0 TRACE
0000_0111 QSPI_A_IO1 QuadSPI
- - CMP0_IN6 CMP0
PTD8 PCR_PTD8 0000_0000 DISABLED
0000_0001 PTD8 PTD
0000_0010 LPI2C1_SDA LPI2C1
0000_0011 MII_RXD3 ENET
0000_0100 FTM2_FLT2 FTM2
0000_0101 FXIO_D1 FXIO
0000_0110 FTM1_CH4 FTM1
0000_0111 QSPI_B_IO5 QuadSPI
PTD9 PCR_PTD9 0000_0000 DISABLED
0000_0001 PTD9 PTD
 0000_0010 LPI2C1_SCL LPI2C1
0000_0011 FXIO_D0 FXIO
0000_0100 FTM2_FLT3 FTM2
0000_0101 MII_RXD2 ENET
0000_0110 FTM1_CH5 FTM1
0000_0111 QSPI_B_IO4 QuadSPI
PTD10 PCR_PTD10 0000_0000 DISABLED
0000_0001 PTD10 PTD
0000_0010 FTM2_CH0 FTM2
0000_0011 FTM2_QD_PHB FTM2
0000_0100 ETM_TRACE_D3 TRACE
0000_0101 MII_RX_CLK ENET
0000_0110 CLKOUT SYSTEM
0000_0111 QSPI_A_SCK QuadSPI
PTD11 PCR_PTD11 0000_0000 DISABLED
0000_0001 PTD11 PTD
0000_0010 FTM2_CH1 FTM2
0000_0011 FTM2_QD_PHA FTM2
0000_0100 ETM_TRACE_D2 TRACE
0000_0101 MII_RMII_TX_CLK ENET
0000_0110 LPUART2_CTS LPUART2
0000_0111 QSPI_A_IO0 QuadSPI
PTD12 PCR_PTD12 0000_0000 DISABLED
0000_0001 PTD12 PTD
0000_0010 FTM2_CH2 FTM2
0000_0011 LPI2C1_HREQ LPI2C1
0000_0100 ETM_TRACE_D1 TRACE
0000_0101 MII_RMII_TX_EN ENET
0000_0110 LPUART2_RTS LPUART2
0000_0111 QSPI_A_IO2 QuadSPI
PTD13 PCR_PTD13 0000_0000 DISABLED
0000_0001 PTD13 PTD
0000_0010 FTM2_CH4 FTM2
0000_0011 LPUART1_RX LPUART1
0000_0101 ENET_TMR1 ENET
0000_0111 RTC_CLKOUT RTC
PTD14 PCR_PTD14 0000_0000 DISABLED
0000_0001 PTD14 PTD
0000_0010 FTM2_CH5 FTM2
0000_0011 LPUART1_TX LPUART1
0000_0101 ENET_TMR0 ENET
0000_0111 CLKOUT SYSTEM
PTD15 PCR_PTD15 0000_0000 DISABLED
0000_0001 PTD15 PTD
0000_0010 FTM0_CH0 FTM0
0000_0011 ETM_TRACE_D3 TRACE
0000_0100 LPSPI0_SCK LPSPI0
0000_0101 ENET_TMR2 ENET
PTD16 PCR_PTD16 0000_0000 DISABLED
0000_0001 PTD16 PTD
0000_0010 FTM0_CH1 FTM0
0000_0011 ETM_TRACE_D2 TRACE
0000_0100 LPSPI0_SIN LPSPI0
0000_0101 CMP0_RRT CMP0
0000_0110 ETM_TRACE_CLKOUT TRACE
PTD17 PCR_PTD17 0000_0000 DISABLED
0000_0001 PTD17 PTD
0000_0010 FTM0_FLT2 FTM0
0000_0011 LPUART2_RX LPUART2
0000_0100 FTM5_FLT1 FTM5
PTD18 PCR_PTD18 0000_0000 DISABLED
0000_0001 PTD18 PTD
0000_0010 FTM5_CH7 FTM5
0000_0011 FXIO_D2 FXIO
0000_0100 LPI2C1_SCLS LPI2C1
- - ADC1_SE16 ADC1
PTD19 PCR_PTD19 0000_0000 DISABLED
0000_0001 PTD19 PTD
0000_0010 FTM6_CH0 FTM6
0000_0011 FXIO_D3 FXIO
0000_0100 LPI2C1_SCL LPI2C1
- - ADC1_SE17 ADC1
PTD20 PCR_PTD20 0000_0000 DISABLED
0000_0001 PTD20 PTD
0000_0010 FTM6_CH1 FTM6
PTD21 PCR_PTD21 0000_0000 DISABLED
0000_0001 PTD21 PTD
0000_0010 FTM6_CH2 FTM6
PTD22 PCR_PTD22 0000_0000 DISABLED
0000_0001 PTD22 PTD
0000_0010 FTM6_CH3 FTM6
- - ADC1_SE18 ADC1
PTD23 PCR_PTD23 0000_0000 DISABLED
0000_0001 PTD23 PTD
0000_0010 FTM6_CH4 FTM6
- - ADC1_SE19 ADC1
PTD24 PCR_PTD24 0000_0000 DISABLED
0000_0001 PTD24 PTD
0000_0010 FTM6_CH5 FTM6
- - ADC1_SE20 ADC1
PTD25 PCR_PTD25 0000_0000 DISABLED
0000_0001 PTD25 PTD
0000_0010 FTM6_CH6 FTM6
PTD26 PCR_PTD26 0000_0000 DISABLED
0000_0001 PTD26 PTD
0000_0010 FTM6_CH7 FTM6
 0000_0011 FXIO_D7 FXIO
PTD27 PCR_PTD27 0000_0000 DISABLED
0000_0001 PTD27 PTD
0000_0010 FTM7_CH0 FTM7
- - ADC1_SE21 ADC1
PTD28 PCR_PTD28 0000_0000 DISABLED
0000_0001 PTD28 PTD
0000_0010 FTM7_CH1 FTM7
- - ADC1_SE22 ADC1
PTD29 PCR_PTD29 0000_0000 DISABLED
0000_0001 PTD29 PTD
0000_0010 FTM7_CH2 FTM7
- - ADC1_SE23 ADC1
PTD30 PCR_PTD30 0000_0000 DISABLED
0000_0001 PTD30 PTD
0000_0010 FTM7_CH3 FTM7
0000_0011 FTM6_FLT1 FTM6
- - ADC1_SE24 ADC1
PTD31 PCR_PTD31 0000_0000 DISABLED
0000_0001 PTD31 PTD
0000_0010 FTM7_CH4 FTM7
0000_0011 FXIO_D6 FXIO
0000_0101 FTM6_FLT0 FTM6
PTE0 PCR_PTE0 0000_0000 DISABLED
0000_0001 PTE0 PTE
0000_0010 LPSPI0_SCK LPSPI0
0000_0011 TCLK1 FTM
0000_0100 LPI2C1_SDA LPI2C1
0000_0101 LPSPI1_SOUT LPSPI1
0000_0110 FTM1_FLT2 FTM1
0000_0111 SAI0_D2 SAI0
PTE1 PCR_PTE1 0000_0000 DISABLED
0000_0001 PTE1 PTE
0000_0010 LPSPI0_SIN LPSPI0
0000_0011 LPI2C0_HREQ LPI2C0
0000_0100 LPI2C1_SCL LPI2C1
0000_0101 LPSPI1_PCS0 LPSPI1
0000_0110 FTM1_FLT1 FTM1
0000_0111 SAI0_D1 SAI0
PTE2 PCR_PTE2 0000_0000 DISABLED
0000_0001 PTE2 PTE
0000_0010 LPSPI0_SOUT LPSPI0
0000_0011 LPTMR0_ALT3 LPTMR0
0000_0100 FTM3_CH6 FTM3
0000_0110 LPUART1_CTS LPUART1
0000_0111 SAI1_SYNC SAI1
- - ADC1_SE10 ADC1
PTE3 PCR_PTE3 0000_0000 DISABLED
 0000_0001 PTE3 PTE
0000_0010 FTM0_FLT0 FTM0
0000_0011 LPUART2_RTS LPUART2
0000_0100 FTM2_FLT0 FTM2
0000_0110 TRGMUX_IN6 TRGMUX
0000_0111 CMP0_OUT CMP0
PTE4 PCR_PTE4 0000_0000 DISABLED
0000_0001 PTE4 PTE
0000_0010 ETM_TRACE_D1 TRACE
0000_0011 FTM2_QD_PHB FTM2
0000_0100 FTM2_CH2 FTM2
0000_0101 CAN0_RX CAN0
0000_0110 FXIO_D6 FXIO
0000_0111 EWM_OUT_b EWM
PTE5 PCR_PTE5 0000_0000 DISABLED
0000_0001 PTE5 PTE
0000_0010 TCLK2 FTM
0000_0011 FTM2_QD_PHA FTM2
0000_0100 FTM2_CH3 FTM2
0000_0101 CAN0_TX CAN0
0000_0110 FXIO_D7 FXIO
0000_0111 EWM_IN EWM
PTE6 PCR_PTE6 0000_0000 DISABLED
0000_0001 PTE6 PTE
0000_0010 LPSPI0_PCS2 LPSPI0
0000_0011 FTM7_FLT1 FTM7
0000_0100 FTM3_CH7 FTM3
0000_0110 LPUART1_RTS LPUART1
- - ADC1_SE11 ADC1
PTE7 PCR_PTE7 0000_0000 DISABLED
0000_0001 PTE7 PTE
0000_0010 FTM0_CH7 FTM0
0000_0011 FTM3_FLT0 FTM3
PTE8 PCR_PTE8 0000_0000 DISABLED
0000_0001 PTE8 PTE
0000_0010 FTM0_CH6 FTM0
0000_0101 MII_RMII_MDC ENET
- - CMP0_IN3 CMP0
PTE9 PCR_PTE9 0000_0000 DISABLED
0000_0001 PTE9 PTE
0000_0010 FTM0_CH7 FTM0
0000_0011 LPUART2_CTS LPUART2
0000_0101 ENET_TMR3 ENET
PTE10 PCR_PTE10 0000_0000 DISABLED
0000_0001 PTE10 PTE
0000_0010 CLKOUT SYSTEM
0000_0011 LPSPI2_PCS1 LPSPI2
0000_0100 FTM2_CH4 FTM2
 0000_0110 FXIO_D4 FXIO
0000_0111 TRGMUX_OUT4 TRGMUX
PTE11 PCR_PTE11 0000_0000 DISABLED
0000_0001 PTE11 PTE
0000_0010 LPSPI2_PCS0 LPSPI2
0000_0011 LPTMR0_ALT1 LPTMR0
0000_0100 FTM2_CH5 FTM2
0000_0110 FXIO_D5 FXIO
0000_0111 TRGMUX_OUT5 TRGMUX
PTE12 PCR_PTE12 0000_0000 DISABLED
0000_0001 PTE12 PTE
0000_0010 FTM0_FLT3 FTM0
0000_0011 LPUART2_TX LPUART2
0000_0100 FTM5_FLT0 FTM5
PTE13 PCR_PTE13 0000_0000 DISABLED
0000_0001 PTE13 PTE
0000_0010 FTM4_CH5 FTM4
0000_0011 LPSPI2_PCS2 LPSPI2
0000_0100 FTM2_FLT0 FTM2
PTE14 PCR_PTE14 0000_0000 DISABLED
0000_0001 PTE14 PTE
0000_0010 FTM0_FLT1 FTM0
0000_0100 FTM2_FLT1 FTM2
PTE15 PCR_PTE15 0000_0000 DISABLED
0000_0001 PTE15 PTE
0000_0010 LPUART1_CTS LPUART1
0000_0011 LPSPI2_SCK LPSPI2
0000_0100 FTM2_CH6 FTM2
0000_0101 FTM4_FLT1 FTM4
0000_0110 FXIO_D2 FXIO
0000_0111 TRGMUX_OUT6 TRGMUX
PTE16 PCR_PTE16 0000_0000 DISABLED
0000_0001 PTE16 PTE
0000_0010 LPUART1_RTS LPUART1
0000_0011 LPSPI2_SIN LPSPI2
0000_0100 FTM2_CH7 FTM2
0000_0101 FTM4_FLT0 FTM4
0000_0110 FXIO_D3 FXIO
0000_0111 TRGMUX_OUT7 TRGMUX
PTE17 PCR_PTE17 0000_0000 DISABLED
0000_0001 PTE17 PTE
0000_0010 FTM7_CH5 FTM7
0000_0011 FXIO_D5 FXIO
PTE18 PCR_PTE18 0000_0000 DISABLED
0000_0001 PTE18 PTE
0000_0010 FTM7_CH6 FTM7
0000_0011 FXIO_D4 FXIO
PTE19 PCR_PTE19 0000_0000 DISABLED
 0000_0001 PTE19 PTE
0000_0010 FTM7_CH7 FTM7
- - ADC1_SE25 ADC1
PTE20 PCR_PTE20 0000_0000 DISABLED
0000_0001 PTE20 PTE
0000_0010 FTM4_CH0 FTM4
- - ADC1_SE26 ADC1
PTE21 PCR_PTE21 0000_0000 DISABLED
0000_0001 PTE21 PTE
0000_0010 FTM4_CH1 FTM4
- - ADC1_SE27 ADC1
PTE22 PCR_PTE22 0000_0000 DISABLED
0000_0001 PTE22 PTE
0000_0010 FTM4_CH2 FTM4
- - ADC1_SE28 ADC1
PTE23 PCR_PTE23 0000_0000 DISABLED
0000_0001 PTE23 PTE
0000_0010 FTM4_CH3 FTM4
- - ADC1_SE29 ADC1
PTE24 PCR_PTE24 0000_0000 DISABLED
0000_0001 PTE24 PTE
0000_0010 FTM4_CH4 FTM4
0000_0011 CAN2_TX CAN2
- - ADC1_SE30 ADC1
PTE25 PCR_PTE25 0000_0000 DISABLED
0000_0001 PTE25 PTE
0000_0010 FTM4_CH5 FTM4
0000_0011 CAN2_RX CAN2
- - ADC1_SE31 ADC1
PTE26 PCR_PTE26 0000_0000 DISABLED
0000_0001 PTE26 PTE
0000_0010 FTM4_CH6 FTM4
PTE27 PCR_PTE27 0000_0000 DISABLED
0000_0001 PTE27 PTE
0000_0010 FTM4_CH7 FTM4
* NOTE: QSPI NOT AVAILABLE IN 100 LQFP PACKAGE
 Direction
Description Pad Type
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPI2C Secondary Clock I/O I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM quadrature Decode PhaseA I
Clear To Send (bar) I
Trigger Mux Output O
ADC Single Ended Input I
Comparator Input Signal I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPI2C Secondary Data I/O I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM quadrature Decode PhaseA I
Request To Send O
Trigger Mux Output O
ADC Single Ended Input I
Comparator Input Signal I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPI2C Data I/O I/O
External Watchdog Monitor Output O
FlexIO Bi-directional Shift/timer I/O I/O
Receive I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPI2C Clock I/O I/O
External Watchdog Monitor Input I
FlexIO Bi-directional Shift/timer I/O I/O
Transmit I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
Comparator Output trigger O
 External Watchdog Monitor Output O
JTAG Test Mode Select/Serial Wire Debug Data I/O I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM External Clock Input I
Reset I/O I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Fault Input I
Peripheral Chip Select 1 I/O
FTM Channel I/O
Clear To Send (bar) I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Fault Input I
FTM Channel I/O
RTC Clock Input I
Request To Send O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
Receive I
LPSPI Serial Data Output I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM Fault Input I
FTM Fault Input I
Signal Path Disabled - GPIO
Port A I/O I/O
Transmit I/O
Peripheral Chip Select 0 I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM Fault Input I
FTM Fault Input I
FTM Fault Input I
Signal Path Disabled - GPIO-HD
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
JTAG Test Data Output/Trace Output O
Signal Path Disabled - GPIO-HD
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Round Robin port output Trigger O
Synchronous Audio Interface Frame Sync I/O
Signal Path Disabled - GPIO-HD
Port A I/O I/O
 FTM Channel I/O
CAN Rx channel I
LPI2C Secondary Data I/O I/O
FTM quadrature Decode PhaseB I
Synchronous Audio Interface Bit Clock I/O
Signal Path Disabled - GPIO-HD
Port A I/O I/O
FTM Channel I/O
CAN Tx Channel O
LPI2C Secondary Clock I/O I/O
FTM quadrature Decode PhaseA I
Synchronous Audio Interface Tx/Rx Data I/O
Signal Path Disabled - GPIO-HD
Port A I/O I/O
FTM Fault Input I
FTM Fault Input I
External Watchdog Monitor Input I
FTM Fault Input I
Synchronous Audio Interface Tx/Rx Data I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Peripheral Chip Select 3 I/O
Peripheral Chip Select 3 I/O
FTM Fault Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Peripheral Chip Select 2 I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
FTM Fault Input I
External Watchdog Monitor Output O
FTM Fault Input I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Transmit I/O
LPSPI Serial Data Output I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Receive I
LPSPI Serial Clock I/O I/O
 Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Peripheral Chip Select 0 I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Peripheral Chip Select 1 I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Peripheral Chip Select 0 I/O
Peripheral Chip Select 0 I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
Transmit I/O
CAN Tx Channel O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
Receive I
CAN Rx channel I
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Transmit I/O
LPSPI Serial Data Input I/O
Signal Path Disabled - GPIO
 Port A I/O I/O
FTM Channel I/O
Receive I
LPSPI Serial Data Output I/O
Signal Path Disabled - GPIO
Port A I/O I/O
FTM Channel I/O
Peripheral Chip Select 1 I/O
Signal Path Disabled - GPIO
Port B I/O I/O
Receive I
Peripheral Chip Select 0 I/O
Low Power Timer Input Channel I
CAN Rx channel I
FTM Channel I/O
ADC Single Ended Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
Transmit I/O
LPSPI Serial Data Output I/O
FTM External Clock Input I
CAN Tx Channel O
FTM Channel I/O
ADC Single Ended Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
FTM quadrature Decode PhaseB I
Trigger Mux Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
FTM quadrature Decode PhaseA I
Trigger Mux Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
ENET Control data to/from PHY I/O
Trigger Mux Input I
QuadSPI Serial data for serial flash / RAM device B * I/O
Signal Path Disabled - GPIO-HD
 Port B I/O I/O
FTM Channel I/O
Peripheral Chip Select 1 I/O
Peripheral Chip Select 0 I/O
External Clock Output O
Trigger Mux Input I
ENET clock for control data transfer to PHY O
Signal Path Disabled - GPIO-HD
Port B I/O I/O
LPI2C Data I/O I/O
External Crystal Output O
Signal Path Disabled - GPIO
Port B I/O I/O
LPI2C Clock I/O I/O
External Crystal Input I
Signal Path Disabled - GPIO-HD
Port B I/O I/O
FTM Channel I/O
Synchronous Audio Interface Bit Clock I/O
Signal Path Disabled - GPIO-HD
Port B I/O I/O
FTM Channel I/O
LPI2C Secondary Clock I/O I/O
Synchronous Audio Interface Tx/Rx Data I/O
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPI2C Secondary Data I/O I/O
Synchronous Audio Interface I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPI2C Host Request Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
FTM Fault Input I
CAN Rx channel I
FTM Fault Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
FTM Fault Input I
CAN Tx Channel O
FTM Fault Input I
ADC Single Ended Input I
ADC Single Ended Input I
 Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
ADC Single Ended Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Peripheral Chip Select 3 I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Peripheral Chip Select 1 I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
ENET MII Carrier Sense I
Transmit I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Receive I
ENET MII Collision detected I
 ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Peripheral Chip Select 0 I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port B I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO-HD
Port C I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
ENET Receive Data I
ENET Receive Data I
FTM Channel I/O
QuadSPI Read Write Data Strobe for serial flash / RAM device B * I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port C I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
ENET Receive Data I
ENET Receive Data I
 FTM Channel I/O
QuadSPI Serial Clock for serial flash / RAM device B * I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO-FAST
Port C I/O I/O
FTM Channel I/O
CAN Rx channel I
Receive I
ENET Transmit Data O
O
QuadSPI Serial data for serial flash device A (fast) * I/O
ADC Single Ended Input I
Comparator Input Signal I
Signal Path Disabled - GPIO-HD
Port C I/O I/O
FTM Channel I/O
CAN Tx Channel O
Transmit I/O
O
QuadSPI Chip select for serial flash device A * O
QuadSPI Serial data for serial flash / RAM device B * I/O
ADC Single Ended Input I
Comparator Input Signal I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
RTC Clock Output O
External Watchdog Monitor Input I
FTM quadrature Decode PhaseB I
JTAG Test Clock Input/Serial Wire Debug Clock I
Comparator Input Signal I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
RTC Clock Output O
LPI2C Host Request Input I
FTM quadrature Decode PhaseB I
JTAG Test Data input I
Signal Path Disabled - GPIO
Port C I/O I/O
Receive I
CAN Rx channel I
FTM Channel I/O
FTM quadrature Decode PhaseB I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
Transmit I/O
 CAN Tx Channel O
FTM Channel I/O
FTM quadrature Decode PhaseA I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
Receive I
FTM Fault Input I
FTM Channel I/O
Clear To Send (bar) I
Signal Path Disabled - GPIO
Port C I/O I/O
Transmit I/O
FTM Fault Input I
FTM Channel I/O
Request To Send O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Trigger Mux Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FTM Channel I/O
Trigger Mux Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FTM Channel I/O
Clear To Send (bar) I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FTM Channel I/O
Request To Send O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Peripheral Chip Select 0 I/O
ENET MII Collision detected I
Trigger Mux Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
ENET MII Carrier Sense I
Trigger Mux Input I
QuadSPI Chip select for serial flash / RAM device B * O
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port C I/O I/O
FTM Fault Input I
CAN Rx channel I
LPI2C Secondary Data I/O I/O
ENET Receive Error I
QuadSPI Serial data for serial flash / RAM device B * I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port C I/O I/O
FTM Fault Input I
CAN Tx Channel O
LPI2C Secondary Clock I/O I/O
ENET Receive Data Valid I
QuadSPI Serial data for serial flash / RAM device B * I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Peripheral Chip Select 1 I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port C I/O I/O
LPSPI Serial Clock I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port C I/O I/O
 FTM Channel I/O
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
LPI2C Secondary Data I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port C I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
LPI2C Data I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port D I/O I/O
FTM Channel I/O
LPSPI Serial Clock I/O I/O
FTM Channel I/O
O
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO-HD
Port D I/O I/O
FTM Channel I/O
LPSPI Serial Data Input I/O
FTM Channel I/O
Synchronous Audio Interface I
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
LPSPI Serial Data Output I/O
FlexIO Bi-directional Shift/timer I/O I/O
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Input I
 ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Peripheral Chip Select 0 I/O
FlexIO Bi-directional Shift/timer I/O I/O
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Input I
Non Maskable Interrupt I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Fault Input I
FTM Fault Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO-HD
Port D I/O I/O
FTM Channel I/O
Low Power Timer Input Channel I
FTM Fault Input I
ENET Transmit data (MII mode only) O
Trigger Mux Input I
QuadSPI Serial data for serial flash / RAM device B * I/O
Signal Path Disabled - GPIO-HD
Port D I/O I/O
Receive I
FTM Fault Input I
ENET Transmit data (MII mode only) O
QuadSPI Serial data for serial flash / RAM device B * I/O
Comparator Input Signal I
Signal Path Disabled - GPIO-FAST
Port D I/O I/O
Transmit I/O
FTM Fault Input I
ENET Transmit Data O
O
QuadSPI Serial data for serial flash device A (fast) * I/O
Comparator Input Signal I
Signal Path Disabled - GPIO-HD
Port D I/O I/O
LPI2C Data I/O I/O
ENET Receive Data (MII mode only) I
FTM Fault Input I
FlexIO Bi-directional Shift/timer I/O I/O
FTM Channel I/O
QuadSPI Serial data for serial flash / RAM device B * I/O
Signal Path Disabled - GPIO-HD
Port D I/O I/O
 LPI2C Clock I/O I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM Fault Input I
ENET Receive Data (MII mode only) I
FTM Channel I/O
QuadSPI Serial data for serial flash / RAM device B * I/O
Signal Path Disabled - GPIO-FAST
Port D I/O I/O
FTM Channel I/O
FTM quadrature Decode PhaseB I
O
ENET MII Receive Clock I
External Clock Output O
QuadSPI Serial Clock for serial flash device A (fast) * I/O
Signal Path Disabled - GPIO-FAST
Port D I/O I/O
FTM Channel I/O
FTM quadrature Decode PhaseA I
O
ENET Transmit Clock I/O
Clear To Send (bar) I
QuadSPI Serial data for serial flash device A (fast) * I/O
Signal Path Disabled - GPIO-FAST
Port D I/O I/O
FTM Channel I/O
LPI2C Host Request Input I
O
ENET Transmit Enable O
Request To Send O
QuadSPI Serial data for serial flash device A (fast) * I/O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Receive I
ENET 1588 Timer Channel I/O
RTC Clock Output O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Transmit I/O
ENET 1588 Timer Channel I/O
External Clock Output O
Signal Path Disabled - GPIO-HD
Port D I/O I/O
FTM Channel I/O
O
LPSPI Serial Clock I/O I/O
ENET 1588 Timer Channel I/O
 Signal Path Disabled - GPIO-HD
Port D I/O I/O
FTM Channel I/O
O
LPSPI Serial Data Input I/O
Round Robin port output Trigger O
O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Fault Input I
Receive I
FTM Fault Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
LPI2C Secondary Clock I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
LPI2C Clock I/O I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
 FlexIO Bi-directional Shift/timer I/O I/O
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
FTM Fault Input I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port D I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
FTM Fault Input I
Signal Path Disabled - GPIO-HD
Port E I/O I/O
LPSPI Serial Clock I/O I/O
FTM External Clock Input I
LPI2C Data I/O I/O
LPSPI Serial Data Output I/O
FTM Fault Input I
Synchronous Audio Interface Tx/Rx Data I/O
Signal Path Disabled - GPIO-HD
Port E I/O I/O
LPSPI Serial Data Input I/O
LPI2C Host Request Input I
LPI2C Clock I/O I/O
Peripheral Chip Select 0 I/O
FTM Fault Input I
Synchronous Audio Interface Tx/Rx Data I/O
Signal Path Disabled - GPIO-HD
Port E I/O I/O
LPSPI Serial Data Output I/O
Low Power Timer Input Channel I
FTM Channel I/O
Clear To Send (bar) I
Synchronous Audio Interface Frame Sync I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
 Port E I/O I/O
FTM Fault Input I
Request To Send O
FTM Fault Input I
Trigger Mux Input I
Comparator Output trigger O
Signal Path Disabled - GPIO-HD
Port E I/O I/O
O
FTM quadrature Decode PhaseB I
FTM Channel I/O
CAN Rx channel I
FlexIO Bi-directional Shift/timer I/O I/O
External Watchdog Monitor Output O
Signal Path Disabled - GPIO
Port E I/O I/O
FTM External Clock Input I
FTM quadrature Decode PhaseA I
FTM Channel I/O
CAN Tx Channel O
FlexIO Bi-directional Shift/timer I/O I/O
External Watchdog Monitor Input I
Signal Path Disabled - GPIO
Port E I/O I/O
Peripheral Chip Select 2 I/O
FTM Fault Input I
FTM Channel I/O
Request To Send O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
ENET clock for control data transfer to PHY O
Comparator Input Signal I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
Clear To Send (bar) I
ENET 1588 Timer Channel I/O
Signal Path Disabled - GPIO
Port E I/O I/O
External Clock Output O
Peripheral Chip Select 1 I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO
Port E I/O I/O
Peripheral Chip Select 0 I/O
Low Power Timer Input Channel I
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Fault Input I
Transmit I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
Peripheral Chip Select 2 I/O
FTM Fault Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Fault Input I
FTM Fault Input I
Signal Path Disabled - GPIO
Port E I/O I/O
Clear To Send (bar) I
LPSPI Serial Clock I/O I/O
FTM Channel I/O
FTM Fault Input I
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO
Port E I/O I/O
Request To Send O
LPSPI Serial Data Input I/O
FTM Channel I/O
FTM Fault Input I
FlexIO Bi-directional Shift/timer I/O I/O
Trigger Mux Output O
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
FlexIO Bi-directional Shift/timer I/O I/O
Signal Path Disabled - GPIO
 Port E I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
CAN Tx Channel O
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
CAN Rx channel I
ADC Single Ended Input I
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
Signal Path Disabled - GPIO
Port E I/O I/O
FTM Channel I/O
 PCR
S32K148_144lqfp

S32K148_176lqfp

S32K148_100lqfp
S32K148_BGA

MUX[2:0]
IRQC[3:0]

DSE
PFE
Reset
ISF

PE
PS
LK
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 Bits Configurable
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'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'
'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011100000011'
'00000001000011111000011100010011'

'00000001000011111000011100000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'
'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011101000011'
'00000001000011111000011101000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011101000011'

'00000001000011111000011100000011'
'00000001000011111000011101000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'

'00000001000011111000011100000011'
Destination Instance Destination Function
CAN0 CAN0_RX

CAN1 CAN1_RX

CAN2 CAN2_RX

ENET MII_COL

ENET MII_CRS

ENET MII_RMII_RXD[0]

ENET MII_RMII_RXD[1]

EWM EWM_IN

FTM TCLK1

FTM0 FTM0_CH0

FTM0 FTM0_CH1

FTM0 FTM0_CH2

FTM0 FTM0_CH3
FTM0 FTM0_CH4

FTM0 FTM0_CH5

FTM0 FTM0_CH6

FTM0 FTM0_CH7

FTM0 FTM0_FLT0

FTM0 FTM0_FLT1

FTM0 FTM0_FLT2

FTM0 FTM0_FLT3

FTM1 FTM1_CH0

FTM1 FTM1_CH1

FTM1 FTM1_CH2

FTM1 FTM1_CH3

FTM1 FTM1_CH4

FTM1 FTM1_CH5

FTM1 FTM1_CH6

FTM1 FTM1_CH7
FTM1 FTM1_FLT0

FTM1 FTM1_FLT1

FTM1 FTM1_FLT2

FTM1 FTM1_FLT3

FTM1 FTM1_QD_PHA

FTM1 FTM1_QD_PHB

FTM2 FTM2_CH0

FTM2 FTM2_CH1

FTM2 FTM2_CH2

FTM2 FTM2_CH3

FTM2 FTM2_CH4

FTM2 FTM2_CH5

FTM2 FTM2_CH6

FTM2 FTM2_CH7

FTM2 FTM2_FLT0
FTM2 FTM2_FLT1

FTM2 FTM2_FLT2

FTM2 FTM2_FLT3

FTM2 FTM2_QD_PHA

FTM2 FTM2_QD_PHB

FTM3 FTM3_CH0

FTM3 FTM3_CH1

FTM3 FTM3_CH2

FTM3 FTM3_CH3

FTM3 FTM3_CH4

FTM3 FTM3_CH5

FTM3 FTM3_CH6

FTM3 FTM3_CH7

FTM3 FTM3_FLT0
FTM3 FTM3_FLT1

FTM3 FTM3_FLT2

FTM3 FTM3_FLT3

FTM4 FTM4_CH0

FTM4 FTM4_CH1

FTM4 FTM4_CH2

FTM4 FTM4_CH3

FTM4 FTM4_CH4

FTM4 FTM4_CH5

FTM4 FTM4_CH6

FTM4 FTM4_CH7

FTM4 FTM4_FLT0

FTM4 FTM4_FLT1

FTM5 FTM5_CH0
FTM5 FTM5_CH1

FTM5 FTM5_CH2

FTM5 FTM5_CH3

FTM5 FTM5_CH4

FTM5 FTM5_CH5

FTM5 FTM5_CH6

FTM5 FTM5_CH7

FTM5 FTM5_FLT0

FTM5 FTM5_FLT1

FTM6 FTM6_CH0

FTM6 FTM6_CH1

FTM6 FTM6_CH2

FTM6 FTM6_CH3

FTM6 FTM6_CH4

FTM6 FTM6_CH5
FTM6 FTM6_CH6

FTM6 FTM6_CH7

FTM6 FTM6_FLT0

FTM6 FTM6_FLT1

FTM7 FTM7_CH0

FTM7 FTM7_CH1

FTM7 FTM7_CH2

FTM7 FTM7_CH3

FTM7 FTM7_CH4

FTM7 FTM7_CH5

FTM7 FTM7_CH6

FTM7 FTM7_CH7

FTM7 FTM7_FLT0

FTM7 FTM7_FLT1

FXIO FXIO_D0
FXIO FXIO_D1

FXIO FXIO_D2

FXIO FXIO_D3

FXIO FXIO_D4

FXIO FXIO_D5

FXIO FXIO_D6

FXIO FXIO_D7

LPI2C0 LPI2C0_HREQ

LPI2C0 LPI2C0_SCL

LPI2C0 LPI2C0_SCLS

LPI2C0 LPI2C0_SDA
LPI2C0 LPI2C0_SDAS

LPI2C1 LPI2C1_HREQ

LPI2C1 LPI2C1_SCL

LPI2C1 LPI2C1_SCLS

LPI2C1 LPI2C1_SDA

LPI2C1 LPI2C1_SDAS

LPSPI0 LPSPI0_PCS0

LPSPI0 LPSPI0_PCS1

LPSPI0 LPSPI0_SCK

LPSPI0 LPSPI0_SIN

LPSPI0 LPSPI0_SOUT

LPSPI1 LPSPI1_PCS0
LPSPI1 LPSPI1_PCS1

LPSPI1 LPSPI1_SCK

LPSPI1 LPSPI1_SIN

LPSPI1 LPSPI1_SOUT

LPSPI2 LPSPI2_PCS0

LPSPI2 LPSPI2_PCS1

LPSPI2 LPSPI2_SCK

LPSPI2 LPSPI2_SIN

LPSPI2 LPSPI2_SOUT

LPTMR0 LPTMR0_ALT3

LPUART0 LPUART0_CTS

LPUART0 LPUART0_RX
LPUART0 LPUART0_TX

LPUART1 LPUART1_CTS

LPUART1 LPUART1_RX

LPUART1 LPUART1_TX

LPUART2 LPUART2_CTS

LPUART2 LPUART2_RX

LPUART2 LPUART2_TX
Priority SSS Source Instance Source Signal
1 0000_0011 IO_PAD PTC2
2 0000_0101 IO_PAD PTE4
3 0000_0101 IO_PAD PTB0
4 0000_0101 IO_PAD PTA28
5 - disable low
1 0000_0011 IO_PAD PTC6
2 0000_0011 IO_PAD PTA12
3 - disable low
1 0000_0011 IO_PAD PTC16
2 0000_0100 IO_PAD PTB12
3 0000_0011 IO_PAD PTE25
4 - disable low
1 0000_0100 IO_PAD PTB23
2 0000_0100 IO_PAD PTC14
3 - disable low
1 0000_0011 IO_PAD PTB22
2 0000_0100 IO_PAD PTC15
3 - disable low
1 0000_0101 IO_PAD PTC1
2 0000_0101 IO_PAD PTC0
3 - disable low
1 0000_0100 IO_PAD PTC0
2 0000_0100 IO_PAD PTC1
3 - disable low
1 0000_0100 IO_PAD PTA3
2 0000_0101 IO_PAD PTC4
3 0000_0100 IO_PAD PTA14
4 0000_0111 IO_PAD PTE5
5 - disable low
1 0000_0011 IO_PAD PTE0
2 0000_0011 IO_PAD PTA5
3 - disable low
1 0000_0010 IO_PAD PTB12
2 0000_0010 IO_PAD PTD15
3 0000_0010 IO_PAD PTC0
4 - disable low
1 0000_0010 IO_PAD PTC1
2 0000_0010 IO_PAD PTB13
3 0000_0010 IO_PAD PTD16
4 - disable low
1 0000_0010 IO_PAD PTD0
2 0000_0010 IO_PAD PTC2
3 0000_0010 IO_PAD PTB14
4 - disable low
1 0000_0010 IO_PAD PTB15
2 0000_0010 IO_PAD PTD1
3 0000_0010 IO_PAD PTC3
4 - disable low
1 0000_0010 IO_PAD PTB4
2 0000_0010 IO_PAD PTB16
3 - disable low
1 0000_0010 IO_PAD PTB5
2 0000_0010 IO_PAD PTB17
3 - disable low
1 0000_0010 IO_PAD PTE8
2 0000_0010 IO_PAD PTA17
3 - disable low
1 0000_0010 IO_PAD PTE9
2 0000_0010 IO_PAD PTE7
3 - disable low
1 0000_0010 IO_PAD PTA14
2 0000_0010 IO_PAD PTE3
3 - disable low
1 0000_0010 IO_PAD PTA6
2 0000_0010 IO_PAD PTE14
3 - disable low
1 0000_0010 IO_PAD PTA7
2 0000_0010 IO_PAD PTD17
3 - disable low
1 0000_0010 IO_PAD PTD4
2 0000_0010 IO_PAD PTE12
3 - disable low
1 0000_0010 IO_PAD PTB2
2 0000_0010 IO_PAD PTC4
3 - disable low
1 0000_0010 IO_PAD PTA1
2 0000_0010 IO_PAD PTB3
3 - disable low
1 0000_0010 IO_PAD PTC14
2 0000_0010 IO_PAD PTA15
3 - disable low
1 0000_0010 IO_PAD PTC15
2 0000_0010 IO_PAD PTA16
3 - disable low
1 0000_0110 IO_PAD PTD8
2 0000_0010 IO_PAD PTA10
3 - disable low
1 0000_0010 IO_PAD PTA11
2 0000_0110 IO_PAD PTD9
3 - disable low
1 0000_0010 IO_PAD PTA12
2 0000_0110 IO_PAD PTC0
3 - disable low
1 0000_0110 IO_PAD PTC1
2 0000_0010 IO_PAD PTA13
3 - disable low
1 0000_0110 IO_PAD PTA14
2 0000_0011 IO_PAD PTC8
3 - disable low
1 0000_0110 IO_PAD PTE1
2 0000_0011 IO_PAD PTC9
3 - disable low
1 0000_0010 IO_PAD PTC16
2 0000_0110 IO_PAD PTE0
3 - disable low
1 0000_0110 IO_PAD PTA9
2 0000_0010 IO_PAD PTC17
3 - disable low
1 0000_0101 IO_PAD PTA1
2 0000_0100 IO_PAD PTB3
3 0000_0110 IO_PAD PTC7
4 - disable low
1 0000_0100 IO_PAD PTB2
2 0000_0110 IO_PAD PTC4
3 0000_0110 IO_PAD PTC6
4 - disable low
1 0000_0100 IO_PAD PTD0
2 0000_0010 IO_PAD PTC5
3 0000_0010 IO_PAD PTD10
4 - disable low
1 0000_0100 IO_PAD PTD1
2 0000_0010 IO_PAD PTA0
3 0000_0010 IO_PAD PTD11
4 - disable low
1 0000_0010 IO_PAD PTD12
2 0000_0100 IO_PAD PTE4
3 - disable low
1 0000_0100 IO_PAD PTE5
2 0000_0010 IO_PAD PTD5
3 - disable low
1 0000_0010 IO_PAD PTD13
2 0000_0100 IO_PAD PTE10
3 - disable low
1 0000_0010 IO_PAD PTD14
2 0000_0100 IO_PAD PTE11
3 - disable low
1 0000_0100 IO_PAD PTE15
2 0000_0011 IO_PAD PTC12
3 - disable low
1 0000_0011 IO_PAD PTC13
2 0000_0100 IO_PAD PTE16
3 - disable low
1 0000_0100 IO_PAD PTE13
2 0000_0100 IO_PAD PTE3
3 - disable low
1 0000_0100 IO_PAD PTE14
2 0000_0100 IO_PAD PTD5
3 - disable low
1 0000_0100 IO_PAD PTD6
2 0000_0100 IO_PAD PTD8
3 - disable low
1 0000_0100 IO_PAD PTD7
2 0000_0100 IO_PAD PTD9
3 - disable low
1 0000_0011 IO_PAD PTE5
2 0000_0101 IO_PAD PTA0
3 0000_0011 IO_PAD PTD11
4 0000_0110 IO_PAD PTA13
5 - disable low
1 0000_0110 IO_PAD PTC5
2 0000_0011 IO_PAD PTD10
3 0000_0011 IO_PAD PTE4
4 0000_0110 IO_PAD PTA12
5 - disable low
1 0000_0010 IO_PAD PTB8
2 0000_0010 IO_PAD PTA2
3 - disable low
1 0000_0010 IO_PAD PTA3
2 0000_0010 IO_PAD PTB9
3 - disable low
1 0000_0100 IO_PAD PTC6
2 0000_0010 IO_PAD PTB10
3 - disable low
1 0000_0010 IO_PAD PTB11
2 0000_0100 IO_PAD PTC7
3 - disable low
1 0000_0010 IO_PAD PTD2
2 0000_0010 IO_PAD PTC10
3 - disable low
1 0000_0010 IO_PAD PTC11
2 0000_0010 IO_PAD PTD3
3 - disable low
1 0000_0100 IO_PAD PTE2
2 0000_0010 IO_PAD PTC12
3 - disable low
1 0000_0010 IO_PAD PTC13
2 0000_0100 IO_PAD PTE6
3 - disable low
1 0000_0011 IO_PAD PTE7
2 0000_0011 IO_PAD PTA17
3 - disable low
1 0000_0011 IO_PAD PTB13
2 0000_0011 IO_PAD PTA14
3 - disable low
1 0000_0011 IO_PAD PTB12
2 0000_0101 IO_PAD PTA9
3 - disable low
1 0000_0011 IO_PAD PTD4
2 0000_0101 IO_PAD PTA8
3 - disable low
1 0000_0010 IO_PAD PTA18
2 0000_0010 IO_PAD PTE20
3 0000_0010 IO_PAD PTC24
4 - disable low
1 0000_0010 IO_PAD PTA19
2 0000_0010 IO_PAD PTC25
3 0000_0010 IO_PAD PTE21
4 - disable low
1 0000_0011 IO_PAD PTC11
2 0000_0010 IO_PAD PTA20
3 0000_0010 IO_PAD PTE22
4 - disable low
1 0000_0010 IO_PAD PTA21
2 0000_0010 IO_PAD PTE23
3 0000_0010 IO_PAD PTC26
4 - disable low
1 0000_0010 IO_PAD PTA22
2 0000_0010 IO_PAD PTC27
3 0000_0010 IO_PAD PTE24
4 - disable low
1 0000_0110 IO_PAD PTB1
2 0000_0010 IO_PAD PTE25
3 0000_0010 IO_PAD PTE13
4 - disable low
1 0000_0110 IO_PAD PTB0
2 0000_0010 IO_PAD PTA23
3 0000_0010 IO_PAD PTE26
4 - disable low
1 0000_0010 IO_PAD PTA24
2 0000_0010 IO_PAD PTE27
3 0000_0010 IO_PAD PTC28
4 - disable low
1 0000_0101 IO_PAD PTE16
2 0000_0111 IO_PAD PTA9
3 - disable low
1 0000_0101 IO_PAD PTE15
2 0000_0110 IO_PAD PTA8
3 - disable low
1 0000_0100 IO_PAD PTC9
2 0000_0010 IO_PAD PTA25
3 - disable low
1 0000_0100 IO_PAD PTC8
2 0000_0010 IO_PAD PTA26
3 - disable low
1 0000_0010 IO_PAD PTA27
2 0000_0010 IO_PAD PTC29
3 - disable low
1 0000_0011 IO_PAD PTA7
2 0000_0010 IO_PAD PTA28
3 - disable low
1 0000_0010 IO_PAD PTA29
2 0000_0010 IO_PAD PTC30
3 - disable low
1 0000_0100 IO_PAD PTA6
2 0000_0010 IO_PAD PTA30
3 - disable low
1 0000_0010 IO_PAD PTC31
2 0000_0010 IO_PAD PTA31
3 - disable low
1 0000_0010 IO_PAD PTB18
2 0000_0010 IO_PAD PTB19
3 0000_0010 IO_PAD PTD18
4 - disable low
1 0000_0100 IO_PAD PTE12
2 0000_0101 IO_PAD PTA17
3 - disable low
1 0000_0100 IO_PAD PTD17
2 0000_0100 IO_PAD PTB17
3 - disable low
1 0000_0101 IO_PAD PTA18
2 0000_0010 IO_PAD PTB20
3 0000_0010 IO_PAD PTD19
4 - disable low
1 0000_0010 IO_PAD PTB21
2 0000_0010 IO_PAD PTD20
3 - disable low
1 0000_0010 IO_PAD PTB22
2 0000_0010 IO_PAD PTD21
3 - disable low
1 0000_0010 IO_PAD PTB23
2 0000_0010 IO_PAD PTD22
3 - disable low
1 0000_0010 IO_PAD PTB24
2 0000_0010 IO_PAD PTD23
3 - disable low
1 0000_0010 IO_PAD PTB25
2 0000_0010 IO_PAD PTD24
3 - disable low
1 0000_0010 IO_PAD PTB26
2 0000_0010 IO_PAD PTD25
3 - disable low
1 0000_0010 IO_PAD PTB27
2 0000_0010 IO_PAD PTD26
3 - disable low
1 0000_0101 IO_PAD PTD31
2 0000_0101 IO_PAD PTB13
3 - disable low
1 0000_0011 IO_PAD PTD30
2 0000_0101 IO_PAD PTB12
3 - disable low
1 0000_0010 IO_PAD PTD27
2 0000_0010 IO_PAD PTB28
3 - disable low
1 0000_0010 IO_PAD PTD28
2 0000_0010 IO_PAD PTB29
3 - disable low
1 0000_0010 IO_PAD PTD29
2 0000_0010 IO_PAD PTB30
3 - disable low
1 0000_0010 IO_PAD PTD30
2 0000_0010 IO_PAD PTB31
3 - disable low
1 0000_0010 IO_PAD PTD31
2 0000_0010 IO_PAD PTC18
3 - disable low
1 0000_0010 IO_PAD PTE17
2 0000_0010 IO_PAD PTC19
3 - disable low
1 0000_0010 IO_PAD PTE18
2 0000_0010 IO_PAD PTC20
3 - disable low
1 0000_0010 IO_PAD PTE19
2 0000_0010 IO_PAD PTC21
3 - disable low
1 0000_0101 IO_PAD PTA15
2 0000_0100 IO_PAD PTC21
3 - disable low
1 0000_0011 IO_PAD PTE6
2 0000_0010 IO_PAD PTC22
3 - disable low
1 0000_0110 IO_PAD PTD0
2 0000_0100 IO_PAD PTA10
3 0000_0011 IO_PAD PTA21
4 0000_0011 IO_PAD PTC30
5 0000_0011 IO_PAD PTD9
6 - disable low
1 0000_0110 IO_PAD PTD1
2 0000_0100 IO_PAD PTA11
3 0000_0011 IO_PAD PTA22
4 0000_0011 IO_PAD PTC31
5 0000_0101 IO_PAD PTD8
6 - disable low
1 0000_0110 IO_PAD PTE15
2 0000_0100 IO_PAD PTA0
3 0000_0011 IO_PAD PTA23
4 0000_0011 IO_PAD PTD18
5 - disable low
1 0000_0100 IO_PAD PTA1
2 0000_0110 IO_PAD PTE16
3 0000_0011 IO_PAD PTA24
4 0000_0011 IO_PAD PTD19
5 - disable low
1 0000_0100 IO_PAD PTD2
2 0000_0110 IO_PAD PTE10
3 0000_0101 IO_PAD PTA2
4 0000_0011 IO_PAD PTE18
5 - disable low
1 0000_0110 IO_PAD PTE11
2 0000_0100 IO_PAD PTD3
3 0000_0101 IO_PAD PTA3
4 0000_0011 IO_PAD PTE17
5 - disable low
1 0000_0110 IO_PAD PTE4
2 0000_0100 IO_PAD PTA8
3 0000_0101 IO_PAD PTD2
4 0000_0011 IO_PAD PTD31
5 - disable low
1 0000_0110 IO_PAD PTE5
2 0000_0100 IO_PAD PTA9
3 0000_0101 IO_PAD PTD3
4 0000_0011 IO_PAD PTD26
5 - disable low
1 0000_0011 IO_PAD PTB11
2 0000_0011 IO_PAD PTE1
3 - disable low
1 0000_0011 IO_PAD PTA3
2 0000_0010 IO_PAD PTB7
3 - disable low
1 0000_0011 IO_PAD PTB9
2 0000_0011 IO_PAD PTA0
3 - disable low
1 0000_0010 IO_PAD PTB6
2 0000_0011 IO_PAD PTA2
3 - disable low
1 0000_0011 IO_PAD PTA1
2 0000_0011 IO_PAD PTB10
3 - disable low
1 0000_0011 IO_PAD PTD12
2 0000_0100 IO_PAD PTC5
3 - disable low
1 0000_0100 IO_PAD PTE1
2 0000_0010 IO_PAD PTD9
3 0000_0100 IO_PAD PTD19
4 - disable low
1 0000_0100 IO_PAD PTA13
2 0000_0100 IO_PAD PTC17
3 0000_0100 IO_PAD PTD18
4 - disable low
1 0000_0010 IO_PAD PTD8
2 0000_0100 IO_PAD PTE0
3 0000_0100 IO_PAD PTC31
4 - disable low
1 0000_0100 IO_PAD PTC16
2 0000_0100 IO_PAD PTA12
3 0000_0100 IO_PAD PTC30
4 - disable low
1 0000_0011 IO_PAD PTB0
2 0000_0100 IO_PAD PTB5
3 0000_0100 IO_PAD PTA26
4 - disable low
1 0000_0011 IO_PAD PTB5
2 0000_0100 IO_PAD PTA31
3 - disable low
1 0000_0011 IO_PAD PTB2
2 0000_0010 IO_PAD PTE0
3 0000_0100 IO_PAD PTD15
4 0000_0010 IO_PAD PTC23
5 - disable low
1 0000_0010 IO_PAD PTE1
2 0000_0011 IO_PAD PTB3
3 0000_0100 IO_PAD PTD16
4 - disable low
1 0000_0010 IO_PAD PTE2
2 0000_0011 IO_PAD PTB4
3 0000_0011 IO_PAD PTB1
4 0000_0100 IO_PAD PTA30
5 - disable low
1 0000_0011 IO_PAD PTD3
2 0000_0101 IO_PAD PTE1
3 0000_0100 IO_PAD PTA21
4 0000_0011 IO_PAD PTA26
5 - disable low
1 0000_0011 IO_PAD PTA6
2 0000_0100 IO_PAD PTB18
3 0000_0100 IO_PAD PTA22
4 - disable low
1 0000_0011 IO_PAD PTD0
2 0000_0011 IO_PAD PTB14
3 0000_0100 IO_PAD PTA19
4 0000_0011 IO_PAD PTA28
5 - disable low
1 0000_0011 IO_PAD PTB15
2 0000_0011 IO_PAD PTD1
3 0000_0100 IO_PAD PTA20
4 0000_0101 IO_PAD PTA29
5 - disable low
1 0000_0011 IO_PAD PTD2
2 0000_0011 IO_PAD PTB16
3 0000_0101 IO_PAD PTE0
4 0000_0100 IO_PAD PTA18
5 0000_0011 IO_PAD PTA27
6 - disable low
1 0000_0011 IO_PAD PTA9
2 0000_0011 IO_PAD PTC14
3 0000_0010 IO_PAD PTE11
4 0000_0101 IO_PAD PTB25
5 - disable low
1 0000_0011 IO_PAD PTE10
2 0000_0101 IO_PAD PTC19
3 - disable low
1 0000_0011 IO_PAD PTE15
2 0000_0011 IO_PAD PTC15
3 0000_0101 IO_PAD PTB29
4 - disable low
1 0000_0011 IO_PAD PTE16
2 0000_0011 IO_PAD PTC0
3 0000_0101 IO_PAD PTB28
4 - disable low
1 0000_0011 IO_PAD PTA8
2 0000_0011 IO_PAD PTC1
3 0000_0101 IO_PAD PTB27
4 - disable low
1 0000_0011 IO_PAD PTE2
2 0000_0100 IO_PAD PTB0
3 - disable low
1 0000_0110 IO_PAD PTC8
2 0000_0110 IO_PAD PTA0
3 - disable low
1 0000_0110 IO_PAD PTA2
2 0000_0010 IO_PAD PTB0
3 0000_0100 IO_PAD PTC2
4 0000_0100 IO_PAD PTA28
5 - disable low
1 0000_0110 IO_PAD PTA3
2 0000_0010 IO_PAD PTB1
3 0000_0100 IO_PAD PTC3
4 0000_0100 IO_PAD PTA27
5 - disable low
1 0000_0110 IO_PAD PTA6
2 0000_0110 IO_PAD PTE2
3 0000_0010 IO_PAD PTE15
4 - disable low
1 0000_0010 IO_PAD PTC6
2 0000_0010 IO_PAD PTC8
3 0000_0011 IO_PAD PTD13
4 0000_0011 IO_PAD PTB23
5 0000_0011 IO_PAD PTA19
6 - disable low
1 0000_0010 IO_PAD PTC9
2 0000_0010 IO_PAD PTC7
3 0000_0011 IO_PAD PTD14
4 0000_0011 IO_PAD PTA18
5 0000_0101 IO_PAD PTB22
6 - disable low
1 0000_0011 IO_PAD PTE9
2 0000_0110 IO_PAD PTD11
3 0000_0100 IO_PAD PTC12
4 - disable low
1 0000_0010 IO_PAD PTD6
2 0000_0011 IO_PAD PTD17
3 0000_0010 IO_PAD PTA8
4 0000_0011 IO_PAD PTA30
5 - disable low
1 0000_0010 IO_PAD PTD7
2 0000_0011 IO_PAD PTE12
3 0000_0010 IO_PAD PTA9
4 0000_0100 IO_PAD PTA29
5 - disable low
S32K148_BGA S32K148_144lqfp S32K148_176lqfp S32K148_100lqfp
J3 43 51 30
D1 9 15 9
J10 78 97 54
24 31

C7 118 144 81
A5 134 162 90

J7 57 65 44
E9 98 119 68
133 161

60 68
G6 61 70 46

58 66
H6 59 67 45

H5 52 60 39
J5 53 61 40

J5 53 61 40
H5 52 60 39

D8 104 125 72
D5 140 169 96
C6 127 155 88
D2 8 14 8

B4 138 166 94
C4 141 170 97

E9 98 119 68
G3 29 36 22
J5 53 61 40

H5 52 60 39
E8 97 118 67
G2 28 35 21

C2 4 8 4
J3 43 51 30
F10 96 116 66

F9 95 115 65
B1 3 7 3
J2 42 50 29
K2 41 49 28
F8 94 114 64

K1 40 48 27
E7 93 112 63

H3 39 47 26
F7 92 111 62

H1 30 37 23
G10 87 106 59

C6 127 155 88
F2 21 28 18

G9 85 104 58
F3 20 27 17

H10 83 102 57
G1 25 32 20

E10 100 121 69

F4 23 30 19

K8 68 78 48
D5 140 169 96

B9 113 138 78
H7 63 73 47

G6 61 70 46
B7 120 148 83

H6 59 67 45
A8 119 146 82

J6 55 63 42
C5 136 164 92

B5 135 163 91
K6 54 62 41

A5 134 162 90
J5 53 61 40

H5 52 60 39
A6 130 158 89
C6 127 155 88
G8 81 100 56

A4 137 165 93
H9 80 99 55

J7 57 65 44
B4 138 166 94

A3 143 175 99
K7 56 64 43

B9 113 138 78
H7 63 73 47
B8 117 143 80

K8 68 78 48
D5 140 169 96
C7 118 144 81

C2 4 8 4
D6 139 168 95
K5 49 57 36

B1 3 7 3
A9 115 140 79
G5 48 56 35

H4 47 55 34
D1 9 15 9

D2 8 14 8
K4 46 54 33

J1 35 42 25
C1 6 11 6

H2 34 41 24
A1 5 10 5

B2 2 5 2
K9 71 84 50

J8 70 81 49
A2 1 4 1

D3 7 12 7
F2 21 28 18

F3 20 27 17
K4 46 54 33

J4 45 53 32
J6 55 63 42

K3 44 52 31
K6 54 62 41

D2 8 14 8
A9 115 140 79
G5 48 56 35
A6 130 158 89

D6 139 168 95
K5 49 57 36
D1 9 15 9
A5 134 162 90

A10 111 136 77

C10 105 126 73

D8 104 125 72
C8 109 133 76

C7 118 144 81
B10 108 131 75

C9 107 128 74
B8 117 143 80

D9 102 123 71
K10 75 94 52

H8 74 92 51
D10 101 122 70

B6 122 150 85
K9 71 84 50

J8 70 81 49
A7 121 149 84

G10 87 106 59
F7 92 111 62
E8 97 118 67
C6 127 155 88

E9 98 119 68
A3 143 175 99

E10 100 121 69

B3 144 176 100

1
126 154
90

2
91
128 156

H8 74 92 51
3
129 157

6
131 159
93

9
76 95
132 160

J9 77 96 53
133 161
D3 7 12 7

J10 78 97 54
13
167

16
174
79 98

A2 1 4 1
A3 143 175 99

B2 2 5 2
B3 144 176 100

H9 80 99 55
 10 17

G8 81 100 56
19 26

22 29
82 101

H10 83 102 57
24 31

26 33
84 103

G9 85 104 58
27 34

86 105
33 40

36 43
44
88 107

F4 23 30 19
F7 92 111 62

G1 25 32 20
E7 93 112 63

1
37 45
89 108

38 46
113

58 66
117

60 68
99 120

69
103 124

62 71
106 127
 72
132

64 74
134

142
E8 97 118 67

116 141
E9 98 119 68

110 135
65 75

112 137
69 79

114 139
80

116 141
82

142
83

145
72 85

147
86

125 153
87

B7 120 148 83
87

A7 121 149 84
88

C2 4 8 4
C5 136 164 92
6
84 103
K6 54 62 41
B1 3 7 3
B5 135 163 91
9
86 105
J6 55 63 42

B2 2 5 2
A9 115 140 79
13
88 107

B9 113 138 78
A2 1 4 1
16
89 108

D9 102 123 71
C1 6 11 6
C10 105 126 73
147

A1 5 10 5
D10 101 122 70
D8 104 125 72
145

D1 9 15 9
B3 144 176 100
D9 102 123 71
142

D2 8 14 8
A3 143 175 99
D10 101 122 70
134

C9 107 128 74
A4 137 165 93

D8 104 125 72
E1 17 24 15

C8 109 133 76
A9 115 140 79

F1 18 25 16
C10 105 126 73
B9 113 138 78
B10 108 131 75

H4 47 55 34
D6 139 168 95

A4 137 165 93
K6 54 62 41
89 108

A6 130 158 89
K7 56 64 43
88 107

J6 55 63 42
B4 138 166 94
86 105

J7 57 65 44
A5 134 162 90
84 103

J10 78 97 54
K1 40 48 27
19 26

K1 40 48 27
33 40

K8 68 78 48
B4 138 166 94
G3 29 36 22
73 89

A4 137 165 93
H7 63 73 47
G2 28 35 21

B6 122 150 85
K2 41 49 28
J9 77 96 53
27 34

D10 101 122 70

A4 137 165 93
6
19 26
G9 85 104 58
36 43
9

C2 4 8 4
F10 96 116 66
2
24 31

F9 95 115 65
B1 3 7 3
3
26 33

D9 102 123 71
F8 94 114 64
B4 138 166 94
1
22 29

A3 143 175 99
G6 61 70 46
A1 5 10 5
62 71

C1 6 11 6
72 85

B2 2 5 2
H6 59 67 45
69 79

A2 1 4 1
J5 53 61 40
65 75

B3 144 176 100

H5 52 60 39
64 74

B6 122 150 85
J10 78 97 54

G8 81 100 56
A9 115 140 79

C10 105 126 73

J10 78 97 54
J3 43 51 30
24 31

D8 104 125 72
J9 77 96 53
J2 42 50 29
22 29

G9 85 104 58
B6 122 150 85
B2 2 5 2

C7 118 144 81
G8 81 100 56
J1 35 42 25
60 68
2

H9 80 99 55
B8 117 143 80
H2 34 41 24
1
58 66

H1 30 37 23
G5 48 56 35
K9 71 84 50

J4 45 53 32
G1 25 32 20
B3 144 176 100
27 34

K3 44 52 31
F4 23 30 19
A3 143 175 99
26 33
 S32K148_144lqfp

S32K148_176lqfp

S32K148_100lqfp
S32K148_BGA
Package Net Description ChipTopPort Function
VDD Supply Voltage E5 11 18 10 VDD
E6 32 39 38
F5 51 59 61
F6 67 77 87
91 110
124 129
152
172
VDDA Analogue supply voltage E4 13 20 11 VDDA
VREFH ADC Reference Supply high E3 14 21 12 VREFH
VREFL ADC Reference Supply low E2 15 22 13 VREFL
VSS Supply Ground D4 12 19 14 VSS
D7 16 23 37
G4 31 38 60
G7 50 58 86
66 76
90 109
123 130
151
171
S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA
11 13 20 E4
12 14 21 E3
13 15 22 E2
29 42 50 J2
30 43 51 J3
39 52 60 H5
40 53 61 J5
43 56 64 K7
44 57 65 J7
45 59 67 H6
46 61 70 G6
47 63 73 H7
48 68 78 K8
53 77 96 J9
54 78 97 J10
57 83 102 H10
58 85 104 G9
66 96 116 F10
67 97 118 E8
78 113 138 B9
79 115 140 A9
36 43
37 45
38 46
58 66
60 68
62 71
64 74
65 75
69 79
72 85
73 89
76 95
79 98
82 101
84 103
86 105

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

11 13 20 E4
12 14 21 E3
13 15 22 E2
53 77 96 J9
54 78 97 J10
64 94 114 F8
65 95 115 F9
66 96 116 F10
67 97 118 E8
 68 98 119 E9
69 100 121 E10
70 101 122 D10
71 102 123 D9
72 104 125 D8
73 105 126 C10
80 117 143 B8
81 118 144 C7
82 119 146 A8
83 120 148 B7
84 121 149 A7
85 122 150 B6
88 107
89 108
99 120
103 124
106 127
110 135
112 137
114 139
116 141
125 153
126 154
128 156
129 157
131 159
132 160
133 161

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

8 8 14 D2
9 9 15 D1
29 42 50 J2
30 43 51 J3
53 77 96 J9
54 78 97 J10
22 29
24 31

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

80 117 143 B8
81 118 144 C7
89 130 158 A6
90 134 162 A5
S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA
43 56 64 K7
44 57 65 J7
67 97 118 E8
68 98 119 E9
132 160
133 161

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

18 21 28 F2
21 28 35 G2
26 39 47 H3
29 42 50 J2
30 43 51 J3
31 44 52 K3
32 45 53 J4
78 113 138 B9
79 115 140 A9
91 135 163 B5
96 140 169 D5
98 142 173 C3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

8 8 14 D2
9 9 15 D1
62 92 111 F7
72 104 125 D8
73 105 126 C10
88 127 155 C6
96 140 169 D5
98 142 173 C3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
3 3 7 B1
4 4 8 C2
5 5 10 A1
6 6 11 C1
8 8 14 D2
9 9 15 D1
41 54 62 K6
42 55 63 J6
70 101 122 D10
71 102 123 D9
 72 104 125 D8
73 105 126 C10
78 113 138 B9
79 115 140 A9
91 135 163 B5
92 136 164 C5
99 143 175 A3
100 144 176 B3
6
9
13
16
84 103
86 105
88 107
89 108
134
142
145
147

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

92 136 164 C5
95 139 168 D6
96 140 169 D5
98 142 173 C3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

15 17 24 E1
16 18 25 F1
72 104 125 D8
73 105 126 C10
74 107 128 C9
75 108 131 B10
76 109 133 C8
78 113 138 B9
79 115 140 A9
93 137 165 A4

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

34 47 55 H4
41 54 62 K6
42 55 63 J6
43 56 64 K7
44 57 65 J7
 89 130 158 A6
90 134 162 A5
93 137 165 A4
94 138 166 B4
95 139 168 D6
84 103
86 105
88 107
89 108

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

5 5 10 A1
33 46 54 K4
54 78 97 J10
85 122 150 B6

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

29 42 50 J2
30 43 51 J3
53 77 96 J9
54 78 97 J10
55 80 99 H9
56 81 100 G8
72 104 125 D8
73 105 126 C10
78 113 138 B9
79 115 140 A9
22 29
24 31

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
24 34 41 H2
25 35 42 J1
55 80 99 H9
56 81 100 G8
57 83 102 H10
58 85 104 G9
80 117 143 B8
81 118 144 C7
84 121 149 A7
85 122 150 B6
1
2
 58 66
60 68

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

18 21 28 F2
19 23 30 F4
20 25 32 G1
23 30 37 H1
31 44 52 K3
32 45 53 J4
34 47 55 H4
35 48 56 G5
49 70 81 J8
50 71 84 K9
99 143 175 A3
100 144 176 B3
26 33
27 34

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

15 17 24 E1
16 18 25 F1

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

10 11 39 E5
14 16 38 D4
37 50 76 G4
38 51 77 F5
60 90 130 G7
61 91 129 F6
86 123 151 D7
87 124 152 E6
31 23
66 19
32 18
67 59
12 58
110
109
172
171

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

 57 83 102 H10
58 85 104 G9
62 92 111 F7
72 104 125 D8
73 105 126 C10
78 113 138 B9
79 115 140 A9
82 119 146 A8
83 120 148 B7
88 127 155 C6
89 130 158 A6
90 134 162 A5
91 135 163 B5
92 136 164 C5
97 141 170 C4
98 142 173 C3
99 143 175 A3
100 144 176 B3
1
2
3
6
9
13
16
10 17
19 26
22 29
24 31
26 33
27 34
33 40

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

15 17 24 E1
16 18 25 F1
27 40 48 K1
28 41 49 K2
47 63 73 H7
48 68 78 K8
53 77 96 J9
54 78 97 J10
63 93 112 E7
64 94 114 F8
65 95 115 F9
66 96 116 F10
67 97 118 E8
68 98 119 E9
74 107 128 C9
 75 108 131 B10
76 109 133 C8
77 111 136 A10
36 43
44
37 45
38 46
58 66
60 68
69
62 71
72
64 74
65 75
69 79
80
82

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

29 42 50 J2
30 43 51 J3
39 52 60 H5
40 53 61 J5
43 56 64 K7
44 57 65 J7
45 59 67 H6
46 61 70 G6
49 70 81 J8
50 71 84 K9
51 74 92 H8
52 75 94 K10
55 80 99 H9
56 81 100 G8
80 117 143 B8
81 118 144 C7
95 139 168 D6
96 140 169 D5
83
72 85
86
87
88
73 89
90
91
93
76 95
79 98
82 101
 84 103
86 105

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

3 3 7 B1
4 4 8 C2
20 25 32 G1
21 28 35 G2
22 29 36 G3
24 34 41 H2
25 35 42 J1
31 44 52 K3
32 45 53 J4
33 46 54 K4
34 47 55 H4
35 48 56 G5
36 49 57 K5
41 54 62 K6
42 55 63 J6
69 100 121 E10
70 101 122 D10
71 102 123 D9
88 107
89 108
113
117
99 120
103 124
106 127
132
134
110 135
112 137
114 139
116 141
142

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
5 5 10 A1
6 6 11 C1
7 7 12 D3
8 8 14 D2
9 9 15 D1
17 20 27 F3
18 21 28 F2
 19 23 30 F4
23 30 37 H1
26 39 47 H3
59 87 106 G10
84 121 149 A7
85 122 150 B6
93 137 165 A4
94 138 166 B4
145
147
125 153
126 154
128 156
129 157
131 159
132 160
133 161
167
174

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

25 35 42 J1
57 83 102 H10
95 139 168 D6
96 140 169 D5

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

96 140 169 D5
98 142 173 C3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

6 6 11 C1
24 34 41 H2
27 40 48 K1
36 49 57 K5
70 101 122 D10
97 141 170 C4

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

21 28 35 G2
22 29 36 G3
27 40 48 K1
28 41 49 K2
 47 63 73 H7
48 68 78 K8
53 77 96 J9
54 78 97 J10
83 120 148 B7
84 121 149 A7
85 122 150 B6
93 137 165 A4
94 138 166 B4
19 26
27 34
33 40
73 89

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

3 3 7 B1
4 4 8 C2
58 85 104 G9
63 93 112 E7
64 94 114 F8
65 95 115 F9
66 96 116 F10
70 101 122 D10
71 102 123 D9
82 119 146 A8
93 137 165 A4
94 138 166 B4
1
2
3
6
9
19 26
22 29
24 31
26 33
36 43

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
5 5 10 A1
6 6 11 C1
7 7 12 D3
39 52 60 H5
40 53 61 J5
45 59 67 H6
 46 61 70 G6
83 120 148 B7
99 143 175 A3
100 144 176 B3
62 71
64 74
65 75
69 79
72 85

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

3 3 7 B1
4 4 8 C2
17 20 27 F3
18 21 28 F2
19 23 30 F4
20 25 32 G1
21 28 35 G2
22 29 36 G3
23 30 37 H1
26 39 47 H3
27 40 48 K1
28 41 49 K2
29 42 50 J2
30 43 51 J3
39 52 60 H5
40 53 61 J5
57 83 102 H10
58 85 104 G9
59 87 106 G10
62 92 111 F7
63 93 112 E7
64 94 114 F8
65 95 115 F9
66 96 116 F10
67 97 118 E8
68 98 119 E9
69 100 121 E10
88 127 155 C6

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

39 52 60 H5
40 53 61 J5
41 54 62 K6
42 55 63 J6
43 56 64 K7
44 57 65 J7
 45 59 67 H6
46 61 70 G6
47 63 73 H7
48 68 78 K8
55 80 99 H9
56 81 100 G8
78 113 138 B9
80 117 143 B8
81 118 144 C7
82 119 146 A8
83 120 148 B7
88 127 155 C6
89 130 158 A6
90 134 162 A5
91 135 163 B5
92 136 164 C5
93 137 165 A4
94 138 166 B4
96 140 169 D5
99 143 175 A3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
3 3 7 B1
4 4 8 C2
5 5 10 A1
6 6 11 C1
7 7 12 D3
8 8 14 D2
9 9 15 D1
17 20 27 F3
18 21 28 F2
24 34 41 H2
25 35 42 J1
31 44 52 K3
32 45 53 J4
33 46 54 K4
34 47 55 H4
35 48 56 G5
36 49 57 K5
41 54 62 K6
42 55 63 J6
49 70 81 J8
50 71 84 K9
79 115 140 A9
89 130 158 A6
90 134 162 A5
95 139 168 D6
S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA
49 70 81 J8
50 71 84 K9
51 74 92 H8
52 75 94 K10
59 87 106 G10
62 92 111 F7
67 97 118 E8
68 98 119 E9
69 100 121 E10
70 101 122 D10
71 102 123 D9
72 104 125 D8
73 105 126 C10
74 107 128 C9
75 108 131 B10
76 109 133 C8
77 111 136 A10
80 117 143 B8
81 118 144 C7
84 121 149 A7
85 122 150 B6
88 127 155 C6
99 143 175 A3
100 144 176 B3

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
3 3 7 B1
4 4 8 C2
5 5 10 A1
6 6 11 C1
18 21 28 F2
27 40 48 K1
28 41 49 K2
33 46 54 K4
45 59 67 H6
46 61 70 G6
47 63 73 H7
48 68 78 K8
51 74 92 H8
52 75 94 K10
70 101 122 D10
71 102 123 D9
78 113 138 B9
 79 115 140 A9

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

92 136 164 C5

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

8 8 14 D2
53 77 96 J9
94 138 166 B4
97 141 170 C4

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

22 29 36 G3
23 30 37 H1
24 34 41 H2
25 35 42 J1
26 39 47 H3
27 40 48 K1
28 41 49 K2
29 42 50 J2
30 43 51 J3
31 44 52 K3
32 45 53 J4
33 46 54 K4
34 47 55 H4
35 48 56 G5
36 49 57 K5
39 52 60 H5
40 53 61 J5
41 54 62 K6
42 55 63 J6
43 56 64 K7
44 57 65 J7
45 59 67 H6
46 61 70 G6
58 66
60 68

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

1 1 4 A2
2 2 5 B2
7 7 12 D3
51 74 92 H8
 53 77 96 J9
54 78 97 J10
99 143 175 A3
100 144 176 B3
1
2
3
6
9
13
16
90
91
93
76 95
79 98
126 154
128 156
129 157
131 159
132 160
133 161
167
174

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

19 23 30 F4
20 25 32 G1
55 80 99 H9
56 81 100 G8
57 83 102 H10
58 85 104 G9
62 92 111 F7
63 93 112 E7
10 17
19 26
22 29
24 31
26 33
27 34
33 40
36 43
44
82 101
84 103
86 105
88 107
 S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA
67 97 118 E8
68 98 119 E9
1
37 45
38 46
58 66
60 68
69
62 71
72
64 74
89 108
113
117
99 120
103 124
106 127
132
134
116 141
142

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

83 120 148 B7
84 121 149 A7
65 75
69 79
80
82
83
72 85
86
87
88
110 135
112 137
114 139
116 141
142
145
147
125 153

NOTE: QSPI NOT AVAILABLE IN 100 LQFP PACKAGE

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA
28 41 49 K2
 29 42 50 J2
30 43 51 J3
31 44 52 K3
32 45 53 J4
33 46 54 K4
34 47 55 H4
35 48 56 G5
36 49 57 K5
39 52 60 H5
40 53 61 J5
41 54 62 K6
42 55 63 J6
43 56 64 K7
44 57 65 J7
45 59 67 H6

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

3 3 7 B1
88 127 155 C6
89 130 158 A6
90 134 162 A5
91 135 163 B5
93 137 165 A4
94 138 166 B4

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

4 4 8 C2
9 9 15 D1
21 28 35 G2
22 29 36 G3
30 43 51 J3
31 44 52 K3
34 47 55 H4
35 48 56 G5
36 49 57 K5

S32K148_100lqfp S32K148_144lqfp S32K148_176lqfp S32K148_BGA

75 108 131 B10
76 109 133 C8
77 111 136 A10
85 122 150 B6
 ADC0
VDDA -
VREFH -
VREFL -
ADC0_SE11 I
ADC0_SE10 I
ADC0_SE9 I
ADC0_SE8 I
ADC0_SE15 I
ADC0_SE14 I
ADC0_SE13 I
ADC0_SE12 I
ADC0_SE7 I
ADC0_SE6 I
ADC0_SE5 I
ADC0_SE4 I
ADC0_SE3 I
ADC0_SE2 I
ADC0_SE9 I
ADC0_SE8 I
ADC0_SE1 I
ADC0_SE0 I
ADC0_SE16 I
ADC0_SE17 I
ADC0_SE18 I
ADC0_SE19 I
ADC0_SE20 I
ADC0_SE21 I
ADC0_SE22 I
ADC0_SE23 I
ADC0_SE24 I
ADC0_SE25 I
ADC0_SE26 I
ADC0_SE27 I
ADC0_SE28 I
ADC0_SE29 I
ADC0_SE30 I
ADC0_SE31 I

ADC1
VDDA -
VREFH -
VREFL -
ADC1_SE15 I
ADC1_SE14 I
ADC1_SE15 I
ADC1_SE14 I
ADC1_SE9 I
ADC1_SE8 I
ADC1_SE7 I
ADC1_SE6 I
ADC1_SE3 I
ADC1_SE2 I
ADC1_SE1 I
ADC1_SE0 I
ADC1_SE5 I
ADC1_SE4 I
ADC1_SE13 I
ADC1_SE12 I
ADC1_SE11 I
ADC1_SE10 I
ADC1_SE16 I
ADC1_SE17 I
ADC1_SE18 I
ADC1_SE19 I
ADC1_SE20 I
ADC1_SE21 I
ADC1_SE22 I
ADC1_SE23 I
ADC1_SE24 I
ADC1_SE25 I
ADC1_SE26 I
ADC1_SE27 I
ADC1_SE28 I
ADC1_SE29 I
ADC1_SE30 I
ADC1_SE31 I

CAN0
CAN0_TX O
CAN0_RX I
CAN0_TX O
CAN0_RX I
CAN0_TX O
CAN0_RX I
CAN0_TX O
CAN0_RX I

CAN1
CAN1_TX O
CAN1_RX I
CAN1_TX O
CAN1_RX I
 CAN2
CAN2_TX O
CAN2_RX I
CAN2_TX O
CAN2_RX I
CAN2_TX O
CAN2_RX I

CMP0
CMP0_OUT O
CMP0_RRT O
CMP0_IN3 I
CMP0_IN4 I
CMP0_IN5 I
CMP0_IN6 I
CMP0_IN7 I
CMP0_IN1 I
CMP0_IN0 I
CMP0_RRT O
CMP0_IN2 I
CMP0_OUT O

EWM
EWM_IN I
EWM_OUT_b O
EWM_OUT_b O
EWM_IN I
EWM_OUT_b O
EWM_IN I
EWM_IN I
EWM_OUT_b O

FXIO
FXIO_D3 I/O
FXIO_D2 I/O
FXIO_D1 I/O
FXIO_D0 I/O
FXIO_D5 I/O
FXIO_D4 I/O
FXIO_D7 I/O
FXIO_D6 I/O
FXIO_D0 I/O
FXIO_D1
FXIO_D5 I/O
FXIO_D7
FXIO_D4 I/O
FXIO_D6 I/O
 FXIO_D5 I/O
FXIO_D4 I/O
FXIO_D3 I/O
FXIO_D2 I/O
FXIO_D1 I/O
FXIO_D0 I/O
FXIO_D7 I/O
FXIO_D6 I/O
FXIO_D0 I/O
FXIO_D1 I/O
FXIO_D2 I/O
FXIO_D3 I/O
FXIO_D0 I/O
FXIO_D1 I/O
FXIO_D2 I/O
FXIO_D3 I/O
FXIO_D7 I/O
FXIO_D6 I/O
FXIO_D5 I/O
FXIO_D4 I/O

JTAG
JTAG_TDO O
JTAG_TDI I
JTAG_TCLK I
JTAG_TMS I/O

LPI2C0
LPI2C0_SCL I/O
LPI2C0_SDA I/O
LPI2C0_SCL I/O
LPI2C0_SDA I/O
LPI2C0_HREQ I
LPI2C0_SDAS I/O
LPI2C0_SCLS I/O
LPI2C0_SDAS I/O
LPI2C0_SCLS I/O
LPI2C0_HREQ I

LPI2C1
LPI2C1_HREQ I
LPI2C1_SCL I/O
LPI2C1_SDA I/O
LPI2C1_SCLS I/O
LPI2C1_SDAS I/O
 LPI2C1_SCLS I/O
LPI2C1_SDAS I/O
LPI2C1_SCL I/O
LPI2C1_SDA I/O
LPI2C1_HREQ I
LPI2C1_SDAS I/O
LPI2C1_SDA I/O
LPI2C1_SCLS I/O
LPI2C1_SCL I/O

LPTMR0
LPTMR0_ALT1 I
LPTMR0_ALT2 I
LPTMR0_ALT3 I
LPTMR0_ALT3 I

LPUART0
LPUART0_TX I/O
LPUART0_RX I
LPUART0_TX I/O
LPUART0_RX I
LPUART0_RTS O
LPUART0_CTS I
LPUART0_TX I/O
LPUART0_RX I
LPUART0_RTS O
LPUART0_CTS I
LPUART0_TX I/O
LPUART0_RX I

LPUART1
LPUART1_RTS O
LPUART1_CTS I
LPUART1_TX I/O
LPUART1_RX I
LPUART1_TX I/O
LPUART1_RX I
LPUART1_RTS O
LPUART1_CTS I
LPUART1_TX I/O
LPUART1_RX I
LPUART1_RTS O
LPUART1_CTS I
LPUART1_TX I/O
LPUART1_RX I
LPUART1_TX I/O
LPUART1_RX I

LPUART2
LPUART2_RTS O
LPUART2_TX I/O
LPUART2_RX I
LPUART2_CTS I
LPUART2_TX I/O
LPUART2_RX I
LPUART2_RTS O
LPUART2_CTS I
LPUART2_RTS O
LPUART2_CTS I
LPUART2_TX I/O
LPUART2_RX I
LPUART2_TX I/O
LPUART2_RX I

OSC
EXTAL I
XTAL O

PG
VDD -
VSS -
VSS -
VDD -
VSS -
VDD -
VSS -
VDD -
VSS -
VSS -
VDD -
VDD -
VSS -
VDD -
VSS -
VDD -
VSS -

PTA
PTA7 I/O
PTA6 I/O
PTA17 I/O
PTA3 I/O
PTA2 I/O
PTA1 I/O
PTA0 I/O
PTA16 I/O
PTA15 I/O
PTA14 I/O
PTA13 I/O
PTA12 I/O
PTA11 I/O
PTA10 I/O
PTA5 I/O
PTA4 I/O
PTA9 I/O
PTA8 I/O
PTA18 I/O
PTA19 I/O
PTA20 I/O
PTA21 I/O
PTA22 I/O
PTA23 I/O
PTA24 I/O
PTA25 I/O
PTA26 I/O
PTA27 I/O
PTA28 I/O
PTA29 I/O
PTA30 I/O
PTA31 I/O

PTB
PTB7 I/O
PTB6 I/O
PTB5 I/O
PTB4 I/O
PTB3 I/O
PTB2 I/O
PTB1 I/O
PTB0 I/O
PTB17 I/O
PTB16 I/O
PTB15 I/O
PTB14 I/O
PTB13 I/O
PTB12 I/O
PTB11 I/O
PTB10 I/O
PTB9 I/O
PTB8 I/O
PTB18 I/O
PTB19 I/O
PTB20 I/O
PTB21 I/O
PTB22 I/O
PTB23 I/O
PTB24 I/O
PTB25 I/O
PTB26 I/O
PTB27 I/O
PTB28 I/O
PTB29 I/O
PTB30 I/O
PTB31 I/O

PTC
PTC3 I/O
PTC2 I/O
PTC1 I/O
PTC0 I/O
PTC17 I/O
PTC16 I/O
PTC15 I/O
PTC14 I/O
PTC13 I/O
PTC12 I/O
PTC11 I/O
PTC10 I/O
PTC9 I/O
PTC8 I/O
PTC7 I/O
PTC6 I/O
PTC5 I/O
PTC4 I/O
PTC18 I/O
PTC19 I/O
PTC20 I/O
PTC21 I/O
PTC22 I/O
PTC23 I/O
PTC24 I/O
PTC25 I/O
PTC26 I/O
PTC27 I/O
PTC28 I/O
PTC29 I/O
PTC30 I/O
PTC31 I/O

PTD
PTD1 I/O
PTD0 I/O
PTD17 I/O
PTD16 I/O
PTD15 I/O
PTD14 I/O
PTD13 I/O
PTD7 I/O
PTD6 I/O
PTD5 I/O
PTD12 I/O
PTD11 I/O
PTD10 I/O
PTD9 I/O
PTD8 I/O
PTD4 I/O
PTD3 I/O
PTD2 I/O
PTD18 I/O
PTD19 I/O
PTD20 I/O
PTD21 I/O
PTD22 I/O
PTD23 I/O
PTD24 I/O
PTD25 I/O
PTD26 I/O
PTD27 I/O
PTD28 I/O
PTD29 I/O
PTD30 I/O
PTD31 I/O

PTE
PTE16 I/O
PTE15 I/O
PTE11 I/O
PTE10 I/O
PTE13 I/O
PTE5 I/O
PTE4 I/O
PTE14 I/O
PTE3 I/O
 PTE12 I/O
PTE9 I/O
PTE8 I/O
PTE7 I/O
PTE6 I/O
PTE2 I/O
PTE1 I/O
PTE0 I/O
PTE17 I/O
PTE18 I/O
PTE19 I/O
PTE20 I/O
PTE21 I/O
PTE22 I/O
PTE23 I/O
PTE24 I/O
PTE25 I/O
PTE26 I/O
PTE27 I/O

RTC
RTC_CLKOUT O
RTC_CLKIN I
RTC_CLKOUT O
RTC_CLKOUT O

SWD
SWD_CLK I
SWD_DIO I/O

SYSTEM
CLKOUT O
CLKOUT O
CLKOUT O
CLKOUT O
NMI_b I
RESET_b I/O

LPSPI0
LPSPI0_SIN I/O
LPSPI0_SCK
LPSPI0_PCS0 I/O
LPSPI0_PCS1 I/O
LPSPI0_SOUT I/O
 LPSPI0_SIN I/O
LPSPI0_SCK I/O
LPSPI0_SOUT I/O
LPSPI0_PCS0 I/O
LPSPI0_PCS3 I/O
LPSPI0_PCS2 I/O
LPSPI0_SOUT I/O
LPSPI0_SIN I/O
LPSPI0_SCK I/O
LPSPI0_PCS0 I/O
LPSPI0_SOUT I/O
LPSPI0_PCS1 I/O
LPSPI0_SCK I/O

LPSPI1
LPSPI1_SIN I/O
LPSPI1_SCK I/O
LPSPI1_PCS1 I/O
LPSPI1_PCS3 I/O
LPSPI1_SOUT I/O
LPSPI1_SIN I/O
LPSPI1_SCK I/O
LPSPI1_PCS0 I/O
LPSPI1_SOUT I/O
LPSPI1_PCS2 I/O
LPSPI1_PCS0 I/O
LPSPI1_SOUT I/O
LPSPI1_SOUT I/O
LPSPI1_SCK I/O
LPSPI1_SIN I/O
LPSPI1_PCS0 I/O
LPSPI1_PCS1 I/O
LPSPI1_PCS0 I/O
LPSPI1_SOUT I/O
LPSPI1_SCK I/O
LPSPI1_SIN I/O
LPSPI1_PCS1 I/O

LPSPI2
LPSPI2_SIN I/O
LPSPI2_SCK I/O
LPSPI2_PCS0 I/O
LPSPI2_PCS1 I/O
LPSPI2_PCS2 I/O
LPSPI2_SOUT I/O
LPSPI2_SIN I/O
LPSPI2_SCK I/O
LPSPI2_PCS0 I/O
LPSPI2_PCS3 I/O
LPSPI2_PCS0 I/O
LPSPI2_SOUT I/O
LPSPI2_PCS0 I/O
LPSPI2_SOUT I/O
LPSPI2_SIN I/O
LPSPI2_SCK I/O
LPSPI2_PCS1 I/O

FTM0
FTM0_CH3 I/O
FTM0_CH2 I/O
FTM0_FLT1 I
FTM0_FLT0 I
FTM0_FLT3 I
FTM0_FLT2 I
FTM0_CH1 I/O
FTM0_CH0 I/O
FTM0_CH7 I/O
FTM0_CH6 I/O
FTM0_CH5 I/O
FTM0_CH4 I/O
FTM0_CH3 I/O
FTM0_CH2 I/O
FTM0_CH1 I/O
FTM0_CH0 I/O
FTM0_FLT2 I
FTM0_FLT1 I
FTM0_CH7 I/O
FTM0_CH6 I/O
FTM0_CH5 I/O
FTM0_CH4 I/O
FTM0_CH3 I/O
FTM0_CH2 I/O
FTM0_CH1 I/O
FTM0_CH0 I/O
FTM0_FLT3 I
FTM0_FLT0 I

FTM1
FTM1_CH7 I/O
FTM1_CH6 I/O
FTM1_CH5 I/O
FTM1_CH4 I/O
FTM1_FLT3 I
FTM1_FLT2 I
 FTM1_CH3 I/O
FTM1_CH2
FTM1_CH1 I/O
FTM1_QD_PHA
FTM1_CH0 I/O
FTM1_QD_PHB I/O
FTM1_FLT1 I
FTM1_FLT0
FTM1_CH1 I
FTM1_QD_PHA I/O
FTM1_QD_PHA I
FTM1_QD_PHB I
FTM1_CH3 I/O
FTM1_CH2 I/O
FTM1_FLT0 I
FTM1_CH7 I/O
FTM1_CH6 I/O
FTM1_CH5 I/O
FTM1_CH4 I/O
FTM1_FLT1 I
FTM1_FLT2
FTM1_CH0 I
FTM1_QD_PHB I/O
FTM1_FLT3 I

FTM2
FTM2_CH7 I/O
FTM2_CH6 I/O
FTM2_CH1 I/O
FTM2_CH0 I/O
FTM2_CH5 I/O
FTM2_CH4 I/O
FTM2_FLT0
FTM2_CH3 I
FTM2_QD_PHA
FTM2_CH2 I/O
FTM2_QD_PHB I/O
FTM2_FLT1 I
FTM2_FLT0 I
FTM2_CH5 I/O
FTM2_CH4 I/O
FTM2_FLT3 I
FTM2_FLT2
FTM2_CH3 I
FTM2_FLT1 I/O
FTM2_CH2
FTM2_CH1 I/O
FTM2_QD_PHA
FTM2_CH0 I/O
FTM2_QD_PHB I/O
FTM2_FLT3 I
FTM2_FLT2 I
FTM2_CH7 I/O
FTM2_CH6
FTM2_CH1 I/O
FTM2_QD_PHA I/O
FTM2_QD_PHA I
FTM2_QD_PHB
FTM2_CH0 I
FTM2_QD_PHB I/O
 FTM3
FTM3_CH7 I/O
FTM3_CH6 I/O
FTM3_CH5 I/O
FTM3_CH4 I/O
FTM3_FLT0 I
FTM3_FLT0 I
FTM3_FLT1 I
FTM3_FLT2 I
FTM3_FLT3 I
FTM3_CH5 I/O
FTM3_CH4 I/O
FTM3_CH1 I/O
FTM3_CH0 I/O
FTM3_CH3 I/O
FTM3_CH2 I/O
FTM3_CH1 I/O
FTM3_CH0 I/O
FTM3_CH3 I/O
FTM3_CH2 I/O
FTM3_CH7 I/O
FTM3_CH6 I/O
FTM3_FLT1 I
FTM3_FLT2 I
FTM3_FLT3 I

TRGMUX
TRGMUX_OUT7 O
TRGMUX_OUT6 O
TRGMUX_OUT2 O
TRGMUX_OUT1 O
TRGMUX_OUT5 O
TRGMUX_OUT4 O
TRGMUX_IN6 I
TRGMUX_IN0 I
TRGMUX_IN1 I
TRGMUX_IN7 I
TRGMUX_IN8 I
TRGMUX_IN9 I
TRGMUX_IN2 I
TRGMUX_IN3 I
TRGMUX_IN10 I
TRGMUX_IN11 I
TRGMUX_IN4 I
TRGMUX_IN5 I
TRGMUX_OUT0 O
 TRGMUX_OUT3 O

TRACEnoETM
noetm_TRACE_SWO O

FTM
TCLK2 I
TCLK0 I
TCLK1 I
TCLK1 I

ENET
ENET_TMR2 I/O
ENET_TMR3 I/O
ENET_TMR0 I/O
ENET_TMR1 I/O
MII_RMII_MDC O
MII_RMII_MDC O
MII_RMII_MDIO I/O
MII_TX_ER O
MII_RMII_TXD[0] O
MII_RMII_TXD[1] O
MII_TXD2 O
MII_TXD3 O
MII_RMII_TX_EN O
MII_RMII_TX_CLK I/O
MII_RX_CLK
MII_RMII_RXD[0] I
MII_RMII_RXD[1]
MII_RMII_RXD[0] I
MII_RMII_RXD[1] I
MII_RXD2 I
MII_RXD3 I
MII_RMII_RX_DV I
MII_RMII_RX_ER I
MII_CRS I
MII_COL I
MII_CRS I
MII_COL I

FTM4
FTM4_FLT0 I
FTM4_FLT1 I
FTM4_CH5 I/O
FTM4_CH2 I/O
FTM4_CH5 I/O
FTM4_CH6 I/O
FTM4_FLT0 I
FTM4_FLT1 I
FTM4_CH0 I/O
FTM4_CH1 I/O
FTM4_CH2 I/O
FTM4_CH3 I/O
FTM4_CH4 I/O
FTM4_CH6 I/O
FTM4_CH7 I/O
FTM4_CH0 I/O
FTM4_CH1 I/O
FTM4_CH3 I/O
FTM4_CH4 I/O
FTM4_CH7 I/O
FTM4_CH0 I/O
FTM4_CH1 I/O
FTM4_CH2 I/O
FTM4_CH3 I/O
FTM4_CH4 I/O
FTM4_CH5 I/O
FTM4_CH6 I/O
FTM4_CH7 I/O

FTM5
FTM5_FLT0 I
FTM5_FLT1 I
FTM5_CH0 I/O
FTM5_CH1 I/O
FTM5_CH3 I/O
FTM5_CH5 I/O
FTM5_FLT0 I
FTM5_FLT1 I
FTM5_CH0 I/O
FTM5_CH1 I/O
FTM5_CH2 I/O
FTM5_CH3 I/O
FTM5_CH4 I/O
FTM5_CH5 I/O
FTM5_CH6 I/O
FTM5_CH7 I/O
FTM5_CH7 I/O
FTM5_CH2 I/O
FTM5_CH4 I/O
FTM5_CH6 I/O
FTM5_CH7 I/O
 FTM6
FTM6_FLT0 I
FTM6_FLT1 I
FTM6_CH0 I/O
FTM6_CH0 I/O
FTM6_CH1 I/O
FTM6_CH2 I/O
FTM6_CH3 I/O
FTM6_CH4 I/O
FTM6_CH5 I/O
FTM6_CH6 I/O
FTM6_CH7 I/O
FTM6_CH0 I/O
FTM6_CH1 I/O
FTM6_CH2 I/O
FTM6_CH3 I/O
FTM6_CH4 I/O
FTM6_CH5 I/O
FTM6_CH6 I/O
FTM6_CH7 I/O
FTM6_FLT1 I
FTM6_FLT0 I

FTM7
FTM7_FLT0 I
FTM7_FLT1 I
FTM7_CH0 I/O
FTM7_CH1 I/O
FTM7_CH2 I/O
FTM7_CH3 I/O
FTM7_CH4 I/O
FTM7_CH5 I/O
FTM7_CH6
FTM7_CH7 I/O
FTM7_FLT0 I/O
FTM7_FLT1 I
FTM7_CH0 I/O
FTM7_CH1 I/O
FTM7_CH2 I/O
FTM7_CH3 I/O
FTM7_CH4 I/O
FTM7_CH5 I/O
FTM7_CH6 I/O
FTM7_CH7 I/O

QuadSPI
QSPI_B_IO0 I/O
 QSPI_A_CS
QSPI_B_IO3 I/O
QSPI_A_IO3 I/O
QSPI_A_IO1 I/O
QSPI_B_IO1 I/O
QSPI_B_IO2 I/O
QSPI_A_IO2 I/O
QSPI_A_IO0 I/O
QSPI_A_SCK I/O
QSPI_B_SCK I/O
QSPI_B_RWDS I/O
QSPI_B_IO4 I/O
QSPI_B_IO5 I/O
QSPI_B_IO6 I/O
QSPI_B_IO7 I/O
QSPI_B_CS O

SAI0
SAI0_MCLK I
SAI0_D3 I/O
SAI0_D0 I/O
SAI0_BCLK I/O
SAI0_SYNC I/O
SAI0_D1 I/O
SAI0_D2 I/O

TRACE
ETM_TRACE_D0 O
ETM_TRACE_D1
ETM_TRACE_CLKOUT O
ETM_TRACE_D2 O
ETM_TRACE_D3 O
ETM_TRACE_CLKOUT O
ETM_TRACE_D0 O
ETM_TRACE_D1 O
ETM_TRACE_D2 O
ETM_TRACE_D3 O

SAI1
SAI1_MCLK I
SAI1_D0 I/O
SAI1_BCLK I/O
SAI1_SYNC I/O