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Mic Unit1 Architecture

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Microprocessors

By
Mr. Parag R. Sali
Lecturer
Department of Computer Technology
SNJB’s Shri. Hiralal Hastimal ( Jain Brothers)
Polytechnic, Chandwad
Program Name: Computer Engineering Group
Program Code : CO/CM/IF/CW
Semester : Forth
Course Title : Microprocessors
Course Code : 22415

8086 Microprocessor Architecture


Architecture of 8086 microprocessor:
As shown in the below figure, the 8086 CPU is divided into two independent
functional parts
o Bus Interface Unit(BIU)
o Execution Unit(EU)
The description of each Status flag bit is as follows:
SF- Sign Flag: This flag is set, when the result of any computation is negative. For
signed computations the sign flag equals the MSB of the result.
ZF- Zero Flag: This flag is set, if the result of the computation or comparison
performed by the previous instruction is zero.
PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even
number of 1’s.
CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition
or a borrow in case of subtraction.
AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit
three during addition, or borrow for the lowest nibble, i.e, bit three, during
subtraction.
OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination register. The result is of
more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in
size in case of 16-bit sign operations, and then the overflow will be set.
The description of each control flag bit is as follows:

TF- Trap Flag: If this flag is set, the processor enters the single step execution
mode. The processor executes the current instruction and the control is
transferred to the Trap interrupt service routine.

IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by
the CPU, otherwise they are ignored.

D- Direction Flag: This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest address to the highest
address, i.e., auto incrementing mode. Otherwise, the string is processed from
the highest address towards the lowest address, i.e., auto decrementing mode.
8086 PIPELINING ARCHITECTURE:
• While the EU is decoding an instruction or executing an instruction, which
does not require use of the buses, the BIU fetches up to six instruction bytes
for the instructions.
• The BIU stores these pre-fetched bytes in a first-in-first-out register set called
a queue.
• When the EU is ready for its next instruction from the queue in the BIU. This is
much faster than sending out an address to the system memory and waiting
for memory to send back the next instruction byte or bytes.
• Except in the case of JMP and CALL instructions, where the queue must be
dumped and then reloaded starting from a new address, this pre-fetch and
queue scheme greatly speeds up processing.
• Fetching the next instruction while the current instruction executes is called
pipelining.
Memory Segmentation:
• The memory in an 8086 based system is organized as segmented memory.
• The CPU 8086 is able to access 1MB of physical memory. The complete 1MB
of memory can be divided into 16segments, each of 64KB size and is
addressed by one of the segment register.
• The 16-bit contents of the segment register actually point to the starting
location of a particular segment. The address of the segments may be
assigned as 0000H to F000h respectively.
• To address a specific memory location within a segment, we need an offset
address. The offset address values are from 0000H to FFFFH so that the
physical addresses range from 00000H to FFFFFH.
The main advantages of the segmented memory scheme are as follows:

1. Allows the memory capacity to be 1MB although the actual addresses to be


handled are of 16-bit size.

2. Allows the placing of code, data and stack portions of the same program in
different parts (segments) of memory, for data and code protection.

3. Permits a program and/or its data to be put into different areas of memory
each time the program is executed, i.e., provision for relocation is done.
Physical address is calculated as below:
Ex: Segment address ------- 1005H
Offset address --------------- 5555H
Physical address = Segment address * 10H + Offset address.
Segment address ------------ 1005H ------------ 0001 0000 0000 0101
Shifted left by 4 Positions----------------- 0001 0000 0000 0101 0000
+
Offset address --- ------------5555H ------------- 0101 0101 0101 0101
Physical address -------155A5H----------- 0001 0101 0101 1010 0101

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