Review Paper 2023-2024

ABSTRACT

Dynamic style circuits are preferred over CMOS style static logic circuits
because they have insubstantial dominance in the category of electronic markets for high-performance
electronics design. This preference becomes more glaring in the electronic circuits as the power dissipates
from the clock since it plays a major overall circuit performance.
Therefore, the investigation described in this paper hardly concerns the absolute parameters of
dynamic logic circuits but instead is dedicated to their comparative performance. This work presents a
novel way of designing an innovative PD, PFD, and their comparison using the Tanner tool. The
topology of the proposed detector is dynamic logic designed with the technology nodes of both standard
250nm and 45nm.
It is a design technique to retain the circuits' speed and increase their power efficiency by
improving traditional designing methods with suitable modifications. Most essentially, the number of
transistors has decreased to be used, with this, power is saved and even the layout is made as small as it
could be. All the parameters for the performance of circuits like optimization of transistor delay, power
dissipation, and overall figure of merit has been carried out in this work. The obtained results are glitch-
free and considerably increase the performance of the circuit.
These findings would strongly bring out the optimal trade-offs of the proposed designs against the
existing techniques, presenting improvements to the area, power, and speed for VLSI circuits. This
therefore lays much-needed insights for practical solutions in effectively optimizing electronic designs of
great performance.

Department of Electronics and Communication Engineering, BIT Pg 1

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CHAPTER 1

INTRODUCTION

Electronics has been developing at a great pace over the past couple of decades through the
development of VLSI technology. VLSI advancements have allowed the development and manufacturing
of very complex and efficient electronic gadgets. Power conservation is important in modern-day
technology.

Dynamic logic circuits have been developed and are gaining increased demand for power-
efficient circuitry. These deliver enormous advantages compared to the traditional static logic circuits that
use CMOS. A dynamic logic circuit operates not like their static counterparts that run at a constant
voltage, but through two distinct phases: precharge and evaluation.

A dynamic logic circuit returns the output to a high state unconditionally in the precharge
phase of operation, when the clock signal is low, regardless of the input conditions. This precharge
mechanism prepares the proper state of the circuit to be able to perform the next evaluation phase.

From there, the clock signal is high, and it is here that the circuit output is dependent on the
input signals. This good precharge characteristic, however, is met with a very serious challenge-ringing
during its precharge phase. To address this issue, True Single-Phase Clock based dynamic logic circuits
have been introduced. Accordingly, an extra clock transistor is added to the output stage of the static
inverter, which makes the buffer practically off during the precharge phase—the noise issue is thus
significantly eliminated.

Dynamic logic circuits are used mainly where phase-frequency detection and phase
detection must be done accurately; the typical application is in wireless and wired communication
networks. In these applications, the Phase-Locked Loop is what keeps the synchronization and precise
processing of signals in this type of network.

The correct phase and frequency alignment largely depends on the phase detectors and
phase-frequency detectors used by the PLLs. So, proper communication requires the correct operation of
a PLL, therefore, requiring efficient PDs and PFDs.

More so, we are working on designing and implementing a novel dynamic logic circuit that
operates effectively on channel lengths of 250 nm and 45 nm. Insofar as the general design is undertaken
to reduce power, transistor count, and delay, while increasing the speed, most of the primary

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implementations of these designs are too large, causing a problem in squeezed environments. Our work
seeks to address these challenges in the new design of PD and PFD with dynamic logic.

The main focus of this paper is to decrease the number of transistors and to optimize the
power and delay performance. We shall also refine the conventional approach, with the help of dynamic
logic, to achieve the compactness of layout, low power dissipation, and improved speed. We used a few
techniques to optimize the performance of our dynamic logic circuits.

One key approach involved varying the power supply voltage (Vdd) within a range of 0.6 to
1.4 volt. General adjustment through this respect allows for tuning performance to reach a good match,
balancing power consumption against speed.

Further, we scaled the W/L ratio of PMOS and NMOS transistors from 1 to 5. The W/L
ratio is a very important design parameter for any transistor, which affects the driving capabilities of the
current and switching speed in a circuit.

With choosing the correct value of W/L, we are able to optimize the performance of PDs
and PFDs for the best trade-off between power, speed, and chip area. The proposed designs for PD and
PFD, in comparisons with any existing design, have far better solutions.

In VLSI applications, the presented designs are more efficient because designs were
attempted in such a way to reduce the number of transistors and to present optimizations with respect to
power and delay constraints. The compact layout is advantageous, especially in applications where space
is a limitation.

Also, the optimized consumption of power and the increased speed give the overall
enhanced performance of the dynamic logic circuits and help to develop more effective electronic
devices. This work will address these issues by proposing the new designs of the dynamic logic–based
PD and PFD. This is to reduce the number of transistors, which will result in the optimized consumption
of power and optimized behavior of delay.

Our design features make the conventional approach more refined and exploit dynamic
logic to make the layout more compact with lower power dissipation and improved speed. Summing up,
the advances made in our study offer work that deals with drastically improving the design of dynamic
logic circuits.

With the key focus of transistor count reduction and power and delay constraints optimized,
shallower PD and PFD designs render an efficient solution in the realm of VLSI applications.

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Such improvements have been made to contribute not only to enhance the performance of
dynamic logic circuits but also toward the general objective of developing stronger, smaller, and more
power-efficient electronic devices. Further refinements in the design parameters and new techniques that
enhance the performance of dynamic logic circuits will keep them relevant in this ever-growing field of
electronics.

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CHAPTER 2

BACKGROUND

Dynamic CMOS logic circuits are one of the most important realizations of high-
performance electronic systems, and they have developed applications of high speed and efficiency, for
example in the fields of microprocessor and digital signal processors (DSP). This chapter discusses the
background, working principles, and trade-offs in operation of dynamic CMOS logic for an understanding
in the importance of this kind of logic in this modern electronic era.

Working Principle
Dynamic CMOS Logic Circuits: In dynamic CMOS logic circuits, a two-phase clocking mechanism is
utilized having a precharge phase and an evaluation phase.
Precharge Phase: During this operation, the low clock signal turns on the precharge transistor,
precharging the output node to a high voltage level. This phase is done to let the circuit be prepared at the
beginning if the input signals are not considered.
Evaluation Phase: At the rising edge of the clock signal, the circuit starts the evaluation stage. At this
stage, the pre-charge NMOS transistor turns off, and the NMOS transistors evaluation network yields the
output according to the inputs' logic levels. If the input sent is supposed to be executed through a certain
output, it causes the pre-charged high output node to be discharged conditionally, i.e., it forms a low
output. If the NMOS transistors do not turn on, then its output remains high.

In dynamic CMOS logic circuits such as this evaluation network, the combination of
precharge transistor and evaluation tree is what brings efficiency to the dynamic circuits, as it relies on the
clock signal for states toggling between the charging and evaluating states.

Advantages of Dynamic CMOS Logic

1. Low Transistor Count: Dynamic CMOS logic circuits generally use fewer transistors than static
CMOS. The reduced count in transistors directly implies less area of a chip, which is highly favored,
especially in high-density integrated circuits. In addition, the parasitic capacitance is also reduced, which
enhances the overall speed and reduces consumption of power.

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2. High Speed: The intrinsic speed advantage of dynamic logic arises from two factors: reduced load
capacitance and no need to drive a p-type transistor network for each logic operation. Due to these factors,
dynamic logic circuits outperform static logic circuits to a great extent. This high speed has provided a
unique advantage to dynamic logic for applications requiring high speed, such as microprocessors and
DSPs, which demand a high level of performance.

Disadvantages of Dynamic CMOS Logic

1. Sensitivity to Noise: This high value of logic is one important disadvantage of dynamic CMOS logic.
The output node is precharged to an evaluation high level at every clock cycle. Therefore, any existed
noise in the circuit may accidentally discharge the output node to give an invalid logic status. This is why
DC is so sensitive to noise, and this fact has to be taken into consideration at the design stage.

2. Charge Sharing: Another very important problem attributed to the dynamic CMOS logic circuits is the
related charge sharing. During the evaluation phase, some charge stored on the output node is distributed
among the other nodes so that the voltage on the output node falls under the required threshold. This adds
to some logic errors leading to the malfunction of the circuit. To reduce charge sharing even further, most
designers add keeper transistors, which retain charge on the output node by giving a minor current to
counter the leak and redistribution of that charge.

Design Considerations and Mitigation Techniques

Several design techniques and mitigation strategies have been followed to overcome the native drawbacks
of dynamic CMOS logic circuits. Keeper Transistors: Keeper transistors in the dynamic CMOS logic try to
maintain the charge on the output node during the evaluation phase. In practice, these provide a very weak
pull-up, might counteract some leakage, and prevent the output from degrading.
Shielding and Grounding: Proper layout design with inclusion of shielding and grounding reduces the
effect of noise interference. In other words, correct ground plane and shielding wire layout will distribute
the noise sources so as not to sit by sensitive nodes.

Balanced Evaluation Networks: The charge-sharing effect may be minimized if the designs have
balanced evaluation networks with matched sizes of transistors. This, therefore, will lessen the potential of
unwanted voltage drops by quantifying charge sharing uniformly on all nodes of the evaluation network.

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Clocking Design: Clocking design remains a very critical part of any dynamic CMOS logic circuits. Jitter
or skew in the clock signal could lead to the precharge and evaluation phases going awry in their timings,
hence bringing logic errors.
Dynamic CMOS Logic Circuits: Dynamic CMOS logic circuits have huge advantages
regarding transistor count and speed, so they are much fit for use in high-performance applications.
They, however, also present challenges such as noise sensitivity and charge sharing, the
latter calling for proper design and mitigation strategies. Understanding such trade-offs can allow
engineers to use all the possible dynamics of Darlington CMOS Logic in the design of faster and more
effective electronic systems. This chapter on dynamic CMOS logic principles and issues gives the
foundation to the topics that would be taken up further for more advanced studies and innovations in the
field of VLSI technology..

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CHAPTER 3

PROPOSED WORK
Many researchers have designed and optimized the CMOS-based Phase Frequency Detector
(PFD) and Phase Detector (PD). Traditional PFDs exhibit drawbacks such as higher power consumption
and more layout area due to a large number of transistors. Static-CMOS-logic-based phase detector circuits
are also associated with increased power dissipation, area, and chip size, with large delays. The proposed
design adopts static configuration and avails dynamic CMOS logic for efficient optimization of these
parameters for both phase detector and PFD circuits.

This is in the form of a 2-input XOR gate implemented using dynamic CMOS logic
technology for an actual phase detector circuit, whose results are excellent. This phase frequency detector
circuit, being full dynamic CMOS logic, also uses a created NAND gate symbol made through the
respective schematic, which was developed. The proposed circuits were simulated using T-SPICE tools
and some impressive performance results versus the traditional circuit implementations.
A. Phase Detector (PD)
Phase detectors find vital applications in most electronic applications, especially in
communication systems, phase-locked loops (PLLs). The proposed phase detector circuit makes use of
dynamic CMOS logic to reduce power consumption and augment the operational speed. At the heart of
this design will be a 2-input XOR gate, which will ensure efficient phase detection while leveraging the
merits of dynamic logic for the same.

Figure 1: Dynamic CMOS PD Circuit

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The phase detector design has focused on reducing transistor count. This will have a direct
impact on the reduction of power and compact layout. In this paper, we will show an optimized circuit
architecture using dynamic CMOS logic, which will demonstrate considerable reduction in both power
dissipation and delay, proving the proposed phase detector to be an ideal solution for high-performance
applications.

1. Design Approach
The dynamic CMOS phase detector utilizes a 2-input XOR gate, which is the heart of the
phase detector. This gate works admirably in dynamic logic that allows quick switching and low power
consumption. The output node gets precharged during the precharge phase and is evaluated according to
the inputs during the evaluation phase to produce the correct phase detection.

2. Merits of Dynamic CMOS in PD

Dynamic CMOS logic requires fewer transistors, which flows down to reduced chip area
and parasitic capacitance. Therefore, dynamic logic gate can achieve higher operating speeds and reduced
power consumption. These circuits are plainly faster due to their lower load capacitance and the fact that a
p-type transistor network does not have to be driven for every logic operation.

B. Phase Frequency Detector (PFD)

The other critical component in most of the PLLs and in the frequency synthesis application is the phase
frequency detector. The proposed PFD circuit is using dynamic CMOS logic for offering improved
performance. This is designed using the NAND gate symbol, created from the respective schematic; in this
manner, it guarantees efficient frequency detection.

Figure 2: Dynamic CMOS Phase Frequency Detector Circuit

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Figure 3: NAND Gate Symbol and Schematic

1. Design Approach
We can see that the dynamic CMOS phase frequency detector uses a NAND gate, which
forms the core of frequency detection. Due to the application of dynamic CMOS logic, power consumption
is decreased and speed is increased. The working technique for this circuit is the same as the precharge
node and sees how the inputs perform during the clocking cycle, like the phase detector.

2. Advantages of Dynamic CMOS in PFD

Reduced power consumption, an increased speed, and reduced transistor count are some of
the advantages that usage of dynamic CMOS logic provides when coming up with the design of a PFD. A
reduction in the number of the transistors also implies a reduced layout area, which is advantageous in
some applications where space is limited. Another advantage is the speed factor, such that these dynamic
logic circuits operate faster, thereby making the PFD suitable for high-speed radio frequency applications.
The proposed circuits were simulated using T-SPICE tools. Simulations for the proposed
dynamic CMOS logic-based phase detector and PFD circuits show much better performance than the
traditional design. The results depicted better speed performance, lower power consumption, and reduced
layout area.

1. Performance Metrics
The various performance metrics such as power consumption, speed, and layout area
assessed in the simulations revealed very promising numbers for dynamic CMOS PD and PFD circuitry
when compared to static CMOS. In fact, dynamic CMOS circuits exhibit a notable decrease in power
consumption. The dynamic CMOS PD and PFD circuits were very significantly less in consumed power
when compared to the static CMOS designs. Speed, in terms of propagation delay, was much less. It
means the operation was faster. And, layout area was correspondingly less because the number of
transistors was also less.

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This further proved the point that the designed dynamic CMOS circuits were much better
than traditional static CMOS designs. All the parameters, which the dynamic CMOS phase detector and
PFD were matched against, showed better performance than the static CMOS designs. Hence, the most
enhanced and desired features of these designs are their low power consumption, delay, and area—now
being very efficient for applications requiring high performance.

Some of the significant improvements of the proposed dynamic CMOS logic-based PD and PFD circuits
are presented, but there can be still more optimization techniques studied further. In future work, a further
optimization of the performance of the proposed design can be achieved by fine-tuning the design
parameters, such as the width-to-length ratio of the transistors. Further investigation into other dynamic
logic families and their potential benefits in getting even more efficient designs would be providing
efficient designs.
We hereby managed a lower power consumption, faster operation, and compact layout by exploiting the
benefits of dynamic logic. T-SPICE simulations developed results of the effectiveness of these designs, as
they are plentiful in most high-performance applications, including communication systems and frequency
synthesis. Further research on dynamic CMOS continued to explore different logic families and
applications in the area of VLSI technology.

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CHAPTER 4

SIMULATION RESULTS
Fig. 4 to Fig. 7 give the simulation results for the dynamic CMOS phase detector and phase-
frequency detector circuits. These results show the input and output waveforms with phase-detection and
frequency-detection characteristics.

A. Simulated Results of Proposed Dynamic CMOS PD Circuit

Figure 4: Simulated Results of Proposed Dynamic CMOS PD Circuit

Figure 4 shows the output waveforms which indicate the phase duration between the clock
and two input waveforms. Essentially, the dynamic CMOS PD circuit operates on the clock. In the initial
phase, the evaluation phase, when the clock is high, that is, 1, and all the inputs A and B are also at 1, there
will be no phase change, consequently the output will be 0. During the following clock cycle, after the
clock goes low, that is, low, and this is the precharge phase, the output will always be high, independent of
the input. However, when the clock goes back to the evaluation phase at 100 ns, because both inputs are
out of phase for some of the time, the output is high, indicating a phase change.
In this simulation, a precharge phase sets the output high irrespective of the values in the
inputs, which helps prepare the circuit for the next evaluation phase. At the evaluation phase, conditional
discharge of the output occurs according to the input signals. Transitions from high to low states in the
output waveform indicate that the circuit responds to phase changes between the input signals.

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B. Phase Detection by Proposed Dynamic CMOS PFD Circuit

Figure 5: Phase Detection by Proposed Dynamic CMOS PFD Circuit

Figure 5 is showing the behavior of phase detection under the proposed dynamic CMOS
PFD circuit. In this result, CLOCK2 is lagging in phase compared to CLOCK1, and the output shows the
phase detection of the input signal. The phase difference between the two input clocks will now be
detected and presented through the output in the dynamic CMOS PFD circuit.
This PFD circuit has employed dynamic CMOS logic so that the phase detection could be
efficiently carried out to reduce the consumed power with much faster response time in comparison with
conventional static CMOS designs. Some applications, like phase-locked loops and frequency synthesis,
are very useful for devices possessing correct phase differences, where exact phase matching is necessary.

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C. Frequency Detection by Proposed Dynamic CMOS PFD Circuit

Figure 6: Frequency Detection by Proposed Dynamic CMOS PFD Circuit (CLOCK1 Greater than
CLOCK2)

Figure 7: Frequency Detection by Proposed Dynamic CMOS PFD Circuit (CLOCK2 Greater than
CLOCK1)

Figures 6 and 7 illustrate possible frequency detections based on the abstracted dynamic
CMOS PFD output. In Figure 6, it is the case when CLOCK1 > CLOCK2; in Figure 7, the opposite is true.
Depending on how frequently CLOCK1 and CLOCK2 occur with respect to each other, multiple possible
pulses are seen at the output nodes.
The simulated dynamic CMOS PFD circuit is effective in comparing the frequency
difference between the input signals. The output waveforms indicate that the circuit generates pulses
commensurate with the frequency difference of the two clocks. This is quite important in applications of
frequency synthesis and frequency control, where precise frequency relationships must be enforced.

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In the PFD circuit, the use of the dynamic CMOS logic injects some dynamics in the circuit, which boosts
the performance and accelerates the operation at lower power consumption. Its ability to detect phase and
frequency differences makes this solution versatile and efficient for high-performance applications.

D. Performance Metrics and Comparative Analysis

The simulations took into account the performance metrics, which in this case are power, speed, and layout
area, quantified by the metrics of propagation delay, incurred. The DM_C PDs and PFDs showed a
significant decline in the consumed power compared to the implementation of static CMOS designs. The
PFDs indicated a notable decline, which means it is therefore higher-speed operation. Finally, the reduced
transistor count would yield a smaller area

1. Power Consumed
The built dynamic CMOS circuits exhibit a many times lower power consumption compared to the static
CMOS counterpart. This is because it uses a lesser amount of transistors and because of the efficient
operation of dynamic logic, the overall power dissipation can be minimized.

2. Speed
The propagation delay, which refers to the time taken for the signal to propagate through the circuit, was
used in measurement with respect to the speed of the suggested circuits. Dynamic CMOS PD and PFD
circuits show faster operation and low propagation delay, and are thus favorable for high-speed
applications.

3. Layout Area
The layout area is small for this kind of circuit chip since the number of transistors used is low. For
integrated circuits, the chip area is supposed to be small and compact enough since this is a close
arrangement of the components. The compactness of the layout also yields in lower parasitic capacitance,
making the circuits have excellent performances.

4. Comparative Analysis
A performance comparison with conventional static CMOS designs showed convincingly better results for
the proposed dynamic CMOS circuits. The dynamic CMOS phase detector and PFD circuits substantially
improved the performance for all of the characterized parameters: power, area, and delay. This reduction in
power-delay product and layout area makes it very much efficient.
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Dynamic CMOS is a logic form that provides good performance in such circuits by
reducing power, increasing speed, and minimizing the area of layout. The results obtained create a
connection between the efficacy of the proposed designs and the suitability in high performance-
applications, which are related to communication and frequency synthesis systems. The exploration of
dynamic CMOS logic and its applications promises further development toward the realization of an even
more glorious era in the VLSI domain.
.

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CHAPTER 5
POWER UTILIZATION, DELAY, AND POWER DELAY
ANALYSIS

Here, the performance parameters of the proposed dynamic CMOS Phase Detector and
Phase Frequency Detector have been studied with effective implementations both at 250nm and 45nm
technology nodes. Those parameters are very significant in comparing the circuits for the power
utilization, delay, and the power-delay product in high-performance applications. Simulation results for
these proposed designs are depicted in Figures 8 through 13 below, wherein a significant degree of
progress on all proposed designs, specifically at the 45 nm technology node, is visible.

A. Power Utilization Analysis

Power dissipation is a basic figure of merit for any CMOS circuit, but its importance grows
dramatically with scaling to lower technology nodes. Average power dissipation of the proposed
dynamic CMOS PD circuit at various Vdd is analyzed. The power dissipation decreases with reduced Vdd,
as indicated in Figure 8. At the 45nm node, the dissipated power at 1V supply voltage is 0.279µW, while
at the 250nm node it is 0.453µW. Such a significant power drop as a function of nodes size is testimony to
the efficiency of the dynamic style herein presented in CMOS.

Figure 8: Average Power Dissipation of Proposed Dynamic CMOS PD Circuit in Reference with
Vdd

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The dynamic power dissipation equation lights the fact that a reduction in the Vdd lowers a
drop in the overall power dissipation, hence power-efficient. This is quite very advantageous in most
modern electronic applications where this aspect forms the basis of operation.

B. Analysis of Delay

Delay is another crucial performance parameter that dictates the pace of CMOS Circuits.
The propagation delay of the designed dynamic CMOS PD circuit was analyzed based on Vdd. Fig 9
represents how Vdd varies with regards to the circuit delay. Generally, the delay is characterized by two
parameters; tpLH, which refers to the response time from low to high output transition, and tpHL, meaning
response time from high to low transition.

Figure 9: Delay of Proposed Dynamic CMOS PD Circuit in Reference with Vdd

The math illustrates how, with an increase of Vdd, the delay decreases, an effect much
pronounced in the 45 nm technology node. The smaller technology node will result in a faster transition, .

C. Power-Delay Product (PDP)

PDP can be defined as the product of power utilization and delay; it is a measure of circuit efficiency in
combining both power consumption and speed. Lower PDP means a good circuit because power and delay
are nicely balanced. The PDP of the proposed dynamic CMOS PD circuit is evaluated at different Vdd
levels, as shown in Figure 10.

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Figure 10: Power-Delay Product of Proposed Dynamic CMOS PD Circuit in Reference with Vdd

This indicates, as seen from the results, that compared to the 250 nm of technology node,
the PDP at 45 nm of technology node is very low, thus indicating better performance. The reduced PDP
depicts the efficiency of the proposed design, hence making it suitable for any application that requires
both low power and high speed.

D. Performance Analysis of the Phase Frequency Detector (PFD)

For the dynamic CMOS PFD circuit, a similar set of exercises has been executed in 250 nm
and 45 nm technology nodes. The circuits are analyzed for performance measures including power, delay
and PDP. The results are presented in Figs. 11-13.

Figure 11: Average Power Dissipation of Proposed Dynamic CMOS PFD Circuit in Reference with
Vdd

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Power dissipation results for the PFD circuit look nice and take a heavy slip at the 45 nm
technology node. At the 45 nm technology node, much lower power dissipation is registered; such data are
now very important because many applications require that the equipment operates with maximal energy
saving.

Figure 12: Delay of Proposed Dynamic CMOS PFD Circuit in Reference with Vdd

The analysis of PFD circuit delay shows that the delay is minimized with the increment of
Vdd, contrary to that of the PD circuit. Reduction in delay at the 45 nm node speeds up the circuit and
makes it suitable for high-frequency applications.

Figure 13: Power-Delay Product of Proposed Dynamic CMOS PFD Circuit in Reference with Vdd

A PDP analysis for the PFD circuit shows a dramatically reduced value at the 45-nanometre
technology node. The enhanced PDP value strongly reflects better circuit design exemplifying tailoring
power consumption against speed.

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The elaborate power, delay, and power-delay product analysis for the proposed dynamic
CMOS PD and PFD circuits at 45 nm shows tremendous improvements in performance. The designed
circuits showed better efficiency for modern electronic applications by way of low power dissipation, low
delay, and a better PDP. Such advances made with the proposed designs underline their potential for high-
performance, low-power applications, something that is really wanted by modern electronic systems.

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CHAPTER 6
COMPARISON OF DIFFERENT TECHNIQUES

Finally, summing up the review of the proposed dynamic CMOS phase detector (PD) and
phase frequency detector (PFD) circuits, new designs are found to benchmark an improvement over the
conventional methods. In this regard, comparative analysis of Tables I and II shows better performance on
all parameters for the proposed work in comparison with the previous state of the arts.

Table I: Power, Delay, and PDP of PD Using Different Techniques

CMOS Technique Transistor Count Power (W) Delay (ns) PDP (J)
Conventional 22 0.426 x 10^-6 0.845 x 10^-9 0.36 x 10^-15
Dynamic TGCMOS 20 0.372 x 10^-6 0.796 x 10^-9 0.29 x 10^-15
Domino 18 0.341 x 10^-6 0.735 x 10^-9 0.25 x 10^-15
Proposed Work 12 0.279 x 10^-6 0.524 x 10^-9 0.15 x 10^-15

Comparative results for power consumption, delay, and PDP for various PD designs are
shown in Table I. The current dynamic CMOS PD circuit showed the power dissipation that is the least,
which is 0.279 10-6 W, and the minimum delay, which is 0.524 10-9 s, hence presenting the least PDP of
0.15 10-15 J. Performance obtained with proposed work is better than conventional and Dynamic
TGCMOS and even Domino logic techniques and hence it is very effective for phase detection
applications.
Table II: Power, Delay, and PDP of PFD Using Different Techniques

CMOS Technique Transistor Count Power (W) Delay (ns) PDP (J)
Conventional 26 0.738 x 10^-6 1.293 x 10^-9 0.54 x 10^-15
Dynamic TGCMOS 22 0.663 x 10^-6 1.172 x 10^-9 0.49 x 10^-15
Domino 20 0.613 x 10^-6 1.035 x 10^-9 0.40 x 10^-15
Proposed Work 14 0.451 x 10^-6 0.746 x 10^-9 0.34 x 10^-15

The different parameters of the proposed and existing PFD designs are compared in Table
II. The dynamic CMOS PFD circuit shows considerable improvements in power dissipation of 0.451 ×
10^-6 W, a delay of 0.746 × 10^-9 s, and PDP of 0.34 × 10^-15 J.

These values are quite improved over the conventional and existing dynamic TGCMOS and
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Domino logic-based designs of PFD and hence show the effectiveness of the proposed circuit in terms of
power reduction and speed enhancement.

Overall, the proposed dynamic CMOS logic-based designs for PD and PFD circuits not
only reduce transistor count but also give the optimized performances in terms of power, delay, and PDP,
and thus may be very useful during high-performance VLSI applications.

CHAPTER 7

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CONCLUSION

In this paper, a review of the proposed dynamic CMOS circuits for phase sensor (PD) and
phase-frequency sensor (PFD) that obtained marked improvements in power consumption, delay, and
power-delay product (PDP) has been shown. The fully implemented design, with and without technologies
of 250 nm and 45 nm, had outperformed to beat the shop specifications. The proposed circuits have low
power deviations, high-speed operation, and a small area utilization, making them appropriate for high-
performance VLSI operations. The simulation results have shown that

• The average power dissipation and dissipation are dramatically reduced with 45 nm technology in
comparison to 250 nm.
• The proposed dynamic CMOS PD and PFD have less power dissipation, dissipation, and PDP as
compared to that of other designs including those using lower technology bumps.

To sum up, this design elicited an effective power and detention-able circuit for CMOS phase sensors and
phase frequence sensors, which provide implicit operations in high-performance VLSI circuits.

CHAPTER 8
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FUTURE WORK
Of special note is the exciting exploration in using dynamic CMOS phase detectors (PD)
and phase frequency detectors (PFD) to reduce power consumption and drive towards perfecting speed.
However there are a great number of areas where further work can be done to make these circuits more
and more useful in colourful operations.
A very important area for the future is to get these dynamic CMOS circuits into place with-
in larger systems. For instance, a more general approach toward embedding the architectures of PD and
PFD within microprocessors, communication systems, and other digital bias could help to increase the
overall effectiveness of such systems. In this manner, the benefits of low power use and higher speed
capability could be leveraged on a more widespread basis. Another thrust for further research is to adapt
the architectures to smaller technology bumps that the present 45nm. As technology keeps moving
forward, the circuits are getting smaller, and it will be important to see how these dynamic CMOS circuits
will perform at sizes of 22 nm or 14 nm.
This could also help address challenges in this class, similar to those that arise as leakage
currents increase and shelf-channel goods that come with lower sizes. Another important area is making
these circuits suitable for low-power, battery-operated bias. As demand for portable and wearable
electronics increases, it is imperative that these circuits work optimally with, in fact, the lowest power
possible to enhance battery run-times. This leads to the design of ultra-low power consuming circuits and
adaptation of power operation schemes.
Real- world algorithm implementation is essential to ascertain the working of the circuits in
live performance. Joining forces with industry partners to take these designs into actual products can
provide valuable feedback, aiding in betterment and updating the circuits outside a laboratory. Similar
hookups can also help to bring these advanced designs from the exploration stage to commercially feasible
products.
Conclusion: Although the recent part of good research has been carried out on the dynamic
CMOS Pᴅ and PғD circuits, there still exist many opportunities for continuous improvement. Such effort
channels in the direction the researcher should take in the future, as it will direct the research into better
and more relevant systems. More importantly, better performance, improvement, scalability, and useful
functionalities that are yet to be developed for these circuits are realized.

Department of Electronics and Communication Engineering, BIT Pg 25