6/8/2018

ECE4740:
Digital VLSI Design
Lecture 3: Nanometer MOSFETs

75

It’s not that complicated…

Body effect revisited

76

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Body effect revisited

• Again: What is the impact of VB to VT?

+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

77

Body effect revisited (cont’d)

• Let us lower VB (such that VB<VS)
• Equivalent with reducing VBS=VB-VS or
increasing VSB=VS-VB
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

B
reduces potential in
p –substrate
78

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Body effect revisited (cont’d)

• Means we need larger VG
to form n-channel!
• Threshold voltage
VT increases S
-
+
V GS
G
D

n+ n+

n-channel Depletion
Region
p-substrate

79

Other explanation
• If we lower VB, then depletion region at
source and drain grows  think reverse
biased pn-junctions (diodes)
• Charge gets pulled S
-
+
V GS
G
D

out of channel
n+ n+
to depletion region
n-channel Depletion
• Requires larger VGS p-substrate
Region

to undo that effect B

80

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Summary of body effect

• Reducing VB such that VB<VS is equivalent
to reducing VBS or increasing VSB
• VSB means threshold voltage VT
• VSB means threshold voltage VT
• Opposite behavior for VBS

81

The graph
0.9

0.85

0.8

0.75
(V)

0.7
VVT (V)

0.65
T

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
-VSB=VBS (V)BS

increasing VSB reduces VBS ,

which increases VT
82

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Why should we care?

• The body effect can be used to
– Make switching faster (reducing VT)
– Reduce static power consumption
due to leakage (increasing VT):

• normal operation:
 connect B with S
• standby operation:
 lower VBS

83
Image taken from: http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html

Today’s devices are tiny!

Short-channel effects

84

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Modern transistors are tiny

10nm likely to be the realistic limit

for standard Si based devices
85
Image taken from: https://theglobalscientist.com/2014/04/07/the-next-big-step-in-computers-what-can-physics-offer-us/

How about short-channel devices?

-4
L<0.25µm
x 10
2.5

VGS= 2.5 V
early saturation
2

VGS= 2.0 V
1.5
linear relation
ID (A)

1
VGS= 1.5 V for fixed VDS

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)
86

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Velocity saturation
• Velocity of carriers
saturates due to
scattering (collisions)

• For L=0.25µm
NMOS, only VDS
2V
is sufficient to reach
velocity saturation

87
Image taken from: http://ic.sjtu.edu.cn/ic/dic/wp-content/uploads/sites/10/2013/04/CMOS-VLSI-design.pdf

Effects of velocity saturation

10 • Short-channel device
enters saturation
before VDS=VGS-VT
• Saturation current
IDS(sat) shows linear
dependence with VGS
0

• Vsat more pronounced in NFET than PFET

88

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(First-order model)

• Carrier velocity can be modeled as:

• We can redo the calculations for the resistive

and saturation region (not important)
89

Improved FET models this term

lowers the
carrier
mobility
• Resistive (linear) region: VGS-VT>VDSat

• (Velocity) saturation region: VGS-VT<VDSat

VDSat=κ(VGT)*VGT, VGT=VGS-VT 90

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ID vs. VGS characteristics

-4
x 10 x 10
-4
6 2.5

5
2

4
linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS (V) VGS (V)

long channel short channel

91

Short-channel PFET
• Once, again: polarities of all voltages and
currents reversed
-4
x 10
0
V GS = -1.0V

-0.2
V GS = -1.5V

-0.4
ID (A)

V GS = -2.0V
-0.6

-0.8
V GS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
92
Image taken from: http://spongebobia.com/spongebob-captures/gallery.php?prod=009b

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What happens if VGS<VT?

Subthreshold conduction

93

Another look at ID vs. VGS curves

-4
long channel short channel
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)

1
2

1 0.5
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS (V) VGS (V)

current does not drop

abruptly to 0 for VGS<VT 94

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Subthreshold conduction (leakage)

• FETs are conducting partially for VGS<VT
• Parasitic bipolar transistor

n+ n+

Body
• Two diode equations:

95

Subthreshold conduction (cont’d)

• Undesirable effect: 10-2

linear region
– Current flowing when
transistor should be quadratic region
off
• Affects dynamic subthreshold
circuits (DRAMs) exponential
region
• Affects static power
consumption 10-12 VT
WHY?
0 0.5 1 1.5 2 2.5
VGS (V)
96

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They will affect the dynamic behavior!

FET capacitances
and resistances

97

MOSFET capacitance model

G

CGS CGD

S D

CSB CGB CDB

B
• We are typically interested in modeling this
as a single capacitance CG
Image taken from: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f10/Lectures/Lecture11- 98
MOS_Cap_Delay-6up.pdf

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Gate capacitance*
polysilicon gate

Source Drain
W
n+ xd xd n+

gate-bulk
Ld
overlap
lateral top view
diffusion
gate oxide
tox
n+ L n+ overlap capacitances;
no big deal in deep
cross section submicron technology!
*The gate capacitance is necessary to form the channel; all other capacitances are parasitic and not needed.
Image taken from: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f10/Lectures/Lecture11- 99
MOS_Cap_Delay-6up.pdf

C’s depend on operation regime!

VGS<VT VGS>VT+VDS VGS<VT+VDS
G G G

CGC CGC CGC

S D S D S D

Region CGB CGS CGD CG

Subthreshold CoxWL 0 0 CoxWL + 2CoW
Linear 0 CoxWL/2 CoxWL/2 CoxWL + 2CoW
Saturation 0 2/3CoxWL 0 2/3CoxWL + 2CoW
Co=overlap cap.
often ignored
• Important regions are saturation and subtreshold
100

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Junction (diffusion) capacitances

• Caused by reverse-biased source-body

and drain-body pn-junctions
• Nonlinear (voltage N A+ channel-stop implant

dependent) side wall

source
W
ND

bottom

xj side wall
channel
Image taken from: LS substrate NA
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f10 101
/Lectures/Lecture11-MOS_Cap_Delay-6up.pdf

Parasitic resistances

• Drain-source on resistance (RDSon)

Polysilicon gate
Drain
contact
LD
W

n+ n+

Drain

channel resistance Body parasitic resistance

from channel to
contact RC

102

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Challenges of deep-submicron devices

Nanometer transistors

103

Threshold variations
• For deep submicron devices, threshold voltage
becomes function of (small) L, W, and VDS

• Depletion regions of source and drain junction

cannot be ignored anymore VT
– parts of gate already depleted
Long-channel threshold
– reduces VT

L
104

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Threshold variations (cont’d)

• Increasing VD increases width of drain
pn-junction depletion region
– decreases VT: approximate model VT=VT0 – λdVDS
– known as drain-induced barrier lowering (DIBL)
– Not that critical for digital circuits
VT

• If VDS exceeds certain low V DS threshold

voltage: D-S shortened
– called punch-through
– permanent device damage!
VDS
105

Gate leakage
• High electric field can cause tunneling
through gate oxide (insulator)
• Becomes an issue for L=100nm and below
(static power consumption)

high capacitance

http://ixbtlabs.com/articles2/intel-65nm/
106

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Hot carrier effects

• Threshold voltage drifts over time
• Electrons (and holes) can tunnel into the
gate oxide at 1V/µm
– VT increases for NMOS
– VT decreases for PMOS

• Causes long-term reliability issues

107

CMOS latch-up

• Parasitic bipolar transistors

– If one of the bipolar transistors is forward
biased, current flows into other BJT
– Positive feedback  circuit fails
• Rnwell and Rpwell must be minimized!
– provide additional well and substrate
contacts close to source connections 108
Image taken from: https://en.wikipedia.org/wiki/Latch-up

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They will be very useful later

Pass transistors

109

Pass transistor*
• We assumed that VS is on GND
• What if VS>0? E.g., transistor passing VDD

• If VG-VT<VS then
VG=VDD NFET is off
G • NMOS cannot pull
VD=VDD
S D
Vout? higher than VDD-VTn
• PMOS pull no lower
than |VTp|
110
*You should think that there is a big resistor pulling D down to ground.

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Pass transistor (cont’d)

• NMOS cannot pull higher than VDD-VTn
• Simple formula for NMOS:

VG=VDD
G

D S
Vin Vout?

• NFET is a bad pull up (max VDD-VT)

• PFET is a bad pull down (min VT)
111

Pass-transistor delay
VG=VDD
G

D S
Vin Vout
time constant:
Ron
Vin
Cload
but they can be very
cheap switches!

• Pass transistors can be slow,

especially if load capacitance is large
112

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Things to remember

Recap MOSFET

113

Recap: MOSFET
NMOS
saturation region

linear region

quadratic increase in VGS

for long channel FETs,
linear for short channels

FET almost off if VGS<VT

VGS-VT=VDS

114

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Things to remember: NFET/NMOS

• FETs are “switches”; almost off when VGS<VT
• Operating regimes
– linear (resistive) regime: VGS-VT>VDS
– saturation regime: VGS-VT<VDS
• Channel-length modulation
• Short-channel effects: velocity saturation
– transistor earlier in saturation regime
– VGS has linear relationship on ID
• Subthreshold conduction 
115

Square law equations of long NMOS

• Linear (resistive or triode) regime

VGS > VT
VDS < VGS-VT

• Saturation regime
VGS > VT
VDS > VGS-VT

• Subthreshold regime
VGS < VT
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117

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