From Nand to Tetris

Building a Modern Computer from First Principles

Lecture 1

Boolean Logic

These slides support chapter 1 of the book

The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press, 2021

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 1
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 2
 Boolean values

off

on

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 3
 Boolean values

off no false 0

on yes true 1

George Boole
Different labels, all referring to two possible states.
1815 - 1864

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 4
 Boolean values

b1 b0
• 1 binary variable: 2 possible states

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 5
 Boolean values

b1 b0
• 1 binary variable: 2 possible states
• 2 binary variables: 4 possible states

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 6
 Boolean values

b2 b1 b0
• 1 binary variable: 2 possible states
• 2 binary variables: 4 possible states

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 7
 Boolean values

... b2 b1 b0
• 1 binary variable: 2 possible states
• 2 binary variables: 4 possible states
• 3 binary variables: 8 possible states
• ...

Question: How many different states can be

represented by N binary variables?

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 8
 Boolean values

... b2 b1 b0
• 1 binary variable: 2 possible states
• 2 binary variables: 4 possible states
• 3 binary variables: 8 possible states
• ...

Question: How many different states can be

represented by N binary variables?
Answer: 2N

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 9
 Boolean functions

x y f
0 0 0
0 1 0
1 0 0
1 1 1

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 10
 Boolean functions

x y f
0 0 0
0 1 0
1 0 0
1 1 1

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 11
 Boolean functions

x
x y f f(x,y)
y f
0 0 0
0 1 0
1 0 0 1 when x == 1 and y == 1
f(x,y) =
1 1 1 0 otherwise

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 12
 Boolean functions

x
x y And And (x, y)
y And
0 0 0
0 1 0
1 0 0 1 when x == 1 and y == 1
And(x,y) =
1 1 1 0 otherwise

Boolean function
A function that operates on boolean variables, and returns a boolean value

Simple boolean functions (like And):

• Sometimes called operators
• Their variables are called operands
• 𝑓(𝑥, 𝑦) can also be written as 𝑥 𝑓 𝑦

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 13
 Boolean functions
x And y x Or y Not(x)
x y And x y Or x Not
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

x Nand y x Xor y xfy

x y Nand x y Xor x y f
0 0 1 0 0 0 0 0 v1

0 1 1 0 1 1 ... 0 1 v2

1 0 1 1 0 1 1 0 v3

1 1 0 1 1 0 1 1 v4

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 14
 Boolean functions
x And y x Or y Question:
x y And x y Or How many Boolean functions
x f y exist over two binary
0 0 0 0 0 0
(2-valued) variables?
0 1 0 0 1 1
1 0 0 1 0 1
Answer: 16
!
N binary variables span 2!
1 1 1 1 1 1
Boolean functions.

x Nand y x Xor y xfy

x y Nand x y Xor x y f
0 0 1 0 0 0 0 0 v1

0 1 1 0 1 1 ... 0 1 v2

1 0 1 1 0 1 1 0 v3

1 1 0 1 1 0 1 1 v4

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 15
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 16
 The expressive power of Nand

Observations Thus:
• Not ( x ) = x Nand x • Not can be realized using Nand
• x And y = Not ( x Nand y) • And can be realized using Nand
• x Or y = Not(Not(x) And Not(y)) • Or can be realized using Nand
• (De Morgan)

Theorem: Any Boolean function can be realized using only Nand.

Proof : Any Boolean function can be expressed as a truth table. Any truth table can be
expressed as a Boolean function using only Not, And, and Or (synthesized as a DNF,
Disjunctive Normal Form). Combined with the above observations, Q.E.D.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 17
 The expressive power of Nand
Theorem: Any Boolean function can be realized using only Nand.

Conclusion: Any computer can be built from Nand gates only:

Computers:
Machines that realize
Boolean functions:
f (input bits) = output bits

OK, so we can build a computer from Nand gates only.

But… how can we actually do it?

That’s what the Nand to Tetris course is all about!

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 18
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 19
 Logic gates

• Elementary gates (Nand, And, Or, Not, …)

• Composite gates (Mux, Adder, …)

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 20
 Elementary gates

And

if (a==1 and b==1) if (a==1 and b==1)

then out=0 else out=1 then out=1 else out=0

if (a==1 or b==1) if (in==0)

then out=1 else out=0 then out=1 else out=0

Why focus on these particular gates?

• Because either {Nand} or {And, Or, Not} (as well as other subsets of
Boolean operators) can be used to span any given Boolean function
• Because they have efficient hardware implementations.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 21
 Elementary gates

And

if (a==1 and b==1) if (a==1 or b==1)

then out=1 else out=0 then out=1 else out=0

Circuit implementations (conceptual):

And circuit
Or circuit

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 22
 Composite gates

And3

if (a==1 and b==1 and c==1)

then out=1 else out=0

Possible implementations:
Physical Logical

• This course does not deal with physical implementations

• (circuits, transistors,... that’s EE, not CS)

• We’ll focus on logical implementations.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 23
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 24
 Building a chip

a
Xor out ?
b

if ((a == 0 and b == 1) or (a == 1 and b == 0))

out = 1
else
out = 0 (an arbitrary image found on the Internet)

The process
• Design the chip architecture
• Specify the architecture in HDL
• Test the chip in a hardware simulator
• Optimize the design
• Realize the optimized design in silicon.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 25
 Building a chip

a
Xor out ?
b

if ((a == 0 and b == 1) or (a == 1 and b == 0))

out = 1
else
out = 0 (an arbitrary image found on the Internet)

The process
ü Design the chip architecture
ü Specify the architecture in HDL
ü Test the chip in a hardware simulator
• Optimize the design
• Realize the optimized design in silicon.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 26
 Design: Requirements

a a b out
Xor out 0 0 0
Requirement
b
0 1 1 Build a chip that
delivers this
if ((a == 0 and b == 1) or (a == 1 and b == 0)) 1 0 1
functionality
out = 1 1 1 0
else
out = 1

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
// Missing implementation
Xor (a = , b = , out = );
...

HDL stub file

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 27
 Design: Implementation
a
a out
b
And
Gate diagram
in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
// Missing implementation
Xor (a = , b = , out = );
...

HDL stub file

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 28
 Design: Implementation
a
a out
b
And
Gate diagram
in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
// Missing implementation
Xor (a = , b = , out = );
...

HDL stub file

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 29
 Design: Implementation
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
// Missing implementation
Xor (a = , b = , out = );
...

HDL stub file

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 30
 Design: Implementation
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
Not (in=a, out=nota);
Not (in=b, out=notb); Xor (a = , b = , out = );
And (a=a, b=notb, out=aAndNotb); ...
And (a=nota, b=b, out=notaAndb);

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 31
 Design: Implementation
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
Not (in=a, out=nota);
Not (in=b, out=notb); Xor (a = , b = , out = );
And (a=a, b=notb, out=aAndNotb); ...
And (a=nota, b=b, out=notaAndb);

}
Question: What is the missing HDL line?

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 32
 Design: Implementation
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */ /** Chips set (APIs): */
CHIP Xor { ...
IN a, b; Not (in = , out = );
OUT out;
And (a = , b = , out = );
PARTS:
Or (a = , b = , out = );
Not (in=a, out=nota);
Not (in=b, out=notb); Xor (a = , b = , out = );
And (a=a, b=notb, out=aAndNotb); ...
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 33
 Interface / Implementation
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

/** out = (a And Not(b)) Or (Not(a) And b)) */

gate CHIP Xor {
interface IN a, b; A logic gate has:
OUT out;
PARTS: • One interface
Not (in=a, out=nota);
gate Not (in=b, out=notb);
• Many possible
Implement And (a=a, b=notb, out=aAndNotb); implementations
-ation And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 34
 Hardware description languages

Observations

• HDL: a functional / declarative language

• An HDL program can be viewed as a textual specification of a chip diagram

• The order of HDL statements is insignificant.

/** out = (a And Not(b)) Or (Not(a) And b)) */

CHIP Xor {
IN a, b;
OUT out;
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 35
 Hardware description languages

Common HDLs Our HDL

• VHDL • Captures the essence of other HDLs
• Verilog • Minimal and simple
• … • Provides all you need for this course
• Documentation:
The Elements of Computing Systems / Appendix 2: HDL

/** out = (a And Not(b)) Or (Not(a) And b)) */

CHIP Xor {
IN a, b;
OUT out;
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 36
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 37
 Hardware simulation (in a nutshell)

CHIP Xor {
IN a, b;
OUT out;
HDL code hardware
PARTS: simulator
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
load
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}

Simulation options

• Interactive

• Script-based.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 38
 Interactive simulation

1. Load an
HDL program

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 39
 Interactive simulation

3. evaluate the
1. Load an
chip logic
HDL program

4. inspect
output pins
2. manipulate
input pins

5. inspect
internal pins

HDL code

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 40
 Hardware simulation in a nutshell

CHIP Xor {
IN a, b;
OUT out;
HDL code
PARTS:
Not (in=a, out=nota);
load
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb); hardware
load Xor.hdl,
Or (a=aAndNotb, test script
b=notaAndb, out=out);
simulator
} output-file And.out,
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;

Simulation options

• Interactive

• Script-based.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 41
 Script-based simulation
Xor.hdl Xor.tst
CHIP Xor {
load Xor.hdl;
IN a, b;
OUT out; set a 0, set b 0, eval;
set a 0, set b 1, eval;
PARTS: set a 1, set b 0, eval;
Not (in=a, out=nota); set a 1, set b 1, eval;
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
test script = sequence of
}
commands to the simulator

Benefits:

• “Automatic” testing

• Replicable testing.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 42
 Script-based simulation, with an output file
Xor.hdl Xor.tst
CHIP Xor {
IN a, b;
load Xor.hdl,
tested
OUT out; output-file Xor.out,
chip output-list a b out;
PARTS: set a 0, set b 0, eval, output;
Not (in=a, out=nota); set a 0, set b 1, eval, output;
Not (in=b, out=notb);
set a 1, set b 0, eval, output;
And (a=a, b=notb, out=aAndNotb);
set a 1, set b 1, eval, output;
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
Xor.out test
script
The logic of a typical test script | a | b |out|
• Initialize: | 0 | 0 | 0 |
| 0 | 1 | 1 |
q Loads an HDL file
| 1 | 0 | 1 |
q Creates an empty output file | 1 | 1 | 0 |
q Lists the names of the pins whose
values will be written to the output file Output File, created
by the test script,
• Repeat:
as a side-effect of the
q Set (inputs) – eval (chip logic) – output (print) simulation process

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 43
 Script-based simulation

1. Load a
test script

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 44
 Script-based simulation

2. run
1. Load a
the script
test script

test
script

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 45
 Script-based simulation

inspect the
2. run output file
1. Load a
the script
test script

test
script
Xor.out
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
HDL | 1 | 1 | 0 |
code

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 46
 Script-based simulation
Xor.hdl Xor.tst

CHIP Xor { load Xor.hdl,

IN a, b; output-file Xor.out,
OUT out; output-list a b out;
set a 0, set b 0, eval, output;
PARTS: set a 0, set b 1, eval, output;
Not (in=a, out=nota);
set a 1, set b 0, eval, output;
Not (in=b, out=notb);
set a 1, set b 1, eval, output;
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
Xor.out
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 47
 Script-based simulation, with a compare file
Xor.hdl Xor.tst

CHIP Xor { load Xor.hdl,

IN a, b; output-file Xor.out,
OUT out; compare-to Xor.cmp,
output-list a b out;
PARTS: set a 0, set b 0, eval, output;
Not (in=a, out=nota);
set a 0, set b 1, eval, output;
Not (in=b, out=notb);
set a 1, set b 0, eval, output;
And (a=a, b=notb, out=aAndNotb);
set a 1, set b 1, eval, output;
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
Xor.out Xor.cmp
Simulation-with-compare-file logic | a | b |out| | a | b |out|
• When each output command is executed, | 0 | 0 | 0 | | 0 | 0 | 0 |
the outputted line is compared to the | 0 | 1 | 1 | compare | 0 | 1 | 1 |
| 1 | 0 | 1 | | 1 | 0 | 1 |
corresponding line in the compare file
| 1 | 1 | 0 | | 1 | 1 | 0 |
• If the two lines are not the same, the
simulator throws a comparison error.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 48
 Script-based simulation, with a compare file
Xor.hdl Xor.tst

CHIP Xor { load Xor.hdl,

IN a, b; output-file Xor.out,
OUT out; compare-to Xor.cmp,
output-list a b out;
PARTS: set a 0, set b 0, eval, output;
Not (in=a, out=nota);
set a 0, set b 1, eval, output;
Not (in=b, out=notb);
set a 1, set b 0, eval, output;
And (a=a, b=notb, out=aAndNotb);
set a 1, set b 1, eval, output;
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
Xor.out Xor.cmp
Demos: | a | b |out| | a | b |out|
Experimenting with Built-In Chips | 0 | 0 | 0 | | 0 | 0 | 0 |
| 0 | 1 | 1 | compare | 0 | 1 | 1 |
Building and Testing HDL-based Chips | 1 | 0 | 1 | | 1 | 0 | 1 |
| 1 | 1 | 0 | | 1 | 1 | 0 |
Script-Based Chip Testing

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 49
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 50
 Multi-bit bus
• Sometimes we wish to manipulate a sequence of bits as a single entity
• Such a multi-bit entity is termed “bus”

Example: 16-bit bus

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1

MSB = Most LSB = Least

significant bit significant bit

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 51
 Working with buses: Example
/* Adds two 16-bit values. */ 16
CHIP Adder { a 16
16-bit
IN a[16], b[16]; out
16 adder
OUT out[16]; b

PARTS:
...
}
/* Adds three 16-bit inputs. */
15 ... 1 0 CHIP Adder3Way {
a: 1 ... 1 1 IN a[16], b[16], c[16];
OUT out[16];
b: 0 ... 1 0
PARTS:
c: 0 ... 0 1 Adder(a= , b= , out= );
Adder(a= , b= , out= );
out: 1 ... 1 0 }

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 52
 Working with buses: Example
/* Adds two 16-bit values. */ 16
CHIP Adder { a 16
16-bit
IN a[16], b[16]; out
16 adder
OUT out[16]; b

PARTS:
...
}
/* Adds three 16-bit inputs. */
15 ... 1 0 CHIP Adder3Way {
IN a[16], b[16], c[16];
n-bit value (bus) can be
a: 1 ... 1 1
OUT out[16]; treated as a single entity
b: 0 ... 1 0
PARTS:
c: 0 ... 0 1 Adder(a=a , b=b, out=ab); Creates an internal
Adder(a=ab, b=c, out=out); bus pin (ab)
out: 1 ... 1 0 }

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 53
 Working with individual bits within buses
/* Returns 1 if a==1 and b==1,
0 otherwise. */
CHIP And {
IN a, b; /* 4-way And: Ands 4 bits. */
OUT out; CHIP And4Way {
... IN a[4];
} OUT out;

3 2 1 0 PARTS:
And(a= , b= , out= );
a: 0 1 1 1
And(a= , b= , out= );
And(a= , b= , out= );
out: 0
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 54
 Working with individual bits within buses
/* Returns 1 if a==1 and b==1,
0 otherwise. */
CHIP And {
IN a, b; /* 4-way And: Ands 4 bits. */
OUT out; CHIP And4Way {
... IN a[4]; Input bus pins can
} OUT out; be subscripted.

3 2 1 0 PARTS:
And(a=a[0], b=a[1], out=and01);
a: 0 1 1 1
And(a=and01, b=a[2], out=and012);
And(a=and012, b=a[3], out=out);
out: 0
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 55
 Working with individual bits within buses
/* Returns 1 if a==1 and b==1,
0 otherwise. */
CHIP And {
IN a, b; /* 4-way And: Ands 4 bits. */
OUT out; CHIP And4Way {
... IN a[4]; Input bus pins can
} OUT out; be subscripted.

3 2 1 0 PARTS:
And(a=a[0], b=a[1], out=and01);
a: 0 1 1 1
And(a=and01, b=a[2], out=and012);
And(a=and012, b=a[3], out=out);
out: 0
}

/* Bit-wise And of two 4-bit inputs */

3 2 1 0
CHIP And4 {
a: 0 1 0 1
IN a[4], b[4];
OUT out[4];
b: 0 0 1 1
PARTS:
out: 0 0 0 1 And(a= , b= , out= );
And(a= , b= , out= );
And(a= , b= , out=. );
And(a= , b= , out= );
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 56
 Working with individual bits within buses
/* Returns 1 if a==1 and b==1,
0 otherwise. */
CHIP And {
IN a, b; /* 4-way And: Ands 4 bits. */
OUT out; CHIP And4Way {
... IN a[4]; Input bus pins can
} OUT out; be subscripted.

3 2 1 0 PARTS:
And(a=a[0], b=a[1], out=and01);
a: 0 1 1 1
And(a=and01, b=a[2], out=and012);
And(a=and012, b=a[3], out=out);
out: 0
}

/* Bit-wise And of two 4-bit inputs */

3 2 1 0
CHIP And4 {
a: 0 1 0 1 Output bus pins
IN a[4], b[4];
OUT out[4]; can be subscripted
b: 0 0 1 1
PARTS:
out: 0 0 0 1 And(a=a[0], b=b[0], out=out[0]); More on busses:
And(a=a[1], b=b[1], out=out[1]);
And(a=a[2], b=b[2], out=out[2]); The Elements of
And(a=a[3], b=b[3], out=out[3]); Computing Systems /
} Appendix 2: HDL

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 57
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 58
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 59
 Built-in chips
We provide built-in versions of the chips built in this course (in tools/builtInChips).
For example:
Xor.hdl Xor.hdl

/** Sets out to a Xor b */ /** Sets out to a Xor b */

CHIP Xor { CHIP Xor {
IN a, b; Implemented IN a, b; Implemented
OUT out; in HDL OUT out; in Java

PARTS: BUILTIN Xor;

Not (in=a, out=nota); // implemented by a Xor.java class.
Not (in=b, out=notb); }
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out); A built-in chip has the same interface
} as the regular chip, but a different
implementation
Behavioral simulation
• Before building a chip in HDL, one can implement the chip logic in a high-level language
• Enables experimenting with / testing the chip abstraction before actually building it
• Enables high-level planning and testing of hardware architectures.
Demo: Loading and testing a built-in chip in the hardrawe simulator

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 60
 Hardware construction projects
Key players:
Architect
q Decides which chips are needed

q Specifies the chips

Developers
q Build / test the chips

In Nand to Tetris:
The architect is the course team; the developers are the students
For each chip, the architect supplies:
q Built-in chip
q Chip API (skeletal HDL program = stub file)
q Test script
q Compare file

Given these resources, the developers (students) build the chips.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 61
 The developer’s view (of, say, a Xor gate)
Xor.hdl Xor.tst

/** Sets out to a Xor b */ load Xor.hdl,

CHIP Xor { stub output-file Xor.out, test
IN a, b; file compare-to Xor.cmp script
OUT out; output-list a b out;
set a 0, set b 0, eval, output;
PARTS: set a 0, set b 1, eval, output;
// Implementation missing set a 1, set b 0, eval, output;
} set a 1, set b 1, eval, output;

compare Xor.cmp
These files specify:
file
• The chip interface (.hdl) | a | b |out|
| 0 | 0 | 0 |
• How the chip is supposed to behave (.cmp) | 0 | 1 | 1 |
| 1 | 0 | 1 |
• How to test the chip (.tst) | 1 | 1 | 0 |

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 62
 The developer’s view (of, say, a Xor gate)
Xor.hdl Xor.tst

/** Sets out to a Xor b */ load Xor.hdl,

CHIP Xor { stub output-file Xor.out, test
IN a, b; file compare-to Xor.cmp script
OUT out; output-list a b out;
set a 0, set b 0, eval, output;
PARTS: set a 0, set b 1, eval, output;
// Implementation missing set a 1, set b 0, eval, output;
} set a 1, set b 1, eval, output;

compare Xor.cmp
These files specify:
file
• The chip interface (.hdl) | a | b |out|
| 0 | 0 | 0 |
• How the chip is supposed to behave (.cmp) | 0 | 1 | 1 |
| 1 | 0 | 1 |
• How to test the chip (.tst) | 1 | 1 | 0 |

The developer’s task:

Implement the chip (complete the supplied .hdl file),
using these resources.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 63
 Project 1

abstraction

machine
language

assembler p6

abstraction p4 p5
hardware platform
building a p2 p3
computer abstraction
computer building p1
ALU, RAM abstraction
chips building
elementary d
logic gates gates Nan

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 64
 Project 1

abstraction

machine
language

assembler p6

abstraction p4 p5
hardware platform
building a p2 p3
computer abstraction
computer building p1
ALU, RAM abstraction
chips building
elementary d
logic gates gates Nan

Project 1
Build 15 elementary logic gates

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 65
 Project 1
Given: Nand
Goal: Build the following gates:

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Why these 15 particular gates?

• Commonly used gates
• Comprise all the elementary logic gates needed to build our computer.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 66
 Project 1
Given: Nand
Goal: Build the following gates:

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 67
 Multiplexor / Demultiplexor

if (sel == 0) if (sel == 0)
out = a {a, b} = {in, 0}
else else
out = b {a, b} = {0, in}

Widely used in:

• Hardware design
• Communications networks.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 68
 Example 1: Using Mux logic to build a programmable gate
a b sel out
0 0 0 0
0 1 0 0
When sel == 0
1 0 0 0 the gate acts like an And gate
1 1 0 1
0 0 1 1
if (sel == 0)
0 1 1 1 When sel == 1
out = a And b
1 0 1 1 the gate acts like an Or gate
else
out = a Or b 1 1 1 0

Mux.hdl
CHIP AndMuxOr {
IN a, b, sel;
OUT out;

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 69
 Example 1: Using Mux logic to build a programmable gate
a b sel out
0 0 0 0
0 1 0 0
When sel == 0
1 0 0 0 the gate acts like an And gate
1 1 0 1
0 0 1 1
if (sel == 0)
0 1 1 1 When sel == 1
out = a And b
1 0 1 1 the gate acts like an Or gate
else
out = a Or b 1 1 1 0

Mux.hdl
CHIP AndMuxOr {
IN a, b, sel;
OUT out;

PARTS:
And (a=a, b=b, out=andOut);
Or (a=a, b=b, out=orOut);
Mux (a=andOut, b=orOut, sel=sel, out=out);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 70
 Example 2: Using Mux logic to build an interleaved channel

source destination

The sel inputs feed from

oscillators that produce
alternating 0 and 1 signals

• Enables transmitting multiple messages simultaneously using a single,

shared communications line
• Conceptual, and unrelated to this course.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 71
 Multiplexor
a b sel out sel out
0 0 0 0 0 a abbreviated
0 1 0 0 1 b truth table
1 0 0 1
1 1 0 1

if (sel == 0) 0 0 1 0
out = a 0 1 1 1
else 1 0 1 0
out = b 1 1 1 1

Mux.hdl

CHIP Mux {
IN a, b, sel; Implementation tip
OUT out;
Can be implemented from And, Or, Not.
PARTS:
// Put your code here:
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 72
 Demultiplexor
in sel a b
if (sel == 0) 0 0 0 0
{a, b} = {in, 0} 0 1 0 0
else 1 0 1 0
{a, b} = {0, in} 1 1 0 1

• The “inverse” of a multiplexor

• Routes the single input value to one of two possible destinations

DMux.hdl
CHIP DMux {
IN in, sel;
OUT a, b; Implementation tip
PARTS: Simple truth table, simple implementation.
// Put your code here:
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 73
 Project 1

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 74
 Project 1

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 75
 And16
Example:
a = 1 0 1 0 1 0 1 1 0 1 0 1 1 1 0 0
b = 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0

out = 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0

CHIP And16 {
IN a[16], b[16];
Implementation tip
OUT out[16];
A straightforward 16-bit extension
PARTS: of the elementary And gate
// Put your code here:
(See the HDL documentation
}
about working with multi-bit buses).

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 76
 Project 1

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 77
 Project 1

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 78
 16-bit, 4-way multiplexor

sel[1] sel[0] out

0 0 a
0 1 b
1 0 c
1 1 d

Mux4Way16.hdl
CHIP Mux4Way16 {
IN a[16], b[16], c[16], d[16],
sel[2];
OUT out[16]; Implementation tip:
PARTS: Can be built from Mux16 gates.
// Put your code here:
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 79
 Chapter 1: Boolean logic

Theory Practice Project 1

• Basic concepts • Logic gates • Introduction

• Nand • HDL • Chips

• Hardware simulation • Guidelines

• Multi-bit buses

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 80
 Project 1

Elementary 16-bit Multi-way

logic gates variants variants
q Not q Not16 q Or8Way
q And q And16 q Mux4Way16
q Or q Or16 q Mux8Way16
q Xor q Mux16 q DMux4Way
q Mux q DMux8Way
q DMux

How to actually build these gates?

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 81
 Files
Xor.cmp
a
Xor out a b out
For every chip built in the course
b 0 0 0
0 1 1 (using Xor as an example), we supply
if ((a == 0 and b == 1) or 1 0 1
(a == 1 and b == 0)) 1 1 0
these three files
sets out = 1
else
sets out = 0

Xor.hdl (stub file) Xor.tst

CHIP Xor { load Xor.hdl,

IN a, b; output-file Xor.out,
OUT out; compare-to Xor.cmp,
PARTS: output-list a b out;
// Put your code here set a 0, set b 0, eval, output;
} set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 82
 Files
Xor.cmp
a The contract:
Xor out a b out
b 0 0 0 When running your Xor.hdl on the
0 1 1
1 0 1
supplied Xor.tst,
if ((a == 0 and b == 1) or
(a == 1 and b == 0)) 1 1 0 your Xor.out should be the same as
sets out = 1
else the supplied Xor.cmp
sets out = 0

Xor.hdl (stub file) Xor.tst

Project 1 folder
CHIP Xor { load Xor.hdl,
IN a, b; output-file Xor.out, (.hdl, .tst, .cmp files):
OUT out; compare-to Xor.cmp, nand2tetris/projects/01
PARTS: output-list a b out;
// Put your code here set a 0, set b 0, eval, output; Tools:
} set a 0, set b 1, eval, output; • Text editor
set a 1, set b 0, eval, output; (for completing the .hdl files)
set a 1, set b 1, eval, output;
• Hardware simulator:
nand2tetris/tools

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 83
 Chip interfaces
a
a out
b
And

in out aAndNotb
Not
notb
a
Or out
b
out
Not nota
in out
notaAndb
a
out
And
b
b

CHIP Xor {
IN a, b;
OUT out; If I want to use some chip-parts,
PARTS: how do I figure out their signatures?
Not (in= , out= );
Not (in= , out= );
And (a= , b=, out=);
And (a= , b=, out=);
Or (a= , b=, out=);
}

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 84
 Chip interfaces: Hack chip set API
Open the Hack chip set API in a window, and copy-paste
Add16 (a= ,b= ,out= );
chip signatures into your HDL code, as needed
ALU (x= ,y= ,zx= ,nx= ,zy= ,ny= ,f= ,no= ,out= ,zr= ,ng= );
And16 (a= ,b= ,out= );
And (a= ,b= ,out= ); Mux8Way (a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= ,sel= ,out= );
Aregister (in= ,load= ,out= ); Mux (a= ,b= ,sel= ,out= );
Bit (in= ,load= ,out= ); Nand (a= ,b= ,out= );
Not16,pc=
CPU (inM= ,instruction= ,reset= ,outM= ,writeM= ,addressM= (in=);,out= );
DFF (in= ,out= ); Not (in= ,out= );
DMux4Way (in= ,sel= ,a= ,b= ,c= ,d= ); Or16 (a= ,b= ,out= );
DMux8Way (in= ,sel= ,a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= ); Or8Way (in= ,out= );
DMux (in= ,sel= ,a= ,b= ); Or (a= ,b= ,out= );
Dregister (in= ,load= ,out= ); PC (in= ,load= ,inc= ,reset= ,out= );
FullAdder (a= ,b= ,c= ,sum= ,carry= ); PCLoadLogic (cinstr= ,j1= ,j2= ,j3= ,load= ,inc= );
HalfAdder (a= ,b= ,sum= , carry= ); RAM16K (in= ,load= ,address= ,out= );
Inc16 (in= ,out= ); RAM4K (in= ,load= ,address= ,out= );
Keyboard (out= ); RAM512 (in= ,load= ,address= ,out= );
Memory (in= ,load= ,address= ,out= ); RAM64 (in= ,load= ,address= ,out= );
Mux16 (a= ,b= ,sel= ,out= ); RAM8 (in= ,load= ,address= ,out= );
Mux4Way16 (a= ,b= ,c= ,d= ,sel= ,out= ); Register (in= ,load= ,out= );
ROM32K (address= ,out= );
Mux8Way16 (a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= ,sel= ,out= );
Screen (in= ,load= ,address= ,out= );
Xor (a= ,b= ,out= );

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 85
 Built-in chips

CHIP Foo {
IN ...;
OUT ...; Q: How can I play with / use a chip-part before implementing it?
PARTS: A: The simulator features built-in chip implementations
...
Bar(...)
...
}

Forcing the simulator to use a built-in chip, say Bar:

• Typically, Bar.hdl will be either a given stub-file, or a file that has an incomplete implementation
• If you want to use Bar as a built-in chip:
Remove the file Bar.hdl from the project folder (or rename it, say, Bar1.hdl)
• The result: Whenever Bar will be mentioned as a chip-part in some chip definition, the simulator
will fail to find Bar.hdl in the current folder. This will cause the simulator to invoke the built-in
version of Bar instead.

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 86
 Project 1

Guidelines: project 1 guidelines

Files: nand2tetris/projects/01 (on your PC)

Tools
• Text editor (for completing the given .hdl stub-files)
• Hardware simulator: nand2tetris/tools (on your PC)

Guides
• Hardware simulator tutorial
• HDL guide
• Hack chip set API

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 87
 Best practice advice
• Implement the chips in the order in which they appear in the project guidelines
• If you don’t implement some chips, you can still use them as chip-parts in other
chips (use their built-in implementations)
• You can invent additional, “helper chips”; However, this is not necessary.
Implement and use only the chips that the architects (we) specified
• In each chip implementation, strive to use as few chip-parts as possible
• When defining 16-bit chips, the same chip-parts may appear many times.
That’s fine, use copy-paste-edit.

That’s It!
Go Do Project 1!

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 88
 What’s next?

abstraction

machine
language

assembler p6

abstraction p4 p5
hardware platform
building a p2 p3
computer abstraction
computer building p1
ALU, RAM abstraction
chips building
elementary d
logic gates gates Nan

This project / chapter:

We build 15 elementary logic gates

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 89
 What’s next?

abstraction

machine
language
Next:
We’ll build chips that do arithmetic,
assembler p6
ending up with an ALU,
using the chips built in project 1

abstraction p4 p5
hardware platform
building a p2 p3
computer abstraction
computer building p1
ALU, RAM abstraction
chips building
elementary d
logic gates gates Nan

This project / chapter:

We build 15 elementary logic gates

Nand to Tetris / www.nand2tetris.org / Chapter 1 / Copyright © Noam Nisan and Shimon Schocken Slide 90