H

Vout

FIGURE 4.13 Non-inverting type nMOS super buffer.

with VDD on its gate, that is, with twice the average voltage that would
tied to the source as in the conventional nMOS inverter. Now, since apply
if the gate was

the effective Ves will increase the current and thus reduce the delay in lá, Ves
a then doubling
on the output, so that more symmetrical transitions are achieved. charging any capacitance
The corresponding non-inverting nMOS
super buffer circuit is given atFigure 4.13 and,
to put matters in perspective, the structures shown when realized in 5 um technology are
capable of driving loads of 2 pF with 5 nsec rise-time.
Other nMOS arrangements such as those based on the native
transistor, and known as
native super buffers, may be used, but such processes are not
reaqily avaitaole-te thedesigner
and are mentioned here only briefly.
VIST
4.8.3 BiCMOS Drivers LIBRARY
The availability of bipolar transistors in BiCMOS
ACC.Mo:J&laz.
technology presents the poss161ny or
bipolar transistor drivers as the output stage of inverter and logic gate circuits. We have
using
already seen (Chapter 2) that bipolar transistors have transconductance gm and current/area
A characteristics that are
greatly superior to those of MOS devices. This indicates high
Current drive capabilities for small areas in silicon.
Bipolar transistors have an exponential dependence of the output current I on the input
ase to emitter voltage Vbe This means that the device can be operated with much smaller
uput voltage swings than MOS transistors and still switch relatively large currents. Thus,
Oupolar transistors have a much better switching performance, primarily as a result of the
URaller input voltage swings. Only a small amount of charge must be moved during switching.
O n e point to consider is the possible effect of temperature T on the required input
agebeAlthough Vse is logarithmically dependent on base width WB, doping level Na
electron mobility
thron mob H, and collector current Ie it is only linearly dependent on T. This means
n e r e is no difficulty in matching Vhe values across a circuit, spread over an area on chip,
 102 Essentials of VLSI Circuits and Systems
as the temperature differences across a chip will not be sufficient to cause more than afew
millivolts of difference in Vse between any two bipolar transistors.
The switching performance of a transistor driving a capacitive load may be
initially from the simple model given in Figure 4.14.
visualized
VDD

Vout

Note: The time

Vss
necessary to change the output voltage by an amount that is equal
change is given by to theinnid
where At CUgm
9m device transconductance.
FIGURE 4.14 Driving ability of bipolar transistor.
It may be shown that the
time At necessary to
amount equal to the input change the output voltage Vout by an
voltage Vin is given by

Sm
where gm is the transconductance of the
bipolar transistor.
Clearly, since the bipôlar transistor has a relatively high transconductance,
At is small. the value of
A more exacting
appraisal of the bipolar transistor delay reveals that it
main components: comprises two
1. Tin an initial time necessary to
charge the base emitter junction of the bipolar
transistor. Typically, for the BiCMOS
transistor-based driver we are
("pn
is in the region of 2ns. A
similar consideration of a CMOS considering
technology would reveal a figure of 1Ins for Titransistor
same BiCMOS driver in
taken to charge the input this
gate capacitance. As a matter of interest, a therable being
figure for a GaAs driver is around 50-100 compa
2. ps.
TL-the time taken to charge the output load
this time is less for the capacitance C, and it will be noteu that
bipolar driver by a factor of he, where polar
transistor gain. he is the Dip
Although the bipolar transistor has a
higher value of Tin, T, is smaller
the
faster charging rate as discussed. becau
 Basic Circuit Concepts (103

The combined effect of Tin and T, is represented in it will be seen that

Figure 4.15 and
there is a critical value of load capacitance Clerin below which the BiCMOS driver is slower
a comparable CMOS driver,
than

Delay T

---- CMOS
slope

BICMOS

siope hte
T

Cuar Load capacitance C

Delay of BiCMOS inverter can be described by
T Tn +(VIIG) (1/h) CL
where
Tn time to charge up base/emitter junction
hre transistor current gain (common emitter)
Delay for BICMOS inverter is reduced by a factor of he compared with a CMOS inverter.
FIGURE 4.15 Delay estimation.

A further significant parameter contributing to delay is the collector resistance R, ofa

bipolar transistor. Clearly a high value for Re will mean a long propagation delay through the
transistor when charging a capacitive load. The effect can be assessed from Figure 4.16,
which shows typical delay values at two values of C, for a range of collector resistance R.
The reason for including the buried subcollector region in the BiCMOS process is to keep
Ras low as
possible.
BiCMOS fabrication processes produce reasonably good bipolar transistors-high gm
gn 6, high hfe and low R-without compromising or overelaborating the basic CMOS
cESS. The availability of bipolar transistors in logic gate and driver/buffer design provides
great deal of scope and freedom for the VLSI
designer.
 CSSGI
104
Delay (pS)

C-1,F
1500

1000

500
C =0.1.F

600 800 1000

200 400
Collector resistance (2)

FIGURE 4.16 Gate delay as a function of collector resistance.

4.9 PROPAGATION DELAYS

4.9.1 Cascaded Pass Transistors

A degree of freedom offered by MOS technology is the use of pass transistors as sees 0r

parallel switches in logic arrays. Quite frequently, therefore, logic signals must pa
through a number of pass transistors in series. A chain of four such transistors is shown
Figure 4.17(a) in which all gates have been shown connected to VpDD (logic 1), which wouu
be the case for a signal to be propagated to the output. The circuit thus formed may t
modeled as in Figure 4.17(b) and it is then possible to evaluate the delay through
network.
The response at node V2 with respect to time is given by

cC dt
-1)=-B)-(-K)
R
resin
In the limit as the number of sections in such a network becomes large, tnis
c
reduces to

Rc4 d>y
dt dx

where
R =
resistance per unit length
C =
capacitance per unit length
x =
distance along network frôm input.
 Basic Circuit Concepts 105
(a)

OV
Vin Vout

VpD

(b) A V2 A

Vout

C C C C

FIGURE 4.17 Propagation delays in pass transistor chain.

time for signal to propagate distance x is such that

The propagation t, a a

p 2

and Cs lumped together, then

The analysis can be simplified if all Rs are

R1otalnrR,

Ctotal ndC,
R, and gives the relative
relative resistance per section in terms of
c
where r gives the
capacitance per section in terms of C .
delay ta for n sections is given by
Then, it may be shown that overall
Tan'rc(t)
no more than four pass
Thus, the overall increases rapidly as n increases and in practice
delay be exceeded
transistors should be normally connected
in series. However, this number can
time
i a buffer is inserted between each group
of four pass transistors or if relatively long
delays are acceptable.

Wires
4.9.2 Design of Long Polysilicon
distributed series R and C as was
the case for cascaded
LOng polysilicon wires also contribute also bee
propagation is slowed down. This would
ass transIstors and, in consequence, signal
the value of C may be quite high, and for this
reason
where
C Case for wires in diffusion signals in diffusion except over very
short distances.
Csgner is discouraged from running buffers is recommended. In general, the
use of
of
Tor
long polysilicon runs, the use
effects. First, the signal
propagation
has two desirable
d r i v e long polysilicon
runs
noISe.
reduction in sensit1vity to
Speeded up and, second, there is a
 106 LEssentials of VLSI Circuits and Systems

The reason why noise may be a problem with slowly rising signals may be d.
considering Figure 4. 18. In the diagram the slow rise-time of the signal at the inpub duced by
inverter (to which the signal emerging from the long polysilicon line is connected ohe
that the input voltage spends a relatively long time in the vicinity of Viny So thn
disturbances due to noise will switch the mverter state between °0" and '1' as shounal|
wn at
the
output point.

Vinv
-

Long polysilicon wire

Note: Vnv = Inverter threshold

FIGURE 4.18 Possible effects of delays in long polysilicon wires.

Thus it is essential that long polysilicon wires be driven by suitable buffers to guard
against the effects of noise and to speed up the rise-time of propagated signal edges

4.10 WIRING CAPACITANCES

In section 4.5 we considered the area capacitances associated with the layers to substrate and
from gate to channel. However, there are other significant sources of capacitance whieh
contribute to the overall wiring capacitance. Three such sources are discussed below.

4.10.1 Fringing Fields

Capacitance due to fringing field effects can be a major component of the overall capacitane
of interconnect wires. For fine line
metallization, the value of fringing field capacitance(C
can be of the same order as that of the area
into

capacitance.
Thus, be Cr should ta
account if accurate prediction of performance is needed.

C Esi02eo
4d
 Basic Circuit Concepts
(107
where
I= Wire length
I thickness of wire
d wire to substrate separation
Then. total wire capacitance

C-Carra+ C
4.10.2 Interlayer Capacitances
Quite obviously the parallel plate effects are present between
example. thought
some the matter will confirm the fact
on
one layer and another. For
that, for a given area, metal to
polysihcon capacitance must be higher than metal to substrate. The reason for not taking
such effects into account for simple calculations is that the
effects occur only where layers
cross or when one layer underlies another, and in consequence
interlayer capacitance is
highly dependent on layout. However, for regular structures it is
readily calculated and
contributes significantly to the accuracy of circuit modeling and delay calculation.

4.10.3 Peripheral Capacitance

The source and drain n-diffusion
with the p-substrate or
regions (n-active regions for Orbit processes) form junctions
p-well well-defined and uniform depths; similarly for p-diffusion
at
p-active) regions n-substrates or n-wells. For diffusion
in
has associated with it
regions, each diode thus formed
which, in
a
peripheral (side-wall) capacitance in picofarads per unit length
total, can be considerably
greater than the area capacitance of the diffusion region
to
substrate; the smaller the source or drain area, the greater becomes the relative value of
the peripheral capacitance.
For Orbit
processes, the n-active and
p-active regions are formed by impurity implant at the
Surface of the silicon and
thus, having negligible depth, they have negligible peripheral
However, for n- and p-regions formed by a diffusion process, the capacitance.
simportant and becomes particularly so as we peripheral capacitance
n order to
shrink the device dimensions.
calculate the total diffusion capacitance we must add the contributions
area and of
peripheral components
Ctotal area periph
ypical values follow in Table 4.3. For further considerations on
cader is
referred to Arpad Barna,
capacitive etfects the
VHSIC-Technologies and Tradeotfs, Wiley, 1981.
TaBLE 4.3 TyPiCAL VALUES FOR DIFFUSION CAPACITANCES
Dffusion capaciuance lypical values
2 um 1.2 um
Area C(area)
(as in
Table 4.2) 1.0x *
3.75 x 10 pF/um*
10 * pk/um 1.75 x 10 pF/um*
Periphery (Cperiph) 8.0x 10 " pF/um negligible* negligible*
Assuming mplanted regions of negligible
depth.
 108
CHARACTERISTICS

4.11 FAN-IN AND FAN-OUT

that deal with speed of transie.

have covered some of the basic concepts
Now that we
influence the operational speed of a gate needs to be considere d. These
additional factors that

are
fan-in (its number of inputs)
metal tracks connected to its Outn
fan-out (the number of gates and length of )
The delay associated with fan-in and fan-out for three technologies is illustrated
that the fan-in curve fol
Figure 4.19 by the way of an example. Figure 4.19 highlights
a linear behavior, indicating that as number of inputs to a gate increase the increase in dela
associated with that gate follows a uniform linear path.

0.7 um
10 . 0.5 um
0.35 um

6 =~---
...

0
0 2 4 6 8 10
FIGURE 4.19 Fan-in and fan-out
Characteristics.
However, the fan-out curve shows that the as
the

number of loads being driven delay follows an path

exponential pogate deloy
by the output of the gate is increased. Thus, tne
substantially increases for a high number of fan-out.