07.09.

2023

Semester: III
Mathematics for AV Communication
Course Code: BEA301 CIE Marks: 50
Teaching Hours/Week (L:T:P) L: T:P:S: 3:0:0:0 SEE Marks: 50
Credits: 3 Total Marks 100
Hours: 40 SEE Duration: 3 Hrs.
Course Learning Objectives: The students will be able to
Apply discrete and continuous probability distributions in analyzing the probability
1
models arising in engineering field.
Understand the concepts of Complex variables and transformation for solving
2
Engineering Problems.

3 Apprehend and apply Fourier Series.

4 Demonstrate FourierTransformasatoolforsolvingIntegralequations
5 Realize and use of Z-Transforms

Module-1
Probability Theory: Random variables (discrete and continuous), probability 8 Hrs
density function, cumulative density function.
Probability Distributions: Binomial distribution, Poisson distribution. Normal
distribution, Exponential distribution.
Joint probability distributions.
Self-study: Discrete and continuous probability problems
Applications: Discrete and continuous probability distributions help in analysing
the probability models arising in engineering field.
Video Link:
1. http://nptel.ac.in/courses.php?disciplineID=111
Module-2
Complex Variables: Functions of complex variables, Analytic function, Cauchy- 8 Hrs
Riemann equations in Cartesian and polar coordinates,Construction of analytic
function (Using Milne-Thomson method)
Consequences of Cauchy-Riemann equations, Properties of analytic functions.
Application to flow problems- complex potential, velocity potential, equipotential
lines, stream functions, stream lines.
Self-study: Unique Expression Method
Applications: Application to flow problems
Video Link:
1. http://nptel.ac.in/courses.php?disciplineID=111
Module-3
Fourier Series: Periodic functions, Dirichlet’s condition, Fourier series of 8 Hrs
periodic functions with period2π and arbitrary period2c. Fourier series of even and
odd functions. Half range Fourier Series, Practical harmonic Analysis
andProblems.
 07.09.2023

Self study: Complex form of Fourier series.

Applications:TheFourierserieshasmanysuchapplicationsinharmonicanalysis,vibrat
ionanalysis,acoustics, opticsetc.
Video Link:
1. http://nptel.ac.in/courses.php?disciplineID=111
Module-4
Fourier Transforms:Infinite Fourier transform, Infinite Fourier sine and cosine 8 Hrs
transforms, Inverse Fourier transforms, Inverse. Fourier sine and cosine transforms,
Convolution theorem

Self-study: Complex form of Fourier series.

Applications: Fourier transforms used in image
Video Link:
1. http://nptel.ac.in/courses.php?disciplineID=111
Module-5
Z-Transforms: Definition, standard Z-transforms, properties of Z- transforms- 8 Hrs
Shifting property, Reversal property, Multiplication by n, initial value and final
value theorems. Inverse Z- transform, convolution theorem (proof and problems)
Application of Z-transforms to solve difference equations.
Self-study: Damping rule and problems on them.
Applications: Fourier transforms used in image processing and Z-transforms in Digital
signal processing.

Video Link:
1. http://nptel.ac.in/courses.php?disciplineID=111

Course Outcomes: After completing the course, the students will be able to
CO Apply discrete and continuous probability distributions in analyzing the probability
1 models arising in engineering field.
CO Use the concepts of analytic function and complex potentials to solve the problems
2 arising in electromagnetic field theory
CO KnowtheuseofperiodicsignalsandFourierseriestoanalyzecircuitsandsystem.
3
CO Demonstrate FourierTransformasatoolforsolvingIntegralequations.
4
CO Learn to evaluate Z-transform to solve difference equations.
5

Reference Books
1. B.S. Grewal, “Higher Engineering Mathematics” Khanna Publishers, 44th Edition, 2013.

2. Erwin Kreyszig, “Advanced Engineering Mathematics”, Wiley-India publishers,

10thedition, 2014.
 07.09.2023

3. Bali N. P. & Manish Goyal, “A text book of Engineering Mathematics”, Laxmi

Publications, 8th Edition
4. Ramana B. V., “Higher Engineering Mathematics”, Tata Mc Graw-Hill, 2006.

Continuous Internal Evaluation (CIE):

Theory for 50 Marks
CIE is executed by way of quizzes (Q), tests (T) and assignments. A minimum of three quizzes are
conducted along with tests. Test portion is evaluated for 50 marks and quiz is evaluated for 10
marks. Faculty may adopt innovative methods for conducting quizzes effectively. The number of
quizzes may be more than three (conduct additional quizzes and take best three). The three tests are
conducted for 50 marks each and the average of all the tests are calculated for 50. The marks for the
assignments are 20 (2 assignments for 10 marks each). The marks obtained in test, quiz and
assignment are added to get marks out of 100 and report CIE for 50 marks.

Semester End Examination (SEE):

Total marks: 50+50=100

SEE for 50 marksis executed by means of an examination. The Question paper for each course
contains two parts, Part – A and Part – B. Part – A consists of objective type questions for 20
marks covering the entire syllabus. Part – B Students have to answer five questions, one from each
unit for 16 marks adding up to 80 marks. Each main question may have a maximum of three sub
divisions. Each unit will have internal choice in which both questions cover entire unit having
same complexity in terms of COs and Bloom’s taxonomy level.
CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 0 3 0 0 0 0 0 0 0 1
CO2 3 3 0 3 0 0 0 0 0 0 0 1
CO3 3 3 0 2 0 0 0 0 0 0 0 1
CO4 3 3 0 3 0 0 0 0 0 0 0 1
CO5 3 2 0 3 0 0 0 0 0 0 0 1
Analysis and Design of Digital Circuits Semester III
(Theory and Practice)
Course Code 22EA302 CIE Marks 50
Teaching Hours/Week (L:T:P) 3 +2 Hours/Week (L:T:P: 3:0:2) SEE Marks 50
Total Hours of Pedagogy 40 L+ 26 P Total Marks 100
Credits 4 3+3
Exam Hours
Hrs
Examination type (SEE) Theory + Practical

Course objectives:
 Familiarize with the simplification techniques & design various combinational digital circuitsusing
logic gates.
 Introduce the analysis and design procedures for synchronous and asynchronous sequential
circuits.
 07.09.2023

 Analysing & designing different applications of Combinational & Sequential Circuits

 Analysing & designing sequential circuits using SR, JK, D, T flip-flops and Mealy & Moore machines
 Know the importance of programmable devices used for designing digital circuits.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: Number systems, Boolean Algebra, Logic Gates, Comparison of Combinational & Sequential
Circuits.
Principles of combinational logic: Introduction, Canonical forms, Generation of switching equations from
truth tables, Karnaugh maps-3, 4 variables, Incompletely specified functions (Don‘tcare terms), Quine-
McClusky techniques- 3 & 4 variables.

Module-2
Prerequisites: Decoder, Encoders, Multiplexers & Demultiplexer
Design and Analysis of combinational logic: Full Adder & Subtractors, Parallel Adder and Subtractor, Look
ahead carry Adder, Binary comparators, Decoders & Multiplexers as minterm/maxterm Generator.

Module-3
Prerequisites: SR, JK, D, T flipflops
Flip-Flops and its Applications: Latches and Flip Flops, Master-slave JK flip-flop, Timing concerns in
sequential circuits, Shift Registers – SISO, SIPO, PISO PIPO, Universal shift register, Counters – Synchronous
and Asynchronous.
Module-4
Sequential Circuit Design: Characteristic equations, Design of a synchronous mod-n counter using clocked
JK, D, T and SR flip-flops, Melay& Moore Models

Module-5
Applications of Digital Circuits:
Design of a Sequence Detector, Guidelines for construction of state graphs, Design Example – Code
Converter, Design of Binary Multiplier, Design of Binary Divider.
 07.09.2023

Programmable Logic Devices: PLA, PAL, FPGA.

LABORATORY EXPERIMENTS
1. Verify
a) The sum-of product expression using universal gates.
b) The product-of-sum expression using universal gates.
2. Design and implement
(a) Full Adder using basic logic gates.
(b) Full subtractor using basic logic gates.
3. Design and implement
4-bitParallelAdder/ Subtractor using IC 7483.
4. Design and implement BCD to Excess-3 code conversion and vice-versa using IC 7483.
5. Realize
(i) Adder & Subtractors using IC 74153
6. Realize 4-variable function using IC 74151(8:1MUX)
7. Realize the following flip-flops using NAND Gates.
(a) Clocked SR Flip-Flop
(b) JK Flip-Flop
8. Design and implement the following flip-flops using NAND Gates
(a) D-Flip-Flop
(b) T-Flip-Flop
9. Realize the following shift registers using IC7474
(a)SISO (b) SIPO (c) PISO (d) PIPO
10 Realize the following shift registers using IC7474
(a) Ring Counter (b) Johnson Counter.
11. Realize
(a) Mod-N Counter using IC7490
Virtual Lab Links: http://vlabs.iitkgp.ernet.in/dec/
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Illustrate simplification of Algebraic equations using K-map & Quine-McCluskey Technique.
2. Design the combinational logic circuits.
3. Analyse& design different applications of Combinational & Sequential Circuits to meet desired
need within realistic constraints.
4. Design the sequential circuits using SR, JK, D, T flip-flops and Mealy & Moore machines
 07.09.2023

5. Know the importance of programmable devices used for designing digital circuits.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. John M Yarbrough, “Digital Logic Applications and Design”, Thomson Learning, 2001.
2. Donald D. Givone, “Digital Principles and Design”, McGraw Hill, 2002.
 07.09.2023

3. Charles H Roth Jr., Larry L. Kinney ―Fundamentals of Logic Design, CengageLearning, 7th Edition.
4. Morris Mano, ―Digital Design, Prentice Hall of India, Third Edition.

Web links and Video Lectures (e-Resources):

 https://nptel.ac.in/courses/117108040/
 https://nptel.ac.in/courses/117106086

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Study of Logic Gates – NOT, OR, AND, NOR, NAND, XOR and XNOR.
2. Design a 4-bit Binary to Gray code converter using logic gates.
3. Design 4-bit comparator using IC7485.
4. Realize a Boolean expression using decoder IC74139
5. Design a Synchronous Counter for a given sequence- 0, 2, 4, 6, 0

6. 6. Designing of sequence detector using necessary digital components.

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 1 1 - - - - - - - 2
CO2 1 - - - 3 - - - - - - 2
CO3 1 2 3 - 1 - - - - - - 2
CO4 1 2 2 2 - - - - - - - 1
CO5 1 1 1 - 2 - - - - - - 1
High-3, Medium-2, Low-1

Analog Electronic Circuits (Theory and Lab) Semester III

Course Code BEA303 CIE Marks 50
Teaching Hours/Week (L: T:P) 3+2 Hours/Week (L:T:P: 3:0:2) SEE Marks 50
Total Hours of Pedagogy 40L+26 P Total Marks 100
Credits 4 3+3
Exam Hours
Hrs
Examination type (SEE) Theory+ Practical

Course objectives:
 To know low frequency response for various configurations of BJT and FET amplifier.
 Understand the different topologies of feedback amplifiers and oscillators.
 Analyse the Power amplifier circuits in different modes of operation
 Sketch and explain typical Frequency Response graphs for each of the Filter circuits and switching
circuits of Op-Amps and analyse its operations.
 Differentiate between various types of DACs and ADCs, Timer IC’s and evaluate the performance
of each with neat circuit diagrams.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: Operation ofTransistor
Transistor Biasing:
Fixed bias circuits, Emitter stabilized biased circuits, Voltage divider biased circuits.
Transistor at Low Frequencies: BJT transistor modeling, CE Fixed bias configuration, Voltage divider bias,
Emitter follower, Analysis of circuits re model.

Module-2
Prerequisites: Working of JFET
FET Amplifiers: JFET small signal model, Fixed bias configuration, Voltage divider configuration,
Common Gate configuration,
Feedback Amplifier: The Four Basic Feedback Topologies, The series-shunt, series-series, shunt-shunt and
shunt-series amplifiers.

Module-3
Oscillators: Oscillator operation, FET based Phase shift oscillator, Wien bridge oscillator, LC and Crystal
Oscillators.
Output Stages and Power Amplifiers: Introduction, Classification of output stages, Class A output stage,
Class B output stage: Transfer Characteristics, Power Dissipation, Power Conversion efficiency, Class AB
output stage, Class C tuned Amplifier.

Module-4
OP-Amps as DC Amplifiers: Direct coupled voltage followers, Non-inverting amplifiers, inverting
amplifiers.
Op-Amps as AC Amplifiers: Capacitor coupled voltage follower, Capacitor coupled non inverting
amplifiers, Capacitor coupled inverting amplifiers, Capacitor coupled difference amplifier.

Module-5
Op-Amp Circuits: DAC - Weighted resistor and R-2R ladder, ADC- Successive approximation type, Active
Filters, First and second order low-pass and high-pass Butterworth filters, Band-pass filters, Band reject
filters.
 07.09.2023

555 Timer and its applications: Mono-stable and Astable Multivibrators.

Laboratory Experiments
1. Design and set up the RC coupled Single stage BJT amplifier and determine the
gain-frequency response, input and output impedances
2.Design an oscillator with tank circuit having two inductances and one capacitance and compare the
practical frequency with theoretical frequency.
3.Design an oscillator with tank circuit having two capacitance and one inductance and compare the
practical frequency with theoretical frequency.
4. Design an Oscillator using FET whose tank circuit produces a total phase shit of 180 and calculate the
frequency of output waveform.
5. Design an oscillator whose frequency is 2MHZ and compare with the theoretical frequency.
6. Find a suitable power amplifier that removes the cross over distortion and calculate the efficiency
7. Design active second order Butterworth low pass filters.
8. Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP
values and obtain the hysteresis.
9.Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input
from toggle switches and (ii) by generating digital inputs using mod-16 counter.
10. Design Astable Multivibrator using 555 Timer.
11. Design Monostable Multivibrator using 555 Timer.
12. To set up and study a triangular waveform generator using Op-amp for 1kHz frequency .
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Analyse the DC biasing & frequency response of BJT Amplifier and FET amplifier
2. Design various Feedback amplifiers.
3. Evaluate the efficiency of power amplifiers and working of oscillator.
4. Describe DC amplifier, AC Amplifiers and its application.
5. Acquire knowledge about Active Filters, DAC, ADC and Timer.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Robert L.Boylestad and louis Nashelsky, “Electronic Devices and circuit Theory”, PHI/Pearson
Education,11 TH Edition.
2. Adel S Sedra, Kenneth C Smith “Microelectronic Circuits, Theory and Applications”, 6th Edition,
Oxford, 2015.ISBN:978-0-19-808913-1.
3. Behzad Razavi, “Fundamentals of Microelectronics”, John Weily ISBN 2013 978-81- 265-2207-8,2nd
Edition, 2013.
4. K.A.Navas, “Electronics Lab Manual”, Volume I, PHI, 5th Edition, 2015, ISBN: 9788120351424.
5. “Operational Amplifiers and Linear IC‟s”, David A. Bell, 2nd edition, PHI/Pearson, 2004. ISBN 978-81-
203-2259-9.
 07.09.2023

6. “Linear Integrated Circuits”, D. Roy Choudhury and Shail B. Jain, 4th edition, Reprint 2006, New Age
International ISBN 978-81-224-3098-1.

Web links and Video Lectures (e-Resources):

 http://www.nptelvideos.in/2012/12/electronics.html
 https://onlinecourses.nptel.ac.in/noc23_ee77
 https://nptel.ac.in/courses/108102112
 https://archive.nptel.ac.in/courses/108/106/108106084/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Demonstrate a simple light circuit that uses a decade counter to drive two traffic lights and uses
555 timer chips as clock.
2. Design and find the gain of a Differential Amplifier.
3. Plot the frequency response using any class of power amplifier

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 2 1 - - - - - 1
CO2 3 3 3 2 2 1 - - - - - 1
CO3 3 3 3 2 2 1 - - - - - 1
CO4 3 3 3 2 2 1 - - - - - 1
CO5 3 3 3 2 2 1 - - - - - 1
High-3, Medium-2, Low-1

NETWORK ANALYSIS Semester III

Course Code BEA304 CIE Marks 50
Teaching Hours/Week (L: T:P) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Describe basic network concepts emphasizing source transformation source shifting, mesh
and nodal techniques to solve for resistance/impedance, voltage, current and power.
 Explain network Thevenin‘s, Millman‘s, Superposition, Reciprocity, Maximum Power transfer
and Norton‘s Theorems and apply them in solving the problems related to Electrical Circuits.
 Describe Series and Parallel Combination of Passive Components as resonating circuits, related
parameters and to analyze frequency response.
 Explain the behavior of networks subjected to transient conditions. Use applications of Laplace
transform to solve network problems.
 Study two port network parameters like Z, Y, T and h and their inter-relationships.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: Ohm’s law, Kirchhoff's laws
Basic Concepts: Introduction, Practical sources, Source transformations, Star – Delta transformation, Loop
and node analysis with linearly dependent and independent sources for DC networks, Concepts of super
node and super mesh.

Module-2
Graph Theory and Network equations: Graph of a network, Trees, Co-trees and Loops, Incidence Matrix,
Cut-set Matrix, Tie-set Matrix and loop currents, Number of possible trees of a graph, Analysis of
networks, Duality.

Module-3
Network Theorems: Superposition Theorem, Millman‘s theorem, Thevenin‘s and Norton‘s theorems,
Reciprocity theorem, Maximum Power transfer theorem.

Module-4
Prerequisites: Laplace Transforms, Properties of Laplace Transform and Inverse Laplace Transform using
partial fraction method.
Transient behaviour and initial conditions: Behaviour of circuit elements under switching condition and
their Representation, evaluation of initial and final conditions in RL, RC and RLC circuits for DC excitations,
Applications of Laplace Transforms in circuit analysis.

Module-5
 07.09.2023

Two port network parameters: Introduction, open circuit impedance parameter, short circuit admittance
parameter, hybrid parameters, transmission parameter, relationship between parameters.

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Determine currents and voltages in a circuit using network simplification techniques.
2. To solve the network problems using graphical methods.
3. To simplify the complex circuits using network theorems.
4. To analyze simple DC circuits and applies the concepts to transient conditions.
5. Solve the given network using specified two port network parameters like Z or Y or T or h and
Evaluate frequency response related parameters through the RLC elements, in resonant circuits.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. M.E. Van Valkenberg (2000), “Network analysis”, Prentice Hall of India, 3rd edition, 2000, ISBN:
9780136110958.
2. Roy Choudhury, “Networks and systems”, 2nd edition, New Age International Publications, 2006,
ISBN: 9788122427677.
3. Hayt, Kemmerly and Durbin ―Engineering Circuit Analysis”, TMH 7th Edition, 2010.
4. J. David Irwin /R. Mark Nelms, “Basic Engineering Circuit Analysis”, John Wiley, 8th edition, 2006.

Web links and Video Lectures (e-Resources):

 07.09.2023

 https://archive.nptel.ac.in/courses/108/105/108105159/
 https://nptel.ac.in/courses/108105159
 https://onlinecourses.nptel.ac.in/noc22_ee07
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
1. Plot the frequency response characteristics for a series RL, RC circuit.
2. Verify superposition theorem for a given circuit.
3. Measure two port parameters for a given network

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 2 1 - - - - - 1
CO2 3 3 3 2 2 1 - - - - - 1
CO3 3 3 3 2 2 1 - - - - - 1
CO4 3 3 3 2 2 1 - - - - - 1
CO5 3 3 3 2 2 1 - - - - - 1
High-3, Medium-2, Low-1

Analog and Digital Electronics Laboratory Semester III

Course Code BEAL305 CIE Marks 50
Teaching Hours/Week (L: T:P: S) 2 Hours/Week (L:T:P: 0:0:2) SEE Marks 50
Total Hours of Pedagogy 20 Total Marks 100
Credits 1 Exam Hours 3 Hrs
Examination type (SEE) Practical

Course objectives:
 Demonstrate various circuits using PSPICE and verify functionality.
 To be exposed to the operation and application of electronic devices and their circuits.
 To analyze circuit characteristics with signal analysis using Op-amp ICs.
 Familiarize with Modern EDA tool such as Verilog.
 Acquire knowledge on different types of description in Verilog.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

PART A
 07.09.2023

Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus, CircuitLab or any other equivalent
tool can be used)

1. Monostable Multivibrator using 555 Timer.

2. Astable Multivibrator using 555 Timer.
3. RC Phase shift oscillator.
4. Inverting Schmitt Trigger.
5. Narrow Band-pass Filter and Narrow band-reject filter
6. Precision full-wave rectifier.

PART B
Simulate the following using Verilog Code
1. Write a Verilog program for 2 to 4 decoder.
2. Write a Verilog program for 8 to 3 encoder (without priority & with priority)
3. Write Verilog code to convert 4 bit binary to gray code.
4. Write a Verilog code for 8 to 1 multiplexer
5.Write Verilog code of Comparator
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Demonstrate various circuits using PSPICE and verify functionality.
2. Design and test of analog circuits using OPAMPs
3. Design and implement basic circuits using IC (OPAMP and 555 timers).
4. Use the modern engineering tool such as Verilog necessary for engineering practice.
5. Write code and verify functionality of digital circuit/system
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books

Web links and Video Lectures (e-Resources):

 07.09.2023

 https://nptel.ac.in/courses/117105147
 https://nptel.ac.in/courses/106105165
 https://onlinecourses.nptel.ac.in/noc20_cs63

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 1 1 - - - - - - - 2
CO2 1 - - - 3 - - - - - - 2
CO3 1 2 3 - 1 - - - - - - 2
CO4 1 2 2 2 - - - - - - - 1
CO5 1 1 1 - 2 - - - - - - 1
High-3, Medium-2, Low-1

Engineering Science Course:

Digital System Design using Verilog Semester III

Course Code BEA306A CIE Marks 50
Teaching Hours/Week (L: T:P: S) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Understand the concepts of Verilog Language
 Study of verilog data flow descriptions.
 Study of design and operation of behavioral programming using verilog
 Understand the concepts of Verilog Structural Language
 Design and diagnosis of verilog circuits using synthesis module.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Introduction to Verilog: Structure of verilog Module, Operators, Data types, Units and ports, Verilog
constructs.

Module-2
Data-Flow Description: Highlights Of Data-Flow Description, Signal Declaration And Assignment Statement
, Constant Declaration and Constant Assignment Statements , Assigning a Delay Time to the Signal-
Assignment Statement

Module-3
Behavioral Description: Behavioral Description Highlights, Structure of the Verilog Behavioral Description ,
Sequential Statements: IF Statement , The case Statement , Verilog casex and casez , The wait-for
Statement , The Loop Statement: For-Loop, While-Loop , Verilog repeat , Verilog forever

Module-4
Structural Description: Highlights of Structural Description, Organization of Structural Description , Half
adder and full adder design using structural description, Half subtractor and full subtractor design using
structural description, generate and parameter (Verilog) , Exercises

Module-5
Synthesis Basics: Highlights of Synthesis, Synthesis Information From Module , Mapping Always in the
Hardware Domain ,Mapping the Signal-Assignment Statement to Gate Level, Mapping Logical Operators,
Mapping the IF Statement, Mapping the case Statement , Mapping the Loop Statement

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Understand verilog programming basics
2. Describe how dataflow description of verilog code works and write simple programs using
dataflow description.
3. Describe how Behavioural description of verilog code works and write simple programs using
dataflow description.
 07.09.2023

4. Design simple circuits using verilog structural description.

5. Synthesize different assign statements and simple applications using verilog.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. HDL WITH DIGITAL DESIGN VHDL AND VERILOG, Nazeih Botros, MERCURY LEARNING AND
INFORMATION Dulles, Virginia Boston, Massachusetts New Delhi, 2015.
 07.09.2023

2. Samir Palnitkar “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second
Edition
3. Charles H Roth Jr., Larry L. Kinney “Fundamentals of Logic Design”, Cengage Learning, 7th Edition

Web links and Video Lectures (e-Resources):

 https://onlinecourses.nptel.ac.in/noc21_ee97
 https://onlinecourses.nptel.ac.in/noc21_ee39
 https://nptel.ac.in/courses/117106114
 https://onlinecourses.nptel.ac.in/noc22_ee38

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Study of Logic Gates – NOT, OR, AND, NOR, NAND, XOR and XNOR.
2. Design a 4-bit Binary to Gray code converter using logic gates.

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 2 - 1 - - 1 - - 1
CO2 3 3 2 2 - 1 - - 1 - - 1
CO3 3 3 2 2 - 1 - - 1 - - 1
CO4 3 3 2 2 - 1 - - 1 - - 1
CO5 3 3 2 2 - 1 - - 1 - - 1
High-3, Medium-2, Low-1

SENSOR AND INSTRUMENTATION Semester III

(Theory)
Course Code BEA306B CIE Marks 50
Teaching Hours/Week (L: T:P: S) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 3 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 To understand the basic concepts of transducers.
 To identify the mathematical model of transducer and its response for various inputs.
 To understand the construction and working principle of resistive type transducers.
 To impart knowledge on capacitive type and inductive type transducer.
 To understand the construction and working principle of sensors and its real time applications.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: knowledge of basic of sensors
General block diagram of measurements systems – Methods of measurements – Classification and
selection of transducers – Error analysis – Statistical methods – Odds and uncertainty, classification of
instruments, applications of measurement systems.

Module-2
Static characteristics – Accuracy, precision, resolution, sensitivity, linearity – Dynamic characteristics –
Mathematical model of transducer – Zero, first and second order transducers – Response for impulse,
step, ramp and sinusoidal inputs

Module-3
Principle of operation – Construction details – Characteristics and application of resistance potentiometer
– Strain gauge – Resistance thermometer – Thermistor – Hot-wire anemometer – Humidity sensor –
Induction potentiometer – Variable reluctance transducers – LVDT.

Module-4
Capacitive transducer and types – Capacitor microphone – Frequency response – Piezoelectric transducer
– Hall effect transducer – Magnetostrictive – Digital transducers – Fiber optic sensors – Thick and thin film
sensors (Bio sensor and chemical sensor)

Module-5
Environmental monitoring sensors (Water quality and air pollution) – Photo electric transducer – Vibration
sensor – Ultrasonic based sensors – Introduction to MEMS and Nanotechnology – Applications –
Robotics – Home appliance.
 07.09.2023

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Choose appropriate sensors for the measurement of various physical parameters.
2. Obtain the mathematical model of the transducer and its response for various inputs.
3. Choose appropriate resistive type transducer for the measurement of various physical
parameters.
4. Select capacitive and inductive type transducers for the measurement of various physical
parameters.
5. Select the suitable type of sensors for real time applications.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
 07.09.2023

1. “A Course in Electrical and Electronics Measurements and Instrumentation”, Sawhney A K, Dhanpat

Rai and Sons, New Delhi, 2013
2. “Sensors and Transducers”, Patranabis D, Prentice Hall of India, Second Edition, 2010
3. “Transducers and Instrumentation”, Murthy D V S, Prentice Hall of India, New Delhi,
4. Second Edition, 2010.

Web links and Video Lectures (e-Resources):

 https://onlinecourses.nptel.ac.in/noc21_ee32
 https://onlinecourses.nptel.ac.in/noc23_ee105
 https://archive.nptel.ac.in/courses/108/105/108105064/
 https://onlinecourses.nptel.ac.in/noc23_ee95/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Displacement versus output voltage characteristics of a potentiometer transducer.
2. Characteristics of Strain gauge.
3. Characteristics of thermocouple.
4. Characteristics of LVDT.

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3 2 2 2 - - - - - 1
CO2 3 3 2 2 1 2 - - - - - 2
CO3 3 3 3 2 2 2 - - - - - 1
CO4 3 2 2 2 2 2 - - - - - 1
CO5 3 2 3 2 2 2 - - - - - 1
High-3, Medium-2, Low-1

COMPUTER ORGANIZATION & ARCHITECTURE (Theory) Semester III

Course Code BEA306C CIE Marks 50
Teaching Hours/Week (L: T:P) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Explain the basic sub systems of a computer, their organization, structure and Operation.
 Illustrate the concept of programs as sequences of machine instructions.
 To understand the different ways of communicating with I/O devices and to introduce memory
types including cache memories.
 Describe memory hierarchy and concept of virtual memory.
 To analyse concepts of Pipelining and other computing systems.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts, Bus
Structures, Software, Performance – Processor Clock, Basic Performance Equation.
Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE standard for
Floating point Numbers, Memory Location and Addresses, Memory Operations, Instructions and
Instruction Sequencing.

Module-2
Prerequisite:Number system
Addressing Modes: Assembly Language, Basic Input and Output Operations, Stacks and Queues,
Subroutines, Additional Instructions.

Module-3
Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and
Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Direct Memory Access, and
Buses.

Module-4
Memory System: Basic Concepts, Semiconductor RAM Memories-Internal organization of memory chips,
Static memories, Asynchronous DRAMS, Read Only Memories, Cash Memories, Mapping Functions,
Replacement Algorithm, Virtual Memories, Secondary Storage-Magnetic Hard Disks.

Module-5
Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple Bus
Organization, Hardwired Control, Micro programmed Control,Pipelining,Basic concepts, Role of Cache
memory, Pipeline Performance
 07.09.2023

Course outcome (Course Skill Set)

At the end of the course, the student will be able to:

1. Identify the functional units of the processor and the factors affecting the performance of a
computer
2. Demonstrate the ability to classify the addressing modes, instructions sets and design programs.
3. Understand the different ways of accessing an input / output device including interrupts.
4. Illustrate the organization of different types of semiconductor and other secondary storage
memories.
5. Illustrate the simple processor organization based on hardwired control and micro programmed
control.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Carl Hamacher, ZvonkoVranesic, SafwatZaky: “Computer Organization”, 6th Edition, Tata McGraw Hill,
2011.
2. Andrew S. Tanenbaum, Todd Austin, “Structured Computer Organization”, 6th Edition, Pearson, 2013.
3. David A. Patterson, John L. Hennessy: “Computer Organization and Design – The Hardware / Software
Interface ARM Edition”, 4th Edition, Elsevier, 2009.
4. William Stallings: “Computer Organization & Architecture”, 7th Edition, PHI, 2006.

Web links and Video Lectures (e-Resources):

 07.09.2023

 https://nptel.ac.in/courses/106105163
 https://nptel.ac.in/courses/106106166
 https://nptel.ac.in/courses/106103180
 https://onlinecourses.nptel.ac.in/noc23_cs67

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Write an ALP to find the sum of two numbers and verify if the sum is an even or odd number and
simulate the output.
2. Study any one input/output device and examine its various input output ports details.
3. Implement and simulate a simple memory unit which is capable of reading and writing data within
a single clock cycle.
4. Evaluate the possible control sequence for implementing a multiplication instruction using
registers for a single bus organization

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 2 - 1 - - 1 - - 1
CO2 3 3 2 2 - 1 - - 1 - - 1
CO3 3 3 2 2 - 1 - - 1 - - 1
CO4 3 3 2 2 - 1 - - 1 - - 1
CO5 3 3 2 2 - 1 - - 1 - - 1
High-3, Medium-2, Low-1
 07.09.2023

Engineering Electro magnetics Semester IV

Course Code BEA401 CIE Marks 50
Teaching Hours/Week (L: T:P) 2 Hours/Week (L:T:P: 2:0:0) SEE Marks 50
Total Hours of Pedagogy 30L Total Marks 100
Credits 2 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Understand the applications of Coulomb’s law and Gauss law to different charge
Distributions.
 Understand the physical significance of Biot-Savart’s Law, Amperes’ Circuital Law and Stokes’
theorem for different current distributions.
 Know the physical interpretation of Maxwell’s equations and its applications in plane waves.
 Understand the concepts of Smith Chart for impedance matching.
 Acquire knowledge on different types of transmission lines.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: Vector Algebra, Coordinate systems (Rectangular Coordinate System, Cylindrical Coordinate
System and Spherical Coordinate System), gradient, divergence and curl
Electrostatics: Coulomb’s Law, Electric Field Intensity, Flux density and potential:
Coulomb’s law , Electric field intensity, Field due to line charge, Field due to Sheet of charge, Field due to
continuous volume charge distribution, Electric flux, Electric flux density, Electric potential, Potential
difference, relation between Electric field intensity (E) & potential (V), potential gradient, Electric dipole,
Energy density in electrostatic fields.

Module-2
Gauss’ law, Divergence, Poisson’s and Laplace’s Equations:
Gauss law, Maxwell’s First equation, Application of Gauss’ law, Divergence theorem, Current, Current
density, Conductor, The continuity equation, Boundary conditions (dielectric-dielectric, conductor-
dielectric, conductor-free space), Poisson’s and Laplace’s Equations, Uniqueness theorem.

Module-3
 07.09.2023

Magnetostatics: Steady Magnetic Field-Biot-Savart Law, Ampere’s circuital law, Curl, Stokes’ theorem,
Gauss’s law for magnetic fields, Magnetic flux and Magnetic flux density, Maxwell’s equations for static
fields, Magnetic Scalar and Vector Potentials.
Magnetic Forces and magnetic materials: Force on a moving charge and differential current element,
Force between differential current elements, Magnetization, magnetic susceptibility, permeability,
Magnetic boundary conditions, Inductances, magnetic energy, magnetic circuit.

Module-4
Time varying Fields and Electromagnetic wave propagation: Time varying fields & Maxwell’s equations,
Faraday’s law, Transformer and Motional Electro - Motive Forces, Displacement current, Maxwell's
equation in differential and integral form, Time varying potentials.
Electromagnetic wave propagation: Derivation of wave equations from Maxwell’s equations, Relation
between E and H, Wave propagation in - lossy dielectrics, lossless dielectrics, free space and good
conductor, skin-effect, Poynting theorem.

Module-5
Transmission line: Introduction, Transmission line parameters, Transmission line equations, input
impedance, standing wave ratio and power, Smith Chart basic fundamentals, types of transmission lines -
coaxial line, strip line, micro strip line.
Applications of transmission line: Impedance matching and tuning: single stub tuning, double stub tuning,
and the quarter wave transformer.
Laboratory Sessions/ Experimental learning: Simulation of micro strip transmission line using FEKO
software.

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Evaluate problems on electrostatic force, electric field due to point, linear, surface charge and
volume charges.
2. Apply Gauss law to evaluate Electric fields due to different charge distributions by using
Divergence Theorem. Determine potential and capacitance using Laplace equation and Poisson
equation.
3. Apply Biot-Savart’s and Ampere’s laws for evaluating Magnetic field for different current
configurations.
4. Apply Maxwell’s equations for time varying fields and evaluate power associated with EM waves
using Poynting theorem.
5. Determine the parameters of transmission lines and use Smith chart for determining the
impedance and admittance.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Matthew N. O. Sadiku, “Elements of Electromagnetics”, Oxford University Press, Edition VII, 2018.
2. David M Pozar, “Microwave Engineering”, John Wiley & Sons, Inc., 4th edition, 2014.
3. W.H. Hayt. J.A. Buck & M Jaleel Akhtar, “Engineering Electromagnetics”, Tata McGraw – Hill, Edition
VIII, 2014.

Web links and Video Lectures (e-Resources):

 https://archive.nptel.ac.in/courses/108/104/108104087/
 https://onlinecourses.nptel.ac.in/noc21_ee83
 https://nptel.ac.in/courses/115101005
 07.09.2023

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Determine the magnetic field intensity at a point due to magnetic field using MATLAB.
2. Determine the parameters of wave using MATLAB.

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 2 1 - - - - - 1
CO2 3 3 3 2 2 1 - - - - - 1
CO3 3 3 3 2 2 1 - - - - - 1
CO4 3 3 3 2 2 1 - - - - - 1
CO5 3 3 3 2 2 1 - - - - - 1

High-3, Medium-2, Low-1

Principles of Communication Systems (Theory and Lab) Semester IV

Course Code BEA402 CIE Marks 50
Teaching Hours/Week (L: T:P) 3+2 Hours/Week (L:T:P: 3:0:2) SEE Marks 50
Total Hours of Pedagogy 40L+26P Total Marks 100
Credits 4 3+3
Exam Hours
Hrs
Examination type (SEE) Theory+ Practical

Course objectives:
 Understand the concepts of Analog Modulation schemes viz; AM, FM.
 Interpret the different types of noise in communication system.
 Learn the concepts of digitization of signals viz; sampling, quantizing, and encoding.
 Analyze the Base Band data transmission system.
 Realize the basic concepts of coherent and non-coherent digital modulation techniques and
 understand the basics of spread spectrum modulation.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites:Modulation,NeedforModulation,andtypesofModulation.

AmplitudeModulation:IntroductiontoAM,Time-Domaindescription,Frequency-
Domaindescription,GenerationofAMwave:SquareLawModulator,switchingmodulator,DetectionofAM
waves:Envelop detector.
Double side band suppressed carrier modulation (DSBSC): Time-Domain description,Frequency-
Domainrepresentation,GenerationofDSBSCwaves:Ringmodulator.CoherentdetectionofDSBSC
 07.09.2023

modulated waves. Costas loop.

SingleSide-BandModulation(SSB):Singleside-bandmodulation,Time-Domaindescription, Frequency-
Domain description of SSB wave, Phase discrimination method forgeneratingan SSBmodulated wave.

Module-2
FrequencyModulation:Basicdefinitions,FM,narrowbandFM,widebandFM,transmission bandwidth of FM
waves, and generation of FM waves: indirect FM and directFM.
DemodulationofFMwaves:Phase-lockedloop,Nonlinearmodelofthephase–lockedloop,Linearmodel ofthe
phase –locked loop,Nonlineareffects inFM systems.
Noise:Introduction,Typesofnoise,NoiseFigure,Equivalentnoisetemperature,NoiseinAMreceivers, Noise
inFM receivers, Superheterodyne receivers.
Module-3
NOISE:ShotNoise,Thermalnoise,WhiteNoise,NoiseEquivalentBandwidth.
NOISEINANALOGMODULATION:Introduction,ReceiverModel,NoiseinDSB-
SCreceivers.NoiseinAMreceivers,Thresholdeffect,NoiseinFMreceivers,Captureeffect,FM threshold effect,
FM threshold reduction, Pre-emphasis, and De-emphasis in FM

Module-4
Inter-symbolInterference&SignalSpacerepresentation:Basebandtransmission:Discrete PAM Signals,
Power spectra of Discrete PAM Signals, Inter Symbol
Interference,NyquistcriterionforDistortionlessBasebandBinaryTransmission,Eyediagram,Geometric
representation of signals, Gram-Schmidt Orthogonalization procedure, Optimumreceiversfor
coherentdetection:CorrelationReceivers andMatchedFilterreceiver.

Module-5
Prerequisites:Probability&RandomProcess
Pass band transmission: Digital modulation techniques: Phase shift Keying
techniquesusingCoherentdetection:Generation,DetectionandErrorprobabilitiesofBPSKandQPSK,QAM,Fr
equency shiftkeying techniquesusingCoherentdetection:BFSKgeneration,detection,and error probability.
Non-coherent orthogonal modulation techniques: BFSK, DPSK Symbol representation,Block diagrams
of Transmitter and Receiver, Probability of error (without derivation ofprobabilityoferrorequation)
PrinciplesofSpreadSpectrumCommunicationSystems:ModelofaSpreadSpectrum,
DigitalCommunicationSystem,DirectSequenceSpreadSpectrumSystems(DSSS),Someapplications of DS
Spread Spectrum Signals, Generation of PN Sequences, FrequencyHoppedSpread Spectrum (FHSS).
 07.09.2023

Lab Experiments

Hardware Experiments

1. AmplitudeModulationandDemodulationusing transistor
2. DSBSC Modulation.
3. Frequencymodulationand FSKusingIC8038/2206
4. Pre-emphasis&de-emphasis
5. Demonstrate sampling and reconstructionPulseAmplitudeModulationandDetection
6. GenerationofPWM/PPM signal
7. GenerationanddetectionofASKWaveform
8. FSK Generation and detection.
9. TDM of two band limited signals.
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Examine the concepts of analog modulation techniques such as amplitude, modulations and its
variations like DSB-SC and SSB-SC.
2. Analyze frequency modulation and compute performance of different types of noise.
3. Apply the concepts of noise in analog modulation and analysis of pre-emphasis and
4. deemphasis circuit.
5. Analyze the signal space representation of digital signals.
6. Evaluate the performance of a baseband and pass band digital communication system.
7. and spread spectrum techniques.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Simon Haykins& Moher, Communication Systems, 5th Edition, John Wiley, India Pvt. Ltd,
2. 2010, ISBN 978 – 81 – 265 – 2151 – 7.
3. Simon Haykins, “An Introduction to Analog and Digital Communication”, John Wiley, 2003.
4. John G Proakis and MasoudSalehi, “Fundamentals of Communication Systems”, 2014
5. Edition, Pearson Education, ISBN 978-8-131-70573-5.
6. B P Lathi and Zhi Ding, Modern Digital and Analog Communication Systems, Oxford
7. University Press., 4th edition, 2010, ISBN: 97801980738002.

Web links and Video Lectures (e-Resources):

 07.09.2023

 https://nptel.ac.in/courses/117/105/117105143/
 https://onlinecourses.nptel.ac.in/noc22_ee05
 https://archive.nptel.ac.in/courses/108/104/108104091/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

1. Analyze constellation of 16-QAM Using MATLAB
2. Eye diagram using MATLAB
3. ASK modulation and demodulation in MATLAB.

CO-POMapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 1 1 - - - - - 1
CO2 3 3 3 2 1 1 - - - - - 1
CO3 3 3 3 2 1 1 - - - - - 1
CO4 3 3 3 2 1 1 - - - - - 1
CO5 3 3 3 2 1 1 - - - - - 1

High-3, Medium-2, Low-1

Modern Control systems Semester IV

Course Code BEA403 CIE Marks 50
Teaching Hours/Week (L: T:P) 3+2 Hours/Week (L:T:P: 3:0:2) SEE Marks 50
Total Hours of Pedagogy 50L Total Marks 100
Credits 04 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Formulate the mathematical modelling of systems and understand the concepts of transfer
function
 Obtain transfer function using block diagram reduction and signal flow graph techniques.
 Analyse the response of first and second order systems using standard test signals and analyse
steady state error.
 Analyse stability of systems using RH criteria, Root Locus, Nyquist, Bode plot and polar plot.
 Obtain state variable model for electrical systems.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
 07.09.2023

Introduction to Control Systems: open loop and closed loop systems, Types of feedback, Differential
equation of Physical Systems – Mechanical Systems, Electrical Systems, Analogous Systems.
Block diagrams and signal flow graphs: Transfer functions, Block diagram algebra and Signal Flow graphs.

Module-2
Time Response of feedback control systems: Standard test signals, Unit step response of First and Second
order Systems. Time response specifications, Time response specifications of second order systems for
underdamped system, steady state errors and error constants.
Introduction to Controllers: P, PI, PD and PID Controllers.

Module-3
Stability analysis using RH Criteria and root locus: Concepts of stability, Necessary conditions for stability,
Routh Hurwitz stability criterion, Relative stability analysis, Introduction to Root-Locus Techniques, the
root locus concepts, Construction of root loci.

Module-4
Stability analysis using Nyquist criteria and Bode plots: Polar plot, Nyquist Stability criterion, Nyquist
plots, Bode plots, Gain and phase margin.

Module-5
Introduction to State variable analysis: Concepts of state, state variable and state models for electrical
systems, Solution of state equations, State transition matrix and its properties.Lag, lead and lag lead
compensation.

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Write the mathematical model for electrical systems and find the transfer function using block
diagram reduction technique and signal flow graph.
2. Analyze transient and steady state response of second order systems using standard test signals
and analyze steady state error.
3. Analyze the stability of the systems by applying RH criteria and root locus techniques.
4. Analyze the stability of the system using frequency domain techniques such as Nyquist and Bode
plots.
5. Write state space equations and solutions of a given electrical system.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Nagarath and M.Gopal, ― Control Systems Engineering‖, New Age International (P) Limited,
Publishers, Fifth edition-2005, ISBN: 81-224-2008-
2. Modern Control Engineering, K.Ogata, Pearson Education Asia/PHI, 4th Edition, 2002. ISBN 978-81-
203-4010-7.
3. Automatic Control Systems‖, Benjamin C. Kuo, John Wiley India Pvt. Ltd., 8th Edition, 2008.

Web links and Video Lectures (e-Resources):

 07.09.2023

 https://archive.nptel.ac.in/courses/107/106/107106081/
 https://onlinecourses.nptel.ac.in/noc20_ee90
 https://www.youtube.com/watch?v=39Ggoj2fQ2c
 https://www.youtube.com/watch?v=5NltqMpJG2k
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 1 1 - - - - - - - -
CO2 3 2 2 1 - - - - - - - -
CO3 3 2 2 2 - - - - - - - -
CO4 3 2 2 2 - - - - - - - -
CO5 3 2 2 1 - - - - - - - -

High-3, Medium-2, Low-1

Communication laboratory Semester IV

Course Code BEAL404 CIE Marks 50
Teaching Hours/Week (L: T:P) 2 Hours/Week (L:T:P: 0:0:2) SEE Marks 50
Total Hours of Pedagogy 26P Total Marks 100
Credits 1 Exam Hours 3 Hrs
Examination type (SEE) Practical

Course objectives:
 To visualize the effects of sampling and TDM
 To Implement AM & FM modulation and demodulation
 To implement PCM & DM
 To simulate Digital Modulation schemes

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

EXPERIMENTS
 07.09.2023

1. Signal Sampling and reconstruction

2. Time Division Multiplexing
3. AM Modulator and Demodulator
4. FM Modulator and Demodulator
5. Pulse Code Modulation and Demodulation
6. Delta Modulation and Demodulation
7. Line coding schemes
8. Simulation of ASK, FSK, and BPSK generation schemes
9. Simulation of DPSK, QPSK and QAM generation schemes
10. Simulation of signal constellations of BPSK, QPSK and QAM
11. Simulation of ASK, FSK and BPSK detection schemes
12. Simulation of Linear Block and Cyclic error control coding schemes
13. Simulation of Convolutional coding scheme
14. Communication link simulation
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Simulate & validate the various functional modules of a communication system.
2. Demonstrate their knowledge in base band signaling schemes through
3. Implementation of digital modulation schemes.
4. Apply various channel coding schemes & demonstrate their capabilities.
5. Towards the improvement of the noise performance of communication system
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books

Web links and Video Lectures (e-Resources):

 https://onlinecourses.nptel.ac.in/noc20_hs15
 https://www.vlab.co.in/ba-nptel-labs-electronics-and-communications
 07.09.2023

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 2 1 1 - - - - - 1

CO2 3 3 3 2 1 1 - - - - - 1

CO3 3 3 3 2 1 1 - - - - - 1

CO4 3 3 3 2 1 1 - - - - - 1

CO5 3 3 3 2 1 1 - - - - - 1

High-3, Medium-2, Low-1

8051 Microcontroller Semester IV

Course Code BEA405A CIE Marks 50
Teaching Hours/Week (L: T:P) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Explain the difference between Microprocessors & Microcontrollers, Architecture of 8051
Microcontroller.
 Write 8051 Assembly level programs using 8051 instructionset
 Explain the Interrupt system, operation of Timers/Counters and Serial port of 8051.
 Interfacing of 8051 to external memory.
 Interface simple switches, simple LEDs, ADC 0804, LCD and Stepper Motor to 8051 using 8051 I/O
ports.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
 07.09.2023

8051 Microcontroller:

Microprocessor Vs Microcontroller, Embedded Systems, Embedded Microcontrollers, 8051 Architecture-

Registers, Pin diagram, I/O ports functions, Internal Memory organization. External Memory (ROM & RAM)
interfacing.

Module-2
8051 Instruction Set:

Addressing Modes, Data Transfer instructions, Arithmetic instructions, Logical instructions, Branch
instructions, Bit manipulationinstructions. Simple Assembly language program examples (without loops) to
use these instructions.

Module-3
8051 Stack, I/O Port Interfacing and Programming:8051 Stack, Stack and Subroutine instructions.
Assembly language program examples on subroutine and involving loops. Interfacing simple switch and
LED to I/O ports to switch on/off LED with respect to switch status.

Module-4
8051 Timers and Serial Port:

8051 Timers and Counters – Operation and Assembly language programming to generate a pulse using
Mode-1 and a square wave using Mode- 2 on a port pin. 8051 Serial Communication- Basics of Serial Data
Communication, RS- 232 standard, 9 pin RS232 signals, Simple Serial Port programming in Assembly and C
to transmit a message and to receive data serially.

Module-5
8051 Interrupts and Interfacing Applications:

8051 Interrupts. 8051 Assembly language programming to generate an external interrupt using a switch,
8051 C programming to generate a square waveform on a port pin using a Timer interrupt. Interfacing
8051 to ADC-0804, DAC, LCD and Stepper motor and their 8051 Assembly language interfacing
programming.
 07.09.2023

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Explain the difference between Microprocessors & Microcontrollers, Architecture of 8051
Microcontroller, Interfacing of 8051 to external memory and Instruction set of 8051.
2. Write 8051 Assembly level programs using 8051 instruction set.
3. Write 8051 Assembly language program to generate timings and waveforms using 8051 timers, to
send & receive serial data using 8051 serial port and to generate an external interrupt using a
switch.
4. Write 8051 Assembly language programs to generate square wave on 8051 I/O port pin using
interrupt and C Program to send & receive serial data using 8051 serial port.
5. Interface simple switches, simple LEDs, ADC 0804, LCD and Stepper Motor to 8051 using 8051 I/O
ports.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.
 07.09.2023

Suggested Learning Resources:

Books
1. The 8051 Microcontroller and Embedded Systems – using assembly and C”, Muhammad Ali Mazidi and
Janice Gillespie Mazidi and Rollin D. McKinlay; PHI, 2006 / Pearson, 2006.
2. “The 8051 Microcontroller”, Kenneth J. Ayala, 3rd Edition, Thomson/Cengage Learning.
3. “The 8051 Microcontroller Based Embedded Systems”, Manish K Patel, McGraw Hill, 2014, ISBN: 978-
93-329-0125-4.
4. “Microcontrollers: Architecture, Programming, Interfacing and System Design”, Raj Kamal, Pearson
Education, 2005.

Web links and Video Lectures (e-Resources):

 https://archive.nptel.ac.in/courses/108/105/108105102/
 https://nptel.ac.in/courses/117104072
 https://nptel.ac.in/courses/108105102
 https://onlinecourses.nptel.ac.in/noc22_ee12

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 2 2 - - - - - 1 1
CO2 3 3 2 3 3 - - - - - 3 2
CO3 3 3 2 3 3 - - - - - 3 1
CO4 3 3 2 2 3 - - - - - 3 1
CO5 3 2 2 3 3 - - - - - 3 2
High-3, Medium-2, Low-1

Data Structures and Algorithms using Python Semester IV

Course Code BEA405B CIE Marks 50
Teaching Hours/Week (L: T:P) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory
 07.09.2023

Course objectives:
 Understand the fundamentals of data structures and their applications in logic building and
project assessment.
 Understand the concept of linked lists and sorting techniques.
 Acquire the knowledge of algorithms of queues and stacks.
 Analyze the concepts of Binary trees.
 To Understand Graphs and its algorithms.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Python Primer: Python Overview, Objects in Python, Expressions, Operators, Control Flow, Functions,
Simple i/p and o/p, Modules.
Basic Concepts of Data Structures and Algorithms: Introduction- Variables, Datatypes, Data Structures,
ADT, what is an algorithm, How to compare algorithms, Rate growth, Types of analysis, Asymptotic
Notation, Performance Analysis: Space complexity, Time complexity, Guidelines for asymptotic analysis.

Module-2
Prerequisites: Programming using the concept of Arrays and pointers
Linked Lists: Definition, Linked list operations: Traversing, Searching, Insertion, and Deletion. Doubly
Linked lists and its operations, Circular linked lists and its operations.
Sorting Techniques: Bubble Sort, Insertion Sort, Selection Sort, Quick Sort and Merge Sort.

Module-3
Stacks: Definition, Stack Implementation using arrays/lists and linked lists, Stack ADT, Stack Operations
(Insertion and Deletion), Array Representation of Stacks, Stack Applications: Infix to postfix conversion,
Tower of Hanoi.
Queues: Definition, Array Representation, Queue Implementation using arrays/lists and linked lists, Queue
ADT, Operations on queues (Insertion and Deletion), Circular Queues and its operations, Priority Queues
and its operations.

Module-4
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Trees: Terminology, Binary Trees, Types of Binary trees, Properties of Binary trees, Array Representation
of Binary Trees, Binary Tree Traversals – Inorder, Postorder, Preorder.
Binary Search Trees – Definition, Insertion, Deletion, Searching, Implementation of Binary tree, Heaps and
Heap Sort, Construction of Expression Trees, AVL Trees.

Module-5
Graphs: Definitions, Terminologies, Matrix and Adjacency List Representation of Graphs, Elementary
Graph operations, Traversal methods: Breadth First Search and Depth First Search, DAG, Minimum
Spanning Trees: Prim – Kruskal algorithm, Single Source Shortest Path: Weighted graphs, Dijkstra
algorithm.

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Acquire knowledge of Python fundamentals and data structures.
2. Analyse and design of algorithms for Linked lists and sorting techniques.
3. Apply the concepts of Stacks and queues.
4. Utilize the operations of search trees and their applications.
5. Understand the concepts of Graphical algorithms.
 07.09.2023

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Rance D Necaise “Data Structures and Algorithms using Python”, Wiley, John Wiley and Sons.
2. Michael T. Goodrich, R. Tamassia and Michael H Goldwasser “Data structures and Algorithms
3. in python”, Wiley student edition, John Wiley and Sons.
4. Narasimha Karumanchi “Data Structures and Algorithmic Thinking with Python”,
5. CareerMonk Publications.

Web links and Video Lectures (e-Resources):

 07.09.2023

 http://www.nptelvideos.com/video.php?id=1442
 https://nptel.ac.in/courses/106105085/

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 2 - 1 - - 1 - - 1
CO2 3 3 2 2 - 1 - - 1 - - 1
CO3 3 3 2 2 - 1 - - 1 - - 1
CO4 3 3 2 2 - 1 - - 1 - - 1
CO5 3 3 2 2 - 1 - - 1 - - 1

High-3, Medium-2, Low-1

Operating System Semester IV

Course Code 22EA405C CIE Marks 50
Teaching Hours/Week (L: T:P) 3 Hours/Week (L:T:P: 3:0:0) SEE Marks 50
Total Hours of Pedagogy 40L Total Marks 100
Credits 03 Exam Hours 3 Hrs
Examination type (SEE) Theory

Course objectives:
 Understand the services provided by an operating system.
 Learn how processes are synchronized and scheduled.
 Identify different approaches of memory management and virtual memory management.
 Study the structure and organization of the file system
 Understand inter process communication and deadlock situations.
 07.09.2023

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

Module-1
Prerequisites: Computer Organization and Architecture
Introduction to Operating Systems: OS, Goals of an OS, Operation of an OS, Program’s, Resource
allocation techniques, Efficiency, System Performance and User Convenience, Classes of operating System,
Batch processing, Multi programming, Time Sharing Systems, Real Time , distributed and modern
Operating Systems.

Module-2
Process Management: OS View of Processes, PCB, Process States and Transitions, Threads, Kernel and
User level Threads, Non-preemptive scheduling- FCFS and SRN, Preemptive Scheduling- RR and LCN, Long
term, medium term and short term scheduling in a time sharing system.

Module-3
Memory Management: Static and Dynamic memory allocation, Contiguous Memory allocation, Non-
Contiguous Memory Allocation, Paging, Segmentation, Segmentation with paging, Virtual Memory
Management, Demand Paging, Paging Hardware, VM handler, Page replacement policies - FIFO, LRU

Module-4
File Systems: File systems and IOCS, Files and File Operations, Fundamental File Organizations, Directory
structures, File Protection, Interface between File system and IOCS, Allocation of diskspace, Implementing
file access, and File sharing schematics.

Module-5
Message Passing and Deadlocks: Overview of Message Passing, Implementing message passing,
Mailboxes, Deadlocks, Deadlocks in resource allocation, Handling Deadlocks, Deadlock detection
algorithm, Deadlock Prevention, Deadlock avoidance-Bankers algorithm.
Course outcome (Course Skill Set)

At the end of the course, the student will be able to :

1. Summarize the goals, structure, operation and types of operating systems.
2. Apply scheduling techniques to find performance factors.
3. Apply suitable techniques for contiguous and non-contiguous memory allocation.
4. Interpret the organization of file systems and IOCS.
 07.09.2023

5. Describe message passing, deadlock detection and prevention methods.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE
minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student is declared as a
pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

 There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
 Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage of the
syllabus. The average of the two tests shall be scaled down to 25 marks
 Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then only
one assignment for the course shall be planned. The schedule for assignments shall be planned
properly by the course teacher. The teacher should not conduct two assignments at the end of the
semester if two assignments are planned. Each assignment shall be conducted for 25 marks. (If two
assignments are conducted then the sum of the two assignments shall be scaled down to 25 marks)
 The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers
for the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 3. sub-questions), should have a mix of topics under that module.
4. The students have to answer 5 full questions, selecting one full question from each module.
5. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Books
1. Abraham Silberschatz, Peter Baer Galvin, Greg Gagne, Operating System Principles 7th edition, Wiley-
India, 2006
2. Ann McHoes Ida M Fylnn, Understanding Operating System, Cengage Learning, 6th Edition
 07.09.2023

3. D.M Dhamdhere, Operating Systems: A Concept Based Approach 3rd Ed, McGraw- Hill, 2013.
4. P.C.P. Bhatt, An Introduction to Operating Systems: Concepts and Practice 4th Edition, PHI(EEE), 2014.
5. William Stallings Operating Systems: Internals and Design Principles, 6th Edition, Pearson.

Web links and Video Lectures (e-Resources):

 https://nptel.ac.in/courses/106/105/106105214/
 https://www.youtube.com/watch?v=qJ_bXhrUOkc&t=12s

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning



CO-PO Mapping
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2 2 2 1 - - 1 - - 1
CO2 3 3 2 2 2 1 - - 1 - - 1
CO3 3 3 2 2 2 1 - - 1 - - 1
CO4 3 3 2 2 2 1 - - 1 - - 1
CO5 3 3 2 2 2 1 - - 1 - - 1

High-3, Medium-2, Low-1