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Design and analysis of folded cascode operational amplifier using 0.13 µm CMOS
technology

Conference Paper in AIP Conference Proceedings · January 2020

DOI: 10.1063/1.5142133

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Design and analysis of folded cascode
operational amplifier using 0.13 µm CMOS
technology
Cite as: AIP Conference Proceedings 2203, 020041 (2020); https://doi.org/10.1063/1.5142133
Published Online: 08 January 2020

Lee Cha Sing, N. Ahmad, M. Mohamad Isa, and F. A. S. Musa

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© 2020 Author(s).
 Design and Analysis of Folded Cascode Operational
Amplifier using 0.13 µm CMOS Technology
Lee Cha Sing1, a), N. Ahmad 1, b), M. Mohamad Isa1, c) and F.A.S. Musa1, d)
1
School of Microelectronic, Universiti Malaysia Perlis, Kampus Pauh Putra, 02600 Arau, Perlis, Malaysia
a)
Corresponding author: [email protected]
b)
[email protected]
c)
[email protected]
d)
[email protected]

Abstract. In this paper, a folded cascode operational amplifier is designed and analysed by using 0.13 μm CMOS
technology. Several analyses such as DC analysis and AC analysis are carried out to analyse the performances of the
proposed folded cascode op-amp. Through the simulation of Mentor Graphics, under 3.3 V power supply, the circuit’ s DC
gain is 32.3590 dB, the phase margin is 83.754 degree with high stability, the bandwidth is larger than 10 MHz, the unity
gain bandwidth is as high as 906.8953 MHz and the power dissipation is 86.9774 mW.

INTRODUCTION
The design of high performance operational amplifier is essential in designing analog integrated circuit due to its
performance which will directly affect the overall performance of circuits and system. In order to obtain high gain and
better performance op-amp, various op-amp topologies have been designed using past CMOS technology with the
downsizing of transistor length of CMOS over year. However, many studies on past technologies have found out that
the performance parameters are still not sufficient enough in order to meet the performance goal. Besides that, it is
also unclear on which circuit topologies could give the maximum performance when using CMOS 0.13μm technology.
Folded cascode is one of the efforts in the field of enhancing the performance of practical op-amp in order to achieve
the characteristics of an ideal op-amp.

The demand for amplifiers with high DC gain and bandwidth is increasing. In a high speed and high-resolution
ADC, operational amplifiers are expected to have both high DC gain and high unity-gain frequency in order to satisfy
the accuracy and fast setting requirements of the system (B. Li, “A High DC Gain Op-Amp for Sample and Hold
Circuits,” Proc. 2nd Int. Conf. Comput. Sci. Electron. Eng. (ICCSEE 2013), vol. 9, no. Iccsee, pp. 1781–1784, 2013).
For high-performance systems, high gain and high unity gain frequency amplifiers are needed to meet the
requirements. It is difficult to satisfy both of these requirements, since high unity gain frequency calls for short channel
devices which lead to a low intrinsic gain while high dc gain is achieved using long-channel devices and multistage
design (L. Ping, “A Fully Differential CMOS Operational Amplifier Implemented with Mos Gain Boosting
Technique,” p. 84, 1996). It is important to ensure that the system can reach high open loop gain and wide unity-gain
bandwidth with low supply voltage in designing analog circuits. In order to implement the negative feedback concept,
the primary requirement is to have a sufficiently large open-loop gain (E. Rajni, “Design of High Gain Folded-Cascode
Operational Amplifier Using 1.25 um CMOS Technology,” Int. J. Sci. Eng. Res., vol. 2, no. 11, pp. 1–9, 2011).

This paper presents the design of a folded cascode op-amp by using 0.13 μm CMOS technology with the Mentor
Graphics pyxis software. This paper is presented as follows: In Folded Cascode Operational Amplifier, the concept of
this topology will be discussed and the circuit design for this work will be presented in Proposed Circuit Design.
Meanwhile, Results and Discussions will be analyzed from the simulated results obtained. Lastly, the conclusion will
deduce the findings of this work.

The 2nd International Conference on Applied Photonics and Electronics 2019 (InCAPE 2019)
AIP Conf. Proc. 2203, 020041-1–020041-5; https://doi.org/10.1063/1.5142133
Published by AIP Publishing. 978-0-7354-1954-4/$30.00

020041-1
 FOLDED CASCODE OPERATIONAL AMPLIFIER

FIGURE 1. Basic folded cascode operational amplifier

Figure 1 shows typical structure of a folded cascode op-amp Folded cascade topology is called as ‘folded cascode’
because it comes from a folding down n-channel cascode active loads of a different-pair and changing the MOSFET
to the p-channel. These topologies allow the input common-mode level of being close to the power supply voltage as
well as providing a high output swing, wide input common-mode range and preferably steering in low voltage supply
circuits. However, this topology has higher noise compare to the telescopic op-amp (C. Paper, I. S. Ishak, S. Anuar,
Z. Murad, A. Universiti, S. Chin, and N. Universiti, “Design of Folded Cascode Operational Amplifier (Op-Amp)
with Common-Mode Feedback (CMFB) for Pipeline ADC Design of Folded Cascode Operational Amplifier (Op-
Amp) with,” no. November 2015, pp. 1–7, 2013).

Folded cascode amplifier is a single-pole operational amplifier with large output swing and has higher gain
compared to the ordinary op-amp. It is very suitable for deep negative feedback because of its small signal gain that
can be very large. Comparing to the ordinary telescopic amplifiers, folded cascode operational amplifiers have a larger
output swing (E. Rajni, “Design of High Gain Folded-Cascode Operational Amplifier Using 1.25 um CMOS
Technology,” Int. J. Sci. Eng. Res., vol. 2, no. 11, pp. 1–9, 2011). Input and output can be short circuited to make it
easier for the selection of input common-mode level due to its relatively large output swing. The input common-mode
level can be close to the power supply voltage by using folded cascode op-amp. By using NMOS input, the common-
mode level of the gate pole can reach VDD . While PMOS input can lower the input common-mode level to 0V.

PROPOSED CIRCUIT DESIGN

Figure 2 illustrates the schematic design of the proposed folded cascode op-amp. The circuit design of the
proposed folded cascode op-amp is represented with the different colour box to focus on the basic topologies of each
block.

020041-2
 FIGURE 2. The proposed folded cascode op-amp.

The pink colour block represents the cascade current mirror. M8 and M9 pair, M10 and M11 pair are both basic
current mirror. A cascode current source is used to suppress the effect of channel-length modulation. M8 is diode-
connected to make sure that M9 and M10 always remain in saturation mode. The composition of this cascode current
mirror transforms the double-ended output into single-ended output without the present of other extra components. In
this circuit, the output voltage or current is taken from the drains of M7 and M9. While the green colour block
represents the multiple current mirrors. Since the transistors are not identical pair, their currents are not identical.

The yellow colour block represents the differential input pair. M1 and M2 are NMOS differential pair with
identical transistors. Thus, 𝐼1 = 𝐼2 since they are identical pair. NMOS differential pair is chosen instead of PMOS due
to its high electron mobility. The input stage provides the gain for the operational amplifier. PMOS input differential
pair has smaller transconductance, gm than a NMOS pair. Therefore, the NMOS differential pair has been chosen to
ensure a larger gain. Besides that, NMOS has a higher transition frequency, 𝑓𝑇 than PMOS, which able to maintain
high bandwidth.

The blue colour block represents the basic folded cascode topology. It is a high gain, a single-pole operational
amplifier with large output swing if compared to a two-stage or multi-stage amplifier. The advantage of a single-pole
amplifier is that the phase margin is very high and stable. It has higher gain compared to the ordinary operational
amplifier. The drawback to folded cascade op-amp is it consumes high power. The power dissipation is doubled for a
given settling requirement since it has two extra current legs.

RESULTS AND DISCUSSIONS

The proposed folded cascode op-amp has been simulated using Mentor Graphic pyxis. The performances of the
op-amp are verified based on the DC and AC analysis. The relationship of transfer characteristic of Vin and Vout is
shown in this DC analysis while the performance of the gain, unity gain bandwidth (UGB), phase margin (PM) and
cut-off frequency (fc ) are obtained by using AC analysis.

020041-3
 FIGURE 3. Transfer Characteristic Graph ( Vout versus Vin )

From the graph obtained, Vo(max) = 3 V and Vo(min) = -3.3 V. These peak-to-peak outputs represent the maximum
output voltage swings. When the output voltage exceeds this range, the wave obtained will experience clipping. Q-
point of approximately 0.3 V is obtained. The transistor will have sufficient biasing (Vout = Vin = 0.4 V) to operates
in the saturation region when Vin reached 0.4 V.

FIGURE 4. AC open-loop frequency response

The graph simulated in Fig. 4 shows a DC gain of 32.3590 dB, a gain crossover of 905.11, a phase margin of
83.754 degrees and a unity gain bandwidth of 906.8953 MHz. The -3 dB or 70.7% of Vmax down a point from the
frequency response curve is given as 29.3590 dB. By taking a line across until it intersects with the main GBP curve,
a cut-off frequency, fc of 17.1092 MHz is obtained.

020041-4
 CONCLUSIONS

In this work, a folded cascode operational amplifier is designed and simulated. The performance of the proposed
folded cascade op-amp circuit is studied. Through the simulation of Mentor Graphics, under ±3.3 V voltage supply,
the circuit’ s DC gain is 32.3590 dB, the phase margin is 83.754 degree with a high stability, the bandwidth is 17.1092
MHz, the unity gain bandwidth is as high as 906.8953 MHz and the slightly high power dissipation which is 86.9774
mW.

REFERENCES

1. B. Li, “A High DC Gain Op-Amp for Sample and Hold Circuits,” Proc. 2nd Int. Conf. Comput. Sci. Electron.
Eng. (ICCSEE 2013), vol. 9, no. Iccsee, pp. 1781–1784, 2013.
2. C.-M. Yu, Z.-M. Lin, and J.-D. Chen, “A Low Voltage High Unity-Gain Bandwidth CMOS Op-Amp,” 2004
IEEE Asia-Pacific Conf. Circuits Syst., 2004.
3. C. Paper, I. S. Ishak, S. Anuar, Z. Murad, A. Universiti, S. Chin, and N. Universiti, “Design of Folded Cascode
Operational Amplifier (Op-Amp) with Common-Mode Feedback (CMFB) for Pipeline ADC Design of Folded
Cascode Operational Amplifier (Op-Amp) with,” no. November 2015, pp. 1–7, 2013
4. E. Rajni, “Design of High Gain Folded-Cascode Operational Amplifier Using 1 . 25 um CMOS Technology,”
Int. J. Sci. Eng. Res., vol. 2, no. 11, pp. 1–9, 2011.
5. I. Manideep and D. Vijaya Kumar, “A 2.5GHz CMOS Folded Cascode Operational Amplifier,” Int. J. Adv. Eng.
Res. Dev. Sci. J. Impact Factor (SJIF, vol. 314, no. 4, pp. 2348–4470, 2016.E. Rodriguez-Villegas. (2006). Low
Power and Low Voltage Circuit Design with the FGMOS Transistor.
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Bandwidth , High Slew Rate and Low Power Dissipation CMOS Folded Cascode OTA for Wide Band
Applications,” vol. 4, no. 2, pp. 2–6, 2015
7. L. Ping, “A Fully Differential CMOS Operational Amplifier Implemented with Mos Gain Boosting Technique,”
p. 84, 1996
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amplifier in 0.13um technology,” Mod. Appl. Sci., vol. 9, no. 1, pp. 34–44, 2015.

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