MODULE 1: ARM Embedded Systems

1. List the difference between RISC and CISC?

2. List the difference between microprocessor and microcontroller?

3. Explain RISC design philosophy?
The ARM core uses reduced instruction set computer (RISC) architecture.it aimed at delivering simple
but powerful instructions that execute within a single cycle. It concentrates on reducing the complexity
of instructions.
The RISC philosophy is implemented with four major design rules:
1. Instruction: RISC processors have a reduced number of instruction classes. These classes provide
simple operations that can each execute in a single cycle. Each instruction is having fixed length which
supports pipelining.
In contrast, in CISC processors the instructions are often of variable size and take many cycles to
execute.
2. Pipelines: The processing of instructions is broken down into smaller units that can be executed in
parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput.
Instructions can be decoded in one pipeline stage.
There is no need for an instruction to be executed by a mini-program called microcode as on CISC
processors.
3. Registers: RISC machines have a large general-purpose register set. Any register can contain either
data or an address. Registers act as the fast local memory store for all data processing operations.
Incontrast, CISC processors have dedicated registers for specific purposes.
4. Load-store architecture: The processor operates on data held in registers. Separate load andstore
instructions transfer data between the register bank and external memory. Memory accesses are costly,
so separating memory accesses from data processing provides an advantage because you can use data
items held in the register bank multiple times without needing multiple memory accesses.
In contrast, with a CISC design the data processing operations can act on memory directly.
These design rules allow a RISC processor to be simpler, and thus the core can operate at higher clock
frequencies.
In contrast, traditional CISC processors are more complex and operate at lower clock frequencies.
4. Explain ARM design philosophy?
1.Battery power: The ARM processor has been specially designed to be small to reduce power
consumption and extend battery operation-essential for applications such as mobile phones and
personal digital assistants (PDAs).
2.High Code Density: it is another major requirement since embedded systems have limited memory
due to cost and/or physical size restrictions—useful for applications that have limited on-board
memory, such as mobile phones and mass storage devices.
3.Price Sensitive: embedded systems are price sensitive.

• Hence, use slow and low-cost memory devices to get substantial savings—essential for high-
volume applications like digital cameras.
• Also, reduce the area of the die taken up by the embedded processor; smaller the area used by
the embedded processor, reduced cost of the design and manufacturing for the end product.
 4.hardware debug technology: ARM has incorporated hardware debug technology within the
processor so that software engineers can view what is happening while the processor is executing code.
With greater visibility, software engineers can resolve issues faster.
5.Not a pure RISC architecture: The ARM core is not a pure RISC architecture because of the
constraints of its primary application—the embedded system. In some sense, the strength of the ARM
core is that it does not take the RISC concept too far.

MODULE: 2
1. Explain ARM core dataflow model?

• The arrows represent the flow of data, the lines represent the buses, and the boxes represent either
an operation unit or a storage area.
Flow of data:
• Data enters the processor core through the Data bus
• The instruction decoder translates instructions before they are executed.
• The ARM processor, like all RISC processors, uses load-store architecture-
✓ load instructions copy data from memory to registers in the core
✓ store instructions copy data from registers to memory.
• There are no data processing instructions that directly manipulate data in memory. Thus, data
processing is carried out in registers.
• Data items are placed in the register file - a storage bank made up of 32-bit registers.
• The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are
read from memory and placed in a register.
• ARM instructions typically have two source registers, Rn and Rm, and a single result or
destination register, Rd. Source operands are read from the register file using the internal buses
A and B, respectively.
 • The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values
Rn and Rm from the A and B buses and computes a result. Data processing instructions write
the result in Rd directly to the register file. Load and store instructions use the ALU to generate
an address to be held in the address register and broadcast on the Address bus.
• One important feature of the ARM is that register Rm alternatively can be preprocessed in the
barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide
range of expressions and addresses.
• After passing through the functional units, the result in Rd is written back to the register file
using the Result bus. For load and store instructions the Incrementer updates the address register

2. Explain Banked Registers?

There are 37 registers in the register file. Of these, 20 registers are hidden from a program at different
times. These registers are called banked registers. They are available only when the processor is in a
particular mode; for example,
abort mode has banked registers r13_abt, r14_abt and spsr_abt.
✓ Banked registers of a particular mode are denoted by an underline character post-fixed to the
mode.
✓ Every processor mode except user mode can change mode by writing directly to the mode bits of
the cpsr.
✓ All processor modes except system mode have a set of associated banked registers that are a
subset of the main 16 registers.
✓ A banked register maps one-to-one on to a user mode register.
✓ If you change processor mode, a banked register from the new mode will replace an existing
register
3. Explain processor modes?
The processor mode determines which registers are active and the access rights to the CPSR Register
itself.
2 types in processor mode.
I. Privileged mode: it allows full read-write access to the CPSR.
II. Non-privileged mode: only allows read access to the control field in the CPSR, but still allows
read-write access to the condition flags.
There are seven processor modes in total:
six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system, and
undefined).
• The processor enters abort mode when there is a failed attempt to access memory.
• Fast interrupt request and interrupt request modes correspond to the two interrupt levels
available on the ARM processor.
• Supervisor mode is the mode that the processor is in after reset and is generally the mode that an
operating system kernel operates in.
• System mode is a special version of user mode that allows full read-write access to the cpsr.
• Undefined mode is used when the processor encounters an instruction that is undefined or not
supported by the implementation.
One non-privileged mode (user).
 • Usermode is used for programs and applications.

4. Explain CPSR resisters?

The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated 32-bit
register and resides in the register file

• The CPSR is divided into four fields, each 8bits wide: flags, status, extension, and control.
✓ The control field contains the processor mode, state, and interrupt mask bits.
✓ The flags field contains the condition flags.
• Some ARM processor cores have extra bits allocated. For example, the J bit, which can be found
in the flags field, is only available on Jazelle-enabled processors, which execute 8-bit instructions.
5. Explain pipeline?
• A pipeline is the mechanism in a RISC processor, which is used to execute instructions.
• Pipeline speeds up execution by fetching the next instruction while other instructions are being
decoded and executed.
• As the pipeline length increases, the amount of work done at each stage is reduced.
Fetch loads an instruction from memory.
Decode identifies the instruction to be executed.
Execute processes the instruction and writes the result back to a register.
 ✓ In the first cycle, the core fetches the ADD instruction from memory.
✓ In the second cycle, the core fetches the SUB instruction and decodes the ADD instruction.
✓ In the third cycle, both the SUB and ADD instructions are moved along the pipeline.
✓ The ADD instruction is executed, the SUB instruction is decoded, and the CMP instruction is
fetched. This procedure is called filling the pipeline.
➢ Five stage pipelining: The ARM9 core increases the pipeline length to five stages. The ARM9 adds
a memory and write stages to the pipelining which is increases the instruction throughput in ARM9
by around 13% compared with an ARM7.

Six stage pipelining: The ARM10 increases the pipeline length still further by adding a sixth stage
called ‘issue’. It have about 34% more throughput than an ARM7 processor core but again at a higher
latency cost.

6. With a neat diagram, explain the main hardware component of an ARM based embedded device.
four main hardware components:
i. ARM processor: The ARM processor controls the embedded device. Different versions of
the ARM processor are available to suit the desired operating characteristics. An ARM
processor comprises a core (the execution engine) plus the surrounding components (memory
and cache) that interface it with a bus. These components can include memory management
and caches.
ii. Controllers: Controllers coordinate important functional blocks of the system. Two
commonly found controllers are interrupt and memory controllers.
• Memory controller: it connect different types of memory to the processor bus. On power-up
a memory controller is configured in hardware to allow certain memory devices to be active.
• Interrupt controller: it provides a programmable governing policy that allows software to
determine which peripheral or device can interrupt the processor at any specific time by setting
the appropriate bits in the interrupt controller registers.
There are 2 types:
▪ The standard interrupt controller sends an interrupt signal to the processor core when an
external device requests servicing.
▪ The vector interrupt controller (VIC): it prioritizes interrupts and simplifies the
determination of which device caused the interrupt.
iii. The peripherals provide all the input-output capability external to the chip and are responsible
for the uniqueness of the embedded device. Each peripheral device usually performs a single
function and may reside on-chip. All ARM peripherals are memory mapped—the programming
interface is a set of memory addressed registers.
 iv. A bus is used to communicate between different parts of the device.

7. Explain interrupts?