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2-IAS Architecture - Instruction Formats-19!07!2024

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22 views13 pages

2-IAS Architecture - Instruction Formats-19!07!2024

Uploaded by

Saatwik Nalluri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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IAS Architecture

ANISHA M. LAL
Von Neumann Machine
• Stored Program concept:
• – The task of entering and altering programs for the ENIAC was extremely
tedious.
• – The programming process could be facilitated if the program could be
presented in a form suitable for storing in memory alongside the data.
• – Then a computer could get its instructions by reading them from
memory, and a program could be set or altered by setting the values of a
portion of memory.
• – The stored program concept idea is given by a mathematician John Von
Neumann, who was the consultant on the ENIAC project.
Von Neumann machine
IAS – Institute of Advanced Studies
A prototype developed by John Von Neumann in 1946 at
Princeton University.
IAS – memory format
• 1000 x 40 bit words ( 1000 storage locations of 40
binary bits each)
• Data Word Format:
– Each number is represented by a sign bit and a 39
bit value.
• Instruction word Format:
– A word may contain two 20 bit instructions.
– Each instruction consisting of :
– an 8 bit operation code (opcode) specifying the
operation to be performed
– a 12 bit address designating one of the words in
memory (0 to 999)
IAS – memory format
Structure of IAS Machine
– Memory Address Register
(MAR)
• Specifies the address in
memory of the word to be
written from or read into the
MBR.
– Instruction Register (IR)
• Contains the 8 bit opcode
instruction being executed.
– Instruction Buffer Register
(IBR)
• Employed to hold
temporarily the right hand
instruction from a word in
memory
– Program Counter (PC)
• Contains the address of the
next instruction pair to be
fetched from memory
Registers in IAS Machine
– Memory Buffer Register (MBR)
• Contains a word to be stored in memory or sent
to the I/O unit, or it is used to receive a word
from memory or from the I/O unit.
– Accumulator (AC) & Multiplier Quotient
(MQ)
• Employed to hold temporarily the output data.
For eg. The result of multiplying two 40 bit
numbers is an 80 bit number, the most
significant 40 bits are stored in the AC and the
least significant in the MQ.
IAS Operation - Flowchart AC MQ

MARPC No Is next instruction


in IBR?
MBRM[MAR] Arithmetic & Logic Input/output
Circuits Equipments
IBRMBR<20..39>
IRMBR<0..7>
yes
MARMBR<8..19> MBR
MBRM[MAR]
ACAC+MBR
IRIBR<0..7>
MARIBR<8..19> IBR PC

PCPC+1
Main
PCMAR
Memory
MBRM[MAR]
IR
AC MBR MAR

Control
Circuits
Fetch / Execute Cycle
IAS Instructions

IAS – Total 21 Instructions

• Data Transfer
• Unconditional Branch Instruction
• Conditional Branch Instruction
• Arithmetic
• Address Modify Instruction
IAS Instruction set
IAS Instruction set Contd..

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