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RTL to GDS Implementation and Verification of UART using UVM and

OpenROAD

Conference Paper · January 2024

DOI: 10.1109/CCWC60891.2024.10427771

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 RTL to GDS Implementation and Verification of
UART using UVM and OpenROAD
2024 IEEE 14th Annual Computing and Communication Workshop and Conference (CCWC) | 979-8-3503-6013-4/24/$31.00 ©2024 IEEE | DOI: 10.1109/CCWC60891.2024.10427771

Purav Bhatt Dharmik Joshi Shrikant Jadhav

Dept. of Electrical Engineering Dept. of Electrical Engineering Dept. of Electrical Engineering
San Jose State University San Jose State University San Jose State University
San Jose San Jose San Jose
[email protected] [email protected] [email protected]

Abstract—The paper outlines a thorough Application Spe- and simulation are employed to verify compliance with the
cific Integrated Circuit (ASIC) design flow for Universal Asyn- requirements. The gate-level representation is transformed into
chronous Receiver and Transmitter (UART) utilizing RTL to a physically feasible layout in the physical design stage. Tasks
GDS implementation and verification. Hardware verification
employs the Universal Verification Methodology (UVM), while like floorplanning, placement, clock tree synthesis, routing,
the OpenROAD tool is integrated for physical designs spanning and optimization are performed to meet time, power, and
synthesis to Graphic Data System (GDS). The paper states the rel- space constraints. Once the final layout database is created,
evance of UART in real-time systems, particularly in the context containing all the necessary design data, it is ready for manu-
of the increasing prevalence of IoT and Big Data applications. It facturing after thoroughly reviewing it and satisfies all relevant
delves into the encountered challenges during the research project
and offers recommendations for future advancements. Through requirements. The manufacturing process involves sending this
our experimentations with the OpenROAD, we demonstrated the database to a semiconductor foundry for fabrication.
design and verification process of the sophisticated digital circuit. The verification process plays a critical role in developing
The results of the verification are shown via waveforms for test Very Large Scale Integration (VLSI) chips. It involves running
cases. The results of the backend implementation include layouts numerous test cases to ensure the design functions as intended.
and a QoR (Quality of Results) report table. The paper concludes
by stating the significance of each stage in the ASIC design Verification and performance measurement of integrated cir-
cycle with future scope in optimizing the design for heightened cuits are demanding tasks that require significant time and
frequencies and enhanced performance. effort. As the complexity of the device design increases, verifi-
Index Terms—UART, OpenROAD, Verilog, UVM, ASIC, Phys- cation becomes even more challenging. Traditional verification
ical design, approaches often lack reusability, and their time to market is
typically lengthy. The UVM library addresses these limitations
I. I NTRODUCTION by providing reusable components and testing environments
With the increase of IoT applications, HPC, and Big Data using System Verilog. UVM is a widely adopted methodology
solutions, it has become crucial to have a communication for verifying integrated circuit designs, offering advantages
protocol to match those demands. A reliable, reusable, and such as reusability, scalability, and interoperability. Employing
plug-and-play solution can help with the sharp rise in data UVM enables the realization of these qualities and brings
communication. In real-time systems, a communication proto- multiple benefits to the verification process. The physical de-
col is center stage for peripherals to interact with the processor, sign of the UART is facilitated using the OpenROAD toolsets
so the propagation delay would be as low as possible. If the [1]. OpenROAD is a leading open-source application for
communication is not reliable, the real-time system would semiconductor digital design. It aims to promote open access,
essentially be a failure. UART is often used as an Integrated expertise, rapid innovation, and accelerated design turnaround
Circuit (IC) for serial communication through a computer or by eliminating hardware design barriers related to cost, risk,
a peripheral device. and uncertainty. It offers flexible flow control by providing an
The first step of the ASIC Design flow is the register API with TCL and Python bindings. It is an integral part of
transfer level (RTL) design, where the high-level architectural open-source digital design flows, exemplified by OpenROAD-
description is transformed into a digital representation using flow-scripts. In this paper, the physical design using Open-
hardware description languages (HDLs) like Verilog or VHDL. ROAD is presented. Physical design plays a vital role in
This involves designing and implementing the behavior and creating a wide range of products, systems, and structures,
connections of individual digital components. After RTL im- encompassing architecture, industrial design, integrated circuit
plementation of a digital component, it undergoes rigorous layouts, and urban planning. It transforms intangible require-
functional verification to ensure it executes as expected. ments, ideas, and concepts into tangible and practical forms.
Techniques such as hardware emulation, formal verification, Physical design aims to optimize the placement of elements
and physical features to achieve effectiveness, efficiency, and
979-8-3503-6013-4/24/$31.00 ⃝2024
c IEEE user satisfaction. Partitioning is a crucial step in physical

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design, where a complex circuit is divided into manageable
subsystems or sub-blocks with minimal interconnections. Dur-
ing this phase, each block’s shape and approximate location
on the silicon chip are determined. The placement of pins for
each block is also decided, ensuring easy routing of connec-
tions between these blocks in the future. Placement involves
precisely positioning the sub-blocks to allow sufficient space
between them for routing Vdd and Ground supply lines and
connector wires. Static timing analysis is performed on the
final routed netlist, representing or simulating the chip’s layout
to validate its timing performance. To ensure the design’s
functionality remains unchanged, Layout vs. schematic (LVS)
equivalency verification and physical design implementation
Layout is conducted. These steps confirm that the design’s
intended functionality is preserved throughout the physical
design process. Fig. 1. UART Design

II. R ELATED W ORK

The UVM verification approach is used to verify the UART
protocol. This verification method includes setting up a UART UART module. UART is a serial communication protocol that
configuration type in which all the UART protocol param- allows devices to communicate without a clock signal. It sends
eter information is packaged and sent the UART protocol parallel data that has been converted to serial format [9]. Data
parameter information to related platform parts like a driver, that is received in serial format is transformed into parallel
a monitor, and a grade recording board through a config-db format. The baud rate generator, receiver, transmitter, interrupt,
mechanism provided by the UVM [2]. This process involves and FIFO modules are all designed as part of the UART
finishing an overall framework of UART protocol verification design process. Verification entails checking the design by
using a UVM verification platform structure and a verification establishing a verification environment that permits testbench
idea. Our work signifies the importance and the need for reuse and minimizes code complexity, tests the difficult-to-
UVM to verify the UART protocol, as it can make verifying reach corner situations, and randomization [10]. The design
a block simpler and more efficient than other conventional and verification of UART are the subjects of this study.
verification methods [3]. It also gives a detailed overview of
how UART works and how the verification environment should UARTs are included in microcontrollers quite frequently.
be set up to check for communication with the same. This A UART is typically an exclusive integrated circuit (IC) or a
study aims to use System Verilog to develop a UART and component of an IC that is used for serial communication
a UVM-based testbench to validate the design. One of the on a serial port on a computer or peripheral device [11].
most popular serial communication protocols that can be used It works flawlessly when connected to a PC’s serial port
without a clock stimulation is UART [4]. The Baud rate gen- for data transfer with customized electronics. Today, UARTs
erator, control, bus interface, interrupt control, and receiver- are frequently included in microcontrollers. A full duplex
transmitter FIFO blocks are all included in the architecture transmitter or receiver is a UART. In [12] explains how the
[5]. System bus parallel data are serialized, transported, and metastable state can be eliminated. It requires the input of
converted to parallel data at the receiving end. A reusable the first-stage trigger to meet the holding time. The output
and adaptable verification environment reduces complexity then stabilizes before the next edge comes. [13] presents an
and processing time. This paper details the System Verilog on-chip functional verification system that includes a high-
(SV) hardware description language design for the UART level software model, the verification flow, and the abstract
and SPI functional modules. The UVM is used for functional description of the IP that needs to be verified. UART IP ver-
verification of the UART and SPI [6]. The reusable UVM ification includes a wishbone interface that allows integrated
testbench architecture is meant to push the randomized stimuli circuits to communicate [14]. It also presents a FIFO control
to the unit under test to assess the functional correctness by register and a LINE control register that provides both the
comparing the collected response to the intended response via specification of the data format and whether to select the FIFO
the scoreboard mechanism. The overall execution time will trigger level or not. [15] involves implementing the UART
be shortened by the stimulus’s reusability [7]. The UVM- protocol on FPGA. It also presents a FIFO buffer that helps
based verification will reduce the time the logic gates need the design to be flexible and avoid data loss. [16] presents
to operate. The overall execution time will be reduced since XCVR, a transceiver unit that emulates a UART, which can
the tests of sequences are kept separate from the original be used to make the transactions for the UART specification.
test bench hierarchy and the reusability of stimulus [8]. Our It also involves a self-test for the verification platform used to
primary goal is to use SV to design and test a full duplex validate the functionality of every module.

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 Fig. 2. Transmitter block Diagram Fig. 4. Receiver Block Diagram

Fig. 3. Transmitter FSM

Fig. 5. Receiver FSM

III. UART D ESIGN I MPLEMENTATION
Figure 1 explains the block diagram of UART. The UART
design has a transmission FIFO, receiver FIFO, two shift parity-enable signal is not turned ON, and finally, the FSM
registers, a baud rate generator, and a control unit. The baud enters the last stage, the STOP bit. If the parity-enable signal
rate generator produces various baud rates for transmission. is turned ON, the transmitter adds a parity bit before entering
It then gives that information to the control unit, producing the STOP bit. The data frame is given out as an output from
read, write, and other control signals. The shift register links the pin Tx-out. During all the operations, the busy signal is
the data packet generation to the FIFOs. The BRG is a flexible set to 1 to indicate that the next data frame has to wait till the
and programmable unit that produces a baud clock. The shift current operations are finished.
register helps to hold the data packet by adding parity bits Figure 4 shows the UART receiver. The receiver module
and BRG bits. The FIFO helps to transmit and receive the takes in three inputs and produces three outputs. The inputs
data serially. The control unit helps to know when to read or are clock, reset, and data. The outputs are data-out, ready, and
write data. parity signal. The reset signal shuts off all the operations of
This paper demonstrates the whole ASIC flow for the the circuit. The clock signal is used to transit from one state to
UART. It highlights the architecture that uses the shift register another. It has various internal registers such as shift register,
for the transmitter of five FSM states and the receiver of three state register, bit-count register, and received-data register. The
FSM states. Moreover, the work involves the physical design shift register is used to shift the data frame coming from
flow implementation and optimization using modern nodes and the transmitter. The state register has information about the
open-source tools that demonstrate a way for students and three states of the receiver. The bit-count register is used to
early start-ups to implement the flow. set as a base for the counter to go through the state frame.
Figure 2 explains the transmitter block diagram. The trans- The received data register stores the data coming from the
mitter module takes inputs clk, reset, enable, data, and the transmitter. The rx-data signal indicates whether the data is
parity enable bit, producing data to transmit and busy bit as received and stored in the internal register. The RX-ready
outputs. It uses an internal shift register to transmit the data, a signal indicates if the receiver is ready, i.e., if the operations
counter that counts the number of bits to be transmitted, and are ongoing, it cannot accept the next set of data frames. A
a register for keeping the state machine information. parity-error signal indicates if the receiver catches the parity
Figure 3 shows the state flow of the transmitter. It has five error.
states: IDLE, START, DATA, PARITY, and STOP. By default, Figure 5 shows the finite state machine of the receiver. It has
it starts with the IDLE state before the Tx-enable signal is three states, namely, IDLE-STATE, SHIFT-DATA-STATE, and
switched ON. Then, it goes to the START state. Here, the PARITY-CHECK-STATE. The state machine starts by waiting
transmitter adds the start bit to the shift register and shifts the for the start bit to be received in the IDLE-STATE. The state
data left. It transits into the DATA state. Here, the transmitter machine switches to the SHIFT-DATA-STATE after detecting
shifts data left until all eight bits have been transmitted. If the the start bit, where it inserts incoming data bits one at a time
user does not want to add the parity bit to the data frame, the until all data bits and the parity bit are received. The state

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machine switches to PARITY-CHECK-STATE after receiving
all the data bits and the parity bit, which checks the parity bit
for parity mistakes.
IV. P HYSICAL D ESIGN I MPLEMENTATION
We used an open-source tool for RTL to GDS flow,
OpenROAD, for the backend implementation. The flow starts
with the design synthesis. It takes inputs such as HDL files
(.v, .sv, .vhd), libraries, and constraints (.sdc), generating a
netlist for the area and timing reports. We have used 7nm
FINFET process technology. The output of the synthesis stage
is provided as input to the partitioning along with physical
libraries (.lef file) to get the design portion. The output of the
partitioning is fed to the floorplan that generates a .def file.
The placement stage places the cells in their unique position
on the floorplan. The clock tree is generated using RC delay
models.
The timing tool performs a timing analysis of the design and
generates a timing report. OpenROAD has a separate tool for
every stage. The synthesis uses Yosys and ABC, the floorplan
uses Placer PDN, and the placement uses RePLace, Resizer,
and OpenDP. The clock tree synthesis uses TritionCTS, and Fig. 6. Test Plan Flowchart
routing uses FastRoute. Tools like Magic and Klayout are used
for checks and GDSII generation. The flow also generates logs
and reports, which are used to analyze the performance of
the design. For example, the timing reports present the slack
value. The placement report mentions the utilization of macros
and standard cells. The routing stage provides the congestion
report, which implies the amount of congestion between two
metal layers. These metrics are used to analyze the design
performance.
V. UVM BASED V ERIFICATION
The flow chart in Figure 6 depicts the verification method-
ology used to verify UART hardware. We divided UVM
verification of UART into several steps. The first step is to
build a UVM test bench with a scoreboard, a monitor, and a
test sequence generator. In this instance, the test sequence gen- Fig. 7. UVM Environment
erator generates a stimulus that activates the UART module,
which is the Design Under Test (DUT). The monitor gathers
data from the signals sent and received at the DUT’s interface to the scoreboard. The scoreboard analyzes any discrepancies
produces transactions sent to the scoreboard. The scoreboard between the transactions produced by the monitor and the
analyzes any discrepancies between the transactions produced expected transactions and reports them. If there are any dis-
by the monitor and the expected transactions and reports them. crepancies, the testbench can be troubleshot to determine the
The driver uses the virtual interface to communicate the trans- root of the issue. UVM can be used to automate, standardize,
actions produced by the test sequence generator with the DUT. and streamline the verification of UART, producing designs
The sequencer manages the transaction flow to ensure that the with higher quality and faster time to market.
transactions are sent in the right order. In addition to isolating To drive the UART DUT with the test stimulus and record
the testbench from the DUT’s implementation specifics, the the response, the UVM environment is essential to the ver-
virtual interface offers a transaction-level interface between ification process. The UVM environment is built using the
the two. We have used an open-source simulation platform, libraries, a standardized methodology for developing reusable
EDA Playground [17], to run our simulations and waveforms. verification environments. Several UVM elements, such as the
The test sequence generator generates a stimulus sent to the agent, monitor, scoreboard, and driver, make up the UVM
DUT through the driver and the virtual interface during the environment. The agent is responsible for applying the test
simulation. The monitor gathers data from the signals sent and stimulus to the UART DUT and recording the response. It
received at the DUT’s interface and produces transactions sent includes a sequence generator that uses the earlier test plan

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 Fig. 9. Receiver Simulation

Fig. 8. Transmitter simulation

few of the possible responses. As an illustration, when the
transmitter receives a fresh data byte, it buffers it and waits for
to create test sequences. The agent also includes a driver, the subsequent transmission cycle. The transmitter signals the
which transforms the test sequences into signals sent to the end of transmission and awaits the arrival of the following data
UART DUT, and a monitor, which records the UART DUT’s byte after completing a data frame. The transmitter reports any
response. Verifying the accuracy of the UART DUT’s response errors it may find and re-transmits it when it finds one, such as
is the responsibility of the scoreboard. When there is a a parity or framing error. The clock signal is generated inside
discrepancy between the response from the monitor and the the testbench for reference using the baud rate calculations
anticipated outcomes specified in the test plan, an error is provided in the report, where data-in is 8-bit data coming via
generated. The UVM environment created by the verification the transmitter. The device defined here is an active low reset
is shown in Figure 7. A configuration object is used to pass design, so as soon as the rst-n signal is de-asserted, the design
parameters to the various UVM components, and a test bench, accepts the incoming data and processes it further. The data is
which organizes the execution of the test sequences, is also then sampled and shifted and takes eight clock cycles depicted
included in the UVM environment in addition to the UVM by a variable bit-cnt in the waveform to track whether the
components. A UVM testbench environment must be created data coming in is in multiples of 8, which is the required
with a driver, a sequencer, and a virtual interface.. The driver data frame in the design, and stores it in the data-reg in the
uses the virtual interface to communicate the transactions design. Whenever there is an a-out on the transmitter end, the
produced by the test sequence generator with the DUT. txout signal is asserted and de-asserted, respectively, to match
the transmission and processing of the design. The start and
VI. E XPERIMENTAL R ESULTS stop bits show the starting and stop of the transmission in the
The experimental environment involves Windows Subsys- design. This snippet is a partial waveform and has a stop-bit
tem for Linux (WSL2). It has Ubuntu 22.04.2 as the Linux signal asserted at the end of the simulation.
version. The processor of the computer is an i7 with a clock of Figure 9 shows the receiver waveform. The clock, reset, and
2.6 GHz and 32 GB of RAM. The physical design flow also the signals for sending and receiving data are defined at the
used the docker desktop. We used EDA playground to simulate beginning of the code. Additionally, it specifies the validity and
the design and used the OpenROAD GitHub repository for the signals for the data received. The correct signal connections
physical design implementation. are then made when the DUT is first created. Several param-
Figure 8 depicts how the UART design reacts to the stimulus eters are defined, including the simulation time, baud rate,
provided by the test bench. The UART TX (transmitter) number of data bits, and stop bits. The test-bench variables
begins transmitting data when data is written to it. A start and signals are initialized. The test data to be transmitted is
bit, which is always sent by the transmitter at a low logic specified as a vector with the logic value [7:0]. The test-bench
level to indicate the beginning of a new data frame, is sent variables and signals are initialized after the test-bench clock
first. Following that, it sends the data bits one at a time, is created using an ”always” block in the code. The DUT is
beginning with the least significant bit (LSB) and concluding reset before sending the test data and given time to stabilize.
with the most significant bit (MSB). In most cases, depending The transmission of the data is made possible by using the
on the configuration, there are 7 or 8 data bits. The transmitter start bit, data bits, and stop bits signals to create the defined
optionally sends a parity bit for error detection after the data baud rate, data bits, and stop bits signals. The transmitted
bits to help with transmission. It is based on the data bits data is declared valid after comparing the transmitted and
to calculate the parity bit, which can be even, odd, or none. received data. The test is successful if the transmitted and
The transmitter sends a high logic stop bit to indicate the end received data are identical and the data is marked as valid.
of the data frame. The UART TX responds to several events Upon reaching a certain number of clock cycles, the simulation
that occur during transmission, including receiving new data is over. It’s critical to thoroughly understand the design and
bytes, completing data frames, and spotting errors. Interrupt test bench before you can debug effectively. This entails being
creation, error reporting, and state modifications are just a aware of the timing and order of signals, the expected DUT

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 Fig. 10. Floorplan layout
Fig. 12. Route layout

Fig. 11. Placement layout

behavior, and the operation of the UVM components. The Fig. 13. GDS generation
tests must be run to ensure that the changes have introduced
no new problems after the problems have been located and
fixed. The coverage report should be updated to reflect any layout of the placement stage. Figure 8 presents the layout of
additional coverage the modified tests may have produced. the placement stage. The standard cells are not placed inside
This iterative process is continued until the desired coverage the spaces created by the floorplan stage. Figure 12 shows the
and functionality objectives are met, and the UART DUT is output of the routing stage. The lines connecting two standard
prepared for integration into the larger system. cells are the metal layers. There are six metal layers, each
Figure 10 shows the output layout of the floorplan stage. The connected to a nearby layer with vias. Just like two floors of
arrows on the outside of the die are the inputs and outputs. a building are connected via pillars, similarly, all the layers
Inward arrows are inputs, and outward arrows are outputs. The are connected through vias. Figure 13 shows the final GDS
red lines are the Vdd and Vss, i.e., the power and ground pins. picture of the design. It contains the shape, size, and location
Starting from the top, the first red line is the power line, and the of every cell, along with the routing. The green lines are the
next is the ground line. The bold blue lines in the middle are metal layers, and the square shapes are the interconnections
the metal layers. The spacing between the red lines is where between them. Figure 13 shows the zoomed picture of the
the standard cells will be placed. Figure 11 shows the output GDS with the metal interconnections between two layers. The

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verification tools and the foundries use this file, for example,
Intel Foundry Services or TSMC, for chip fabrication.
Table 2 Key Parameters
No. Parameter Value
1 Technology Process node 7 nm
2 Clock frequency 25MHz
3 Setup slack -3.14 ns
4 Hold slack -155.97 ns
5 Utilization 0.56
6 Total Power 12.8 milli-watts
7 Average IR drop 74.9 milli-volts
8 number of nets 528

TABLE I
T EST C ASE C OVERAGE

Test Case Coverage

No. Test name Test case description Status
1 Transmitter check Correct data to Tx check Pass
2 Transmitter address allocation check Whether the Tx data is allocated to the right address Pass
3 Receiver check Correct data to Rx check Pass
4 Receiver address allocation check Whether the Rx data is allocated to the right address Pass
5 Transmitter and Receiver working in parallel Full duplex check Pass
6 Baud rate check Whether the system operates at the right baud rate Pass
7 Baud rate change check Toggling baud rates Unchecked
8 Transmission with correct baud rate check Whether the tx baud rate is accurately generated as mentioned in the spec Pass
9 Receiving with correct baud rate check Whether the Rx baud rate is accurately generated as mentioned in the spec Pass
10 Variable baud rate Tx and Rx check Operating Tx and Rx at different speeds Fail
11 Parity check Checking the purity of the signals Pass
12 Data conversion with correct parity check Checking the tx and rx as a whole after adding parity bits Pass

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